| stats.txt (8983:8800b05e1cb3) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.025989 # Number of seconds simulated 4sim_ticks 25988864000 # Number of ticks simulated 5final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.025989 # Number of seconds simulated 4sim_ticks 25988864000 # Number of ticks simulated 5final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 71403 # Simulator instruction rate (inst/s) 8host_op_rate 71915 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20482160 # Simulator tick rate (ticks/s) 10host_mem_usage 364344 # Number of bytes of host memory used 11host_seconds 1268.85 # Real time elapsed on the host | 7host_inst_rate 141606 # Simulator instruction rate (inst/s) 8host_op_rate 142623 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40620332 # Simulator tick rate (ticks/s) 10host_mem_usage 364696 # Number of bytes of host memory used 11host_seconds 639.80 # Real time elapsed on the host |
| 12sim_insts 90599356 # Number of instructions simulated 13sim_ops 91249910 # Number of ops (including micro ops) simulated | 12sim_insts 90599356 # Number of instructions simulated 13sim_ops 91249910 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 999040 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 46144 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 2048 # Number of bytes written to this memory 17system.physmem.num_reads 15610 # Number of read requests responded to by this memory 18system.physmem.num_writes 32 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 38441080 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1775530 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 78803 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 38519883 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 46144 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 952896 # Number of bytes read from this memory 16system.physmem.bytes_read::total 999040 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 46144 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 46144 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory 20system.physmem.bytes_written::total 2048 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 721 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14889 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15610 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 32 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1775530 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 36665550 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 38441080 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1775530 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1775530 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 78803 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 78803 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 78803 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1775530 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 36665550 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 38519883 # Total bandwidth to/from this memory (bytes/s) |
| 24system.cpu.dtb.inst_hits 0 # ITB inst hits 25system.cpu.dtb.inst_misses 0 # ITB inst misses 26system.cpu.dtb.read_hits 0 # DTB read hits 27system.cpu.dtb.read_misses 0 # DTB read misses 28system.cpu.dtb.write_hits 0 # DTB write hits 29system.cpu.dtb.write_misses 0 # DTB write misses 30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 332 unchanged lines hidden (view full) --- 364system.cpu.icache.overall_miss_latency::total 33892500 # number of overall miss cycles 365system.cpu.icache.ReadReq_accesses::cpu.inst 14156722 # number of ReadReq accesses(hits+misses) 366system.cpu.icache.ReadReq_accesses::total 14156722 # number of ReadReq accesses(hits+misses) 367system.cpu.icache.demand_accesses::cpu.inst 14156722 # number of demand (read+write) accesses 368system.cpu.icache.demand_accesses::total 14156722 # number of demand (read+write) accesses 369system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses 370system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses 371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses | 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 332 unchanged lines hidden (view full) --- 377system.cpu.icache.overall_miss_latency::total 33892500 # number of overall miss cycles 378system.cpu.icache.ReadReq_accesses::cpu.inst 14156722 # number of ReadReq accesses(hits+misses) 379system.cpu.icache.ReadReq_accesses::total 14156722 # number of ReadReq accesses(hits+misses) 380system.cpu.icache.demand_accesses::cpu.inst 14156722 # number of demand (read+write) accesses 381system.cpu.icache.demand_accesses::total 14156722 # number of demand (read+write) accesses 382system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses 383system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses 384system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses |
| 385system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses |
|
| 372system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses | 386system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses |
| 387system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses |
|
| 373system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses | 388system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses |
| 389system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses |
|
| 374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency | 390system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency |
| 391system.cpu.icache.ReadReq_avg_miss_latency::total 34868.827160 # average ReadReq miss latency |
|
| 375system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency | 392system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency |
| 393system.cpu.icache.demand_avg_miss_latency::total 34868.827160 # average overall miss latency |
|
| 376system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency | 394system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency |
| 395system.cpu.icache.overall_avg_miss_latency::total 34868.827160 # average overall miss latency |
|
| 377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 381system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 382system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 383system.cpu.icache.fast_writes 0 # number of fast writes performed 384system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 396system.cpu.icache.overall_mshr_misses::total 749 # number of overall MSHR misses 397system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25625000 # number of ReadReq MSHR miss cycles 398system.cpu.icache.ReadReq_mshr_miss_latency::total 25625000 # number of ReadReq MSHR miss cycles 399system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25625000 # number of demand (read+write) MSHR miss cycles 400system.cpu.icache.demand_mshr_miss_latency::total 25625000 # number of demand (read+write) MSHR miss cycles 401system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles 402system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles 403system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses | 396system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 400system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 401system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.cpu.icache.fast_writes 0 # number of fast writes performed 403system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 415system.cpu.icache.overall_mshr_misses::total 749 # number of overall MSHR misses 416system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25625000 # number of ReadReq MSHR miss cycles 417system.cpu.icache.ReadReq_mshr_miss_latency::total 25625000 # number of ReadReq MSHR miss cycles 418system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25625000 # number of demand (read+write) MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::total 25625000 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles 422system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses |
| 423system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses |
|
| 404system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses | 424system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses |
| 425system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses |
|
| 405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses | 426system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses |
| 427system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses |
|
| 406system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency | 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency |
| 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34212.283044 # average ReadReq mshr miss latency |
|
| 407system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency | 430system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency |
| 431system.cpu.icache.demand_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency |
|
| 408system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency | 432system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency |
| 433system.cpu.icache.overall_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency |
|
| 409system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 410system.cpu.dcache.replacements 943602 # number of replacements 411system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use 412system.cpu.dcache.total_refs 28436874 # Total number of references to valid blocks. 413system.cpu.dcache.sampled_refs 947698 # Sample count of references to valid blocks. 414system.cpu.dcache.avg_refs 30.006261 # Average number of references to valid blocks. 415system.cpu.dcache.warmup_cycle 8214901000 # Cycle when the warmup percentage was hit. 416system.cpu.dcache.occ_blocks::cpu.data 3646.405021 # Average occupied blocks per requestor --- 39 unchanged lines hidden (view full) --- 456system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses) 457system.cpu.dcache.StoreCondReq_accesses::cpu.data 5797 # number of StoreCondReq accesses(hits+misses) 458system.cpu.dcache.StoreCondReq_accesses::total 5797 # number of StoreCondReq accesses(hits+misses) 459system.cpu.dcache.demand_accesses::cpu.data 29605337 # number of demand (read+write) accesses 460system.cpu.dcache.demand_accesses::total 29605337 # number of demand (read+write) accesses 461system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses 462system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses 463system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses | 434system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 435system.cpu.dcache.replacements 943602 # number of replacements 436system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use 437system.cpu.dcache.total_refs 28436874 # Total number of references to valid blocks. 438system.cpu.dcache.sampled_refs 947698 # Sample count of references to valid blocks. 439system.cpu.dcache.avg_refs 30.006261 # Average number of references to valid blocks. 440system.cpu.dcache.warmup_cycle 8214901000 # Cycle when the warmup percentage was hit. 441system.cpu.dcache.occ_blocks::cpu.data 3646.405021 # Average occupied blocks per requestor --- 39 unchanged lines hidden (view full) --- 481system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.StoreCondReq_accesses::cpu.data 5797 # number of StoreCondReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::total 5797 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.demand_accesses::cpu.data 29605337 # number of demand (read+write) accesses 485system.cpu.dcache.demand_accesses::total 29605337 # number of demand (read+write) accesses 486system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses 487system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses 488system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses |
| 489system.cpu.dcache.ReadReq_miss_rate::total 0.040373 # miss rate for ReadReq accesses |
|
| 464system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses | 490system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses |
| 491system.cpu.dcache.WriteReq_miss_rate::total 0.037182 # miss rate for WriteReq accesses |
|
| 465system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses | 492system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses |
| 493system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001355 # miss rate for LoadLockedReq accesses |
|
| 466system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses | 494system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses |
| 495system.cpu.dcache.demand_miss_rate::total 0.039863 # miss rate for demand accesses |
|
| 467system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses | 496system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses |
| 497system.cpu.dcache.overall_miss_rate::total 0.039863 # miss rate for overall accesses |
|
| 468system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency | 498system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency |
| 499system.cpu.dcache.ReadReq_avg_miss_latency::total 5760.542992 # average ReadReq miss latency |
|
| 469system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency | 500system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency |
| 501system.cpu.dcache.WriteReq_avg_miss_latency::total 26197.875726 # average WriteReq miss latency |
|
| 470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency | 502system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency |
| 503system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16125 # average LoadLockedReq miss latency |
|
| 471system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency | 504system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency |
| 505system.cpu.dcache.demand_avg_miss_latency::total 8809.367484 # average overall miss latency |
|
| 472system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency | 506system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency |
| 507system.cpu.dcache.overall_avg_miss_latency::total 8809.367484 # average overall miss latency |
|
| 473system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 2402147500 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1077084130 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 1077084130 # number of WriteReq MSHR miss cycles 505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3479231630 # number of demand (read+write) MSHR miss cycles 506system.cpu.dcache.demand_mshr_miss_latency::total 3479231630 # number of demand (read+write) MSHR miss cycles 507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3479231630 # number of overall MSHR miss cycles 508system.cpu.dcache.overall_mshr_miss_latency::total 3479231630 # number of overall MSHR miss cycles 509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036356 # mshr miss rate for ReadReq accesses | 508system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked 509system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 510system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked 511system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 512system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked 513system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 514system.cpu.dcache.fast_writes 0 # number of fast writes performed 515system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 537system.cpu.dcache.ReadReq_mshr_miss_latency::total 2402147500 # number of ReadReq MSHR miss cycles 538system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1077084130 # number of WriteReq MSHR miss cycles 539system.cpu.dcache.WriteReq_mshr_miss_latency::total 1077084130 # number of WriteReq MSHR miss cycles 540system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3479231630 # number of demand (read+write) MSHR miss cycles 541system.cpu.dcache.demand_mshr_miss_latency::total 3479231630 # number of demand (read+write) MSHR miss cycles 542system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3479231630 # number of overall MSHR miss cycles 543system.cpu.dcache.overall_mshr_miss_latency::total 3479231630 # number of overall MSHR miss cycles 544system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036356 # mshr miss rate for ReadReq accesses |
| 545system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036356 # mshr miss rate for ReadReq accesses |
|
| 510system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009190 # mshr miss rate for WriteReq accesses | 546system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009190 # mshr miss rate for WriteReq accesses |
| 547system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009190 # mshr miss rate for WriteReq accesses |
|
| 511system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for demand accesses | 548system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for demand accesses |
| 549system.cpu.dcache.demand_mshr_miss_rate::total 0.032011 # mshr miss rate for demand accesses |
|
| 512system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for overall accesses | 550system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for overall accesses |
| 551system.cpu.dcache.overall_mshr_miss_rate::total 0.032011 # mshr miss rate for overall accesses |
|
| 513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2656.699127 # average ReadReq mshr miss latency | 552system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2656.699127 # average ReadReq mshr miss latency |
| 553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2656.699127 # average ReadReq mshr miss latency |
|
| 514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24753.157217 # average WriteReq mshr miss latency | 554system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24753.157217 # average WriteReq mshr miss latency |
| 555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24753.157217 # average WriteReq mshr miss latency |
|
| 515system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency | 556system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency |
| 557system.cpu.dcache.demand_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency |
|
| 516system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency | 558system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency |
| 559system.cpu.dcache.overall_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency |
|
| 517system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 518system.cpu.l2cache.replacements 770 # number of replacements 519system.cpu.l2cache.tagsinuse 10017.166349 # Cycle average of tags in use 520system.cpu.l2cache.total_refs 1600694 # Total number of references to valid blocks. 521system.cpu.l2cache.sampled_refs 15595 # Sample count of references to valid blocks. 522system.cpu.l2cache.avg_refs 102.641488 # Average number of references to valid blocks. 523system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 524system.cpu.l2cache.occ_blocks::writebacks 9634.775304 # Average occupied blocks per requestor --- 48 unchanged lines hidden (view full) --- 573system.cpu.l2cache.demand_accesses::cpu.inst 749 # number of demand (read+write) accesses 574system.cpu.l2cache.demand_accesses::cpu.data 947698 # number of demand (read+write) accesses 575system.cpu.l2cache.demand_accesses::total 948447 # number of demand (read+write) accesses 576system.cpu.l2cache.overall_accesses::cpu.inst 749 # number of overall (read+write) accesses 577system.cpu.l2cache.overall_accesses::cpu.data 947698 # number of overall (read+write) accesses 578system.cpu.l2cache.overall_accesses::total 948447 # number of overall (read+write) accesses 579system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963952 # miss rate for ReadReq accesses 580system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000403 # miss rate for ReadReq accesses | 560system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 561system.cpu.l2cache.replacements 770 # number of replacements 562system.cpu.l2cache.tagsinuse 10017.166349 # Cycle average of tags in use 563system.cpu.l2cache.total_refs 1600694 # Total number of references to valid blocks. 564system.cpu.l2cache.sampled_refs 15595 # Sample count of references to valid blocks. 565system.cpu.l2cache.avg_refs 102.641488 # Average number of references to valid blocks. 566system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 567system.cpu.l2cache.occ_blocks::writebacks 9634.775304 # Average occupied blocks per requestor --- 48 unchanged lines hidden (view full) --- 616system.cpu.l2cache.demand_accesses::cpu.inst 749 # number of demand (read+write) accesses 617system.cpu.l2cache.demand_accesses::cpu.data 947698 # number of demand (read+write) accesses 618system.cpu.l2cache.demand_accesses::total 948447 # number of demand (read+write) accesses 619system.cpu.l2cache.overall_accesses::cpu.inst 749 # number of overall (read+write) accesses 620system.cpu.l2cache.overall_accesses::cpu.data 947698 # number of overall (read+write) accesses 621system.cpu.l2cache.overall_accesses::total 948447 # number of overall (read+write) accesses 622system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963952 # miss rate for ReadReq accesses 623system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000403 # miss rate for ReadReq accesses |
| 624system.cpu.l2cache.ReadReq_miss_rate::total 0.001202 # miss rate for ReadReq accesses |
|
| 581system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.325962 # miss rate for ReadExReq accesses | 625system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.325962 # miss rate for ReadExReq accesses |
| 626system.cpu.l2cache.ReadExReq_miss_rate::total 0.325962 # miss rate for ReadExReq accesses |
|
| 582system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963952 # miss rate for demand accesses 583system.cpu.l2cache.demand_miss_rate::cpu.data 0.015720 # miss rate for demand accesses | 627system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963952 # miss rate for demand accesses 628system.cpu.l2cache.demand_miss_rate::cpu.data 0.015720 # miss rate for demand accesses |
| 629system.cpu.l2cache.demand_miss_rate::total 0.016469 # miss rate for demand accesses |
|
| 584system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963952 # miss rate for overall accesses 585system.cpu.l2cache.overall_miss_rate::cpu.data 0.015720 # miss rate for overall accesses | 630system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963952 # miss rate for overall accesses 631system.cpu.l2cache.overall_miss_rate::cpu.data 0.015720 # miss rate for overall accesses |
| 632system.cpu.l2cache.overall_miss_rate::total 0.016469 # miss rate for overall accesses |
|
| 586system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.396122 # average ReadReq miss latency 587system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34262.362637 # average ReadReq miss latency | 633system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.396122 # average ReadReq miss latency 634system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34262.362637 # average ReadReq miss latency |
| 635system.cpu.l2cache.ReadReq_avg_miss_latency::total 34279.005525 # average ReadReq miss latency |
|
| 588system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.380625 # average ReadExReq miss latency | 636system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.380625 # average ReadExReq miss latency |
| 637system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34352.380625 # average ReadExReq miss latency |
|
| 589system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency 590system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency | 638system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency 639system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency |
| 640system.cpu.l2cache.demand_avg_miss_latency::total 34347.279129 # average overall miss latency |
|
| 591system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency 592system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency | 641system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency 642system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency |
| 643system.cpu.l2cache.overall_avg_miss_latency::total 34347.279129 # average overall miss latency |
|
| 593system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 594system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 595system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 596system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 597system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 598system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 599system.cpu.l2cache.fast_writes 0 # number of fast writes performed 600system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 27 unchanged lines hidden (view full) --- 628system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22414000 # number of demand (read+write) MSHR miss cycles 629system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 463107000 # number of demand (read+write) MSHR miss cycles 630system.cpu.l2cache.demand_mshr_miss_latency::total 485521000 # number of demand (read+write) MSHR miss cycles 631system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22414000 # number of overall MSHR miss cycles 632system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463107000 # number of overall MSHR miss cycles 633system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles 634system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses 635system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses | 644system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 645system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 647system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 648system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 649system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu.l2cache.fast_writes 0 # number of fast writes performed 651system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 27 unchanged lines hidden (view full) --- 679system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22414000 # number of demand (read+write) MSHR miss cycles 680system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 463107000 # number of demand (read+write) MSHR miss cycles 681system.cpu.l2cache.demand_mshr_miss_latency::total 485521000 # number of demand (read+write) MSHR miss cycles 682system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22414000 # number of overall MSHR miss cycles 683system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463107000 # number of overall MSHR miss cycles 684system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles 685system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses 686system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses |
| 687system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001190 # mshr miss rate for ReadReq accesses |
|
| 636system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses | 688system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses |
| 689system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.325962 # mshr miss rate for ReadExReq accesses |
|
| 637system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses 638system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses | 690system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses 691system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses |
| 692system.cpu.l2cache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses |
|
| 639system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses 640system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses | 693system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses 694system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses |
| 695system.cpu.l2cache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses |
|
| 641system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency 642system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency | 696system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency 697system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency |
| 698system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31123.141264 # average ReadReq mshr miss latency |
|
| 643system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency | 699system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency |
| 700system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31101.726985 # average ReadExReq mshr miss latency |
|
| 644system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency 645system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency | 701system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency 702system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency |
| 703system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency |
|
| 646system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency 647system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency | 704system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency 705system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency |
| 706system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency |
|
| 648system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 649 650---------- End Simulation Statistics ---------- | 707system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 708 709---------- End Simulation Statistics ---------- |