| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.025989 # Number of seconds simulated 4sim_ticks 25988864000 # Number of ticks simulated 5final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.025989 # Number of seconds simulated 4sim_ticks 25988864000 # Number of ticks simulated 5final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 238212 # Simulator instruction rate (inst/s) 8host_op_rate 239922 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 68332245 # Simulator tick rate (ticks/s) 10host_mem_usage 357212 # Number of bytes of host memory used 11host_seconds 380.33 # Real time elapsed on the host | 7host_inst_rate 71403 # Simulator instruction rate (inst/s) 8host_op_rate 71915 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20482160 # Simulator tick rate (ticks/s) 10host_mem_usage 364344 # Number of bytes of host memory used 11host_seconds 1268.85 # Real time elapsed on the host |
| 12sim_insts 90599356 # Number of instructions simulated 13sim_ops 91249910 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 999040 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 46144 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 2048 # Number of bytes written to this memory 17system.physmem.num_reads 15610 # Number of read requests responded to by this memory 18system.physmem.num_writes 32 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 353 unchanged lines hidden (view full) --- 373system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses 374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency 375system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency 376system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency 377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 90599356 # Number of instructions simulated 13sim_ops 91249910 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 999040 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 46144 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 2048 # Number of bytes written to this memory 17system.physmem.num_reads 15610 # Number of read requests responded to by this memory 18system.physmem.num_writes 32 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 353 unchanged lines hidden (view full) --- 373system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses 374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency 375system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency 376system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency 377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 381system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 382system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 381system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 382system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 383system.cpu.icache.fast_writes 0 # number of fast writes performed 384system.cpu.icache.cache_copies 0 # number of cache copies performed 385system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits 386system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits 387system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits 388system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits 389system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits 390system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits --- 79 unchanged lines hidden (view full) --- 470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency 471system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency 473system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked | 383system.cpu.icache.fast_writes 0 # number of fast writes performed 384system.cpu.icache.cache_copies 0 # number of cache copies performed 385system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits 386system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits 387system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits 388system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits 389system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits 390system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits --- 79 unchanged lines hidden (view full) --- 470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency 471system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency 473system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked |
| 478system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 942908 # number of writebacks 482system.cpu.dcache.writebacks::total 942908 # number of writebacks 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 99918 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 99918 # number of ReadReq MSHR hits 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132542 # number of WriteReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::total 132542 # number of WriteReq MSHR hits --- 102 unchanged lines hidden (view full) --- 589system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency 590system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency 591system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency 592system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency 593system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 594system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 595system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 596system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 942908 # number of writebacks 482system.cpu.dcache.writebacks::total 942908 # number of writebacks 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 99918 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 99918 # number of ReadReq MSHR hits 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132542 # number of WriteReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::total 132542 # number of WriteReq MSHR hits --- 102 unchanged lines hidden (view full) --- 589system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency 590system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency 591system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency 592system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency 593system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 594system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 595system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 596system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 597system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 598system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 597system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 598system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 599system.cpu.l2cache.fast_writes 0 # number of fast writes performed 600system.cpu.l2cache.cache_copies 0 # number of cache copies performed 601system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks 602system.cpu.l2cache.writebacks::total 32 # number of writebacks 603system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 604system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits 605system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits 606system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits --- 44 unchanged lines hidden --- | 599system.cpu.l2cache.fast_writes 0 # number of fast writes performed 600system.cpu.l2cache.cache_copies 0 # number of cache copies performed 601system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks 602system.cpu.l2cache.writebacks::total 32 # number of writebacks 603system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 604system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits 605system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits 606system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits --- 44 unchanged lines hidden --- |