| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.058328 # Number of seconds simulated 4sim_ticks 58328364500 # Number of ticks simulated 5final_tick 58328364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.058675 # Number of seconds simulated 4sim_ticks 58675371500 # Number of ticks simulated 5final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 135523 # Simulator instruction rate (inst/s) 8host_op_rate 136198 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 87259482 # Simulator tick rate (ticks/s) 10host_mem_usage 492508 # Number of bytes of host memory used 11host_seconds 668.45 # Real time elapsed on the host | 7host_inst_rate 111966 # Simulator instruction rate (inst/s) 8host_op_rate 112523 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 72520515 # Simulator tick rate (ticks/s) 10host_mem_usage 490592 # Number of bytes of host memory used 11host_seconds 809.09 # Real time elapsed on the host |
| 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.data 218752 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 921408 # Number of bytes read from this memory 20system.physmem.bytes_read::total 1184896 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.data 218240 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 923072 # Number of bytes read from this memory 20system.physmem.bytes_read::total 1186048 # Number of bytes read from this memory |
| 21system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory | 21system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory |
| 23system.physmem.bytes_written::writebacks 5696 # Number of bytes written to this memory 24system.physmem.bytes_written::total 5696 # Number of bytes written to this memory | 23system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6656 # Number of bytes written to this memory |
| 25system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory | 25system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::cpu.data 3418 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 14397 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 18514 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 89 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 89 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 766968 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 3750354 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 15796911 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 20314233 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 766968 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 766968 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 97654 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 97654 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 97654 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 766968 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 3750354 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 15796911 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 20411887 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 18515 # Number of read requests accepted 45system.physmem.writeReqs 89 # Number of write requests accepted 46system.physmem.readBursts 18515 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 89 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 1179904 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue 50system.physmem.bytesWritten 4480 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 1184960 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 5696 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one | 26system.physmem.num_reads::cpu.data 3410 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 14423 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 18532 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 104 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 762432 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 3719448 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 15731848 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 20213728 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 762432 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 762432 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 113438 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 113438 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 113438 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 762432 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 3719448 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 15731848 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 20327166 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 18533 # Number of read requests accepted 45system.physmem.writeReqs 104 # Number of write requests accepted 46system.physmem.readBursts 18533 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 104 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 1180480 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue 50system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 1186112 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 6656 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one |
| 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 3247 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 3245 # Per bank write bursts |
| 57system.physmem.perBankRdBursts::1 921 # Per bank write bursts | 57system.physmem.perBankRdBursts::1 921 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::2 949 # Per bank write bursts | 58system.physmem.perBankRdBursts::2 952 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::3 1031 # Per bank write bursts | 59system.physmem.perBankRdBursts::3 1031 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::4 1061 # Per bank write bursts 61system.physmem.perBankRdBursts::5 1117 # Per bank write bursts 62system.physmem.perBankRdBursts::6 1095 # Per bank write bursts 63system.physmem.perBankRdBursts::7 1097 # Per bank write bursts | 60system.physmem.perBankRdBursts::4 1065 # Per bank write bursts 61system.physmem.perBankRdBursts::5 1118 # Per bank write bursts 62system.physmem.perBankRdBursts::6 1097 # Per bank write bursts 63system.physmem.perBankRdBursts::7 1096 # Per bank write bursts |
| 64system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 65system.physmem.perBankRdBursts::9 962 # Per bank write bursts 66system.physmem.perBankRdBursts::10 932 # Per bank write bursts 67system.physmem.perBankRdBursts::11 899 # Per bank write bursts | 64system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 65system.physmem.perBankRdBursts::9 962 # Per bank write bursts 66system.physmem.perBankRdBursts::10 932 # Per bank write bursts 67system.physmem.perBankRdBursts::11 899 # Per bank write bursts |
| 68system.physmem.perBankRdBursts::12 902 # Per bank write bursts 69system.physmem.perBankRdBursts::13 896 # Per bank write bursts 70system.physmem.perBankRdBursts::14 1399 # Per bank write bursts 71system.physmem.perBankRdBursts::15 904 # Per bank write bursts | 68system.physmem.perBankRdBursts::12 904 # Per bank write bursts 69system.physmem.perBankRdBursts::13 895 # Per bank write bursts 70system.physmem.perBankRdBursts::14 1401 # Per bank write bursts 71system.physmem.perBankRdBursts::15 903 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::0 0 # Per bank write bursts 73system.physmem.perBankWrBursts::1 0 # Per bank write bursts | 72system.physmem.perBankWrBursts::0 0 # Per bank write bursts 73system.physmem.perBankWrBursts::1 0 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::2 2 # Per bank write bursts 75system.physmem.perBankWrBursts::3 1 # Per bank write bursts 76system.physmem.perBankWrBursts::4 2 # Per bank write bursts 77system.physmem.perBankWrBursts::5 9 # Per bank write bursts 78system.physmem.perBankWrBursts::6 10 # Per bank write bursts 79system.physmem.perBankWrBursts::7 8 # Per bank write bursts 80system.physmem.perBankWrBursts::8 2 # Per bank write bursts | 74system.physmem.perBankWrBursts::2 3 # Per bank write bursts 75system.physmem.perBankWrBursts::3 3 # Per bank write bursts 76system.physmem.perBankWrBursts::4 12 # Per bank write bursts 77system.physmem.perBankWrBursts::5 10 # Per bank write bursts 78system.physmem.perBankWrBursts::6 15 # Per bank write bursts 79system.physmem.perBankWrBursts::7 0 # Per bank write bursts 80system.physmem.perBankWrBursts::8 1 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::9 0 # Per bank write bursts | 81system.physmem.perBankWrBursts::9 0 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::10 3 # Per bank write bursts | 82system.physmem.perBankWrBursts::10 1 # Per bank write bursts |
| 83system.physmem.perBankWrBursts::11 3 # Per bank write bursts | 83system.physmem.perBankWrBursts::11 3 # Per bank write bursts |
| 84system.physmem.perBankWrBursts::12 2 # Per bank write bursts 85system.physmem.perBankWrBursts::13 9 # Per bank write bursts 86system.physmem.perBankWrBursts::14 13 # Per bank write bursts 87system.physmem.perBankWrBursts::15 6 # Per bank write bursts | 84system.physmem.perBankWrBursts::12 5 # Per bank write bursts 85system.physmem.perBankWrBursts::13 12 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7 # Per bank write bursts 87system.physmem.perBankWrBursts::15 0 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 90system.physmem.totGap 58328356000 # Total gap between requests | 90system.physmem.totGap 58675363000 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 18515 # Read request sizes (log2) | 97system.physmem.readPktSize::6 18533 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 89 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 13470 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 2526 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 477 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 104 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 12556 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 3396 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see |
| 108system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see | 108system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see |
| 109system.physmem.rdQLenPdf::4 307 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 310 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 283 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see | 109system.physmem.rdQLenPdf::4 314 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 300 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 296 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 280 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 99 # What read queue length does an incoming req see |
| 115system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see --- 21 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 115system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see --- 21 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 4 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 4 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 4 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 4 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 4 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 4 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 4 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 5 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 5 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 5 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 5 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 5 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 5 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see --- 19 unchanged lines hidden (view full) --- 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 166system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see --- 19 unchanged lines hidden (view full) --- 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 201system.physmem.bytesPerActivate::samples 3107 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 380.704216 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 201.847183 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 402.867268 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 1088 35.02% 35.02% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 865 27.84% 62.86% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 94 3.03% 65.88% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 72 2.32% 68.20% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 65 2.09% 70.29% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 68 2.19% 72.48% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 56 1.80% 74.28% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 51 1.64% 75.93% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 748 24.07% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 3107 # Bytes accessed per row activation | 201system.physmem.bytesPerActivate::samples 2974 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 397.815736 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 217.392167 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 406.651837 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 841 28.28% 28.28% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 992 33.36% 61.63% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 92 3.09% 64.73% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 59 1.98% 66.71% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 59 1.98% 68.70% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 62 2.08% 70.78% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 53 1.78% 72.56% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 59 1.98% 74.55% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 757 25.45% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 2974 # Bytes accessed per row activation |
| 215system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes | 215system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::mean 4608 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::gmean 1496.681558 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::stdev 7484.705695 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::0-511 1 25.00% 25.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::512-1023 1 25.00% 50.00% # Reads before turning the bus around for writes | 216system.physmem.rdPerTurnAround::mean 4542 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::gmean 1434.998534 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::stdev 7438.956513 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes 224system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads | 220system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads |
| 225system.physmem.wrPerTurnAround::mean 17.500000 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::gmean 17.477704 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::16 1 25.00% 25.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::18 3 75.00% 100.00% # Writes before turning the bus around for reads | 224system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads |
| 230system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads | 227system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads |
| 231system.physmem.totQLat 204802662 # Total ticks spent queuing 232system.physmem.totMemAccLat 550477662 # Total ticks spent from burst creation until serviced by the DRAM 233system.physmem.totBusLat 92180000 # Total ticks spent in databus transfers 234system.physmem.avgQLat 11108.84 # Average queueing delay per DRAM burst | 228system.physmem.totQLat 819558662 # Total ticks spent queuing 229system.physmem.totMemAccLat 1165402412 # Total ticks spent from burst creation until serviced by the DRAM 230system.physmem.totBusLat 92225000 # Total ticks spent in databus transfers 231system.physmem.avgQLat 44432.57 # Average queueing delay per DRAM burst |
| 235system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 232system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 236system.physmem.avgMemAccLat 29858.84 # Average memory access latency per DRAM burst 237system.physmem.avgRdBW 20.23 # Average DRAM read bandwidth in MiByte/s | 233system.physmem.avgMemAccLat 63182.57 # Average memory access latency per DRAM burst 234system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s |
| 238system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s | 235system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s |
| 239system.physmem.avgRdBWSys 20.32 # Average system read bandwidth in MiByte/s 240system.physmem.avgWrBWSys 0.10 # Average system write bandwidth in MiByte/s | 236system.physmem.avgRdBWSys 20.21 # Average system read bandwidth in MiByte/s 237system.physmem.avgWrBWSys 0.11 # Average system write bandwidth in MiByte/s |
| 241system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 242system.physmem.busUtil 0.16 # Data bus utilization in percentage 243system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads 244system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 238system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 239system.physmem.busUtil 0.16 # Data bus utilization in percentage 240system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads 241system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 245system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 246system.physmem.avgWrQLen 22.38 # Average write queue length when enqueuing 247system.physmem.readRowHits 15382 # Number of row buffer hits during reads 248system.physmem.writeRowHits 10 # Number of row buffer hits during writes 249system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads 250system.physmem.writeRowHitRate 11.49 # Row buffer hit rate for writes 251system.physmem.avgGap 3135258.87 # Average gap between requests 252system.physmem.pageHitRate 83.10 # Row buffer hit rate, read and write combined 253system.physmem_0.actEnergy 17803800 # Energy for activate commands per rank (pJ) 254system.physmem_0.preEnergy 9714375 # Energy for precharge commands per rank (pJ) 255system.physmem_0.readEnergy 81876600 # Energy for read commands per rank (pJ) 256system.physmem_0.writeEnergy 162000 # Energy for write commands per rank (pJ) 257system.physmem_0.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) 258system.physmem_0.actBackEnergy 6575109030 # Energy for active background per rank (pJ) 259system.physmem_0.preBackEnergy 29228595750 # Energy for precharge background per rank (pJ) 260system.physmem_0.totalEnergy 39722884515 # Total energy per rank (pJ) 261system.physmem_0.averagePower 681.036990 # Core power per rank (mW) 262system.physmem_0.memoryStateTime::IDLE 48583441495 # Time in different power states 263system.physmem_0.memoryStateTime::REF 1947660000 # Time in different power states 264system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 265system.physmem_0.memoryStateTime::ACT 7795971005 # Time in different power states 266system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 267system.physmem_1.actEnergy 5609520 # Energy for activate commands per rank (pJ) 268system.physmem_1.preEnergy 3060750 # Energy for precharge commands per rank (pJ) 269system.physmem_1.readEnergy 61760400 # Energy for read commands per rank (pJ) 270system.physmem_1.writeEnergy 187920 # Energy for write commands per rank (pJ) 271system.physmem_1.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) 272system.physmem_1.actBackEnergy 2425538385 # Energy for active background per rank (pJ) 273system.physmem_1.preBackEnergy 32868570000 # Energy for precharge background per rank (pJ) 274system.physmem_1.totalEnergy 39174349935 # Total energy per rank (pJ) 275system.physmem_1.averagePower 671.632528 # Core power per rank (mW) 276system.physmem_1.memoryStateTime::IDLE 54671634140 # Time in different power states 277system.physmem_1.memoryStateTime::REF 1947660000 # Time in different power states 278system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 279system.physmem_1.memoryStateTime::ACT 1708703360 # Time in different power states 280system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 281system.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states 282system.cpu.branchPred.lookups 28233990 # Number of BP lookups 283system.cpu.branchPred.condPredicted 23266525 # Number of conditional branches predicted 284system.cpu.branchPred.condIncorrect 835401 # Number of conditional branches incorrect 285system.cpu.branchPred.BTBLookups 11829630 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 11747896 # Number of BTB hits | 242system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing 243system.physmem.avgWrQLen 17.01 # Average write queue length when enqueuing 244system.physmem.readRowHits 15523 # Number of row buffer hits during reads 245system.physmem.writeRowHits 12 # Number of row buffer hits during writes 246system.physmem.readRowHitRate 84.16 # Row buffer hit rate for reads 247system.physmem.writeRowHitRate 11.88 # Row buffer hit rate for writes 248system.physmem.avgGap 3148326.61 # Average gap between requests 249system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined 250system.physmem_0.actEnergy 15986460 # Energy for activate commands per rank (pJ) 251system.physmem_0.preEnergy 8481825 # Energy for precharge commands per rank (pJ) 252system.physmem_0.readEnergy 75141360 # Energy for read commands per rank (pJ) 253system.physmem_0.writeEnergy 224460 # Energy for write commands per rank (pJ) 254system.physmem_0.refreshEnergy 1848222480.000000 # Energy for refresh commands per rank (pJ) 255system.physmem_0.actBackEnergy 457291620 # Energy for active background per rank (pJ) 256system.physmem_0.preBackEnergy 99494880 # Energy for precharge background per rank (pJ) 257system.physmem_0.actPowerDownEnergy 3995273070 # Energy for active power-down per rank (pJ) 258system.physmem_0.prePowerDownEnergy 3179264640 # Energy for precharge power-down per rank (pJ) 259system.physmem_0.selfRefreshEnergy 10079734425 # Energy for self refresh per rank (pJ) 260system.physmem_0.totalEnergy 19762775190 # Total energy per rank (pJ) 261system.physmem_0.averagePower 336.815504 # Core power per rank (mW) 262system.physmem_0.totalIdleTime 57405272063 # Total Idle time Per DRAM Rank 263system.physmem_0.memoryStateTime::IDLE 196297250 # Time in different power states 264system.physmem_0.memoryStateTime::REF 786242000 # Time in different power states 265system.physmem_0.memoryStateTime::SREF 40364411250 # Time in different power states 266system.physmem_0.memoryStateTime::PRE_PDN 8279321820 # Time in different power states 267system.physmem_0.memoryStateTime::ACT 287560187 # Time in different power states 268system.physmem_0.memoryStateTime::ACT_PDN 8761538993 # Time in different power states 269system.physmem_1.actEnergy 5305020 # Energy for activate commands per rank (pJ) 270system.physmem_1.preEnergy 2804505 # Energy for precharge commands per rank (pJ) 271system.physmem_1.readEnergy 56548800 # Energy for read commands per rank (pJ) 272system.physmem_1.writeEnergy 151380 # Energy for write commands per rank (pJ) 273system.physmem_1.refreshEnergy 250773120.000000 # Energy for refresh commands per rank (pJ) 274system.physmem_1.actBackEnergy 129702360 # Energy for active background per rank (pJ) 275system.physmem_1.preBackEnergy 13640160 # Energy for precharge background per rank (pJ) 276system.physmem_1.actPowerDownEnergy 769421340 # Energy for active power-down per rank (pJ) 277system.physmem_1.prePowerDownEnergy 250623360 # Energy for precharge power-down per rank (pJ) 278system.physmem_1.selfRefreshEnergy 13483521390 # Energy for self refresh per rank (pJ) 279system.physmem_1.totalEnergy 14962606875 # Total energy per rank (pJ) 280system.physmem_1.averagePower 255.006594 # Core power per rank (mW) 281system.physmem_1.totalIdleTime 58353889098 # Total Idle time Per DRAM Rank 282system.physmem_1.memoryStateTime::IDLE 22210250 # Time in different power states 283system.physmem_1.memoryStateTime::REF 106530000 # Time in different power states 284system.physmem_1.memoryStateTime::SREF 56015166500 # Time in different power states 285system.physmem_1.memoryStateTime::PRE_PDN 652672389 # Time in different power states 286system.physmem_1.memoryStateTime::ACT 191421152 # Time in different power states 287system.physmem_1.memoryStateTime::ACT_PDN 1687371209 # Time in different power states 288system.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 289system.cpu.branchPred.lookups 28234010 # Number of BP lookups 290system.cpu.branchPred.condPredicted 23266490 # Number of conditional branches predicted 291system.cpu.branchPred.condIncorrect 835433 # Number of conditional branches incorrect 292system.cpu.branchPred.BTBLookups 11829728 # Number of BTB lookups 293system.cpu.branchPred.BTBHits 11748003 # Number of BTB hits |
| 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 288system.cpu.branchPred.BTBHitPct 99.309074 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 74550 # Number of times the RAS was used to get a target. | 295system.cpu.branchPred.BTBHitPct 99.309156 # BTB Hit Percentage 296system.cpu.branchPred.usedRAS 74546 # Number of times the RAS was used to get a target. |
| 290system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. | 297system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. |
| 291system.cpu.branchPred.indirectLookups 27225 # Number of indirect predictor lookups. 292system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. 293system.cpu.branchPred.indirectMisses 1747 # Number of indirect misses. | 298system.cpu.branchPred.indirectLookups 27219 # Number of indirect predictor lookups. 299system.cpu.branchPred.indirectHits 25475 # Number of indirect target hits. 300system.cpu.branchPred.indirectMisses 1744 # Number of indirect misses. |
| 294system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. 295system.cpu_clk_domain.clock 500 # Clock period in ticks | 301system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. 302system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 296system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states | 303system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states |
| 297system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 318system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 319system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 320system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 321system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 322system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 323system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 324system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 325system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 326system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states | 333system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states |
| 327system.cpu.dtb.walker.walks 0 # Table walker walks requested 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 348system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 349system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 350system.cpu.dtb.read_accesses 0 # DTB read accesses 351system.cpu.dtb.write_accesses 0 # DTB write accesses 352system.cpu.dtb.inst_accesses 0 # ITB inst accesses 353system.cpu.dtb.hits 0 # DTB hits 354system.cpu.dtb.misses 0 # DTB misses 355system.cpu.dtb.accesses 0 # DTB accesses | 334system.cpu.dtb.walker.walks 0 # Table walker walks requested 335system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.dtb.read_accesses 0 # DTB read accesses 358system.cpu.dtb.write_accesses 0 # DTB write accesses 359system.cpu.dtb.inst_accesses 0 # ITB inst accesses 360system.cpu.dtb.hits 0 # DTB hits 361system.cpu.dtb.misses 0 # DTB misses 362system.cpu.dtb.accesses 0 # DTB accesses |
| 356system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states | 363system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states |
| 357system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 378system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 364system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 385system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 386system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 388system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 389system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 390system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 391system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 392system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 386system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states | 393system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states |
| 387system.cpu.itb.walker.walks 0 # Table walker walks requested 388system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 409system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 410system.cpu.itb.read_accesses 0 # DTB read accesses 411system.cpu.itb.write_accesses 0 # DTB write accesses 412system.cpu.itb.inst_accesses 0 # ITB inst accesses 413system.cpu.itb.hits 0 # DTB hits 414system.cpu.itb.misses 0 # DTB misses 415system.cpu.itb.accesses 0 # DTB accesses 416system.cpu.workload.num_syscalls 442 # Number of system calls | 394system.cpu.itb.walker.walks 0 # Table walker walks requested 395system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 416system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu.itb.read_accesses 0 # DTB read accesses 418system.cpu.itb.write_accesses 0 # DTB write accesses 419system.cpu.itb.inst_accesses 0 # ITB inst accesses 420system.cpu.itb.hits 0 # DTB hits 421system.cpu.itb.misses 0 # DTB misses 422system.cpu.itb.accesses 0 # DTB accesses 423system.cpu.workload.num_syscalls 442 # Number of system calls |
| 417system.cpu.pwrStateResidencyTicks::ON 58328364500 # Cumulative time (in ticks) in various power states 418system.cpu.numCycles 116656730 # number of cpu cycles simulated | 424system.cpu.pwrStateResidencyTicks::ON 58675371500 # Cumulative time (in ticks) in various power states 425system.cpu.numCycles 117350744 # number of cpu cycles simulated |
| 419system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 420system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 426system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 427system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 421system.cpu.fetch.icacheStallCycles 746133 # Number of cycles fetch is stalled on an Icache miss 422system.cpu.fetch.Insts 134907690 # Number of instructions fetch has processed 423system.cpu.fetch.Branches 28233990 # Number of branches that fetch encountered 424system.cpu.fetch.predictedBranches 11847924 # Number of branches that fetch has predicted taken 425system.cpu.fetch.Cycles 115018036 # Number of cycles fetch has run and was not squashing or blocked 426system.cpu.fetch.SquashCycles 1674227 # Number of cycles fetch has spent squashing 427system.cpu.fetch.MiscStallCycles 853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 428system.cpu.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR 429system.cpu.fetch.CacheLines 32275439 # Number of cache lines fetched 430system.cpu.fetch.IcacheSquashes 555 # Number of outstanding Icache misses that were squashed 431system.cpu.fetch.rateDist::samples 116602964 # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.rateDist::mean 1.162155 # Number of instructions fetched each cycle (Total) 433system.cpu.fetch.rateDist::stdev 1.318550 # Number of instructions fetched each cycle (Total) | 428system.cpu.fetch.icacheStallCycles 746331 # Number of cycles fetch is stalled on an Icache miss 429system.cpu.fetch.Insts 134908246 # Number of instructions fetch has processed 430system.cpu.fetch.Branches 28234010 # Number of branches that fetch encountered 431system.cpu.fetch.predictedBranches 11848024 # Number of branches that fetch has predicted taken 432system.cpu.fetch.Cycles 115699810 # Number of cycles fetch has run and was not squashing or blocked 433system.cpu.fetch.SquashCycles 1674291 # Number of cycles fetch has spent squashing 434system.cpu.fetch.MiscStallCycles 849 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 435system.cpu.fetch.IcacheWaitRetryStallCycles 926 # Number of stall cycles due to full MSHR 436system.cpu.fetch.CacheLines 32275670 # Number of cache lines fetched 437system.cpu.fetch.IcacheSquashes 568 # Number of outstanding Icache misses that were squashed 438system.cpu.fetch.rateDist::samples 117285061 # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::mean 1.155401 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::stdev 1.317679 # Number of instructions fetched each cycle (Total) |
| 434system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 441system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 435system.cpu.fetch.rateDist::0 59067374 50.66% 50.66% # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::1 13933709 11.95% 62.61% # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::2 9228635 7.91% 70.52% # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::3 34373246 29.48% 100.00% # Number of instructions fetched each cycle (Total) | 442system.cpu.fetch.rateDist::0 59749210 50.94% 50.94% # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::1 13933958 11.88% 62.82% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::2 9228354 7.87% 70.69% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::3 34373539 29.31% 100.00% # Number of instructions fetched each cycle (Total) |
| 439system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 446system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 442system.cpu.fetch.rateDist::total 116602964 # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.branchRate 0.242026 # Number of branch fetches per cycle 444system.cpu.fetch.rate 1.156450 # Number of inst fetches per cycle 445system.cpu.decode.IdleCycles 8835100 # Number of cycles decode is idle 446system.cpu.decode.BlockedCycles 64368120 # Number of cycles decode is blocked 447system.cpu.decode.RunCycles 33012562 # Number of cycles decode is running 448system.cpu.decode.UnblockCycles 9561783 # Number of cycles decode is unblocking 449system.cpu.decode.SquashCycles 825399 # Number of cycles decode is squashing 450system.cpu.decode.BranchResolved 4097891 # Number of times decode resolved a branch 451system.cpu.decode.BranchMispred 11814 # Number of times decode detected a branch misprediction 452system.cpu.decode.DecodedInsts 114395515 # Number of instructions handled by decode 453system.cpu.decode.SquashedInsts 1985251 # Number of squashed instructions handled by decode 454system.cpu.rename.SquashCycles 825399 # Number of cycles rename is squashing 455system.cpu.rename.IdleCycles 15271601 # Number of cycles rename is idle 456system.cpu.rename.BlockCycles 50089085 # Number of cycles rename is blocking 457system.cpu.rename.serializeStallCycles 110009 # count of cycles rename stalled for serializing inst 458system.cpu.rename.RunCycles 35409630 # Number of cycles rename is running 459system.cpu.rename.UnblockCycles 14897240 # Number of cycles rename is unblocking 460system.cpu.rename.RenamedInsts 110872720 # Number of instructions processed by rename 461system.cpu.rename.SquashedInsts 1412183 # Number of squashed instructions processed by rename 462system.cpu.rename.ROBFullEvents 11133547 # Number of times rename has blocked due to ROB full 463system.cpu.rename.IQFullEvents 1231881 # Number of times rename has blocked due to IQ full 464system.cpu.rename.LQFullEvents 1645196 # Number of times rename has blocked due to LQ full 465system.cpu.rename.SQFullEvents 486344 # Number of times rename has blocked due to SQ full 466system.cpu.rename.RenamedOperands 129945840 # Number of destination operands rename has renamed 467system.cpu.rename.RenameLookups 483153679 # Number of register rename lookups that rename has made 468system.cpu.rename.int_rename_lookups 119447461 # Number of integer rename lookups 469system.cpu.rename.fp_rename_lookups 433 # Number of floating rename lookups | 449system.cpu.fetch.rateDist::total 117285061 # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.branchRate 0.240595 # Number of branch fetches per cycle 451system.cpu.fetch.rate 1.149616 # Number of inst fetches per cycle 452system.cpu.decode.IdleCycles 8835265 # Number of cycles decode is idle 453system.cpu.decode.BlockedCycles 65049836 # Number of cycles decode is blocked 454system.cpu.decode.RunCycles 33012809 # Number of cycles decode is running 455system.cpu.decode.UnblockCycles 9561722 # Number of cycles decode is unblocking 456system.cpu.decode.SquashCycles 825429 # Number of cycles decode is squashing 457system.cpu.decode.BranchResolved 4097911 # Number of times decode resolved a branch 458system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction 459system.cpu.decode.DecodedInsts 114395758 # Number of instructions handled by decode 460system.cpu.decode.SquashedInsts 1985288 # Number of squashed instructions handled by decode 461system.cpu.rename.SquashCycles 825429 # Number of cycles rename is squashing 462system.cpu.rename.IdleCycles 15272092 # Number of cycles rename is idle 463system.cpu.rename.BlockCycles 50298480 # Number of cycles rename is blocking 464system.cpu.rename.serializeStallCycles 112986 # count of cycles rename stalled for serializing inst 465system.cpu.rename.RunCycles 35409562 # Number of cycles rename is running 466system.cpu.rename.UnblockCycles 15366512 # Number of cycles rename is unblocking 467system.cpu.rename.RenamedInsts 110872789 # Number of instructions processed by rename 468system.cpu.rename.SquashedInsts 1412207 # Number of squashed instructions processed by rename 469system.cpu.rename.ROBFullEvents 11133815 # Number of times rename has blocked due to ROB full 470system.cpu.rename.IQFullEvents 1555614 # Number of times rename has blocked due to IQ full 471system.cpu.rename.LQFullEvents 2094363 # Number of times rename has blocked due to LQ full 472system.cpu.rename.SQFullEvents 506230 # Number of times rename has blocked due to SQ full 473system.cpu.rename.RenamedOperands 129945991 # Number of destination operands rename has renamed 474system.cpu.rename.RenameLookups 483154289 # Number of register rename lookups that rename has made 475system.cpu.rename.int_rename_lookups 119447702 # Number of integer rename lookups 476system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups |
| 470system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed | 477system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed |
| 471system.cpu.rename.UndoneMaps 22632921 # Number of HB maps that are undone due to squashing | 478system.cpu.rename.UndoneMaps 22633072 # Number of HB maps that are undone due to squashing |
| 472system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed 473system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed | 479system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed 480system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed |
| 474system.cpu.rename.skidInsts 21513680 # count of insts added to the skid buffer 475system.cpu.memDep0.insertedLoads 26805319 # Number of loads inserted to the mem dependence unit. 476system.cpu.memDep0.insertedStores 5347286 # Number of stores inserted to the mem dependence unit. 477system.cpu.memDep0.conflictingLoads 522469 # Number of conflicting loads. 478system.cpu.memDep0.conflictingStores 256366 # Number of conflicting stores. 479system.cpu.iq.iqInstsAdded 109667529 # Number of instructions added to the IQ (excludes non-spec) | 481system.cpu.rename.skidInsts 21514760 # count of insts added to the skid buffer 482system.cpu.memDep0.insertedLoads 26805262 # Number of loads inserted to the mem dependence unit. 483system.cpu.memDep0.insertedStores 5347320 # Number of stores inserted to the mem dependence unit. 484system.cpu.memDep0.conflictingLoads 521988 # Number of conflicting loads. 485system.cpu.memDep0.conflictingStores 256188 # Number of conflicting stores. 486system.cpu.iq.iqInstsAdded 109667585 # Number of instructions added to the IQ (excludes non-spec) |
| 480system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ | 487system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ |
| 481system.cpu.iq.iqInstsIssued 101366370 # Number of instructions issued 482system.cpu.iq.iqSquashedInstsIssued 1074686 # Number of squashed instructions issued 483system.cpu.iq.iqSquashedInstsExamined 18634782 # Number of squashed instructions iterated over during squash; mainly for profiling 484system.cpu.iq.iqSquashedOperandsExamined 41671490 # Number of squashed operands that are examined and possibly removed from graph | 488system.cpu.iq.iqInstsIssued 101366888 # Number of instructions issued 489system.cpu.iq.iqSquashedInstsIssued 1074694 # Number of squashed instructions issued 490system.cpu.iq.iqSquashedInstsExamined 18634838 # Number of squashed instructions iterated over during squash; mainly for profiling 491system.cpu.iq.iqSquashedOperandsExamined 41670017 # Number of squashed operands that are examined and possibly removed from graph |
| 485system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed | 492system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed |
| 486system.cpu.iq.issued_per_cycle::samples 116602964 # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::mean 0.869329 # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::stdev 0.988911 # Number of insts issued each cycle | 493system.cpu.iq.issued_per_cycle::samples 117285061 # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::mean 0.864278 # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::stdev 0.988233 # Number of insts issued each cycle |
| 489system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 496system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 490system.cpu.iq.issued_per_cycle::0 54969091 47.14% 47.14% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::1 31363076 26.90% 74.04% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::2 22007447 18.87% 92.91% # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::3 7065313 6.06% 98.97% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::4 1197724 1.03% 100.00% # Number of insts issued each cycle | 497system.cpu.iq.issued_per_cycle::0 55650042 47.45% 47.45% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::1 31364266 26.74% 74.19% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::2 22008003 18.76% 92.95% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::3 7064697 6.02% 98.98% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::4 1197740 1.02% 100.00% # Number of insts issued each cycle |
| 495system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 502system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 502system.cpu.iq.issued_per_cycle::total 116602964 # Number of insts issued each cycle | 509system.cpu.iq.issued_per_cycle::total 117285061 # Number of insts issued each cycle |
| 503system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 510system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 504system.cpu.iq.fu_full::IntAlu 9783594 48.67% 48.67% # attempts to use FU when none available | 511system.cpu.iq.fu_full::IntAlu 9783493 48.67% 48.67% # attempts to use FU when none available |
| 505system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available 506system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available 507system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available 508system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available 509system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available 510system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available 511system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available 512system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 525system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available | 512system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available 513system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available 514system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available 515system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available 516system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available 517system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 532system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available |
| 533system.cpu.iq.fu_full::MemRead 9615674 47.83% 96.50% # attempts to use FU when none available 534system.cpu.iq.fu_full::MemWrite 702930 3.50% 100.00% # attempts to use FU when none available | 540system.cpu.iq.fu_full::MemRead 9615894 47.83% 96.50% # attempts to use FU when none available 541system.cpu.iq.fu_full::MemWrite 702925 3.50% 100.00% # attempts to use FU when none available |
| 535system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 536system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 537system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 542system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 543system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 544system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 538system.cpu.iq.FU_type_0::IntAlu 71970691 71.00% 71.00% # Type of FU issued | 545system.cpu.iq.FU_type_0::IntAlu 71970995 71.00% 71.00% # Type of FU issued |
| 539system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued 540system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued 541system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued 542system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued 543system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued 544system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued 545system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued 546system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued --- 8 unchanged lines hidden (view full) --- 555system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued | 546system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued 547system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued 548system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued 549system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued 550system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued 551system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued 552system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued --- 8 unchanged lines hidden (view full) --- 562system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued |
| 563system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 71.01% # Type of FU issued | 570system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued |
| 564system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued | 571system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued |
| 567system.cpu.iq.FU_type_0::MemRead 24337594 24.01% 95.02% # Type of FU issued 568system.cpu.iq.FU_type_0::MemWrite 5047205 4.98% 100.00% # Type of FU issued | 574system.cpu.iq.FU_type_0::MemRead 24337772 24.01% 95.02% # Type of FU issued 575system.cpu.iq.FU_type_0::MemWrite 5047242 4.98% 100.00% # Type of FU issued |
| 569system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 570system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 576system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 577system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 571system.cpu.iq.FU_type_0::total 101366370 # Type of FU issued 572system.cpu.iq.rate 0.868929 # Inst issue rate 573system.cpu.iq.fu_busy_cnt 20102261 # FU busy when requested | 578system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued 579system.cpu.iq.rate 0.863794 # Inst issue rate 580system.cpu.iq.fu_busy_cnt 20102375 # FU busy when requested |
| 574system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) | 581system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) |
| 575system.cpu.iq.int_inst_queue_reads 340512191 # Number of integer instruction queue reads 576system.cpu.iq.int_inst_queue_writes 128311283 # Number of integer instruction queue writes 577system.cpu.iq.int_inst_queue_wakeup_accesses 99607990 # Number of integer instruction queue wakeup accesses 578system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads 579system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes | 582system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads 583system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes 584system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses 585system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads 586system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes |
| 580system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses | 587system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses |
| 581system.cpu.iq.int_alu_accesses 121468392 # Number of integer alu accesses 582system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses 583system.cpu.iew.lsq.thread0.forwLoads 288047 # Number of loads that had data forwarded from stores | 588system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses 589system.cpu.iq.fp_alu_accesses 238 # Number of floating point alu accesses 590system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores |
| 584system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 591system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 585system.cpu.iew.lsq.thread0.squashedLoads 4329408 # Number of loads squashed | 592system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed |
| 586system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed 587system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations | 593system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed 594system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations |
| 588system.cpu.iew.lsq.thread0.squashedStores 602442 # Number of stores squashed | 595system.cpu.iew.lsq.thread0.squashedStores 602476 # Number of stores squashed |
| 589system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 590system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 591system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled | 596system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 597system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 598system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled |
| 592system.cpu.iew.lsq.thread0.cacheBlocked 130712 # Number of times an access to memory failed due to the cache being blocked | 599system.cpu.iew.lsq.thread0.cacheBlocked 130798 # Number of times an access to memory failed due to the cache being blocked |
| 593system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 600system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 594system.cpu.iew.iewSquashCycles 825399 # Number of cycles IEW is squashing 595system.cpu.iew.iewBlockCycles 8206553 # Number of cycles IEW is blocking 596system.cpu.iew.iewUnblockCycles 706266 # Number of cycles IEW is unblocking 597system.cpu.iew.iewDispatchedInsts 109688634 # Number of instructions dispatched to IQ | 601system.cpu.iew.iewSquashCycles 825429 # Number of cycles IEW is squashing 602system.cpu.iew.iewBlockCycles 8290686 # Number of cycles IEW is blocking 603system.cpu.iew.iewUnblockCycles 768265 # Number of cycles IEW is unblocking 604system.cpu.iew.iewDispatchedInsts 109688691 # Number of instructions dispatched to IQ |
| 598system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 605system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 599system.cpu.iew.iewDispLoadInsts 26805319 # Number of dispatched load instructions 600system.cpu.iew.iewDispStoreInsts 5347286 # Number of dispatched store instructions | 606system.cpu.iew.iewDispLoadInsts 26805262 # Number of dispatched load instructions 607system.cpu.iew.iewDispStoreInsts 5347320 # Number of dispatched store instructions |
| 601system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions | 608system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions |
| 602system.cpu.iew.iewIQFullEvents 180569 # Number of times the IQ has become full, causing a stall 603system.cpu.iew.iewLSQFullEvents 362078 # Number of times the LSQ has become full, causing a stall | 609system.cpu.iew.iewIQFullEvents 180386 # Number of times the IQ has become full, causing a stall 610system.cpu.iew.iewLSQFullEvents 424316 # Number of times the LSQ has become full, causing a stall |
| 604system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations | 611system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations |
| 605system.cpu.iew.predictedTakenIncorrect 435086 # Number of branches that were predicted taken incorrectly 606system.cpu.iew.predictedNotTakenIncorrect 412401 # Number of branches that were predicted not taken incorrectly 607system.cpu.iew.branchMispredicts 847487 # Number of branch mispredicts detected at execute 608system.cpu.iew.iewExecutedInsts 100109489 # Number of executed instructions 609system.cpu.iew.iewExecLoadInsts 23802993 # Number of load instructions executed 610system.cpu.iew.iewExecSquashedInsts 1256881 # Number of squashed instructions skipped in execute | 612system.cpu.iew.predictedTakenIncorrect 435090 # Number of branches that were predicted taken incorrectly 613system.cpu.iew.predictedNotTakenIncorrect 412415 # Number of branches that were predicted not taken incorrectly 614system.cpu.iew.branchMispredicts 847505 # Number of branch mispredicts detected at execute 615system.cpu.iew.iewExecutedInsts 100109953 # Number of executed instructions 616system.cpu.iew.iewExecLoadInsts 23803133 # Number of load instructions executed 617system.cpu.iew.iewExecSquashedInsts 1256935 # Number of squashed instructions skipped in execute |
| 611system.cpu.iew.exec_swp 0 # number of swp insts executed | 618system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 612system.cpu.iew.exec_nop 12822 # number of nop insts executed 613system.cpu.iew.exec_refs 28718621 # number of memory reference insts executed 614system.cpu.iew.exec_branches 20621294 # Number of branches executed 615system.cpu.iew.exec_stores 4915628 # Number of stores executed 616system.cpu.iew.exec_rate 0.858154 # Inst execution rate 617system.cpu.iew.wb_sent 99693258 # cumulative count of insts sent to commit 618system.cpu.iew.wb_count 99608103 # cumulative count of insts written-back 619system.cpu.iew.wb_producers 59691284 # num instructions producing a value 620system.cpu.iew.wb_consumers 95529167 # num instructions consuming a value 621system.cpu.iew.wb_rate 0.853856 # insts written-back per cycle 622system.cpu.iew.wb_fanout 0.624849 # average fanout of values written-back 623system.cpu.commit.commitSquashedInsts 17363279 # The number of squashed insts skipped by commit | 619system.cpu.iew.exec_nop 12823 # number of nop insts executed 620system.cpu.iew.exec_refs 28718801 # number of memory reference insts executed 621system.cpu.iew.exec_branches 20621332 # Number of branches executed 622system.cpu.iew.exec_stores 4915668 # Number of stores executed 623system.cpu.iew.exec_rate 0.853083 # Inst execution rate 624system.cpu.iew.wb_sent 99693665 # cumulative count of insts sent to commit 625system.cpu.iew.wb_count 99608516 # cumulative count of insts written-back 626system.cpu.iew.wb_producers 59691499 # num instructions producing a value 627system.cpu.iew.wb_consumers 95528314 # num instructions consuming a value 628system.cpu.iew.wb_rate 0.848810 # insts written-back per cycle 629system.cpu.iew.wb_fanout 0.624857 # average fanout of values written-back 630system.cpu.commit.commitSquashedInsts 17363350 # The number of squashed insts skipped by commit |
| 624system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards | 631system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards |
| 625system.cpu.commit.branchMispredicts 823687 # The number of times a branch was mispredicted 626system.cpu.commit.committed_per_cycle::samples 113915056 # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::mean 0.799312 # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::stdev 1.736114 # Number of insts commited each cycle | 632system.cpu.commit.branchMispredicts 823717 # The number of times a branch was mispredicted 633system.cpu.commit.committed_per_cycle::samples 114597116 # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::mean 0.794554 # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::stdev 1.732042 # Number of insts commited each cycle |
| 629system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 636system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 630system.cpu.commit.committed_per_cycle::0 77490817 68.03% 68.03% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::1 18611366 16.34% 84.36% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::2 7154135 6.28% 90.64% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::3 3469454 3.05% 93.69% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::4 1644903 1.44% 95.13% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::5 541342 0.48% 95.61% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::6 703110 0.62% 96.23% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::7 178773 0.16% 96.38% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::8 4121156 3.62% 100.00% # Number of insts commited each cycle | 637system.cpu.commit.committed_per_cycle::0 78173194 68.22% 68.22% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::1 18611100 16.24% 84.46% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::2 7154015 6.24% 90.70% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::3 3469592 3.03% 93.73% # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::4 1644807 1.44% 95.16% # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::5 541237 0.47% 95.63% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::6 703127 0.61% 96.25% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::7 178794 0.16% 96.40% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::8 4121250 3.60% 100.00% # Number of insts commited each cycle |
| 639system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 646system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 642system.cpu.commit.committed_per_cycle::total 113915056 # Number of insts commited each cycle | 649system.cpu.commit.committed_per_cycle::total 114597116 # Number of insts commited each cycle |
| 643system.cpu.commit.committedInsts 90602408 # Number of instructions committed 644system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed 645system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 646system.cpu.commit.refs 27220755 # Number of memory references committed 647system.cpu.commit.loads 22475911 # Number of loads committed 648system.cpu.commit.membars 3888 # Number of memory barriers committed 649system.cpu.commit.branches 18732305 # Number of branches committed 650system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 680system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 683system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 684system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 687system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction | 650system.cpu.commit.committedInsts 90602408 # Number of instructions committed 651system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed 652system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 653system.cpu.commit.refs 27220755 # Number of memory references committed 654system.cpu.commit.loads 22475911 # Number of loads committed 655system.cpu.commit.membars 3888 # Number of memory barriers committed 656system.cpu.commit.branches 18732305 # Number of branches committed 657system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 687system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 690system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 691system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 692system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 693system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 694system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction |
| 688system.cpu.commit.bw_lim_events 4121156 # number cycles where commit BW limit reached 689system.cpu.rob.rob_reads 218205084 # The number of ROB reads 690system.cpu.rob.rob_writes 219522331 # The number of ROB writes 691system.cpu.timesIdled 576 # Number of times that the entire CPU went into an idle state and unscheduled itself 692system.cpu.idleCycles 53766 # Total number of cycles that the CPU has spent unscheduled due to idling | 695system.cpu.commit.bw_lim_events 4121250 # number cycles where commit BW limit reached 696system.cpu.rob.rob_reads 218887121 # The number of ROB reads 697system.cpu.rob.rob_writes 219522508 # The number of ROB writes 698system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself 699system.cpu.idleCycles 65683 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 693system.cpu.committedInsts 90589799 # Number of Instructions Simulated 694system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated | 700system.cpu.committedInsts 90589799 # Number of Instructions Simulated 701system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated |
| 695system.cpu.cpi 1.287747 # CPI: Cycles Per Instruction 696system.cpu.cpi_total 1.287747 # CPI: Total CPI of All Threads 697system.cpu.ipc 0.776550 # IPC: Instructions Per Cycle 698system.cpu.ipc_total 0.776550 # IPC: Total IPC of All Threads 699system.cpu.int_regfile_reads 108097252 # number of integer regfile reads 700system.cpu.int_regfile_writes 58691902 # number of integer regfile writes | 702system.cpu.cpi 1.295408 # CPI: Cycles Per Instruction 703system.cpu.cpi_total 1.295408 # CPI: Total CPI of All Threads 704system.cpu.ipc 0.771958 # IPC: Instructions Per Cycle 705system.cpu.ipc_total 0.771958 # IPC: Total IPC of All Threads 706system.cpu.int_regfile_reads 108097860 # number of integer regfile reads 707system.cpu.int_regfile_writes 58692141 # number of integer regfile writes |
| 701system.cpu.fp_regfile_reads 58 # number of floating regfile reads 702system.cpu.fp_regfile_writes 93 # number of floating regfile writes | 708system.cpu.fp_regfile_reads 58 # number of floating regfile reads 709system.cpu.fp_regfile_writes 93 # number of floating regfile writes |
| 703system.cpu.cc_regfile_reads 369002875 # number of cc regfile reads 704system.cpu.cc_regfile_writes 58686679 # number of cc regfile writes 705system.cpu.misc_regfile_reads 28409649 # number of misc regfile reads | 710system.cpu.cc_regfile_reads 369004584 # number of cc regfile reads 711system.cpu.cc_regfile_writes 58686965 # number of cc regfile writes 712system.cpu.misc_regfile_reads 28409767 # number of misc regfile reads |
| 706system.cpu.misc_regfile_writes 7784 # number of misc regfile writes | 713system.cpu.misc_regfile_writes 7784 # number of misc regfile writes |
| 707system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states 708system.cpu.dcache.tags.replacements 5470636 # number of replacements 709system.cpu.dcache.tags.tagsinuse 511.779483 # Cycle average of tags in use 710system.cpu.dcache.tags.total_refs 18249262 # Total number of references to valid blocks. 711system.cpu.dcache.tags.sampled_refs 5471148 # Sample count of references to valid blocks. 712system.cpu.dcache.tags.avg_refs 3.335545 # Average number of references to valid blocks. 713system.cpu.dcache.tags.warmup_cycle 36545500 # Cycle when the warmup percentage was hit. 714system.cpu.dcache.tags.occ_blocks::cpu.data 511.779483 # Average occupied blocks per requestor 715system.cpu.dcache.tags.occ_percent::cpu.data 0.999569 # Average percentage of cache occupancy 716system.cpu.dcache.tags.occ_percent::total 0.999569 # Average percentage of cache occupancy | 714system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 715system.cpu.dcache.tags.replacements 5470621 # number of replacements 716system.cpu.dcache.tags.tagsinuse 511.769293 # Cycle average of tags in use 717system.cpu.dcache.tags.total_refs 18249382 # Total number of references to valid blocks. 718system.cpu.dcache.tags.sampled_refs 5471133 # Sample count of references to valid blocks. 719system.cpu.dcache.tags.avg_refs 3.335576 # Average number of references to valid blocks. 720system.cpu.dcache.tags.warmup_cycle 38111500 # Cycle when the warmup percentage was hit. 721system.cpu.dcache.tags.occ_blocks::cpu.data 511.769293 # Average occupied blocks per requestor 722system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy 723system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy |
| 717system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 724system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 718system.cpu.dcache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id 719system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id | 725system.cpu.dcache.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id 726system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id |
| 720system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 727system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 721system.cpu.dcache.tags.tag_accesses 61906894 # Number of tag accesses 722system.cpu.dcache.tags.data_accesses 61906894 # Number of data accesses 723system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states 724system.cpu.dcache.ReadReq_hits::cpu.data 13887138 # number of ReadReq hits 725system.cpu.dcache.ReadReq_hits::total 13887138 # number of ReadReq hits 726system.cpu.dcache.WriteReq_hits::cpu.data 4353836 # number of WriteReq hits 727system.cpu.dcache.WriteReq_hits::total 4353836 # number of WriteReq hits | 728system.cpu.dcache.tags.tag_accesses 61907171 # Number of tag accesses 729system.cpu.dcache.tags.data_accesses 61907171 # Number of data accesses 730system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 731system.cpu.dcache.ReadReq_hits::cpu.data 13887260 # number of ReadReq hits 732system.cpu.dcache.ReadReq_hits::total 13887260 # number of ReadReq hits 733system.cpu.dcache.WriteReq_hits::cpu.data 4353834 # number of WriteReq hits 734system.cpu.dcache.WriteReq_hits::total 4353834 # number of WriteReq hits |
| 728system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 729system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 730system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits 731system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits 732system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 733system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits | 735system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 736system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 737system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits 738system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits 739system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 740system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits |
| 734system.cpu.dcache.demand_hits::cpu.data 18240974 # number of demand (read+write) hits 735system.cpu.dcache.demand_hits::total 18240974 # number of demand (read+write) hits 736system.cpu.dcache.overall_hits::cpu.data 18241496 # number of overall hits 737system.cpu.dcache.overall_hits::total 18241496 # number of overall hits 738system.cpu.dcache.ReadReq_misses::cpu.data 9587451 # number of ReadReq misses 739system.cpu.dcache.ReadReq_misses::total 9587451 # number of ReadReq misses 740system.cpu.dcache.WriteReq_misses::cpu.data 381145 # number of WriteReq misses 741system.cpu.dcache.WriteReq_misses::total 381145 # number of WriteReq misses | 741system.cpu.dcache.demand_hits::cpu.data 18241094 # number of demand (read+write) hits 742system.cpu.dcache.demand_hits::total 18241094 # number of demand (read+write) hits 743system.cpu.dcache.overall_hits::cpu.data 18241616 # number of overall hits 744system.cpu.dcache.overall_hits::total 18241616 # number of overall hits 745system.cpu.dcache.ReadReq_misses::cpu.data 9587475 # number of ReadReq misses 746system.cpu.dcache.ReadReq_misses::total 9587475 # number of ReadReq misses 747system.cpu.dcache.WriteReq_misses::cpu.data 381147 # number of WriteReq misses 748system.cpu.dcache.WriteReq_misses::total 381147 # number of WriteReq misses |
| 742system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses 743system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses 744system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses 745system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses | 749system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses 750system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses 751system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses 752system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses |
| 746system.cpu.dcache.demand_misses::cpu.data 9968596 # number of demand (read+write) misses 747system.cpu.dcache.demand_misses::total 9968596 # number of demand (read+write) misses 748system.cpu.dcache.overall_misses::cpu.data 9968603 # number of overall misses 749system.cpu.dcache.overall_misses::total 9968603 # number of overall misses 750system.cpu.dcache.ReadReq_miss_latency::cpu.data 88929958000 # number of ReadReq miss cycles 751system.cpu.dcache.ReadReq_miss_latency::total 88929958000 # number of ReadReq miss cycles 752system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000514273 # number of WriteReq miss cycles 753system.cpu.dcache.WriteReq_miss_latency::total 4000514273 # number of WriteReq miss cycles 754system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 284000 # number of LoadLockedReq miss cycles 755system.cpu.dcache.LoadLockedReq_miss_latency::total 284000 # number of LoadLockedReq miss cycles 756system.cpu.dcache.demand_miss_latency::cpu.data 92930472273 # number of demand (read+write) miss cycles 757system.cpu.dcache.demand_miss_latency::total 92930472273 # number of demand (read+write) miss cycles 758system.cpu.dcache.overall_miss_latency::cpu.data 92930472273 # number of overall miss cycles 759system.cpu.dcache.overall_miss_latency::total 92930472273 # number of overall miss cycles 760system.cpu.dcache.ReadReq_accesses::cpu.data 23474589 # number of ReadReq accesses(hits+misses) 761system.cpu.dcache.ReadReq_accesses::total 23474589 # number of ReadReq accesses(hits+misses) | 753system.cpu.dcache.demand_misses::cpu.data 9968622 # number of demand (read+write) misses 754system.cpu.dcache.demand_misses::total 9968622 # number of demand (read+write) misses 755system.cpu.dcache.overall_misses::cpu.data 9968629 # number of overall misses 756system.cpu.dcache.overall_misses::total 9968629 # number of overall misses 757system.cpu.dcache.ReadReq_miss_latency::cpu.data 89371349000 # number of ReadReq miss cycles 758system.cpu.dcache.ReadReq_miss_latency::total 89371349000 # number of ReadReq miss cycles 759system.cpu.dcache.WriteReq_miss_latency::cpu.data 4092576700 # number of WriteReq miss cycles 760system.cpu.dcache.WriteReq_miss_latency::total 4092576700 # number of WriteReq miss cycles 761system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles 762system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles 763system.cpu.dcache.demand_miss_latency::cpu.data 93463925700 # number of demand (read+write) miss cycles 764system.cpu.dcache.demand_miss_latency::total 93463925700 # number of demand (read+write) miss cycles 765system.cpu.dcache.overall_miss_latency::cpu.data 93463925700 # number of overall miss cycles 766system.cpu.dcache.overall_miss_latency::total 93463925700 # number of overall miss cycles 767system.cpu.dcache.ReadReq_accesses::cpu.data 23474735 # number of ReadReq accesses(hits+misses) 768system.cpu.dcache.ReadReq_accesses::total 23474735 # number of ReadReq accesses(hits+misses) |
| 762system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 763system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 764system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) 765system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) 766system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 767system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 768system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 769system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) | 769system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 770system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 771system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) 772system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) 773system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 774system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 775system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 776system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) |
| 770system.cpu.dcache.demand_accesses::cpu.data 28209570 # number of demand (read+write) accesses 771system.cpu.dcache.demand_accesses::total 28209570 # number of demand (read+write) accesses 772system.cpu.dcache.overall_accesses::cpu.data 28210099 # number of overall (read+write) accesses 773system.cpu.dcache.overall_accesses::total 28210099 # number of overall (read+write) accesses 774system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408418 # miss rate for ReadReq accesses 775system.cpu.dcache.ReadReq_miss_rate::total 0.408418 # miss rate for ReadReq accesses | 777system.cpu.dcache.demand_accesses::cpu.data 28209716 # number of demand (read+write) accesses 778system.cpu.dcache.demand_accesses::total 28209716 # number of demand (read+write) accesses 779system.cpu.dcache.overall_accesses::cpu.data 28210245 # number of overall (read+write) accesses 780system.cpu.dcache.overall_accesses::total 28210245 # number of overall (read+write) accesses 781system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408417 # miss rate for ReadReq accesses 782system.cpu.dcache.ReadReq_miss_rate::total 0.408417 # miss rate for ReadReq accesses |
| 776system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses 777system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses 778system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses 779system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses 780system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses 781system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses | 783system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses 784system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses 785system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses 786system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses 787system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses 788system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses |
| 782system.cpu.dcache.demand_miss_rate::cpu.data 0.353376 # miss rate for demand accesses 783system.cpu.dcache.demand_miss_rate::total 0.353376 # miss rate for demand accesses 784system.cpu.dcache.overall_miss_rate::cpu.data 0.353370 # miss rate for overall accesses 785system.cpu.dcache.overall_miss_rate::total 0.353370 # miss rate for overall accesses 786system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9275.662322 # average ReadReq miss latency 787system.cpu.dcache.ReadReq_avg_miss_latency::total 9275.662322 # average ReadReq miss latency 788system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10496.042905 # average WriteReq miss latency 789system.cpu.dcache.WriteReq_avg_miss_latency::total 10496.042905 # average WriteReq miss latency 790system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20285.714286 # average LoadLockedReq miss latency 791system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20285.714286 # average LoadLockedReq miss latency 792system.cpu.dcache.demand_avg_miss_latency::cpu.data 9322.323051 # average overall miss latency 793system.cpu.dcache.demand_avg_miss_latency::total 9322.323051 # average overall miss latency 794system.cpu.dcache.overall_avg_miss_latency::cpu.data 9322.316504 # average overall miss latency 795system.cpu.dcache.overall_avg_miss_latency::total 9322.316504 # average overall miss latency 796system.cpu.dcache.blocked_cycles::no_mshrs 330469 # number of cycles access was blocked 797system.cpu.dcache.blocked_cycles::no_targets 108734 # number of cycles access was blocked 798system.cpu.dcache.blocked::no_mshrs 121517 # number of cycles access was blocked 799system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked 800system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.719529 # average number of cycles each access was blocked 801system.cpu.dcache.avg_blocked_cycles::no_targets 8.469699 # average number of cycles each access was blocked 802system.cpu.dcache.writebacks::writebacks 5470636 # number of writebacks 803system.cpu.dcache.writebacks::total 5470636 # number of writebacks 804system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338792 # number of ReadReq MSHR hits 805system.cpu.dcache.ReadReq_mshr_hits::total 4338792 # number of ReadReq MSHR hits 806system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158657 # number of WriteReq MSHR hits 807system.cpu.dcache.WriteReq_mshr_hits::total 158657 # number of WriteReq MSHR hits | 789system.cpu.dcache.demand_miss_rate::cpu.data 0.353375 # miss rate for demand accesses 790system.cpu.dcache.demand_miss_rate::total 0.353375 # miss rate for demand accesses 791system.cpu.dcache.overall_miss_rate::cpu.data 0.353369 # miss rate for overall accesses 792system.cpu.dcache.overall_miss_rate::total 0.353369 # miss rate for overall accesses 793system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9321.677397 # average ReadReq miss latency 794system.cpu.dcache.ReadReq_avg_miss_latency::total 9321.677397 # average ReadReq miss latency 795system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303 # average WriteReq miss latency 796system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303 # average WriteReq miss latency 797system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency 798system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency 799system.cpu.dcache.demand_avg_miss_latency::cpu.data 9375.811993 # average overall miss latency 800system.cpu.dcache.demand_avg_miss_latency::total 9375.811993 # average overall miss latency 801system.cpu.dcache.overall_avg_miss_latency::cpu.data 9375.805409 # average overall miss latency 802system.cpu.dcache.overall_avg_miss_latency::total 9375.805409 # average overall miss latency 803system.cpu.dcache.blocked_cycles::no_mshrs 331977 # number of cycles access was blocked 804system.cpu.dcache.blocked_cycles::no_targets 129797 # number of cycles access was blocked 805system.cpu.dcache.blocked::no_mshrs 121610 # number of cycles access was blocked 806system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked 807system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.729850 # average number of cycles each access was blocked 808system.cpu.dcache.avg_blocked_cycles::no_targets 10.108801 # average number of cycles each access was blocked 809system.cpu.dcache.writebacks::writebacks 5470621 # number of writebacks 810system.cpu.dcache.writebacks::total 5470621 # number of writebacks 811system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338830 # number of ReadReq MSHR hits 812system.cpu.dcache.ReadReq_mshr_hits::total 4338830 # number of ReadReq MSHR hits 813system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158660 # number of WriteReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::total 158660 # number of WriteReq MSHR hits |
| 808system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits 809system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits | 815system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits 816system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits |
| 810system.cpu.dcache.demand_mshr_hits::cpu.data 4497449 # number of demand (read+write) MSHR hits 811system.cpu.dcache.demand_mshr_hits::total 4497449 # number of demand (read+write) MSHR hits 812system.cpu.dcache.overall_mshr_hits::cpu.data 4497449 # number of overall MSHR hits 813system.cpu.dcache.overall_mshr_hits::total 4497449 # number of overall MSHR hits 814system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248659 # number of ReadReq MSHR misses 815system.cpu.dcache.ReadReq_mshr_misses::total 5248659 # number of ReadReq MSHR misses 816system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222488 # number of WriteReq MSHR misses 817system.cpu.dcache.WriteReq_mshr_misses::total 222488 # number of WriteReq MSHR misses | 817system.cpu.dcache.demand_mshr_hits::cpu.data 4497490 # number of demand (read+write) MSHR hits 818system.cpu.dcache.demand_mshr_hits::total 4497490 # number of demand (read+write) MSHR hits 819system.cpu.dcache.overall_mshr_hits::cpu.data 4497490 # number of overall MSHR hits 820system.cpu.dcache.overall_mshr_hits::total 4497490 # number of overall MSHR hits 821system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248645 # number of ReadReq MSHR misses 822system.cpu.dcache.ReadReq_mshr_misses::total 5248645 # number of ReadReq MSHR misses 823system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses 824system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses |
| 818system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses 819system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses | 825system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses 826system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses |
| 820system.cpu.dcache.demand_mshr_misses::cpu.data 5471147 # number of demand (read+write) MSHR misses 821system.cpu.dcache.demand_mshr_misses::total 5471147 # number of demand (read+write) MSHR misses 822system.cpu.dcache.overall_mshr_misses::cpu.data 5471151 # number of overall MSHR misses 823system.cpu.dcache.overall_mshr_misses::total 5471151 # number of overall MSHR misses 824system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43429617000 # number of ReadReq MSHR miss cycles 825system.cpu.dcache.ReadReq_mshr_miss_latency::total 43429617000 # number of ReadReq MSHR miss cycles 826system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285050165 # number of WriteReq MSHR miss cycles 827system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285050165 # number of WriteReq MSHR miss cycles 828system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 217500 # number of SoftPFReq MSHR miss cycles 829system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 217500 # number of SoftPFReq MSHR miss cycles 830system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45714667165 # number of demand (read+write) MSHR miss cycles 831system.cpu.dcache.demand_mshr_miss_latency::total 45714667165 # number of demand (read+write) MSHR miss cycles 832system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45714884665 # number of overall MSHR miss cycles 833system.cpu.dcache.overall_mshr_miss_latency::total 45714884665 # number of overall MSHR miss cycles 834system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses 835system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses | 827system.cpu.dcache.demand_mshr_misses::cpu.data 5471132 # number of demand (read+write) MSHR misses 828system.cpu.dcache.demand_mshr_misses::total 5471132 # number of demand (read+write) MSHR misses 829system.cpu.dcache.overall_mshr_misses::cpu.data 5471136 # number of overall MSHR misses 830system.cpu.dcache.overall_mshr_misses::total 5471136 # number of overall MSHR misses 831system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817219500 # number of ReadReq MSHR miss cycles 832system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817219500 # number of ReadReq MSHR miss cycles 833system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2296823105 # number of WriteReq MSHR miss cycles 834system.cpu.dcache.WriteReq_mshr_miss_latency::total 2296823105 # number of WriteReq MSHR miss cycles 835system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles 836system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles 837system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46114042605 # number of demand (read+write) MSHR miss cycles 838system.cpu.dcache.demand_mshr_miss_latency::total 46114042605 # number of demand (read+write) MSHR miss cycles 839system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46114278105 # number of overall MSHR miss cycles 840system.cpu.dcache.overall_mshr_miss_latency::total 46114278105 # number of overall MSHR miss cycles 841system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223587 # mshr miss rate for ReadReq accesses 842system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223587 # mshr miss rate for ReadReq accesses |
| 836system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses 837system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses 838system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses 839system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses | 843system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses 844system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses 845system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses 846system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses |
| 840system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses 841system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses 842system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses 843system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses 844system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8274.421524 # average ReadReq mshr miss latency 845system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8274.421524 # average ReadReq mshr miss latency 846system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.442294 # average WriteReq mshr miss latency 847system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.442294 # average WriteReq mshr miss latency 848system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54375 # average SoftPFReq mshr miss latency 849system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54375 # average SoftPFReq mshr miss latency 850system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8355.591097 # average overall mshr miss latency 851system.cpu.dcache.demand_avg_mshr_miss_latency::total 8355.591097 # average overall mshr miss latency 852system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8355.624742 # average overall mshr miss latency 853system.cpu.dcache.overall_avg_mshr_miss_latency::total 8355.624742 # average overall mshr miss latency 854system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states 855system.cpu.icache.tags.replacements 447 # number of replacements 856system.cpu.icache.tags.tagsinuse 427.481000 # Cycle average of tags in use 857system.cpu.icache.tags.total_refs 32274286 # Total number of references to valid blocks. 858system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. 859system.cpu.icache.tags.avg_refs 35701.643805 # Average number of references to valid blocks. | 847system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193945 # mshr miss rate for demand accesses 848system.cpu.dcache.demand_mshr_miss_rate::total 0.193945 # mshr miss rate for demand accesses 849system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193941 # mshr miss rate for overall accesses 850system.cpu.dcache.overall_mshr_miss_rate::total 0.193941 # mshr miss rate for overall accesses 851system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.291702 # average ReadReq mshr miss latency 852system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.291702 # average ReadReq mshr miss latency 853system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10323.403637 # average WriteReq mshr miss latency 854system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10323.403637 # average WriteReq mshr miss latency 855system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency 856system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency 857system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8428.610862 # average overall mshr miss latency 858system.cpu.dcache.demand_avg_mshr_miss_latency::total 8428.610862 # average overall mshr miss latency 859system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8428.647744 # average overall mshr miss latency 860system.cpu.dcache.overall_avg_mshr_miss_latency::total 8428.647744 # average overall mshr miss latency 861system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 862system.cpu.icache.tags.replacements 448 # number of replacements 863system.cpu.icache.tags.tagsinuse 427.600534 # Cycle average of tags in use 864system.cpu.icache.tags.total_refs 32274508 # Total number of references to valid blocks. 865system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. 866system.cpu.icache.tags.avg_refs 35623.077263 # Average number of references to valid blocks. |
| 860system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 867system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 861system.cpu.icache.tags.occ_blocks::cpu.inst 427.481000 # Average occupied blocks per requestor 862system.cpu.icache.tags.occ_percent::cpu.inst 0.834924 # Average percentage of cache occupancy 863system.cpu.icache.tags.occ_percent::total 0.834924 # Average percentage of cache occupancy 864system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id | 868system.cpu.icache.tags.occ_blocks::cpu.inst 427.600534 # Average occupied blocks per requestor 869system.cpu.icache.tags.occ_percent::cpu.inst 0.835157 # Average percentage of cache occupancy 870system.cpu.icache.tags.occ_percent::total 0.835157 # Average percentage of cache occupancy 871system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id |
| 865system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 866system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id | 872system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 873system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id |
| 867system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id | 874system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id |
| 868system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id | 875system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id |
| 869system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id 870system.cpu.icache.tags.tag_accesses 64551760 # Number of tag accesses 871system.cpu.icache.tags.data_accesses 64551760 # Number of data accesses 872system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states 873system.cpu.icache.ReadReq_hits::cpu.inst 32274286 # number of ReadReq hits 874system.cpu.icache.ReadReq_hits::total 32274286 # number of ReadReq hits 875system.cpu.icache.demand_hits::cpu.inst 32274286 # number of demand (read+write) hits 876system.cpu.icache.demand_hits::total 32274286 # number of demand (read+write) hits 877system.cpu.icache.overall_hits::cpu.inst 32274286 # number of overall hits 878system.cpu.icache.overall_hits::total 32274286 # number of overall hits 879system.cpu.icache.ReadReq_misses::cpu.inst 1142 # number of ReadReq misses 880system.cpu.icache.ReadReq_misses::total 1142 # number of ReadReq misses 881system.cpu.icache.demand_misses::cpu.inst 1142 # number of demand (read+write) misses 882system.cpu.icache.demand_misses::total 1142 # number of demand (read+write) misses 883system.cpu.icache.overall_misses::cpu.inst 1142 # number of overall misses 884system.cpu.icache.overall_misses::total 1142 # number of overall misses 885system.cpu.icache.ReadReq_miss_latency::cpu.inst 61976480 # number of ReadReq miss cycles 886system.cpu.icache.ReadReq_miss_latency::total 61976480 # number of ReadReq miss cycles 887system.cpu.icache.demand_miss_latency::cpu.inst 61976480 # number of demand (read+write) miss cycles 888system.cpu.icache.demand_miss_latency::total 61976480 # number of demand (read+write) miss cycles 889system.cpu.icache.overall_miss_latency::cpu.inst 61976480 # number of overall miss cycles 890system.cpu.icache.overall_miss_latency::total 61976480 # number of overall miss cycles 891system.cpu.icache.ReadReq_accesses::cpu.inst 32275428 # number of ReadReq accesses(hits+misses) 892system.cpu.icache.ReadReq_accesses::total 32275428 # number of ReadReq accesses(hits+misses) 893system.cpu.icache.demand_accesses::cpu.inst 32275428 # number of demand (read+write) accesses 894system.cpu.icache.demand_accesses::total 32275428 # number of demand (read+write) accesses 895system.cpu.icache.overall_accesses::cpu.inst 32275428 # number of overall (read+write) accesses 896system.cpu.icache.overall_accesses::total 32275428 # number of overall (read+write) accesses 897system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses 898system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses 899system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses 900system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses 901system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses 902system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses 903system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54270.122592 # average ReadReq miss latency 904system.cpu.icache.ReadReq_avg_miss_latency::total 54270.122592 # average ReadReq miss latency 905system.cpu.icache.demand_avg_miss_latency::cpu.inst 54270.122592 # average overall miss latency 906system.cpu.icache.demand_avg_miss_latency::total 54270.122592 # average overall miss latency 907system.cpu.icache.overall_avg_miss_latency::cpu.inst 54270.122592 # average overall miss latency 908system.cpu.icache.overall_avg_miss_latency::total 54270.122592 # average overall miss latency 909system.cpu.icache.blocked_cycles::no_mshrs 19008 # number of cycles access was blocked 910system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked 911system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked 912system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 913system.cpu.icache.avg_blocked_cycles::no_mshrs 86.794521 # average number of cycles each access was blocked 914system.cpu.icache.avg_blocked_cycles::no_targets 29.600000 # average number of cycles each access was blocked 915system.cpu.icache.writebacks::writebacks 447 # number of writebacks 916system.cpu.icache.writebacks::total 447 # number of writebacks 917system.cpu.icache.ReadReq_mshr_hits::cpu.inst 237 # number of ReadReq MSHR hits 918system.cpu.icache.ReadReq_mshr_hits::total 237 # number of ReadReq MSHR hits 919system.cpu.icache.demand_mshr_hits::cpu.inst 237 # number of demand (read+write) MSHR hits 920system.cpu.icache.demand_mshr_hits::total 237 # number of demand (read+write) MSHR hits 921system.cpu.icache.overall_mshr_hits::cpu.inst 237 # number of overall MSHR hits 922system.cpu.icache.overall_mshr_hits::total 237 # number of overall MSHR hits 923system.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses 924system.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses 925system.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses 926system.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses 927system.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses 928system.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses 929system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50842984 # number of ReadReq MSHR miss cycles 930system.cpu.icache.ReadReq_mshr_miss_latency::total 50842984 # number of ReadReq MSHR miss cycles 931system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50842984 # number of demand (read+write) MSHR miss cycles 932system.cpu.icache.demand_mshr_miss_latency::total 50842984 # number of demand (read+write) MSHR miss cycles 933system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50842984 # number of overall MSHR miss cycles 934system.cpu.icache.overall_mshr_miss_latency::total 50842984 # number of overall MSHR miss cycles | 876system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id 877system.cpu.icache.tags.tag_accesses 64552224 # Number of tag accesses 878system.cpu.icache.tags.data_accesses 64552224 # Number of data accesses 879system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 880system.cpu.icache.ReadReq_hits::cpu.inst 32274508 # number of ReadReq hits 881system.cpu.icache.ReadReq_hits::total 32274508 # number of ReadReq hits 882system.cpu.icache.demand_hits::cpu.inst 32274508 # number of demand (read+write) hits 883system.cpu.icache.demand_hits::total 32274508 # number of demand (read+write) hits 884system.cpu.icache.overall_hits::cpu.inst 32274508 # number of overall hits 885system.cpu.icache.overall_hits::total 32274508 # number of overall hits 886system.cpu.icache.ReadReq_misses::cpu.inst 1151 # number of ReadReq misses 887system.cpu.icache.ReadReq_misses::total 1151 # number of ReadReq misses 888system.cpu.icache.demand_misses::cpu.inst 1151 # number of demand (read+write) misses 889system.cpu.icache.demand_misses::total 1151 # number of demand (read+write) misses 890system.cpu.icache.overall_misses::cpu.inst 1151 # number of overall misses 891system.cpu.icache.overall_misses::total 1151 # number of overall misses 892system.cpu.icache.ReadReq_miss_latency::cpu.inst 79113980 # number of ReadReq miss cycles 893system.cpu.icache.ReadReq_miss_latency::total 79113980 # number of ReadReq miss cycles 894system.cpu.icache.demand_miss_latency::cpu.inst 79113980 # number of demand (read+write) miss cycles 895system.cpu.icache.demand_miss_latency::total 79113980 # number of demand (read+write) miss cycles 896system.cpu.icache.overall_miss_latency::cpu.inst 79113980 # number of overall miss cycles 897system.cpu.icache.overall_miss_latency::total 79113980 # number of overall miss cycles 898system.cpu.icache.ReadReq_accesses::cpu.inst 32275659 # number of ReadReq accesses(hits+misses) 899system.cpu.icache.ReadReq_accesses::total 32275659 # number of ReadReq accesses(hits+misses) 900system.cpu.icache.demand_accesses::cpu.inst 32275659 # number of demand (read+write) accesses 901system.cpu.icache.demand_accesses::total 32275659 # number of demand (read+write) accesses 902system.cpu.icache.overall_accesses::cpu.inst 32275659 # number of overall (read+write) accesses 903system.cpu.icache.overall_accesses::total 32275659 # number of overall (read+write) accesses 904system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses 905system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses 906system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses 907system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses 908system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses 909system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses 910system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68734.995656 # average ReadReq miss latency 911system.cpu.icache.ReadReq_avg_miss_latency::total 68734.995656 # average ReadReq miss latency 912system.cpu.icache.demand_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency 913system.cpu.icache.demand_avg_miss_latency::total 68734.995656 # average overall miss latency 914system.cpu.icache.overall_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency 915system.cpu.icache.overall_avg_miss_latency::total 68734.995656 # average overall miss latency 916system.cpu.icache.blocked_cycles::no_mshrs 21173 # number of cycles access was blocked 917system.cpu.icache.blocked_cycles::no_targets 759 # number of cycles access was blocked 918system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked 919system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked 920system.cpu.icache.avg_blocked_cycles::no_mshrs 94.102222 # average number of cycles each access was blocked 921system.cpu.icache.avg_blocked_cycles::no_targets 126.500000 # average number of cycles each access was blocked 922system.cpu.icache.writebacks::writebacks 448 # number of writebacks 923system.cpu.icache.writebacks::total 448 # number of writebacks 924system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits 925system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits 926system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits 927system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits 928system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits 929system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits 930system.cpu.icache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses 931system.cpu.icache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses 932system.cpu.icache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses 933system.cpu.icache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses 934system.cpu.icache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses 935system.cpu.icache.overall_mshr_misses::total 907 # number of overall MSHR misses 936system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60405484 # number of ReadReq MSHR miss cycles 937system.cpu.icache.ReadReq_mshr_miss_latency::total 60405484 # number of ReadReq MSHR miss cycles 938system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60405484 # number of demand (read+write) MSHR miss cycles 939system.cpu.icache.demand_mshr_miss_latency::total 60405484 # number of demand (read+write) MSHR miss cycles 940system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60405484 # number of overall MSHR miss cycles 941system.cpu.icache.overall_mshr_miss_latency::total 60405484 # number of overall MSHR miss cycles |
| 935system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 936system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 937system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 938system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 939system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 940system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses | 942system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 943system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 944system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 945system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 946system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 947system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses |
| 941system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56180.092818 # average ReadReq mshr miss latency 942system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56180.092818 # average ReadReq mshr miss latency 943system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56180.092818 # average overall mshr miss latency 944system.cpu.icache.demand_avg_mshr_miss_latency::total 56180.092818 # average overall mshr miss latency 945system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56180.092818 # average overall mshr miss latency 946system.cpu.icache.overall_avg_mshr_miss_latency::total 56180.092818 # average overall mshr miss latency 947system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states 948system.cpu.l2cache.prefetcher.num_hwpf_issued 4982437 # number of hwpf issued 949system.cpu.l2cache.prefetcher.pfIdentified 5296601 # number of prefetch candidates identified 950system.cpu.l2cache.prefetcher.pfBufferHit 273114 # number of redundant prefetches already in prefetch queue | 948system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66599.210584 # average ReadReq mshr miss latency 949system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66599.210584 # average ReadReq mshr miss latency 950system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency 951system.cpu.icache.demand_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency 952system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency 953system.cpu.icache.overall_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency 954system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 955system.cpu.l2cache.prefetcher.num_hwpf_issued 4988856 # number of hwpf issued 956system.cpu.l2cache.prefetcher.pfIdentified 5295771 # number of prefetch candidates identified 957system.cpu.l2cache.prefetcher.pfBufferHit 266816 # number of redundant prefetches already in prefetch queue |
| 951system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 952system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 958system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 959system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 953system.cpu.l2cache.prefetcher.pfSpanPage 14074231 # number of prefetches not generated due to page crossing 954system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states 955system.cpu.l2cache.tags.replacements 123 # number of replacements 956system.cpu.l2cache.tags.tagsinuse 11197.361342 # Cycle average of tags in use 957system.cpu.l2cache.tags.total_refs 5291777 # Total number of references to valid blocks. 958system.cpu.l2cache.tags.sampled_refs 14677 # Sample count of references to valid blocks. 959system.cpu.l2cache.tags.avg_refs 360.548954 # Average number of references to valid blocks. | 960system.cpu.l2cache.prefetcher.pfSpanPage 14074045 # number of prefetches not generated due to page crossing 961system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 962system.cpu.l2cache.tags.replacements 140 # number of replacements 963system.cpu.l2cache.tags.tagsinuse 11212.925557 # Cycle average of tags in use 964system.cpu.l2cache.tags.total_refs 5291618 # Total number of references to valid blocks. 965system.cpu.l2cache.tags.sampled_refs 14696 # Sample count of references to valid blocks. 966system.cpu.l2cache.tags.avg_refs 360.071992 # Average number of references to valid blocks. |
| 960system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 967system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 961system.cpu.l2cache.tags.occ_blocks::writebacks 11137.339599 # Average occupied blocks per requestor 962system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 60.021743 # Average occupied blocks per requestor 963system.cpu.l2cache.tags.occ_percent::writebacks 0.679769 # Average percentage of cache occupancy 964system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003663 # Average percentage of cache occupancy 965system.cpu.l2cache.tags.occ_percent::total 0.683433 # Average percentage of cache occupancy 966system.cpu.l2cache.tags.occ_task_id_blocks::1022 61 # Occupied blocks per task id 967system.cpu.l2cache.tags.occ_task_id_blocks::1024 14493 # Occupied blocks per task id | 968system.cpu.l2cache.tags.occ_blocks::writebacks 11154.278216 # Average occupied blocks per requestor 969system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 58.647341 # Average occupied blocks per requestor 970system.cpu.l2cache.tags.occ_percent::writebacks 0.680803 # Average percentage of cache occupancy 971system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003580 # Average percentage of cache occupancy 972system.cpu.l2cache.tags.occ_percent::total 0.684383 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_task_id_blocks::1022 60 # Occupied blocks per task id 974system.cpu.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id |
| 968system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 969system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id | 975system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id |
| 970system.cpu.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id 971system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id 972system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3478 # Occupied blocks per task id 973system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9594 # Occupied blocks per task id 974system.cpu.l2cache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1024::4 837 # Occupied blocks per task id 976system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003723 # Percentage of cache occupancy per task id 977system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884583 # Percentage of cache occupancy per task id 978system.cpu.l2cache.tags.tag_accesses 180526187 # Number of tag accesses 979system.cpu.l2cache.tags.data_accesses 180526187 # Number of data accesses 980system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states 981system.cpu.l2cache.WritebackDirty_hits::writebacks 5457780 # number of WritebackDirty hits 982system.cpu.l2cache.WritebackDirty_hits::total 5457780 # number of WritebackDirty hits 983system.cpu.l2cache.WritebackClean_hits::writebacks 10426 # number of WritebackClean hits 984system.cpu.l2cache.WritebackClean_hits::total 10426 # number of WritebackClean hits 985system.cpu.l2cache.ReadExReq_hits::cpu.data 226022 # number of ReadExReq hits 986system.cpu.l2cache.ReadExReq_hits::total 226022 # number of ReadExReq hits 987system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 204 # number of ReadCleanReq hits 988system.cpu.l2cache.ReadCleanReq_hits::total 204 # number of ReadCleanReq hits 989system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241527 # number of ReadSharedReq hits 990system.cpu.l2cache.ReadSharedReq_hits::total 5241527 # number of ReadSharedReq hits 991system.cpu.l2cache.demand_hits::cpu.inst 204 # number of demand (read+write) hits 992system.cpu.l2cache.demand_hits::cpu.data 5467549 # number of demand (read+write) hits 993system.cpu.l2cache.demand_hits::total 5467753 # number of demand (read+write) hits 994system.cpu.l2cache.overall_hits::cpu.inst 204 # number of overall hits 995system.cpu.l2cache.overall_hits::cpu.data 5467549 # number of overall hits 996system.cpu.l2cache.overall_hits::total 5467753 # number of overall hits | 977system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1024::0 477 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3389 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9672 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1024::4 839 # Occupied blocks per task id 983system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003662 # Percentage of cache occupancy per task id 984system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id 985system.cpu.l2cache.tags.tag_accesses 180525801 # Number of tag accesses 986system.cpu.l2cache.tags.data_accesses 180525801 # Number of data accesses 987system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 988system.cpu.l2cache.WritebackDirty_hits::writebacks 5457281 # number of WritebackDirty hits 989system.cpu.l2cache.WritebackDirty_hits::total 5457281 # number of WritebackDirty hits 990system.cpu.l2cache.WritebackClean_hits::writebacks 10913 # number of WritebackClean hits 991system.cpu.l2cache.WritebackClean_hits::total 10913 # number of WritebackClean hits 992system.cpu.l2cache.ReadExReq_hits::cpu.data 226015 # number of ReadExReq hits 993system.cpu.l2cache.ReadExReq_hits::total 226015 # number of ReadExReq hits 994system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 206 # number of ReadCleanReq hits 995system.cpu.l2cache.ReadCleanReq_hits::total 206 # number of ReadCleanReq hits 996system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241513 # number of ReadSharedReq hits 997system.cpu.l2cache.ReadSharedReq_hits::total 5241513 # number of ReadSharedReq hits 998system.cpu.l2cache.demand_hits::cpu.inst 206 # number of demand (read+write) hits 999system.cpu.l2cache.demand_hits::cpu.data 5467528 # number of demand (read+write) hits 1000system.cpu.l2cache.demand_hits::total 5467734 # number of demand (read+write) hits 1001system.cpu.l2cache.overall_hits::cpu.inst 206 # number of overall hits 1002system.cpu.l2cache.overall_hits::cpu.data 5467528 # number of overall hits 1003system.cpu.l2cache.overall_hits::total 5467734 # number of overall hits |
| 997system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses 998system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses | 1004system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses 1005system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses |
| 999system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses 1000system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses | 1006system.cpu.l2cache.ReadExReq_misses::cpu.data 505 # number of ReadExReq misses 1007system.cpu.l2cache.ReadExReq_misses::total 505 # number of ReadExReq misses |
| 1001system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses 1002system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses 1003system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3100 # number of ReadSharedReq misses 1004system.cpu.l2cache.ReadSharedReq_misses::total 3100 # number of ReadSharedReq misses 1005system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses | 1008system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses 1009system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses 1010system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3100 # number of ReadSharedReq misses 1011system.cpu.l2cache.ReadSharedReq_misses::total 3100 # number of ReadSharedReq misses 1012system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses |
| 1006system.cpu.l2cache.demand_misses::cpu.data 3599 # number of demand (read+write) misses 1007system.cpu.l2cache.demand_misses::total 4300 # number of demand (read+write) misses | 1013system.cpu.l2cache.demand_misses::cpu.data 3605 # number of demand (read+write) misses 1014system.cpu.l2cache.demand_misses::total 4306 # number of demand (read+write) misses |
| 1008system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses | 1015system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses |
| 1009system.cpu.l2cache.overall_misses::cpu.data 3599 # number of overall misses 1010system.cpu.l2cache.overall_misses::total 4300 # number of overall misses 1011system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 64500 # number of UpgradeReq miss cycles 1012system.cpu.l2cache.UpgradeReq_miss_latency::total 64500 # number of UpgradeReq miss cycles 1013system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41467500 # number of ReadExReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::total 41467500 # number of ReadExReq miss cycles 1015system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48564000 # number of ReadCleanReq miss cycles 1016system.cpu.l2cache.ReadCleanReq_miss_latency::total 48564000 # number of ReadCleanReq miss cycles 1017system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 228575500 # number of ReadSharedReq miss cycles 1018system.cpu.l2cache.ReadSharedReq_miss_latency::total 228575500 # number of ReadSharedReq miss cycles 1019system.cpu.l2cache.demand_miss_latency::cpu.inst 48564000 # number of demand (read+write) miss cycles 1020system.cpu.l2cache.demand_miss_latency::cpu.data 270043000 # number of demand (read+write) miss cycles 1021system.cpu.l2cache.demand_miss_latency::total 318607000 # number of demand (read+write) miss cycles 1022system.cpu.l2cache.overall_miss_latency::cpu.inst 48564000 # number of overall miss cycles 1023system.cpu.l2cache.overall_miss_latency::cpu.data 270043000 # number of overall miss cycles 1024system.cpu.l2cache.overall_miss_latency::total 318607000 # number of overall miss cycles 1025system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457780 # number of WritebackDirty accesses(hits+misses) 1026system.cpu.l2cache.WritebackDirty_accesses::total 5457780 # number of WritebackDirty accesses(hits+misses) 1027system.cpu.l2cache.WritebackClean_accesses::writebacks 10426 # number of WritebackClean accesses(hits+misses) 1028system.cpu.l2cache.WritebackClean_accesses::total 10426 # number of WritebackClean accesses(hits+misses) | 1016system.cpu.l2cache.overall_misses::cpu.data 3605 # number of overall misses 1017system.cpu.l2cache.overall_misses::total 4306 # number of overall misses 1018system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 63500 # number of UpgradeReq miss cycles 1019system.cpu.l2cache.UpgradeReq_miss_latency::total 63500 # number of UpgradeReq miss cycles 1020system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64129500 # number of ReadExReq miss cycles 1021system.cpu.l2cache.ReadExReq_miss_latency::total 64129500 # number of ReadExReq miss cycles 1022system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58109500 # number of ReadCleanReq miss cycles 1023system.cpu.l2cache.ReadCleanReq_miss_latency::total 58109500 # number of ReadCleanReq miss cycles 1024system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 616309000 # number of ReadSharedReq miss cycles 1025system.cpu.l2cache.ReadSharedReq_miss_latency::total 616309000 # number of ReadSharedReq miss cycles 1026system.cpu.l2cache.demand_miss_latency::cpu.inst 58109500 # number of demand (read+write) miss cycles 1027system.cpu.l2cache.demand_miss_latency::cpu.data 680438500 # number of demand (read+write) miss cycles 1028system.cpu.l2cache.demand_miss_latency::total 738548000 # number of demand (read+write) miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.inst 58109500 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::cpu.data 680438500 # number of overall miss cycles 1031system.cpu.l2cache.overall_miss_latency::total 738548000 # number of overall miss cycles 1032system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457281 # number of WritebackDirty accesses(hits+misses) 1033system.cpu.l2cache.WritebackDirty_accesses::total 5457281 # number of WritebackDirty accesses(hits+misses) 1034system.cpu.l2cache.WritebackClean_accesses::writebacks 10913 # number of WritebackClean accesses(hits+misses) 1035system.cpu.l2cache.WritebackClean_accesses::total 10913 # number of WritebackClean accesses(hits+misses) |
| 1029system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) 1030system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) | 1036system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) 1037system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) |
| 1031system.cpu.l2cache.ReadExReq_accesses::cpu.data 226521 # number of ReadExReq accesses(hits+misses) 1032system.cpu.l2cache.ReadExReq_accesses::total 226521 # number of ReadExReq accesses(hits+misses) 1033system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 905 # number of ReadCleanReq accesses(hits+misses) 1034system.cpu.l2cache.ReadCleanReq_accesses::total 905 # number of ReadCleanReq accesses(hits+misses) 1035system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244627 # number of ReadSharedReq accesses(hits+misses) 1036system.cpu.l2cache.ReadSharedReq_accesses::total 5244627 # number of ReadSharedReq accesses(hits+misses) 1037system.cpu.l2cache.demand_accesses::cpu.inst 905 # number of demand (read+write) accesses 1038system.cpu.l2cache.demand_accesses::cpu.data 5471148 # number of demand (read+write) accesses 1039system.cpu.l2cache.demand_accesses::total 5472053 # number of demand (read+write) accesses 1040system.cpu.l2cache.overall_accesses::cpu.inst 905 # number of overall (read+write) accesses 1041system.cpu.l2cache.overall_accesses::cpu.data 5471148 # number of overall (read+write) accesses 1042system.cpu.l2cache.overall_accesses::total 5472053 # number of overall (read+write) accesses | 1038system.cpu.l2cache.ReadExReq_accesses::cpu.data 226520 # number of ReadExReq accesses(hits+misses) 1039system.cpu.l2cache.ReadExReq_accesses::total 226520 # number of ReadExReq accesses(hits+misses) 1040system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 907 # number of ReadCleanReq accesses(hits+misses) 1041system.cpu.l2cache.ReadCleanReq_accesses::total 907 # number of ReadCleanReq accesses(hits+misses) 1042system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244613 # number of ReadSharedReq accesses(hits+misses) 1043system.cpu.l2cache.ReadSharedReq_accesses::total 5244613 # number of ReadSharedReq accesses(hits+misses) 1044system.cpu.l2cache.demand_accesses::cpu.inst 907 # number of demand (read+write) accesses 1045system.cpu.l2cache.demand_accesses::cpu.data 5471133 # number of demand (read+write) accesses 1046system.cpu.l2cache.demand_accesses::total 5472040 # number of demand (read+write) accesses 1047system.cpu.l2cache.overall_accesses::cpu.inst 907 # number of overall (read+write) accesses 1048system.cpu.l2cache.overall_accesses::cpu.data 5471133 # number of overall (read+write) accesses 1049system.cpu.l2cache.overall_accesses::total 5472040 # number of overall (read+write) accesses |
| 1043system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1044system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 1050system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1051system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 1045system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002203 # miss rate for ReadExReq accesses 1046system.cpu.l2cache.ReadExReq_miss_rate::total 0.002203 # miss rate for ReadExReq accesses 1047system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.774586 # miss rate for ReadCleanReq accesses 1048system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.774586 # miss rate for ReadCleanReq accesses | 1052system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002229 # miss rate for ReadExReq accesses 1053system.cpu.l2cache.ReadExReq_miss_rate::total 0.002229 # miss rate for ReadExReq accesses 1054system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772878 # miss rate for ReadCleanReq accesses 1055system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772878 # miss rate for ReadCleanReq accesses |
| 1049system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000591 # miss rate for ReadSharedReq accesses 1050system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000591 # miss rate for ReadSharedReq accesses | 1056system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000591 # miss rate for ReadSharedReq accesses 1057system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000591 # miss rate for ReadSharedReq accesses |
| 1051system.cpu.l2cache.demand_miss_rate::cpu.inst 0.774586 # miss rate for demand accesses 1052system.cpu.l2cache.demand_miss_rate::cpu.data 0.000658 # miss rate for demand accesses 1053system.cpu.l2cache.demand_miss_rate::total 0.000786 # miss rate for demand accesses 1054system.cpu.l2cache.overall_miss_rate::cpu.inst 0.774586 # miss rate for overall accesses 1055system.cpu.l2cache.overall_miss_rate::cpu.data 0.000658 # miss rate for overall accesses 1056system.cpu.l2cache.overall_miss_rate::total 0.000786 # miss rate for overall accesses 1057system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21500 # average UpgradeReq miss latency 1058system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21500 # average UpgradeReq miss latency 1059system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83101.202405 # average ReadExReq miss latency 1060system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83101.202405 # average ReadExReq miss latency 1061system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 69278.174037 # average ReadCleanReq miss latency 1062system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 69278.174037 # average ReadCleanReq miss latency 1063system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73734.032258 # average ReadSharedReq miss latency 1064system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73734.032258 # average ReadSharedReq miss latency 1065system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69278.174037 # average overall miss latency 1066system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75032.786885 # average overall miss latency 1067system.cpu.l2cache.demand_avg_miss_latency::total 74094.651163 # average overall miss latency 1068system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69278.174037 # average overall miss latency 1069system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75032.786885 # average overall miss latency 1070system.cpu.l2cache.overall_avg_miss_latency::total 74094.651163 # average overall miss latency | 1058system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772878 # miss rate for demand accesses 1059system.cpu.l2cache.demand_miss_rate::cpu.data 0.000659 # miss rate for demand accesses 1060system.cpu.l2cache.demand_miss_rate::total 0.000787 # miss rate for demand accesses 1061system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772878 # miss rate for overall accesses 1062system.cpu.l2cache.overall_miss_rate::cpu.data 0.000659 # miss rate for overall accesses 1063system.cpu.l2cache.overall_miss_rate::total 0.000787 # miss rate for overall accesses 1064system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21166.666667 # average UpgradeReq miss latency 1065system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21166.666667 # average UpgradeReq miss latency 1066system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126989.108911 # average ReadExReq miss latency 1067system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126989.108911 # average ReadExReq miss latency 1068system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82895.149786 # average ReadCleanReq miss latency 1069system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82895.149786 # average ReadCleanReq miss latency 1070system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198809.354839 # average ReadSharedReq miss latency 1071system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198809.354839 # average ReadSharedReq miss latency 1072system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency 1073system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency 1074system.cpu.l2cache.demand_avg_miss_latency::total 171516.024152 # average overall miss latency 1075system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency 1076system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency 1077system.cpu.l2cache.overall_avg_miss_latency::total 171516.024152 # average overall miss latency |
| 1071system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1072system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1073system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1074system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1075system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1076system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1078system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1079system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1080system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1081system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1082system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1083system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1077system.cpu.l2cache.writebacks::writebacks 89 # number of writebacks 1078system.cpu.l2cache.writebacks::total 89 # number of writebacks 1079system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits 1080system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits | 1084system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference 1085system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks 1086system.cpu.l2cache.writebacks::total 104 # number of writebacks 1087system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits 1088system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits |
| 1081system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1082system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits | 1089system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1090system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits |
| 1083system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits 1084system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits | 1091system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits 1092system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits |
| 1085system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits | 1093system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits |
| 1086system.cpu.l2cache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits 1087system.cpu.l2cache.demand_mshr_hits::total 181 # number of demand (read+write) MSHR hits | 1094system.cpu.l2cache.demand_mshr_hits::cpu.data 194 # number of demand (read+write) MSHR hits 1095system.cpu.l2cache.demand_mshr_hits::total 195 # number of demand (read+write) MSHR hits |
| 1088system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits | 1096system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits |
| 1089system.cpu.l2cache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits 1090system.cpu.l2cache.overall_mshr_hits::total 181 # number of overall MSHR hits 1091system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316573 # number of HardPFReq MSHR misses 1092system.cpu.l2cache.HardPFReq_mshr_misses::total 316573 # number of HardPFReq MSHR misses | 1097system.cpu.l2cache.overall_mshr_hits::cpu.data 194 # number of overall MSHR hits 1098system.cpu.l2cache.overall_mshr_hits::total 195 # number of overall MSHR hits 1099system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316848 # number of HardPFReq MSHR misses 1100system.cpu.l2cache.HardPFReq_mshr_misses::total 316848 # number of HardPFReq MSHR misses |
| 1093system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses 1094system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses | 1101system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses 1102system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses |
| 1095system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses 1096system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses | 1103system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses 1104system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # number of ReadExReq MSHR misses |
| 1097system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses 1098system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses | 1105system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses 1106system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses |
| 1099system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3078 # number of ReadSharedReq MSHR misses 1100system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3078 # number of ReadSharedReq MSHR misses | 1107system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3068 # number of ReadSharedReq MSHR misses 1108system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3068 # number of ReadSharedReq MSHR misses |
| 1101system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses | 1109system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses |
| 1102system.cpu.l2cache.demand_mshr_misses::cpu.data 3419 # number of demand (read+write) MSHR misses 1103system.cpu.l2cache.demand_mshr_misses::total 4119 # number of demand (read+write) MSHR misses | 1110system.cpu.l2cache.demand_mshr_misses::cpu.data 3411 # number of demand (read+write) MSHR misses 1111system.cpu.l2cache.demand_mshr_misses::total 4111 # number of demand (read+write) MSHR misses |
| 1104system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses | 1112system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses |
| 1105system.cpu.l2cache.overall_mshr_misses::cpu.data 3419 # number of overall MSHR misses 1106system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316573 # number of overall MSHR misses 1107system.cpu.l2cache.overall_mshr_misses::total 320692 # number of overall MSHR misses 1108system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 866631987 # number of HardPFReq MSHR miss cycles 1109system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 866631987 # number of HardPFReq MSHR miss cycles 1110system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 46500 # number of UpgradeReq MSHR miss cycles 1111system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 46500 # number of UpgradeReq MSHR miss cycles 1112system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32627500 # number of ReadExReq MSHR miss cycles 1113system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32627500 # number of ReadExReq MSHR miss cycles 1114system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44309000 # number of ReadCleanReq MSHR miss cycles 1115system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44309000 # number of ReadCleanReq MSHR miss cycles 1116system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 208942500 # number of ReadSharedReq MSHR miss cycles 1117system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 208942500 # number of ReadSharedReq MSHR miss cycles 1118system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44309000 # number of demand (read+write) MSHR miss cycles 1119system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 241570000 # number of demand (read+write) MSHR miss cycles 1120system.cpu.l2cache.demand_mshr_miss_latency::total 285879000 # number of demand (read+write) MSHR miss cycles 1121system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44309000 # number of overall MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 241570000 # number of overall MSHR miss cycles 1123system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 866631987 # number of overall MSHR miss cycles 1124system.cpu.l2cache.overall_mshr_miss_latency::total 1152510987 # number of overall MSHR miss cycles | 1113system.cpu.l2cache.overall_mshr_misses::cpu.data 3411 # number of overall MSHR misses 1114system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316848 # number of overall MSHR misses 1115system.cpu.l2cache.overall_mshr_misses::total 320959 # number of overall MSHR misses 1116system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of HardPFReq MSHR miss cycles 1117system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1079223443 # number of HardPFReq MSHR miss cycles 1118system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45500 # number of UpgradeReq MSHR miss cycles 1119system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45500 # number of UpgradeReq MSHR miss cycles 1120system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45646000 # number of ReadExReq MSHR miss cycles 1121system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45646000 # number of ReadExReq MSHR miss cycles 1122system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53848500 # number of ReadCleanReq MSHR miss cycles 1123system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53848500 # number of ReadCleanReq MSHR miss cycles 1124system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 589212500 # number of ReadSharedReq MSHR miss cycles 1125system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 589212500 # number of ReadSharedReq MSHR miss cycles 1126system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53848500 # number of demand (read+write) MSHR miss cycles 1127system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 634858500 # number of demand (read+write) MSHR miss cycles 1128system.cpu.l2cache.demand_mshr_miss_latency::total 688707000 # number of demand (read+write) MSHR miss cycles 1129system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53848500 # number of overall MSHR miss cycles 1130system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 634858500 # number of overall MSHR miss cycles 1131system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of overall MSHR miss cycles 1132system.cpu.l2cache.overall_mshr_miss_latency::total 1767930443 # number of overall MSHR miss cycles |
| 1125system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1126system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1127system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1128system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 1133system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1134system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1135system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1136system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 1129system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses 1130system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses 1131system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for ReadCleanReq accesses 1132system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.773481 # mshr miss rate for ReadCleanReq accesses 1133system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000587 # mshr miss rate for ReadSharedReq accesses 1134system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadSharedReq accesses 1135system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for demand accesses 1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for demand accesses 1137system.cpu.l2cache.demand_mshr_miss_rate::total 0.000753 # mshr miss rate for demand accesses 1138system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for overall accesses 1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for overall accesses | 1137system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses 1138system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses 1139system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for ReadCleanReq accesses 1140system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.771775 # mshr miss rate for ReadCleanReq accesses 1141system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000585 # mshr miss rate for ReadSharedReq accesses 1142system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000585 # mshr miss rate for ReadSharedReq accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for demand accesses 1144system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for demand accesses 1145system.cpu.l2cache.demand_mshr_miss_rate::total 0.000751 # mshr miss rate for demand accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for overall accesses 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for overall accesses |
| 1140system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1148system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1141system.cpu.l2cache.overall_mshr_miss_rate::total 0.058605 # mshr miss rate for overall accesses 1142system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average HardPFReq mshr miss latency 1143system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2737.542327 # average HardPFReq mshr miss latency 1144system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency 1145system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency 1146system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95681.818182 # average ReadExReq mshr miss latency 1147system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95681.818182 # average ReadExReq mshr miss latency 1148system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63298.571429 # average ReadCleanReq mshr miss latency 1149system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63298.571429 # average ReadCleanReq mshr miss latency 1150system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67882.553606 # average ReadSharedReq mshr miss latency 1151system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67882.553606 # average ReadSharedReq mshr miss latency 1152system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency 1153system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency 1154system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69404.952658 # average overall mshr miss latency 1155system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency 1156system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency 1157system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average overall mshr miss latency 1158system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3593.825187 # average overall mshr miss latency 1159system.cpu.toL2Bus.snoop_filter.tot_requests 10943139 # Total number of requests made to the snoop filter. 1160system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1161system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1162system.cpu.toL2Bus.snoop_filter.tot_snoops 302176 # Total number of snoops made to the snoop filter. 1163system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302175 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1149system.cpu.l2cache.overall_mshr_miss_rate::total 0.058654 # mshr miss rate for overall accesses 1150system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average HardPFReq mshr miss latency 1151system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3406.123577 # average HardPFReq mshr miss latency 1152system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667 # average UpgradeReq mshr miss latency 1153system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667 # average UpgradeReq mshr miss latency 1154system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201 # average ReadExReq mshr miss latency 1155system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201 # average ReadExReq mshr miss latency 1156system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571 # average ReadCleanReq mshr miss latency 1157system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571 # average ReadCleanReq mshr miss latency 1158system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430 # average ReadSharedReq mshr miss latency 1159system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430 # average ReadSharedReq mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5508.275023 # average overall mshr miss latency 1167system.cpu.toL2Bus.snoop_filter.tot_requests 10943112 # Total number of requests made to the snoop filter. 1168system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471085 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1169system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1170system.cpu.toL2Bus.snoop_filter.tot_snoops 302425 # Total number of snoops made to the snoop filter. 1171system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302424 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1164system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1172system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1165system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states 1166system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::WritebackDirty 5457869 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::WritebackClean 13303 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::HardPFReq 318447 # Transaction distribution | 1173system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 1174system.cpu.toL2Bus.trans_dist::ReadResp 5245519 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::WritebackDirty 5457385 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::WritebackClean 13788 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::CleanEvict 36 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::HardPFReq 318720 # Transaction distribution |
| 1171system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 1172system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution | 1179system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution |
| 1174system.cpu.toL2Bus.trans_dist::ReadExReq 226521 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::ReadExResp 226521 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution 1178system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) 1179system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412942 # Packet count per connected master and slave (bytes) 1180system.cpu.toL2Bus.pkt_count::total 16415198 # Packet count per connected master and slave (bytes) 1181system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) 1182system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274432 # Cumulative packet size per connected master and slave (bytes) 1183system.cpu.toL2Bus.pkt_size::total 700360896 # Cumulative packet size per connected master and slave (bytes) 1184system.cpu.toL2Bus.snoops 318574 # Total snoops (count) 1185system.cpu.toL2Bus.snoopTraffic 5952 # Total snoop traffic (bytes) 1186system.cpu.toL2Bus.snoop_fanout::samples 5790626 # Request fanout histogram 1187system.cpu.toL2Bus.snoop_fanout::mean 0.052683 # Request fanout histogram 1188system.cpu.toL2Bus.snoop_fanout::stdev 0.223400 # Request fanout histogram | 1182system.cpu.toL2Bus.trans_dist::ReadExReq 226520 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::ReadExResp 226520 # Transaction distribution 1184system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution 1185system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244613 # Transaction distribution 1186system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes) 1187system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412897 # Packet count per connected master and slave (bytes) 1188system.cpu.toL2Bus.pkt_count::total 16415158 # Packet count per connected master and slave (bytes) 1189system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes) 1190system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700272512 # Cumulative packet size per connected master and slave (bytes) 1191system.cpu.toL2Bus.pkt_size::total 700359168 # Cumulative packet size per connected master and slave (bytes) 1192system.cpu.toL2Bus.snoops 318864 # Total snoops (count) 1193system.cpu.toL2Bus.snoopTraffic 6912 # Total snoop traffic (bytes) 1194system.cpu.toL2Bus.snoop_fanout::samples 5790903 # Request fanout histogram 1195system.cpu.toL2Bus.snoop_fanout::mean 0.052723 # Request fanout histogram 1196system.cpu.toL2Bus.snoop_fanout::stdev 0.223481 # Request fanout histogram |
| 1189system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1197system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1190system.cpu.toL2Bus.snoop_fanout::0 5485560 94.73% 94.73% # Request fanout histogram 1191system.cpu.toL2Bus.snoop_fanout::1 305065 5.27% 100.00% # Request fanout histogram | 1198system.cpu.toL2Bus.snoop_fanout::0 5485590 94.73% 94.73% # Request fanout histogram 1199system.cpu.toL2Bus.snoop_fanout::1 305312 5.27% 100.00% # Request fanout histogram |
| 1192system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1193system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1194system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1195system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1200system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1201system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1202system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1203system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1196system.cpu.toL2Bus.snoop_fanout::total 5790626 # Request fanout histogram 1197system.cpu.toL2Bus.reqLayer0.occupancy 10942652515 # Layer occupancy (ticks) 1198system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) | 1204system.cpu.toL2Bus.snoop_fanout::total 5790903 # Request fanout histogram 1205system.cpu.toL2Bus.reqLayer0.occupancy 10942625015 # Layer occupancy (ticks) 1206system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%) |
| 1199system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) 1200system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1207system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) 1208system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1201system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) | 1209system.cpu.toL2Bus.respLayer0.occupancy 1360996 # Layer occupancy (ticks) |
| 1202system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1210system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1203system.cpu.toL2Bus.respLayer1.occupancy 8206727492 # Layer occupancy (ticks) 1204system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) 1205system.membus.snoop_filter.tot_requests 18642 # Total number of requests made to the snoop filter. 1206system.membus.snoop_filter.hit_single_requests 3008 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1211system.cpu.toL2Bus.respLayer1.occupancy 8206704493 # Layer occupancy (ticks) 1212system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) 1213system.membus.snoop_filter.tot_requests 18677 # Total number of requests made to the snoop filter. 1214system.membus.snoop_filter.hit_single_requests 3023 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1207system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1208system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1209system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1210system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1215system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1216system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1217system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1218system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1211system.membus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states 1212system.membus.trans_dist::ReadResp 18174 # Transaction distribution 1213system.membus.trans_dist::WritebackDirty 89 # Transaction distribution 1214system.membus.trans_dist::CleanEvict 34 # Transaction distribution | 1219system.membus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 1220system.membus.trans_dist::ReadResp 18190 # Transaction distribution 1221system.membus.trans_dist::WritebackDirty 104 # Transaction distribution 1222system.membus.trans_dist::CleanEvict 36 # Transaction distribution |
| 1215system.membus.trans_dist::UpgradeReq 4 # Transaction distribution | 1223system.membus.trans_dist::UpgradeReq 4 # Transaction distribution |
| 1216system.membus.trans_dist::ReadExReq 340 # Transaction distribution 1217system.membus.trans_dist::ReadExResp 340 # Transaction distribution 1218system.membus.trans_dist::ReadSharedReq 18175 # Transaction distribution 1219system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37156 # Packet count per connected master and slave (bytes) 1220system.membus.pkt_count::total 37156 # Packet count per connected master and slave (bytes) 1221system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1190592 # Cumulative packet size per connected master and slave (bytes) 1222system.membus.pkt_size::total 1190592 # Cumulative packet size per connected master and slave (bytes) | 1224system.membus.trans_dist::ReadExReq 342 # Transaction distribution 1225system.membus.trans_dist::ReadExResp 342 # Transaction distribution 1226system.membus.trans_dist::ReadSharedReq 18191 # Transaction distribution 1227system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37209 # Packet count per connected master and slave (bytes) 1228system.membus.pkt_count::total 37209 # Packet count per connected master and slave (bytes) 1229system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192704 # Cumulative packet size per connected master and slave (bytes) 1230system.membus.pkt_size::total 1192704 # Cumulative packet size per connected master and slave (bytes) |
| 1223system.membus.snoops 0 # Total snoops (count) 1224system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1231system.membus.snoops 0 # Total snoops (count) 1232system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1225system.membus.snoop_fanout::samples 18519 # Request fanout histogram | 1233system.membus.snoop_fanout::samples 18537 # Request fanout histogram |
| 1226system.membus.snoop_fanout::mean 0 # Request fanout histogram 1227system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1228system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1234system.membus.snoop_fanout::mean 0 # Request fanout histogram 1235system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1236system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1229system.membus.snoop_fanout::0 18519 100.00% 100.00% # Request fanout histogram | 1237system.membus.snoop_fanout::0 18537 100.00% 100.00% # Request fanout histogram |
| 1230system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1231system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1232system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1233system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1238system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1239system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1240system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1241system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1234system.membus.snoop_fanout::total 18519 # Request fanout histogram 1235system.membus.reqLayer0.occupancy 29524488 # Layer occupancy (ticks) | 1242system.membus.snoop_fanout::total 18537 # Request fanout histogram 1243system.membus.reqLayer0.occupancy 29625930 # Layer occupancy (ticks) |
| 1236system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1244system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1237system.membus.respLayer1.occupancy 97237655 # Layer occupancy (ticks) | 1245system.membus.respLayer1.occupancy 97326818 # Layer occupancy (ticks) |
| 1238system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1239 1240---------- End Simulation Statistics ---------- | 1246system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1247 1248---------- End Simulation Statistics ---------- |