| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058199 # Number of seconds simulated 4sim_ticks 58199030500 # Number of ticks simulated 5final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058199 # Number of seconds simulated 4sim_ticks 58199030500 # Number of ticks simulated 5final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 218368 # Simulator instruction rate (inst/s) 8host_op_rate 219455 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 140289424 # Simulator tick rate (ticks/s) 10host_mem_usage 534192 # Number of bytes of host memory used 11host_seconds 414.85 # Real time elapsed on the host | 7host_inst_rate 220490 # Simulator instruction rate (inst/s) 8host_op_rate 221588 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 141652578 # Simulator tick rate (ticks/s) 10host_mem_usage 534836 # Number of bytes of host memory used 11host_seconds 410.86 # Real time elapsed on the host |
| 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory 23system.physmem.bytes_written::total 11200 # Number of bytes written to this memory --- 244 unchanged lines hidden (view full) --- 268system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ) 269system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ) 270system.physmem_1.averagePower 671.780705 # Core power per rank (mW) 271system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states 272system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states 273system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 274system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states 275system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory 20system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory 24system.physmem.bytes_written::total 11200 # Number of bytes written to this memory --- 244 unchanged lines hidden (view full) --- 269system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ) 270system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ) 271system.physmem_1.averagePower 671.780705 # Core power per rank (mW) 272system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states 273system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states 274system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 275system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states 276system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 277system.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 276system.cpu.branchPred.lookups 28233538 # Number of BP lookups 277system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted 278system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect 279system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups 280system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits 281system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 282system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage 283system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target. 284system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions. 285system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups. 286system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. 287system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. 288system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. 289system.cpu_clk_domain.clock 500 # Clock period in ticks | 278system.cpu.branchPred.lookups 28233538 # Number of BP lookups 279system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted 280system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect 281system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups 282system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits 283system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 284system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage 285system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target. 286system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions. 287system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups. 288system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. 289system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. 290system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. 291system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 292system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 290system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 311system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 312system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 313system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 314system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 315system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 316system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 317system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 318system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 293system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 314system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 315system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 316system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 317system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 318system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 319system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 320system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 321system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 322system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 319system.cpu.dtb.walker.walks 0 # Table walker walks requested 320system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 340system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 341system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 342system.cpu.dtb.read_accesses 0 # DTB read accesses 343system.cpu.dtb.write_accesses 0 # DTB write accesses 344system.cpu.dtb.inst_accesses 0 # ITB inst accesses 345system.cpu.dtb.hits 0 # DTB hits 346system.cpu.dtb.misses 0 # DTB misses 347system.cpu.dtb.accesses 0 # DTB accesses | 323system.cpu.dtb.walker.walks 0 # Table walker walks requested 324system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 344system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 345system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 346system.cpu.dtb.read_accesses 0 # DTB read accesses 347system.cpu.dtb.write_accesses 0 # DTB write accesses 348system.cpu.dtb.inst_accesses 0 # ITB inst accesses 349system.cpu.dtb.hits 0 # DTB hits 350system.cpu.dtb.misses 0 # DTB misses 351system.cpu.dtb.accesses 0 # DTB accesses |
| 352system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 348system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 369system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 370system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 371system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 372system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 373system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 374system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 375system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 376system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 353system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 374system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 375system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 376system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 377system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 378system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 379system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 380system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 381system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 382system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 377system.cpu.itb.walker.walks 0 # Table walker walks requested 378system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 384system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 399system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.itb.read_accesses 0 # DTB read accesses 401system.cpu.itb.write_accesses 0 # DTB write accesses 402system.cpu.itb.inst_accesses 0 # ITB inst accesses 403system.cpu.itb.hits 0 # DTB hits 404system.cpu.itb.misses 0 # DTB misses 405system.cpu.itb.accesses 0 # DTB accesses 406system.cpu.workload.num_syscalls 442 # Number of system calls | 383system.cpu.itb.walker.walks 0 # Table walker walks requested 384system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 405system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu.itb.read_accesses 0 # DTB read accesses 407system.cpu.itb.write_accesses 0 # DTB write accesses 408system.cpu.itb.inst_accesses 0 # ITB inst accesses 409system.cpu.itb.hits 0 # DTB hits 410system.cpu.itb.misses 0 # DTB misses 411system.cpu.itb.accesses 0 # DTB accesses 412system.cpu.workload.num_syscalls 442 # Number of system calls |
| 413system.cpu.pwrStateResidencyTicks::ON 58199030500 # Cumulative time (in ticks) in various power states |
|
| 407system.cpu.numCycles 116398062 # number of cpu cycles simulated 408system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 409system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 410system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss 411system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed 412system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered 413system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken 414system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 688system.cpu.int_regfile_reads 108097873 # number of integer regfile reads 689system.cpu.int_regfile_writes 58692304 # number of integer regfile writes 690system.cpu.fp_regfile_reads 59 # number of floating regfile reads 691system.cpu.fp_regfile_writes 96 # number of floating regfile writes 692system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads 693system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes 694system.cpu.misc_regfile_reads 28410103 # number of misc regfile reads 695system.cpu.misc_regfile_writes 7784 # number of misc regfile writes | 414system.cpu.numCycles 116398062 # number of cpu cycles simulated 415system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 416system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 417system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss 418system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed 419system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered 420system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken 421system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 695system.cpu.int_regfile_reads 108097873 # number of integer regfile reads 696system.cpu.int_regfile_writes 58692304 # number of integer regfile writes 697system.cpu.fp_regfile_reads 59 # number of floating regfile reads 698system.cpu.fp_regfile_writes 96 # number of floating regfile writes 699system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads 700system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes 701system.cpu.misc_regfile_reads 28410103 # number of misc regfile reads 702system.cpu.misc_regfile_writes 7784 # number of misc regfile writes |
| 703system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 696system.cpu.dcache.tags.replacements 5470634 # number of replacements 697system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use 698system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. 699system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks. 700system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks. 701system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit. 702system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor 703system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy 704system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy 705system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 706system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id 707system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id 708system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 709system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses 710system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses | 704system.cpu.dcache.tags.replacements 5470634 # number of replacements 705system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use 706system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. 707system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks. 708system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks. 709system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit. 710system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor 711system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy 712system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy 713system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 714system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id 715system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id 716system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 717system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses 718system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses |
| 719system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 711system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits 712system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits 713system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits 714system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits 715system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 716system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 717system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits 718system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits --- 114 unchanged lines hidden (view full) --- 833system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency 834system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency 835system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency 836system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency 837system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency 838system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency 839system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency 840system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency | 720system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits 721system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits 722system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits 723system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits 724system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 725system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 726system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits 727system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits --- 114 unchanged lines hidden (view full) --- 842system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency 843system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency 844system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency 845system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency 846system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency 847system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency 848system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency 849system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency |
| 850system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 841system.cpu.icache.tags.replacements 447 # number of replacements 842system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use 843system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. 844system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. 845system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. 846system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 847system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor 848system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy 849system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy 850system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id 851system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 852system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 853system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 854system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id 855system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id 856system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses 857system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses | 851system.cpu.icache.tags.replacements 447 # number of replacements 852system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use 853system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. 854system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. 855system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. 856system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 857system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor 858system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy 859system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy 860system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id 861system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 862system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 863system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 864system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id 865system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id 866system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses 867system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses |
| 868system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 858system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits 859system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits 860system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits 861system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits 862system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits 863system.cpu.icache.overall_hits::total 32273898 # number of overall hits 864system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses 865system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 924system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 925system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 926system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency 927system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency 928system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 929system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency 930system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 931system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency | 869system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits 870system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits 871system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits 872system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits 873system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits 874system.cpu.icache.overall_hits::total 32273898 # number of overall hits 875system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses 876system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 935system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 936system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 937system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency 938system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency 939system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 940system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency 941system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 942system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency |
| 943system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 932system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued 933system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified 934system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue 935system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 936system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 937system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing | 944system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued 945system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified 946system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue 947system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 948system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 949system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing |
| 950system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 938system.cpu.l2cache.tags.replacements 248 # number of replacements 939system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use 940system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. 941system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks. 942system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks. 943system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 944system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor 945system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor --- 10 unchanged lines hidden (view full) --- 956system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id 957system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id 958system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id 959system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id 960system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id 961system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id 962system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses 963system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses | 951system.cpu.l2cache.tags.replacements 248 # number of replacements 952system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use 953system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. 954system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks. 955system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks. 956system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 957system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor 958system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor --- 10 unchanged lines hidden (view full) --- 969system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id 970system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id 971system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id 972system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id 973system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id 974system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id 975system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses 976system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses |
| 977system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 964system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits 965system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits 966system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits 967system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits 968system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits 969system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits 970system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits 971system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits --- 169 unchanged lines hidden (view full) --- 1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency 1143system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. 1144system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1145system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1146system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. 1147system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1148system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 978system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits 979system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits 980system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits 981system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits 982system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits 983system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits 984system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits 985system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits --- 169 unchanged lines hidden (view full) --- 1155system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency 1156system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency 1157system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. 1158system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1159system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1160system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. 1161system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1162system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1163system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 1149system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution --- 22 unchanged lines hidden (view full) --- 1179system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks) 1180system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) 1181system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) 1182system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1183system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) 1184system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1185system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) 1186system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) | 1164system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution --- 22 unchanged lines hidden (view full) --- 1194system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks) 1195system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) 1196system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) 1197system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1198system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) 1199system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1200system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) 1201system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) |
| 1202system.membus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states |
|
| 1187system.membus.trans_dist::ReadResp 16175 # Transaction distribution 1188system.membus.trans_dist::WritebackDirty 175 # Transaction distribution 1189system.membus.trans_dist::CleanEvict 63 # Transaction distribution 1190system.membus.trans_dist::UpgradeReq 4 # Transaction distribution 1191system.membus.trans_dist::ReadExReq 341 # Transaction distribution 1192system.membus.trans_dist::ReadExResp 341 # Transaction distribution 1193system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution 1194system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- | 1203system.membus.trans_dist::ReadResp 16175 # Transaction distribution 1204system.membus.trans_dist::WritebackDirty 175 # Transaction distribution 1205system.membus.trans_dist::CleanEvict 63 # Transaction distribution 1206system.membus.trans_dist::UpgradeReq 4 # Transaction distribution 1207system.membus.trans_dist::ReadExReq 341 # Transaction distribution 1208system.membus.trans_dist::ReadExResp 341 # Transaction distribution 1209system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution 1210system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- |