| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058199 # Number of seconds simulated 4sim_ticks 58199030500 # Number of ticks simulated 5final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058199 # Number of seconds simulated 4sim_ticks 58199030500 # Number of ticks simulated 5final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 158181 # Simulator instruction rate (inst/s) 8host_op_rate 158969 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 101622775 # Simulator tick rate (ticks/s) 10host_mem_usage 491528 # Number of bytes of host memory used 11host_seconds 572.70 # Real time elapsed on the host | 7host_inst_rate 149103 # Simulator instruction rate (inst/s) 8host_op_rate 149846 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 95790656 # Simulator tick rate (ticks/s) 10host_mem_usage 491524 # Number of bytes of host memory used 11host_seconds 607.56 # Real time elapsed on the host |
| 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory --- 761 unchanged lines hidden (view full) --- 781system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency 782system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency 783system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked 784system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked 785system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked 786system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked 787system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked 788system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked | 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory --- 761 unchanged lines hidden (view full) --- 781system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency 782system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency 783system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked 784system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked 785system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked 786system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked 787system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked 788system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked |
| 789system.cpu.dcache.fast_writes 0 # number of fast writes performed 790system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 791system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks 792system.cpu.dcache.writebacks::total 5470634 # number of writebacks 793system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits 794system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits 795system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits 796system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits 797system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits 798system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 835system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency 836system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency 837system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency 838system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency 839system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency 840system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency 841system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency 842system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency | 789system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks 790system.cpu.dcache.writebacks::total 5470634 # number of writebacks 791system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits 792system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits 793system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits 794system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits 795system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits 796system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 833system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency 834system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency 835system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency 836system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency 837system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency 838system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency 839system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency 840system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency |
| 843system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 844system.cpu.icache.tags.replacements 447 # number of replacements 845system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use 846system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. 847system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. 848system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. 849system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 850system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor 851system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 895system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency 896system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency 897system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked 898system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked 899system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked 900system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 901system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked 902system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked | 841system.cpu.icache.tags.replacements 447 # number of replacements 842system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use 843system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. 844system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. 845system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. 846system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 847system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor 848system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 892system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency 893system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency 894system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked 895system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked 896system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked 897system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 898system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked 899system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked |
| 903system.cpu.icache.fast_writes 0 # number of fast writes performed 904system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 905system.cpu.icache.writebacks::writebacks 447 # number of writebacks 906system.cpu.icache.writebacks::total 447 # number of writebacks 907system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits 908system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits 909system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits 910system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits 911system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits 912system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 929system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 930system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 931system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency 932system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency 933system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 934system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency 935system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 936system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency | 900system.cpu.icache.writebacks::writebacks 447 # number of writebacks 901system.cpu.icache.writebacks::total 447 # number of writebacks 902system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits 903system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits 904system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits 905system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits 906system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits 907system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 924system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 925system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 926system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency 927system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency 928system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 929system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency 930system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 931system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency |
| 937system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 938system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued 939system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified 940system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue 941system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 942system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 943system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing 944system.cpu.l2cache.tags.replacements 248 # number of replacements 945system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use --- 112 unchanged lines hidden (view full) --- 1058system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency 1059system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327 # average overall miss latency 1060system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1061system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1062system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1063system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1064system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1065system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 932system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued 933system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified 934system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue 935system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 936system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 937system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing 938system.cpu.l2cache.tags.replacements 248 # number of replacements 939system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use --- 112 unchanged lines hidden (view full) --- 1052system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency 1053system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327 # average overall miss latency 1054system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1055system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1056system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1057system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1058system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1059system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1066system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1067system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1068system.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference 1069system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks 1070system.cpu.l2cache.writebacks::total 175 # number of writebacks 1071system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits 1072system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits 1073system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1074system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1075system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 37 # number of ReadSharedReq MSHR hits --- 67 unchanged lines hidden (view full) --- 1143system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency 1144system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency 1145system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency 1146system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency 1147system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency 1148system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency | 1060system.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference 1061system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks 1062system.cpu.l2cache.writebacks::total 175 # number of writebacks 1063system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits 1064system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits 1065system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1066system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1067system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 37 # number of ReadSharedReq MSHR hits --- 67 unchanged lines hidden (view full) --- 1135system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency 1136system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency 1137system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency 1138system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency 1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency |
| 1151system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1152system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. 1153system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1154system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1155system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. 1156system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1157system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1158system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution --- 64 unchanged lines hidden --- | 1143system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. 1144system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1145system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1146system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. 1147system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1148system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1149system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution --- 64 unchanged lines hidden --- |