| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058203 # Number of seconds simulated 4sim_ticks 58202727500 # Number of ticks simulated 5final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 129726 # Simulator instruction rate (inst/s) 8host_op_rate 130372 # Simulator op (including micro ops) rate (op/s) --- 662 unchanged lines hidden (view full) --- 671system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 673system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 674system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 675system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 676system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 677system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction 678system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058203 # Number of seconds simulated 4sim_ticks 58202727500 # Number of ticks simulated 5final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 129726 # Simulator instruction rate (inst/s) 8host_op_rate 130372 # Simulator op (including micro ops) rate (op/s) --- 662 unchanged lines hidden (view full) --- 671system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 673system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 674system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 675system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 676system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 677system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction 678system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached |
| 679system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 680system.cpu.rob.rob_reads 217986125 # The number of ROB reads 681system.cpu.rob.rob_writes 219581178 # The number of ROB writes 682system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself 683system.cpu.idleCycles 52982 # Total number of cycles that the CPU has spent unscheduled due to idling 684system.cpu.committedInsts 90589798 # Number of Instructions Simulated 685system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated 686system.cpu.cpi 1.284973 # CPI: Cycles Per Instruction 687system.cpu.cpi_total 1.284973 # CPI: Total CPI of All Threads --- 518 unchanged lines hidden --- | 679system.cpu.rob.rob_reads 217986125 # The number of ROB reads 680system.cpu.rob.rob_writes 219581178 # The number of ROB writes 681system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself 682system.cpu.idleCycles 52982 # Total number of cycles that the CPU has spent unscheduled due to idling 683system.cpu.committedInsts 90589798 # Number of Instructions Simulated 684system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated 685system.cpu.cpi 1.284973 # CPI: Cycles Per Instruction 686system.cpu.cpi_total 1.284973 # CPI: Total CPI of All Threads --- 518 unchanged lines hidden --- |