| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.057713 # Number of seconds simulated 4sim_ticks 57712782000 # Number of ticks simulated 5final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.057719 # Number of seconds simulated 4sim_ticks 57719377000 # Number of ticks simulated 5final_tick 57719377000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 133110 # Simulator instruction rate (inst/s) 8host_op_rate 133773 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 84801314 # Simulator tick rate (ticks/s) 10host_mem_usage 388280 # Number of bytes of host memory used 11host_seconds 680.56 # Real time elapsed on the host | 7host_inst_rate 125223 # Simulator instruction rate (inst/s) 8host_op_rate 125847 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 79786059 # Simulator tick rate (ticks/s) 10host_mem_usage 443544 # Number of bytes of host memory used 11host_seconds 723.43 # Real time elapsed on the host |
| 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91041029 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91041029 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 8896 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 68416 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1042048 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1119360 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 8896 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 8896 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 73600 # Number of bytes written to this memory 23system.physmem.bytes_written::total 73600 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 139 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 1069 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 16282 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 17490 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 1150 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 1150 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 154143 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 1185457 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 18055758 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 19395357 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 154143 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 154143 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 1275281 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 1275281 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 1275281 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 154143 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 1185457 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 18055758 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 20670638 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 17490 # Number of read requests accepted 44system.physmem.writeReqs 1150 # Number of write requests accepted 45system.physmem.readBursts 17490 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 1150 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 1100032 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue 49system.physmem.bytesWritten 71488 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 1119360 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 73600 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one | 16system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 43648 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 927744 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1015808 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory 23system.physmem.bytes_written::total 19776 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 682 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 14496 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 15872 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 309 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 769516 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 756211 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 16073354 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 17599081 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 769516 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 769516 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 342623 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 342623 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 342623 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 769516 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 756211 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 16073354 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17941704 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 15872 # Number of read requests accepted 44system.physmem.writeReqs 309 # Number of write requests accepted 45system.physmem.readBursts 15872 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 1006016 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue 49system.physmem.bytesWritten 18432 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 1015808 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one |
| 54system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write | 54system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write |
| 55system.physmem.perBankRdBursts::0 1094 # Per bank write bursts 56system.physmem.perBankRdBursts::1 953 # Per bank write bursts 57system.physmem.perBankRdBursts::2 1083 # Per bank write bursts 58system.physmem.perBankRdBursts::3 1113 # Per bank write bursts 59system.physmem.perBankRdBursts::4 1125 # Per bank write bursts 60system.physmem.perBankRdBursts::5 1235 # Per bank write bursts 61system.physmem.perBankRdBursts::6 1314 # Per bank write bursts 62system.physmem.perBankRdBursts::7 1243 # Per bank write bursts 63system.physmem.perBankRdBursts::8 1060 # Per bank write bursts | 55system.physmem.perBankRdBursts::0 999 # Per bank write bursts 56system.physmem.perBankRdBursts::1 876 # Per bank write bursts 57system.physmem.perBankRdBursts::2 956 # Per bank write bursts 58system.physmem.perBankRdBursts::3 1023 # Per bank write bursts 59system.physmem.perBankRdBursts::4 1064 # Per bank write bursts 60system.physmem.perBankRdBursts::5 1127 # Per bank write bursts 61system.physmem.perBankRdBursts::6 1115 # Per bank write bursts 62system.physmem.perBankRdBursts::7 1101 # Per bank write bursts 63system.physmem.perBankRdBursts::8 1033 # Per bank write bursts |
| 64system.physmem.perBankRdBursts::9 962 # Per bank write bursts | 64system.physmem.perBankRdBursts::9 962 # Per bank write bursts |
| 65system.physmem.perBankRdBursts::10 1021 # Per bank write bursts 66system.physmem.perBankRdBursts::11 923 # Per bank write bursts 67system.physmem.perBankRdBursts::12 921 # Per bank write bursts 68system.physmem.perBankRdBursts::13 987 # Per bank write bursts 69system.physmem.perBankRdBursts::14 1105 # Per bank write bursts 70system.physmem.perBankRdBursts::15 1049 # Per bank write bursts 71system.physmem.perBankWrBursts::0 72 # Per bank write bursts | 65system.physmem.perBankRdBursts::10 937 # Per bank write bursts 66system.physmem.perBankRdBursts::11 899 # Per bank write bursts 67system.physmem.perBankRdBursts::12 910 # Per bank write bursts 68system.physmem.perBankRdBursts::13 886 # Per bank write bursts 69system.physmem.perBankRdBursts::14 919 # Per bank write bursts 70system.physmem.perBankRdBursts::15 912 # Per bank write bursts 71system.physmem.perBankWrBursts::0 23 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::1 0 # Per bank write bursts | 72system.physmem.perBankWrBursts::1 0 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::2 62 # Per bank write bursts 74system.physmem.perBankWrBursts::3 19 # Per bank write bursts 75system.physmem.perBankWrBursts::4 14 # Per bank write bursts 76system.physmem.perBankWrBursts::5 111 # Per bank write bursts 77system.physmem.perBankWrBursts::6 193 # Per bank write bursts 78system.physmem.perBankWrBursts::7 122 # Per bank write bursts 79system.physmem.perBankWrBursts::8 49 # Per bank write bursts | 73system.physmem.perBankWrBursts::2 4 # Per bank write bursts 74system.physmem.perBankWrBursts::3 0 # Per bank write bursts 75system.physmem.perBankWrBursts::4 9 # Per bank write bursts 76system.physmem.perBankWrBursts::5 29 # Per bank write bursts 77system.physmem.perBankWrBursts::6 62 # Per bank write bursts 78system.physmem.perBankWrBursts::7 30 # Per bank write bursts 79system.physmem.perBankWrBursts::8 15 # Per bank write bursts |
| 80system.physmem.perBankWrBursts::9 0 # Per bank write bursts | 80system.physmem.perBankWrBursts::9 0 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::10 68 # Per bank write bursts 82system.physmem.perBankWrBursts::11 20 # Per bank write bursts 83system.physmem.perBankWrBursts::12 15 # Per bank write bursts 84system.physmem.perBankWrBursts::13 94 # Per bank write bursts 85system.physmem.perBankWrBursts::14 168 # Per bank write bursts 86system.physmem.perBankWrBursts::15 110 # Per bank write bursts | 81system.physmem.perBankWrBursts::10 10 # Per bank write bursts 82system.physmem.perBankWrBursts::11 1 # Per bank write bursts 83system.physmem.perBankWrBursts::12 9 # Per bank write bursts 84system.physmem.perBankWrBursts::13 27 # Per bank write bursts 85system.physmem.perBankWrBursts::14 48 # Per bank write bursts 86system.physmem.perBankWrBursts::15 21 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 89system.physmem.totGap 57712604500 # Total gap between requests | 89system.physmem.totGap 57719226000 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 17490 # Read request sizes (log2) | 96system.physmem.readPktSize::6 15872 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 1150 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 11254 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 2508 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 618 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 551 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 423 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 408 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 392 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 391 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 120 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 309 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 10641 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 2671 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 352 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 295 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 287 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 293 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see |
| 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 50 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 51 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 59 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 61 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 62 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 63 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 63 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 66 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 66 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 66 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 68 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 70 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 68 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 63 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 63 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 63 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 63 # What write queue length does an incoming req see | 151system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 15 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 17 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 200system.physmem.bytesPerActivate::samples 2975 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 393.336471 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 197.951950 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 413.488148 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 1360 45.71% 45.71% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 404 13.58% 59.29% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 131 4.40% 63.70% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 68 2.29% 65.98% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 81 2.72% 68.71% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 67 2.25% 70.96% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 54 1.82% 72.77% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 34 1.14% 73.92% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 776 26.08% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 2975 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 63 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 272.444444 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 27.585882 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 1910.173610 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 62 98.41% 98.41% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::14848-15359 1 1.59% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 63 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 63 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 17.730159 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 17.698769 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 1.080716 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16 12 19.05% 19.05% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::17 1 1.59% 20.63% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18 46 73.02% 93.65% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::19 3 4.76% 98.41% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::23 1 1.59% 100.00% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::total 63 # Writes before turning the bus around for reads 231system.physmem.totQLat 228948216 # Total ticks spent queuing 232system.physmem.totMemAccLat 551223216 # Total ticks spent from burst creation until serviced by the DRAM 233system.physmem.totBusLat 85940000 # Total ticks spent in databus transfers 234system.physmem.avgQLat 13320.24 # Average queueing delay per DRAM burst | 200system.physmem.bytesPerActivate::samples 1739 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 588.402530 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 354.168959 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 429.121053 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 443 25.47% 25.47% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 194 11.16% 36.63% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 91 5.23% 41.86% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 64 3.68% 45.54% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 57 3.28% 48.82% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 43 2.47% 51.29% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 46 2.65% 53.94% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 54 3.11% 57.04% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 747 42.96% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 1739 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 981 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 40.634826 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 3762.941438 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 15 93.75% 93.75% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::14848-15359 1 6.25% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 17.975187 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 0.966092 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 11 68.75% 81.25% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::19 2 12.50% 93.75% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads 230system.physmem.totQLat 179464908 # Total ticks spent queuing 231system.physmem.totMemAccLat 474196158 # Total ticks spent from burst creation until serviced by the DRAM 232system.physmem.totBusLat 78595000 # Total ticks spent in databus transfers 233system.physmem.avgQLat 11417.07 # Average queueing delay per DRAM burst |
| 235system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 236system.physmem.avgMemAccLat 32070.24 # Average memory access latency per DRAM burst 237system.physmem.avgRdBW 19.06 # Average DRAM read bandwidth in MiByte/s 238system.physmem.avgWrBW 1.24 # Average achieved write bandwidth in MiByte/s 239system.physmem.avgRdBWSys 19.40 # Average system read bandwidth in MiByte/s 240system.physmem.avgWrBWSys 1.28 # Average system write bandwidth in MiByte/s | 235system.physmem.avgMemAccLat 30167.07 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s 237system.physmem.avgWrBW 0.32 # Average achieved write bandwidth in MiByte/s 238system.physmem.avgRdBWSys 17.60 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 0.34 # Average system write bandwidth in MiByte/s |
| 241system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 242system.physmem.busUtil 0.16 # Data bus utilization in percentage 243system.physmem.busUtilRead 0.15 # Data bus utilization in percentage for reads 244system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 245system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing 246system.physmem.avgWrQLen 14.66 # Average write queue length when enqueuing 247system.physmem.readRowHits 14950 # Number of row buffer hits during reads 248system.physmem.writeRowHits 375 # Number of row buffer hits during writes 249system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads 250system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes 251system.physmem.avgGap 3096169.77 # Average gap between requests 252system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined 253system.physmem.memoryStateTime::IDLE 51355249007 # Time in different power states 254system.physmem.memoryStateTime::REF 1927120000 # Time in different power states 255system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 256system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states 257system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 258system.physmem.actEnergy::0 11854080 # Energy for activate commands per rank (pJ) 259system.physmem.actEnergy::1 10636920 # Energy for activate commands per rank (pJ) 260system.physmem.preEnergy::0 6468000 # Energy for precharge commands per rank (pJ) 261system.physmem.preEnergy::1 5803875 # Energy for precharge commands per rank (pJ) 262system.physmem.readEnergy::0 71299800 # Energy for read commands per rank (pJ) 263system.physmem.readEnergy::1 62602800 # Energy for read commands per rank (pJ) 264system.physmem.writeEnergy::0 3842640 # Energy for write commands per rank (pJ) 265system.physmem.writeEnergy::1 3395520 # Energy for write commands per rank (pJ) 266system.physmem.refreshEnergy::0 3769446720 # Energy for refresh commands per rank (pJ) 267system.physmem.refreshEnergy::1 3769446720 # Energy for refresh commands per rank (pJ) 268system.physmem.actBackEnergy::0 2993861160 # Energy for active background per rank (pJ) 269system.physmem.actBackEnergy::1 3031288785 # Energy for active background per rank (pJ) 270system.physmem.preBackEnergy::0 32001000000 # Energy for precharge background per rank (pJ) 271system.physmem.preBackEnergy::1 31968168750 # Energy for precharge background per rank (pJ) 272system.physmem.totalEnergy::0 38857772400 # Total energy per rank (pJ) 273system.physmem.totalEnergy::1 38851343370 # Total energy per rank (pJ) 274system.physmem.averagePower::0 673.305017 # Core power per rank (mW) 275system.physmem.averagePower::1 673.193618 # Core power per rank (mW) 276system.membus.trans_dist::ReadReq 17158 # Transaction distribution 277system.membus.trans_dist::ReadResp 17158 # Transaction distribution 278system.membus.trans_dist::Writeback 1150 # Transaction distribution 279system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 280system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 281system.membus.trans_dist::ReadExReq 332 # Transaction distribution 282system.membus.trans_dist::ReadExResp 332 # Transaction distribution 283system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 36134 # Packet count per connected master and slave (bytes) 284system.membus.pkt_count::total 36134 # Packet count per connected master and slave (bytes) 285system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192960 # Cumulative packet size per connected master and slave (bytes) 286system.membus.pkt_size::total 1192960 # Cumulative packet size per connected master and slave (bytes) 287system.membus.snoops 0 # Total snoops (count) 288system.membus.snoop_fanout::samples 18642 # Request fanout histogram 289system.membus.snoop_fanout::mean 0 # Request fanout histogram 290system.membus.snoop_fanout::stdev 0 # Request fanout histogram 291system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 292system.membus.snoop_fanout::0 18642 100.00% 100.00% # Request fanout histogram 293system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 294system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 295system.membus.snoop_fanout::min_value 0 # Request fanout histogram 296system.membus.snoop_fanout::max_value 0 # Request fanout histogram 297system.membus.snoop_fanout::total 18642 # Request fanout histogram 298system.membus.reqLayer0.occupancy 32019899 # Layer occupancy (ticks) 299system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 300system.membus.respLayer1.occupancy 163550691 # Layer occupancy (ticks) 301system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 302system.cpu_clk_domain.clock 500 # Clock period in ticks 303system.cpu.branchPred.lookups 28272297 # Number of BP lookups 304system.cpu.branchPred.condPredicted 23289786 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 837936 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 11858499 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 11790100 # Number of BTB hits | 241system.physmem.busUtil 0.14 # Data bus utilization in percentage 242system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 244system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing 245system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing 246system.physmem.readRowHits 14166 # Number of row buffer hits during reads 247system.physmem.writeRowHits 92 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 29.97 # Row buffer hit rate for writes 250system.physmem.avgGap 3567098.82 # Average gap between requests 251system.physmem.pageHitRate 88.97 # Row buffer hit rate, read and write combined 252system.physmem_0.actEnergy 7053480 # Energy for activate commands per rank (pJ) 253system.physmem_0.preEnergy 3848625 # Energy for precharge commands per rank (pJ) 254system.physmem_0.readEnergy 64162800 # Energy for read commands per rank (pJ) 255system.physmem_0.writeEnergy 959040 # Energy for write commands per rank (pJ) 256system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) 257system.physmem_0.actBackEnergy 2338304445 # Energy for active background per rank (pJ) 258system.physmem_0.preBackEnergy 32576022750 # Energy for precharge background per rank (pJ) 259system.physmem_0.totalEnergy 38759797860 # Total energy per rank (pJ) 260system.physmem_0.averagePower 671.607894 # Core power per rank (mW) 261system.physmem_0.memoryStateTime::IDLE 54183699610 # Time in different power states 262system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states 263system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 264system.physmem_0.memoryStateTime::ACT 1601139140 # Time in different power states 265system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 266system.physmem_1.actEnergy 6002640 # Energy for activate commands per rank (pJ) 267system.physmem_1.preEnergy 3275250 # Energy for precharge commands per rank (pJ) 268system.physmem_1.readEnergy 58133400 # Energy for read commands per rank (pJ) 269system.physmem_1.writeEnergy 803520 # Energy for write commands per rank (pJ) 270system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) 271system.physmem_1.actBackEnergy 2319744105 # Energy for active background per rank (pJ) 272system.physmem_1.preBackEnergy 32592295500 # Energy for precharge background per rank (pJ) 273system.physmem_1.totalEnergy 38749701135 # Total energy per rank (pJ) 274system.physmem_1.averagePower 671.433104 # Core power per rank (mW) 275system.physmem_1.memoryStateTime::IDLE 54217128450 # Time in different power states 276system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states 277system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 278system.physmem_1.memoryStateTime::ACT 1573598050 # Time in different power states 279system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 280system.cpu.branchPred.lookups 28271166 # Number of BP lookups 281system.cpu.branchPred.condPredicted 23289258 # Number of conditional branches predicted 282system.cpu.branchPred.condIncorrect 837919 # Number of conditional branches incorrect 283system.cpu.branchPred.BTBLookups 11857915 # Number of BTB lookups 284system.cpu.branchPred.BTBHits 11789421 # Number of BTB hits |
| 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 309system.cpu.branchPred.BTBHitPct 99.423207 # BTB Hit Percentage 310system.cpu.branchPred.usedRAS 75765 # Number of times the RAS was used to get a target. | 286system.cpu.branchPred.BTBHitPct 99.422377 # BTB Hit Percentage 287system.cpu.branchPred.usedRAS 75707 # Number of times the RAS was used to get a target. |
| 311system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. | 288system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. |
| 289system.cpu_clk_domain.clock 500 # Clock period in ticks 290system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 312system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 313system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 314system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 315system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 316system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 317system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 298system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 299system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 300system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 301system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 302system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 303system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 304system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 305system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 311system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 312system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 313system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 314system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 315system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 316system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 317system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 318system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 319system.cpu.dtb.walker.walks 0 # Table walker walks requested 320system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 333system.cpu.dtb.inst_hits 0 # ITB inst hits 334system.cpu.dtb.inst_misses 0 # ITB inst misses 335system.cpu.dtb.read_hits 0 # DTB read hits 336system.cpu.dtb.read_misses 0 # DTB read misses 337system.cpu.dtb.write_hits 0 # DTB write hits 338system.cpu.dtb.write_misses 0 # DTB write misses 339system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.dtb.read_accesses 0 # DTB read accesses 349system.cpu.dtb.write_accesses 0 # DTB write accesses 350system.cpu.dtb.inst_accesses 0 # ITB inst accesses 351system.cpu.dtb.hits 0 # DTB hits 352system.cpu.dtb.misses 0 # DTB misses 353system.cpu.dtb.accesses 0 # DTB accesses | 327system.cpu.dtb.inst_hits 0 # ITB inst hits 328system.cpu.dtb.inst_misses 0 # ITB inst misses 329system.cpu.dtb.read_hits 0 # DTB read hits 330system.cpu.dtb.read_misses 0 # DTB read misses 331system.cpu.dtb.write_hits 0 # DTB write hits 332system.cpu.dtb.write_misses 0 # DTB write misses 333system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 334system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 340system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 341system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 342system.cpu.dtb.read_accesses 0 # DTB read accesses 343system.cpu.dtb.write_accesses 0 # DTB write accesses 344system.cpu.dtb.inst_accesses 0 # ITB inst accesses 345system.cpu.dtb.hits 0 # DTB hits 346system.cpu.dtb.misses 0 # DTB misses 347system.cpu.dtb.accesses 0 # DTB accesses |
| 348system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 354system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 355system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 356system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 357system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 358system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 359system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 360system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 361system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 367system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 370system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 371system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 372system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 373system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 374system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 356system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 357system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 358system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 359system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 360system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 361system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 362system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 363system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 369system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 370system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 371system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 372system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 373system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 374system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 375system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 376system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 377system.cpu.itb.walker.walks 0 # Table walker walks requested 378system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 384system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 375system.cpu.itb.inst_hits 0 # ITB inst hits 376system.cpu.itb.inst_misses 0 # ITB inst misses 377system.cpu.itb.read_hits 0 # DTB read hits 378system.cpu.itb.read_misses 0 # DTB read misses 379system.cpu.itb.write_hits 0 # DTB write hits 380system.cpu.itb.write_misses 0 # DTB write misses 381system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 382system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 389system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 390system.cpu.itb.read_accesses 0 # DTB read accesses 391system.cpu.itb.write_accesses 0 # DTB write accesses 392system.cpu.itb.inst_accesses 0 # ITB inst accesses 393system.cpu.itb.hits 0 # DTB hits 394system.cpu.itb.misses 0 # DTB misses 395system.cpu.itb.accesses 0 # DTB accesses 396system.cpu.workload.num_syscalls 442 # Number of system calls | 385system.cpu.itb.inst_hits 0 # ITB inst hits 386system.cpu.itb.inst_misses 0 # ITB inst misses 387system.cpu.itb.read_hits 0 # DTB read hits 388system.cpu.itb.read_misses 0 # DTB read misses 389system.cpu.itb.write_hits 0 # DTB write hits 390system.cpu.itb.write_misses 0 # DTB write misses 391system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 392system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 399system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.itb.read_accesses 0 # DTB read accesses 401system.cpu.itb.write_accesses 0 # DTB write accesses 402system.cpu.itb.inst_accesses 0 # ITB inst accesses 403system.cpu.itb.hits 0 # DTB hits 404system.cpu.itb.misses 0 # DTB misses 405system.cpu.itb.accesses 0 # DTB accesses 406system.cpu.workload.num_syscalls 442 # Number of system calls |
| 397system.cpu.numCycles 115425565 # number of cpu cycles simulated | 407system.cpu.numCycles 115438755 # number of cpu cycles simulated |
| 398system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 399system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 408system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 409system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 400system.cpu.fetch.icacheStallCycles 745807 # Number of cycles fetch is stalled on an Icache miss 401system.cpu.fetch.Insts 135034231 # Number of instructions fetch has processed 402system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered 403system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken 404system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked 405system.cpu.fetch.SquashCycles 1679445 # Number of cycles fetch has spent squashing 406system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 407system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR 408system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched 409system.cpu.fetch.IcacheSquashes 456 # Number of outstanding Icache misses that were squashed 410system.cpu.fetch.rateDist::samples 115408607 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::mean 1.175345 # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::stdev 1.320714 # Number of instructions fetched each cycle (Total) | 410system.cpu.fetch.icacheStallCycles 750677 # Number of cycles fetch is stalled on an Icache miss 411system.cpu.fetch.Insts 135029605 # Number of instructions fetch has processed 412system.cpu.fetch.Branches 28271166 # Number of branches that fetch encountered 413system.cpu.fetch.predictedBranches 11865128 # Number of branches that fetch has predicted taken 414system.cpu.fetch.Cycles 113801477 # Number of cycles fetch has run and was not squashing or blocked 415system.cpu.fetch.SquashCycles 1679415 # Number of cycles fetch has spent squashing 416system.cpu.fetch.MiscStallCycles 1154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 417system.cpu.fetch.IcacheWaitRetryStallCycles 715 # Number of stall cycles due to full MSHR 418system.cpu.fetch.CacheLines 32315558 # Number of cache lines fetched 419system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed 420system.cpu.fetch.rateDist::samples 115393730 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::mean 1.175455 # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.rateDist::stdev 1.320715 # Number of instructions fetched each cycle (Total) |
| 413system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 423system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 414system.cpu.fetch.rateDist::0 57851940 50.13% 50.13% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::1 13925142 12.07% 62.19% # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::2 9174755 7.95% 70.14% # Number of instructions fetched each cycle (Total) 417system.cpu.fetch.rateDist::3 34456770 29.86% 100.00% # Number of instructions fetched each cycle (Total) | 424system.cpu.fetch.rateDist::0 57838402 50.12% 50.12% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::1 13925125 12.07% 62.19% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::2 9175651 7.95% 70.14% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::3 34454552 29.86% 100.00% # Number of instructions fetched each cycle (Total) |
| 418system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 428system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 421system.cpu.fetch.rateDist::total 115408607 # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.branchRate 0.244940 # Number of branch fetches per cycle 423system.cpu.fetch.rate 1.169881 # Number of inst fetches per cycle 424system.cpu.decode.IdleCycles 8865132 # Number of cycles decode is idle 425system.cpu.decode.BlockedCycles 63135589 # Number of cycles decode is blocked 426system.cpu.decode.RunCycles 33034927 # Number of cycles decode is running 427system.cpu.decode.UnblockCycles 9545475 # Number of cycles decode is unblocking 428system.cpu.decode.SquashCycles 827484 # Number of cycles decode is squashing 429system.cpu.decode.BranchResolved 4101291 # Number of times decode resolved a branch 430system.cpu.decode.BranchMispred 12346 # Number of times decode detected a branch misprediction 431system.cpu.decode.DecodedInsts 114392929 # Number of instructions handled by decode 432system.cpu.decode.SquashedInsts 1987160 # Number of squashed instructions handled by decode 433system.cpu.rename.SquashCycles 827484 # Number of cycles rename is squashing 434system.cpu.rename.IdleCycles 15218972 # Number of cycles rename is idle 435system.cpu.rename.BlockCycles 49233807 # Number of cycles rename is blocking 436system.cpu.rename.serializeStallCycles 108012 # count of cycles rename stalled for serializing inst 437system.cpu.rename.RunCycles 35472939 # Number of cycles rename is running 438system.cpu.rename.UnblockCycles 14547393 # Number of cycles rename is unblocking 439system.cpu.rename.RenamedInsts 110855235 # Number of instructions processed by rename 440system.cpu.rename.SquashedInsts 1413432 # Number of squashed instructions processed by rename 441system.cpu.rename.ROBFullEvents 11041669 # Number of times rename has blocked due to ROB full 442system.cpu.rename.IQFullEvents 1056479 # Number of times rename has blocked due to IQ full 443system.cpu.rename.LQFullEvents 1457795 # Number of times rename has blocked due to LQ full 444system.cpu.rename.SQFullEvents 455993 # Number of times rename has blocked due to SQ full 445system.cpu.rename.RenamedOperands 129914313 # Number of destination operands rename has renamed 446system.cpu.rename.RenameLookups 483072528 # Number of register rename lookups that rename has made 447system.cpu.rename.int_rename_lookups 119436601 # Number of integer rename lookups | 431system.cpu.fetch.rateDist::total 115393730 # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.branchRate 0.244902 # Number of branch fetches per cycle 433system.cpu.fetch.rate 1.169708 # Number of inst fetches per cycle 434system.cpu.decode.IdleCycles 8870766 # Number of cycles decode is idle 435system.cpu.decode.BlockedCycles 63114849 # Number of cycles decode is blocked 436system.cpu.decode.RunCycles 33033969 # Number of cycles decode is running 437system.cpu.decode.UnblockCycles 9546674 # Number of cycles decode is unblocking 438system.cpu.decode.SquashCycles 827472 # Number of cycles decode is squashing 439system.cpu.decode.BranchResolved 4101024 # Number of times decode resolved a branch 440system.cpu.decode.BranchMispred 12335 # Number of times decode detected a branch misprediction 441system.cpu.decode.DecodedInsts 114392732 # Number of instructions handled by decode 442system.cpu.decode.SquashedInsts 1987220 # Number of squashed instructions handled by decode 443system.cpu.rename.SquashCycles 827472 # Number of cycles rename is squashing 444system.cpu.rename.IdleCycles 15224664 # Number of cycles rename is idle 445system.cpu.rename.BlockCycles 49207626 # Number of cycles rename is blocking 446system.cpu.rename.serializeStallCycles 108919 # count of cycles rename stalled for serializing inst 447system.cpu.rename.RunCycles 35472493 # Number of cycles rename is running 448system.cpu.rename.UnblockCycles 14552556 # Number of cycles rename is unblocking 449system.cpu.rename.RenamedInsts 110856042 # Number of instructions processed by rename 450system.cpu.rename.SquashedInsts 1413744 # Number of squashed instructions processed by rename 451system.cpu.rename.ROBFullEvents 11047079 # Number of times rename has blocked due to ROB full 452system.cpu.rename.IQFullEvents 1056491 # Number of times rename has blocked due to IQ full 453system.cpu.rename.LQFullEvents 1457150 # Number of times rename has blocked due to LQ full 454system.cpu.rename.SQFullEvents 456315 # Number of times rename has blocked due to SQ full 455system.cpu.rename.RenamedOperands 129915292 # Number of destination operands rename has renamed 456system.cpu.rename.RenameLookups 483076638 # Number of register rename lookups that rename has made 457system.cpu.rename.int_rename_lookups 119437218 # Number of integer rename lookups |
| 448system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups 449system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed | 458system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups 459system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed |
| 450system.cpu.rename.UndoneMaps 22601394 # Number of HB maps that are undone due to squashing 451system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed | 460system.cpu.rename.UndoneMaps 22602373 # Number of HB maps that are undone due to squashing 461system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed |
| 452system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed | 462system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed |
| 453system.cpu.rename.skidInsts 21215231 # count of insts added to the skid buffer 454system.cpu.memDep0.insertedLoads 26814209 # Number of loads inserted to the mem dependence unit. 455system.cpu.memDep0.insertedStores 5348913 # Number of stores inserted to the mem dependence unit. 456system.cpu.memDep0.conflictingLoads 553765 # Number of conflicting loads. 457system.cpu.memDep0.conflictingStores 291016 # Number of conflicting stores. 458system.cpu.iq.iqInstsAdded 109685133 # Number of instructions added to the IQ (excludes non-spec) | 463system.cpu.rename.skidInsts 21217869 # count of insts added to the skid buffer 464system.cpu.memDep0.insertedLoads 26815015 # Number of loads inserted to the mem dependence unit. 465system.cpu.memDep0.insertedStores 5348915 # Number of stores inserted to the mem dependence unit. 466system.cpu.memDep0.conflictingLoads 559856 # Number of conflicting loads. 467system.cpu.memDep0.conflictingStores 297304 # Number of conflicting stores. 468system.cpu.iq.iqInstsAdded 109685726 # Number of instructions added to the IQ (excludes non-spec) |
| 459system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ | 469system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ |
| 460system.cpu.iq.iqInstsIssued 101428277 # Number of instructions issued 461system.cpu.iq.iqSquashedInstsIssued 1059458 # Number of squashed instructions issued 462system.cpu.iq.iqSquashedInstsExamined 18454529 # Number of squashed instructions iterated over during squash; mainly for profiling 463system.cpu.iq.iqSquashedOperandsExamined 41507183 # Number of squashed operands that are examined and possibly removed from graph | 470system.cpu.iq.iqInstsIssued 101429576 # Number of instructions issued 471system.cpu.iq.iqSquashedInstsIssued 1059441 # Number of squashed instructions issued 472system.cpu.iq.iqSquashedInstsExamined 18455382 # Number of squashed instructions iterated over during squash; mainly for profiling 473system.cpu.iq.iqSquashedOperandsExamined 41507392 # Number of squashed operands that are examined and possibly removed from graph |
| 464system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed | 474system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed |
| 465system.cpu.iq.issued_per_cycle::samples 115408607 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::mean 0.878862 # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::stdev 1.000028 # Number of insts issued each cycle | 475system.cpu.iq.issued_per_cycle::samples 115393730 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::mean 0.878987 # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::stdev 0.999963 # Number of insts issued each cycle |
| 468system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 478system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 469system.cpu.iq.issued_per_cycle::0 54542432 47.26% 47.26% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::1 30109521 26.09% 73.35% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::2 22147517 19.19% 92.54% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::3 7413143 6.42% 98.96% # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::4 1195677 1.04% 100.00% # Number of insts issued each cycle | 479system.cpu.iq.issued_per_cycle::0 54518642 47.25% 47.25% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::1 30124755 26.11% 73.35% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::2 22142664 19.19% 92.54% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::3 7411500 6.42% 98.96% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::4 1195852 1.04% 100.00% # Number of insts issued each cycle |
| 474system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 484system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 481system.cpu.iq.issued_per_cycle::total 115408607 # Number of insts issued each cycle | 491system.cpu.iq.issued_per_cycle::total 115393730 # Number of insts issued each cycle |
| 482system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 492system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 483system.cpu.iq.fu_full::IntAlu 9750275 48.86% 48.86% # attempts to use FU when none available | 493system.cpu.iq.fu_full::IntAlu 9750384 48.86% 48.86% # attempts to use FU when none available |
| 484system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available 485system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available 487system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available 488system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available 489system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available 490system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available 491system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 504system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available | 494system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available 495system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available 501system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 514system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available |
| 512system.cpu.iq.fu_full::MemRead 9493870 47.57% 96.43% # attempts to use FU when none available 513system.cpu.iq.fu_full::MemWrite 712253 3.57% 100.00% # attempts to use FU when none available | 522system.cpu.iq.fu_full::MemRead 9494227 47.58% 96.44% # attempts to use FU when none available 523system.cpu.iq.fu_full::MemWrite 710033 3.56% 100.00% # attempts to use FU when none available |
| 514system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 515system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 516system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 524system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 525system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 526system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 517system.cpu.iq.FU_type_0::IntAlu 71987588 70.97% 70.97% # Type of FU issued | 527system.cpu.iq.FU_type_0::IntAlu 71988081 70.97% 70.97% # Type of FU issued |
| 518system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued 519system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued 521system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued 522system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued 523system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued 524system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued 525system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued --- 6 unchanged lines hidden (view full) --- 532system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued | 528system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued 529system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued 530system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued 531system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued 532system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued 534system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued 535system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued --- 6 unchanged lines hidden (view full) --- 542system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued |
| 540system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 70.98% # Type of FU issued | 550system.cpu.iq.FU_type_0::SimdFloatCvt 55 0.00% 70.98% # Type of FU issued |
| 541system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued | 551system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued |
| 546system.cpu.iq.FU_type_0::MemRead 24380841 24.04% 95.02% # Type of FU issued 547system.cpu.iq.FU_type_0::MemWrite 5048955 4.98% 100.00% # Type of FU issued | 556system.cpu.iq.FU_type_0::MemRead 24381590 24.04% 95.02% # Type of FU issued 557system.cpu.iq.FU_type_0::MemWrite 5049013 4.98% 100.00% # Type of FU issued |
| 548system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 549system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 558system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 559system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 550system.cpu.iq.FU_type_0::total 101428277 # Type of FU issued 551system.cpu.iq.rate 0.878733 # Inst issue rate 552system.cpu.iq.fu_busy_cnt 19956461 # FU busy when requested 553system.cpu.iq.fu_busy_rate 0.196754 # FU busy rate (busy events/executed inst) 554system.cpu.iq.int_inst_queue_reads 339280619 # Number of integer instruction queue reads 555system.cpu.iq.int_inst_queue_writes 128148692 # Number of integer instruction queue writes 556system.cpu.iq.int_inst_queue_wakeup_accesses 99657487 # Number of integer instruction queue wakeup accesses 557system.cpu.iq.fp_inst_queue_reads 461 # Number of floating instruction queue reads | 560system.cpu.iq.FU_type_0::total 101429576 # Type of FU issued 561system.cpu.iq.rate 0.878644 # Inst issue rate 562system.cpu.iq.fu_busy_cnt 19954707 # FU busy when requested 563system.cpu.iq.fu_busy_rate 0.196735 # FU busy rate (busy events/executed inst) 564system.cpu.iq.int_inst_queue_reads 339266571 # Number of integer instruction queue reads 565system.cpu.iq.int_inst_queue_writes 128150140 # Number of integer instruction queue writes 566system.cpu.iq.int_inst_queue_wakeup_accesses 99658235 # Number of integer instruction queue wakeup accesses 567system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads |
| 558system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes | 568system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes |
| 559system.cpu.iq.fp_inst_queue_wakeup_accesses 120 # Number of floating instruction queue wakeup accesses 560system.cpu.iq.int_alu_accesses 121384498 # Number of integer alu accesses 561system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses 562system.cpu.iew.lsq.thread0.forwLoads 285190 # Number of loads that had data forwarded from stores | 569system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses 570system.cpu.iq.int_alu_accesses 121384044 # Number of integer alu accesses 571system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses 572system.cpu.iew.lsq.thread0.forwLoads 285219 # Number of loads that had data forwarded from stores |
| 563system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 573system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 564system.cpu.iew.lsq.thread0.squashedLoads 4338298 # Number of loads squashed 565system.cpu.iew.lsq.thread0.ignoredResponses 1479 # Number of memory responses ignored because the instruction is squashed 566system.cpu.iew.lsq.thread0.memOrderViolation 1420 # Number of memory ordering violations 567system.cpu.iew.lsq.thread0.squashedStores 604069 # Number of stores squashed | 574system.cpu.iew.lsq.thread0.squashedLoads 4339104 # Number of loads squashed 575system.cpu.iew.lsq.thread0.ignoredResponses 1483 # Number of memory responses ignored because the instruction is squashed 576system.cpu.iew.lsq.thread0.memOrderViolation 1422 # Number of memory ordering violations 577system.cpu.iew.lsq.thread0.squashedStores 604071 # Number of stores squashed |
| 568system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 569system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 570system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled | 578system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 579system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 580system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled |
| 571system.cpu.iew.lsq.thread0.cacheBlocked 130354 # Number of times an access to memory failed due to the cache being blocked | 581system.cpu.iew.lsq.thread0.cacheBlocked 130466 # Number of times an access to memory failed due to the cache being blocked |
| 572system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 582system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 573system.cpu.iew.iewSquashCycles 827484 # Number of cycles IEW is squashing 574system.cpu.iew.iewBlockCycles 8008710 # Number of cycles IEW is blocking 575system.cpu.iew.iewUnblockCycles 730406 # Number of cycles IEW is unblocking 576system.cpu.iew.iewDispatchedInsts 109706046 # Number of instructions dispatched to IQ | 583system.cpu.iew.iewSquashCycles 827472 # Number of cycles IEW is squashing 584system.cpu.iew.iewBlockCycles 8003638 # Number of cycles IEW is blocking 585system.cpu.iew.iewUnblockCycles 730506 # Number of cycles IEW is unblocking 586system.cpu.iew.iewDispatchedInsts 109706640 # Number of instructions dispatched to IQ |
| 577system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 587system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 578system.cpu.iew.iewDispLoadInsts 26814209 # Number of dispatched load instructions 579system.cpu.iew.iewDispStoreInsts 5348913 # Number of dispatched store instructions | 588system.cpu.iew.iewDispLoadInsts 26815015 # Number of dispatched load instructions 589system.cpu.iew.iewDispStoreInsts 5348915 # Number of dispatched store instructions |
| 580system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions | 590system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions |
| 581system.cpu.iew.iewIQFullEvents 187279 # Number of times the IQ has become full, causing a stall 582system.cpu.iew.iewLSQFullEvents 360662 # Number of times the LSQ has become full, causing a stall 583system.cpu.iew.memOrderViolationEvents 1420 # Number of memory order violations 584system.cpu.iew.predictedTakenIncorrect 436360 # Number of branches that were predicted taken incorrectly 585system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly 586system.cpu.iew.branchMispredicts 849241 # Number of branch mispredicts detected at execute 587system.cpu.iew.iewExecutedInsts 100145631 # Number of executed instructions 588system.cpu.iew.iewExecLoadInsts 23824107 # Number of load instructions executed 589system.cpu.iew.iewExecSquashedInsts 1282646 # Number of squashed instructions skipped in execute | 591system.cpu.iew.iewIQFullEvents 187146 # Number of times the IQ has become full, causing a stall 592system.cpu.iew.iewLSQFullEvents 360894 # Number of times the LSQ has become full, causing a stall 593system.cpu.iew.memOrderViolationEvents 1422 # Number of memory order violations 594system.cpu.iew.predictedTakenIncorrect 436340 # Number of branches that were predicted taken incorrectly 595system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly 596system.cpu.iew.branchMispredicts 849212 # Number of branch mispredicts detected at execute 597system.cpu.iew.iewExecutedInsts 100146798 # Number of executed instructions 598system.cpu.iew.iewExecLoadInsts 23824665 # Number of load instructions executed 599system.cpu.iew.iewExecSquashedInsts 1282778 # Number of squashed instructions skipped in execute |
| 590system.cpu.iew.exec_swp 0 # number of swp insts executed | 600system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 591system.cpu.iew.exec_nop 12666 # number of nop insts executed 592system.cpu.iew.exec_refs 28742996 # number of memory reference insts executed 593system.cpu.iew.exec_branches 20629033 # Number of branches executed 594system.cpu.iew.exec_stores 4918889 # Number of stores executed 595system.cpu.iew.exec_rate 0.867621 # Inst execution rate 596system.cpu.iew.wb_sent 99755826 # cumulative count of insts sent to commit 597system.cpu.iew.wb_count 99657607 # cumulative count of insts written-back 598system.cpu.iew.wb_producers 59710820 # num instructions producing a value 599system.cpu.iew.wb_consumers 95563157 # num instructions consuming a value | 601system.cpu.iew.exec_nop 12667 # number of nop insts executed 602system.cpu.iew.exec_refs 28743608 # number of memory reference insts executed 603system.cpu.iew.exec_branches 20629236 # Number of branches executed 604system.cpu.iew.exec_stores 4918943 # Number of stores executed 605system.cpu.iew.exec_rate 0.867532 # Inst execution rate 606system.cpu.iew.wb_sent 99756620 # cumulative count of insts sent to commit 607system.cpu.iew.wb_count 99658354 # cumulative count of insts written-back 608system.cpu.iew.wb_producers 59706662 # num instructions producing a value 609system.cpu.iew.wb_consumers 95558908 # num instructions consuming a value |
| 600system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 610system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 601system.cpu.iew.wb_rate 0.863393 # insts written-back per cycle 602system.cpu.iew.wb_fanout 0.624831 # average fanout of values written-back | 611system.cpu.iew.wb_rate 0.863301 # insts written-back per cycle 612system.cpu.iew.wb_fanout 0.624815 # average fanout of values written-back |
| 603system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 613system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 604system.cpu.commit.commitSquashedInsts 17390640 # The number of squashed insts skipped by commit | 614system.cpu.commit.commitSquashedInsts 17391201 # The number of squashed insts skipped by commit |
| 605system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards | 615system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards |
| 606system.cpu.commit.branchMispredicts 825698 # The number of times a branch was mispredicted 607system.cpu.commit.committed_per_cycle::samples 112714742 # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::mean 0.807824 # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::stdev 1.745908 # Number of insts commited each cycle | 616system.cpu.commit.branchMispredicts 825684 # The number of times a branch was mispredicted 617system.cpu.commit.committed_per_cycle::samples 112699801 # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::mean 0.807931 # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::stdev 1.745752 # Number of insts commited each cycle |
| 610system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 620system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 611system.cpu.commit.committed_per_cycle::0 76462569 67.84% 67.84% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::1 18443635 16.36% 84.20% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::2 7118441 6.32% 90.52% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::3 3374531 2.99% 93.51% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::4 1758227 1.56% 95.07% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::5 536893 0.48% 95.55% # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::6 726177 0.64% 96.19% # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::7 179059 0.16% 96.35% # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::8 4115210 3.65% 100.00% # Number of insts commited each cycle | 621system.cpu.commit.committed_per_cycle::0 76441556 67.83% 67.83% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::1 18447200 16.37% 84.20% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::2 7119761 6.32% 90.51% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::3 3375676 3.00% 93.51% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::4 1760831 1.56% 95.07% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::5 536786 0.48% 95.55% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::6 726119 0.64% 96.19% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::7 179056 0.16% 96.35% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::8 4112816 3.65% 100.00% # Number of insts commited each cycle |
| 620system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 630system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 623system.cpu.commit.committed_per_cycle::total 112714742 # Number of insts commited each cycle | 633system.cpu.commit.committed_per_cycle::total 112699801 # Number of insts commited each cycle |
| 624system.cpu.commit.committedInsts 90602407 # Number of instructions committed 625system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed 626system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 627system.cpu.commit.refs 27220755 # Number of memory references committed 628system.cpu.commit.loads 22475911 # Number of loads committed 629system.cpu.commit.membars 3888 # Number of memory barriers committed 630system.cpu.commit.branches 18732304 # Number of branches committed 631system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 661system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 664system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 665system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 666system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 667system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 668system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction | 634system.cpu.commit.committedInsts 90602407 # Number of instructions committed 635system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed 636system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 637system.cpu.commit.refs 27220755 # Number of memory references committed 638system.cpu.commit.loads 22475911 # Number of loads committed 639system.cpu.commit.membars 3888 # Number of memory barriers committed 640system.cpu.commit.branches 18732304 # Number of branches committed 641system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 671system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 674system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 675system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 676system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 677system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 678system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction |
| 669system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached | 679system.cpu.commit.bw_lim_events 4112816 # number cycles where commit BW limit reached |
| 670system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 680system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 671system.cpu.rob.rob_reads 217038076 # The number of ROB reads 672system.cpu.rob.rob_writes 219583065 # The number of ROB writes 673system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself 674system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling | 681system.cpu.rob.rob_reads 217026090 # The number of ROB reads 682system.cpu.rob.rob_writes 219584249 # The number of ROB writes 683system.cpu.timesIdled 586 # Number of times that the entire CPU went into an idle state and unscheduled itself 684system.cpu.idleCycles 45025 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 675system.cpu.committedInsts 90589798 # Number of Instructions Simulated 676system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated | 685system.cpu.committedInsts 90589798 # Number of Instructions Simulated 686system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated |
| 677system.cpu.cpi 1.274156 # CPI: Cycles Per Instruction 678system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads 679system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle 680system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads 681system.cpu.int_regfile_reads 108123923 # number of integer regfile reads 682system.cpu.int_regfile_writes 58738896 # number of integer regfile writes | 687system.cpu.cpi 1.274302 # CPI: Cycles Per Instruction 688system.cpu.cpi_total 1.274302 # CPI: Total CPI of All Threads 689system.cpu.ipc 0.784743 # IPC: Instructions Per Cycle 690system.cpu.ipc_total 0.784743 # IPC: Total IPC of All Threads 691system.cpu.int_regfile_reads 108125012 # number of integer regfile reads 692system.cpu.int_regfile_writes 58739124 # number of integer regfile writes |
| 683system.cpu.fp_regfile_reads 58 # number of floating regfile reads | 693system.cpu.fp_regfile_reads 58 # number of floating regfile reads |
| 684system.cpu.fp_regfile_writes 100 # number of floating regfile writes 685system.cpu.cc_regfile_reads 369252810 # number of cc regfile reads 686system.cpu.cc_regfile_writes 58698459 # number of cc regfile writes 687system.cpu.misc_regfile_reads 28460470 # number of misc regfile reads | 694system.cpu.fp_regfile_writes 99 # number of floating regfile writes 695system.cpu.cc_regfile_reads 369256929 # number of cc regfile reads 696system.cpu.cc_regfile_writes 58699332 # number of cc regfile writes 697system.cpu.misc_regfile_reads 28460693 # number of misc regfile reads |
| 688system.cpu.misc_regfile_writes 7784 # number of misc regfile writes | 698system.cpu.misc_regfile_writes 7784 # number of misc regfile writes |
| 689system.cpu.toL2Bus.trans_dist::ReadReq 5262392 # Transaction distribution 690system.cpu.toL2Bus.trans_dist::ReadResp 5262392 # Transaction distribution 691system.cpu.toL2Bus.trans_dist::Writeback 5407164 # Transaction distribution 692system.cpu.toL2Bus.trans_dist::HardPFReq 28368 # Transaction distribution 693system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 694system.cpu.toL2Bus.trans_dist::ReadExReq 225287 # Transaction distribution 695system.cpu.toL2Bus.trans_dist::ReadExResp 225287 # Transaction distribution 696system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1832 # Packet count per connected master and slave (bytes) 697system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16380692 # Packet count per connected master and slave (bytes) 698system.cpu.toL2Bus.pkt_count::total 16382524 # Packet count per connected master and slave (bytes) 699system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58624 # Cumulative packet size per connected master and slave (bytes) 700system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697211456 # Cumulative packet size per connected master and slave (bytes) 701system.cpu.toL2Bus.pkt_size::total 697270080 # Cumulative packet size per connected master and slave (bytes) 702system.cpu.toL2Bus.snoops 28370 # Total snoops (count) 703system.cpu.toL2Bus.snoop_fanout::samples 10923218 # Request fanout histogram 704system.cpu.toL2Bus.snoop_fanout::mean 5.002597 # Request fanout histogram 705system.cpu.toL2Bus.snoop_fanout::stdev 0.050895 # Request fanout histogram 706system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 707system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 708system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 709system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 710system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 711system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 712system.cpu.toL2Bus.snoop_fanout::5 10894850 99.74% 99.74% # Request fanout histogram 713system.cpu.toL2Bus.snoop_fanout::6 28368 0.26% 100.00% # Request fanout histogram 714system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 715system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 716system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 717system.cpu.toL2Bus.snoop_fanout::total 10923218 # Request fanout histogram 718system.cpu.toL2Bus.reqLayer0.occupancy 10854591744 # Layer occupancy (ticks) 719system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) 720system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) 721system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 722system.cpu.toL2Bus.respLayer0.occupancy 1387749 # Layer occupancy (ticks) 723system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 724system.cpu.toL2Bus.respLayer1.occupancy 8230203749 # Layer occupancy (ticks) 725system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) 726system.cpu.icache.tags.replacements 456 # number of replacements 727system.cpu.icache.tags.tagsinuse 432.039034 # Cycle average of tags in use 728system.cpu.icache.tags.total_refs 32315555 # Total number of references to valid blocks. 729system.cpu.icache.tags.sampled_refs 916 # Sample count of references to valid blocks. 730system.cpu.icache.tags.avg_refs 35278.990175 # Average number of references to valid blocks. 731system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 732system.cpu.icache.tags.occ_blocks::cpu.inst 432.039034 # Average occupied blocks per requestor 733system.cpu.icache.tags.occ_percent::cpu.inst 0.843826 # Average percentage of cache occupancy 734system.cpu.icache.tags.occ_percent::total 0.843826 # Average percentage of cache occupancy 735system.cpu.icache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id 736system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 737system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id 738system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id 739system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id 740system.cpu.icache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id 741system.cpu.icache.tags.tag_accesses 64634074 # Number of tag accesses 742system.cpu.icache.tags.data_accesses 64634074 # Number of data accesses 743system.cpu.icache.ReadReq_hits::cpu.inst 32315555 # number of ReadReq hits 744system.cpu.icache.ReadReq_hits::total 32315555 # number of ReadReq hits 745system.cpu.icache.demand_hits::cpu.inst 32315555 # number of demand (read+write) hits 746system.cpu.icache.demand_hits::total 32315555 # number of demand (read+write) hits 747system.cpu.icache.overall_hits::cpu.inst 32315555 # number of overall hits 748system.cpu.icache.overall_hits::total 32315555 # number of overall hits 749system.cpu.icache.ReadReq_misses::cpu.inst 1024 # number of ReadReq misses 750system.cpu.icache.ReadReq_misses::total 1024 # number of ReadReq misses 751system.cpu.icache.demand_misses::cpu.inst 1024 # number of demand (read+write) misses 752system.cpu.icache.demand_misses::total 1024 # number of demand (read+write) misses 753system.cpu.icache.overall_misses::cpu.inst 1024 # number of overall misses 754system.cpu.icache.overall_misses::total 1024 # number of overall misses 755system.cpu.icache.ReadReq_miss_latency::cpu.inst 21430236 # number of ReadReq miss cycles 756system.cpu.icache.ReadReq_miss_latency::total 21430236 # number of ReadReq miss cycles 757system.cpu.icache.demand_miss_latency::cpu.inst 21430236 # number of demand (read+write) miss cycles 758system.cpu.icache.demand_miss_latency::total 21430236 # number of demand (read+write) miss cycles 759system.cpu.icache.overall_miss_latency::cpu.inst 21430236 # number of overall miss cycles 760system.cpu.icache.overall_miss_latency::total 21430236 # number of overall miss cycles 761system.cpu.icache.ReadReq_accesses::cpu.inst 32316579 # number of ReadReq accesses(hits+misses) 762system.cpu.icache.ReadReq_accesses::total 32316579 # number of ReadReq accesses(hits+misses) 763system.cpu.icache.demand_accesses::cpu.inst 32316579 # number of demand (read+write) accesses 764system.cpu.icache.demand_accesses::total 32316579 # number of demand (read+write) accesses 765system.cpu.icache.overall_accesses::cpu.inst 32316579 # number of overall (read+write) accesses 766system.cpu.icache.overall_accesses::total 32316579 # number of overall (read+write) accesses 767system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses 768system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses 769system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses 770system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses 771system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses 772system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses 773system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.964844 # average ReadReq miss latency 774system.cpu.icache.ReadReq_avg_miss_latency::total 20927.964844 # average ReadReq miss latency 775system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency 776system.cpu.icache.demand_avg_miss_latency::total 20927.964844 # average overall miss latency 777system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency 778system.cpu.icache.overall_avg_miss_latency::total 20927.964844 # average overall miss latency 779system.cpu.icache.blocked_cycles::no_mshrs 3188 # number of cycles access was blocked 780system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 781system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked 782system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 783system.cpu.icache.avg_blocked_cycles::no_mshrs 18.752941 # average number of cycles each access was blocked 784system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 785system.cpu.icache.fast_writes 0 # number of fast writes performed 786system.cpu.icache.cache_copies 0 # number of cache copies performed 787system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits 788system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits 789system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits 790system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits 791system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits 792system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits 793system.cpu.icache.ReadReq_mshr_misses::cpu.inst 916 # number of ReadReq MSHR misses 794system.cpu.icache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses 795system.cpu.icache.demand_mshr_misses::cpu.inst 916 # number of demand (read+write) MSHR misses 796system.cpu.icache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses 797system.cpu.icache.overall_mshr_misses::cpu.inst 916 # number of overall MSHR misses 798system.cpu.icache.overall_mshr_misses::total 916 # number of overall MSHR misses 799system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17850739 # number of ReadReq MSHR miss cycles 800system.cpu.icache.ReadReq_mshr_miss_latency::total 17850739 # number of ReadReq MSHR miss cycles 801system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17850739 # number of demand (read+write) MSHR miss cycles 802system.cpu.icache.demand_mshr_miss_latency::total 17850739 # number of demand (read+write) MSHR miss cycles 803system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17850739 # number of overall MSHR miss cycles 804system.cpu.icache.overall_mshr_miss_latency::total 17850739 # number of overall MSHR miss cycles 805system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 806system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 807system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 808system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 809system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 810system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 811system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19487.706332 # average ReadReq mshr miss latency 812system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19487.706332 # average ReadReq mshr miss latency 813system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency 814system.cpu.icache.demand_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency 815system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency 816system.cpu.icache.overall_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency 817system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 818system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 8891809 # number of hwpf identified 819system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 13933 # number of hwpf that were already in mshr 820system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7995771 # number of hwpf that were already in the cache 821system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 738007 # number of hwpf that were already in the prefetch queue 822system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 823system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 118754 # number of hwpf removed because MSHR allocated 824system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 25344 # number of hwpf issued 825system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 15103327 # number of hwpf spanning a virtual page 826system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 827system.cpu.l2cache.tags.replacements 1672 # number of replacements 828system.cpu.l2cache.tags.tagsinuse 12558.688532 # Cycle average of tags in use 829system.cpu.l2cache.tags.total_refs 10641390 # Total number of references to valid blocks. 830system.cpu.l2cache.tags.sampled_refs 17530 # Sample count of references to valid blocks. 831system.cpu.l2cache.tags.avg_refs 607.038791 # Average number of references to valid blocks. 832system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 833system.cpu.l2cache.tags.occ_blocks::writebacks 10807.797190 # Average occupied blocks per requestor 834system.cpu.l2cache.tags.occ_blocks::cpu.inst 104.008842 # Average occupied blocks per requestor 835system.cpu.l2cache.tags.occ_blocks::cpu.data 299.224972 # Average occupied blocks per requestor 836system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1347.657528 # Average occupied blocks per requestor 837system.cpu.l2cache.tags.occ_percent::writebacks 0.659656 # Average percentage of cache occupancy 838system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006348 # Average percentage of cache occupancy 839system.cpu.l2cache.tags.occ_percent::cpu.data 0.018263 # Average percentage of cache occupancy 840system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082254 # Average percentage of cache occupancy 841system.cpu.l2cache.tags.occ_percent::total 0.766522 # Average percentage of cache occupancy 842system.cpu.l2cache.tags.occ_task_id_blocks::1022 1557 # Occupied blocks per task id 843system.cpu.l2cache.tags.occ_task_id_blocks::1024 14301 # Occupied blocks per task id 844system.cpu.l2cache.tags.age_task_id_blocks_1022::0 48 # Occupied blocks per task id 845system.cpu.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id 846system.cpu.l2cache.tags.age_task_id_blocks_1022::2 89 # Occupied blocks per task id 847system.cpu.l2cache.tags.age_task_id_blocks_1022::3 39 # Occupied blocks per task id 848system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1370 # Occupied blocks per task id 849system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 850system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 851system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id 852system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id 853system.cpu.l2cache.tags.age_task_id_blocks_1024::4 12200 # Occupied blocks per task id 854system.cpu.l2cache.tags.occ_task_id_percent::1022 0.095032 # Percentage of cache occupancy per task id 855system.cpu.l2cache.tags.occ_task_id_percent::1024 0.872864 # Percentage of cache occupancy per task id 856system.cpu.l2cache.tags.tag_accesses 174560305 # Number of tag accesses 857system.cpu.l2cache.tags.data_accesses 174560305 # Number of data accesses 858system.cpu.l2cache.ReadReq_hits::cpu.inst 753 # number of ReadReq hits 859system.cpu.l2cache.ReadReq_hits::cpu.data 5260483 # number of ReadReq hits 860system.cpu.l2cache.ReadReq_hits::total 5261236 # number of ReadReq hits 861system.cpu.l2cache.Writeback_hits::writebacks 5407164 # number of Writeback hits 862system.cpu.l2cache.Writeback_hits::total 5407164 # number of Writeback hits 863system.cpu.l2cache.ReadExReq_hits::cpu.data 224791 # number of ReadExReq hits 864system.cpu.l2cache.ReadExReq_hits::total 224791 # number of ReadExReq hits 865system.cpu.l2cache.demand_hits::cpu.inst 753 # number of demand (read+write) hits 866system.cpu.l2cache.demand_hits::cpu.data 5485274 # number of demand (read+write) hits 867system.cpu.l2cache.demand_hits::total 5486027 # number of demand (read+write) hits 868system.cpu.l2cache.overall_hits::cpu.inst 753 # number of overall hits 869system.cpu.l2cache.overall_hits::cpu.data 5485274 # number of overall hits 870system.cpu.l2cache.overall_hits::total 5486027 # number of overall hits 871system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses 872system.cpu.l2cache.ReadReq_misses::cpu.data 993 # number of ReadReq misses 873system.cpu.l2cache.ReadReq_misses::total 1156 # number of ReadReq misses 874system.cpu.l2cache.ReadExReq_misses::cpu.data 496 # number of ReadExReq misses 875system.cpu.l2cache.ReadExReq_misses::total 496 # number of ReadExReq misses 876system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses 877system.cpu.l2cache.demand_misses::cpu.data 1489 # number of demand (read+write) misses 878system.cpu.l2cache.demand_misses::total 1652 # number of demand (read+write) misses 879system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses 880system.cpu.l2cache.overall_misses::cpu.data 1489 # number of overall misses 881system.cpu.l2cache.overall_misses::total 1652 # number of overall misses 882system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12439500 # number of ReadReq miss cycles 883system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59393247 # number of ReadReq miss cycles 884system.cpu.l2cache.ReadReq_miss_latency::total 71832747 # number of ReadReq miss cycles 885system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31513998 # number of ReadExReq miss cycles 886system.cpu.l2cache.ReadExReq_miss_latency::total 31513998 # number of ReadExReq miss cycles 887system.cpu.l2cache.demand_miss_latency::cpu.inst 12439500 # number of demand (read+write) miss cycles 888system.cpu.l2cache.demand_miss_latency::cpu.data 90907245 # number of demand (read+write) miss cycles 889system.cpu.l2cache.demand_miss_latency::total 103346745 # number of demand (read+write) miss cycles 890system.cpu.l2cache.overall_miss_latency::cpu.inst 12439500 # number of overall miss cycles 891system.cpu.l2cache.overall_miss_latency::cpu.data 90907245 # number of overall miss cycles 892system.cpu.l2cache.overall_miss_latency::total 103346745 # number of overall miss cycles 893system.cpu.l2cache.ReadReq_accesses::cpu.inst 916 # number of ReadReq accesses(hits+misses) 894system.cpu.l2cache.ReadReq_accesses::cpu.data 5261476 # number of ReadReq accesses(hits+misses) 895system.cpu.l2cache.ReadReq_accesses::total 5262392 # number of ReadReq accesses(hits+misses) 896system.cpu.l2cache.Writeback_accesses::writebacks 5407164 # number of Writeback accesses(hits+misses) 897system.cpu.l2cache.Writeback_accesses::total 5407164 # number of Writeback accesses(hits+misses) 898system.cpu.l2cache.ReadExReq_accesses::cpu.data 225287 # number of ReadExReq accesses(hits+misses) 899system.cpu.l2cache.ReadExReq_accesses::total 225287 # number of ReadExReq accesses(hits+misses) 900system.cpu.l2cache.demand_accesses::cpu.inst 916 # number of demand (read+write) accesses 901system.cpu.l2cache.demand_accesses::cpu.data 5486763 # number of demand (read+write) accesses 902system.cpu.l2cache.demand_accesses::total 5487679 # number of demand (read+write) accesses 903system.cpu.l2cache.overall_accesses::cpu.inst 916 # number of overall (read+write) accesses 904system.cpu.l2cache.overall_accesses::cpu.data 5486763 # number of overall (read+write) accesses 905system.cpu.l2cache.overall_accesses::total 5487679 # number of overall (read+write) accesses 906system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177948 # miss rate for ReadReq accesses 907system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000189 # miss rate for ReadReq accesses 908system.cpu.l2cache.ReadReq_miss_rate::total 0.000220 # miss rate for ReadReq accesses 909system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002202 # miss rate for ReadExReq accesses 910system.cpu.l2cache.ReadExReq_miss_rate::total 0.002202 # miss rate for ReadExReq accesses 911system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177948 # miss rate for demand accesses 912system.cpu.l2cache.demand_miss_rate::cpu.data 0.000271 # miss rate for demand accesses 913system.cpu.l2cache.demand_miss_rate::total 0.000301 # miss rate for demand accesses 914system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177948 # miss rate for overall accesses 915system.cpu.l2cache.overall_miss_rate::cpu.data 0.000271 # miss rate for overall accesses 916system.cpu.l2cache.overall_miss_rate::total 0.000301 # miss rate for overall accesses 917system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76315.950920 # average ReadReq miss latency 918system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59811.930514 # average ReadReq miss latency 919system.cpu.l2cache.ReadReq_avg_miss_latency::total 62139.054498 # average ReadReq miss latency 920system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63536.286290 # average ReadExReq miss latency 921system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63536.286290 # average ReadExReq miss latency 922system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency 923system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency 924system.cpu.l2cache.demand_avg_miss_latency::total 62558.562349 # average overall miss latency 925system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency 926system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency 927system.cpu.l2cache.overall_avg_miss_latency::total 62558.562349 # average overall miss latency 928system.cpu.l2cache.blocked_cycles::no_mshrs 820 # number of cycles access was blocked 929system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 930system.cpu.l2cache.blocked::no_mshrs 50 # number of cycles access was blocked 931system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 932system.cpu.l2cache.avg_blocked_cycles::no_mshrs 16.400000 # average number of cycles each access was blocked 933system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 934system.cpu.l2cache.fast_writes 0 # number of fast writes performed 935system.cpu.l2cache.cache_copies 0 # number of cache copies performed 936system.cpu.l2cache.writebacks::writebacks 1150 # number of writebacks 937system.cpu.l2cache.writebacks::total 1150 # number of writebacks 938system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits 939system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 256 # number of ReadReq MSHR hits 940system.cpu.l2cache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits 941system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits 942system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits 943system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits 944system.cpu.l2cache.demand_mshr_hits::cpu.data 418 # number of demand (read+write) MSHR hits 945system.cpu.l2cache.demand_mshr_hits::total 442 # number of demand (read+write) MSHR hits 946system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits 947system.cpu.l2cache.overall_mshr_hits::cpu.data 418 # number of overall MSHR hits 948system.cpu.l2cache.overall_mshr_hits::total 442 # number of overall MSHR hits 949system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 139 # number of ReadReq MSHR misses 950system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 737 # number of ReadReq MSHR misses 951system.cpu.l2cache.ReadReq_mshr_misses::total 876 # number of ReadReq MSHR misses 952system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 25344 # number of HardPFReq MSHR misses 953system.cpu.l2cache.HardPFReq_mshr_misses::total 25344 # number of HardPFReq MSHR misses 954system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 334 # number of ReadExReq MSHR misses 955system.cpu.l2cache.ReadExReq_mshr_misses::total 334 # number of ReadExReq MSHR misses 956system.cpu.l2cache.demand_mshr_misses::cpu.inst 139 # number of demand (read+write) MSHR misses 957system.cpu.l2cache.demand_mshr_misses::cpu.data 1071 # number of demand (read+write) MSHR misses 958system.cpu.l2cache.demand_mshr_misses::total 1210 # number of demand (read+write) MSHR misses 959system.cpu.l2cache.overall_mshr_misses::cpu.inst 139 # number of overall MSHR misses 960system.cpu.l2cache.overall_mshr_misses::cpu.data 1071 # number of overall MSHR misses 961system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 25344 # number of overall MSHR misses 962system.cpu.l2cache.overall_mshr_misses::total 26554 # number of overall MSHR misses 963system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10286000 # number of ReadReq MSHR miss cycles 964system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41114499 # number of ReadReq MSHR miss cycles 965system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51400499 # number of ReadReq MSHR miss cycles 966system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of HardPFReq MSHR miss cycles 967system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 910618800 # number of HardPFReq MSHR miss cycles 968system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 20873252 # number of ReadExReq MSHR miss cycles 969system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 20873252 # number of ReadExReq MSHR miss cycles 970system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10286000 # number of demand (read+write) MSHR miss cycles 971system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61987751 # number of demand (read+write) MSHR miss cycles 972system.cpu.l2cache.demand_mshr_miss_latency::total 72273751 # number of demand (read+write) MSHR miss cycles 973system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10286000 # number of overall MSHR miss cycles 974system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61987751 # number of overall MSHR miss cycles 975system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of overall MSHR miss cycles 976system.cpu.l2cache.overall_mshr_miss_latency::total 982892551 # number of overall MSHR miss cycles 977system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for ReadReq accesses 978system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000140 # mshr miss rate for ReadReq accesses 979system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000166 # mshr miss rate for ReadReq accesses 980system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 981system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 982system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001483 # mshr miss rate for ReadExReq accesses 983system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001483 # mshr miss rate for ReadExReq accesses 984system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for demand accesses 985system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for demand accesses 986system.cpu.l2cache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses 987system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for overall accesses 988system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for overall accesses 989system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 990system.cpu.l2cache.overall_mshr_miss_rate::total 0.004839 # mshr miss rate for overall accesses 991system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74000 # average ReadReq mshr miss latency 992system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55786.294437 # average ReadReq mshr miss latency 993system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58676.368721 # average ReadReq mshr miss latency 994system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average HardPFReq mshr miss latency 995system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35930.350379 # average HardPFReq mshr miss latency 996system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62494.766467 # average ReadExReq mshr miss latency 997system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62494.766467 # average ReadExReq mshr miss latency 998system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency 999system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency 1000system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59730.372727 # average overall mshr miss latency 1001system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency 1002system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency 1003system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average overall mshr miss latency 1004system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37014.858439 # average overall mshr miss latency 1005system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1006system.cpu.dcache.tags.replacements 5486251 # number of replacements 1007system.cpu.dcache.tags.tagsinuse 511.841559 # Cycle average of tags in use 1008system.cpu.dcache.tags.total_refs 18271309 # Total number of references to valid blocks. 1009system.cpu.dcache.tags.sampled_refs 5486763 # Sample count of references to valid blocks. 1010system.cpu.dcache.tags.avg_refs 3.330071 # Average number of references to valid blocks. 1011system.cpu.dcache.tags.warmup_cycle 27123000 # Cycle when the warmup percentage was hit. 1012system.cpu.dcache.tags.occ_blocks::cpu.data 511.841559 # Average occupied blocks per requestor 1013system.cpu.dcache.tags.occ_percent::cpu.data 0.999691 # Average percentage of cache occupancy 1014system.cpu.dcache.tags.occ_percent::total 0.999691 # Average percentage of cache occupancy | 699system.cpu.dcache.tags.replacements 5486247 # number of replacements 700system.cpu.dcache.tags.tagsinuse 511.800439 # Cycle average of tags in use 701system.cpu.dcache.tags.total_refs 18271247 # Total number of references to valid blocks. 702system.cpu.dcache.tags.sampled_refs 5486759 # Sample count of references to valid blocks. 703system.cpu.dcache.tags.avg_refs 3.330062 # Average number of references to valid blocks. 704system.cpu.dcache.tags.warmup_cycle 33236000 # Cycle when the warmup percentage was hit. 705system.cpu.dcache.tags.occ_blocks::cpu.data 511.800439 # Average occupied blocks per requestor 706system.cpu.dcache.tags.occ_percent::cpu.data 0.999610 # Average percentage of cache occupancy 707system.cpu.dcache.tags.occ_percent::total 0.999610 # Average percentage of cache occupancy |
| 1015system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 708system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1016system.cpu.dcache.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id 1017system.cpu.dcache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id | 709system.cpu.dcache.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id 710system.cpu.dcache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id |
| 1018system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 711system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1019system.cpu.dcache.tags.tag_accesses 61969579 # Number of tag accesses 1020system.cpu.dcache.tags.data_accesses 61969579 # Number of data accesses 1021system.cpu.dcache.ReadReq_hits::cpu.data 13905693 # number of ReadReq hits 1022system.cpu.dcache.ReadReq_hits::total 13905693 # number of ReadReq hits 1023system.cpu.dcache.WriteReq_hits::cpu.data 4357334 # number of WriteReq hits 1024system.cpu.dcache.WriteReq_hits::total 4357334 # number of WriteReq hits | 712system.cpu.dcache.tags.tag_accesses 61970439 # Number of tag accesses 713system.cpu.dcache.tags.data_accesses 61970439 # Number of data accesses 714system.cpu.dcache.ReadReq_hits::cpu.data 13905626 # number of ReadReq hits 715system.cpu.dcache.ReadReq_hits::total 13905626 # number of ReadReq hits 716system.cpu.dcache.WriteReq_hits::cpu.data 4357324 # number of WriteReq hits 717system.cpu.dcache.WriteReq_hits::total 4357324 # number of WriteReq hits |
| 1025system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 1026system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits | 718system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 719system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits |
| 1027system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits 1028system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits | 720system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits 721system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits |
| 1029system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 1030system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits | 722system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 723system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits |
| 1031system.cpu.dcache.demand_hits::cpu.data 18263027 # number of demand (read+write) hits 1032system.cpu.dcache.demand_hits::total 18263027 # number of demand (read+write) hits 1033system.cpu.dcache.overall_hits::cpu.data 18263549 # number of overall hits 1034system.cpu.dcache.overall_hits::total 18263549 # number of overall hits 1035system.cpu.dcache.ReadReq_misses::cpu.data 9592430 # number of ReadReq misses 1036system.cpu.dcache.ReadReq_misses::total 9592430 # number of ReadReq misses 1037system.cpu.dcache.WriteReq_misses::cpu.data 377647 # number of WriteReq misses 1038system.cpu.dcache.WriteReq_misses::total 377647 # number of WriteReq misses | 724system.cpu.dcache.demand_hits::cpu.data 18262950 # number of demand (read+write) hits 725system.cpu.dcache.demand_hits::total 18262950 # number of demand (read+write) hits 726system.cpu.dcache.overall_hits::cpu.data 18263472 # number of overall hits 727system.cpu.dcache.overall_hits::total 18263472 # number of overall hits 728system.cpu.dcache.ReadReq_misses::cpu.data 9592929 # number of ReadReq misses 729system.cpu.dcache.ReadReq_misses::total 9592929 # number of ReadReq misses 730system.cpu.dcache.WriteReq_misses::cpu.data 377657 # number of WriteReq misses 731system.cpu.dcache.WriteReq_misses::total 377657 # number of WriteReq misses |
| 1039system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses 1040system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses | 732system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses 733system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses |
| 1041system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses 1042system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses 1043system.cpu.dcache.demand_misses::cpu.data 9970077 # number of demand (read+write) misses 1044system.cpu.dcache.demand_misses::total 9970077 # number of demand (read+write) misses 1045system.cpu.dcache.overall_misses::cpu.data 9970085 # number of overall misses 1046system.cpu.dcache.overall_misses::total 9970085 # number of overall misses 1047system.cpu.dcache.ReadReq_miss_latency::cpu.data 87035855746 # number of ReadReq miss cycles 1048system.cpu.dcache.ReadReq_miss_latency::total 87035855746 # number of ReadReq miss cycles 1049system.cpu.dcache.WriteReq_miss_latency::cpu.data 3957576177 # number of WriteReq miss cycles 1050system.cpu.dcache.WriteReq_miss_latency::total 3957576177 # number of WriteReq miss cycles 1051system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 283250 # number of LoadLockedReq miss cycles 1052system.cpu.dcache.LoadLockedReq_miss_latency::total 283250 # number of LoadLockedReq miss cycles 1053system.cpu.dcache.demand_miss_latency::cpu.data 90993431923 # number of demand (read+write) miss cycles 1054system.cpu.dcache.demand_miss_latency::total 90993431923 # number of demand (read+write) miss cycles 1055system.cpu.dcache.overall_miss_latency::cpu.data 90993431923 # number of overall miss cycles 1056system.cpu.dcache.overall_miss_latency::total 90993431923 # number of overall miss cycles 1057system.cpu.dcache.ReadReq_accesses::cpu.data 23498123 # number of ReadReq accesses(hits+misses) 1058system.cpu.dcache.ReadReq_accesses::total 23498123 # number of ReadReq accesses(hits+misses) | 734system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses 735system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses 736system.cpu.dcache.demand_misses::cpu.data 9970586 # number of demand (read+write) misses 737system.cpu.dcache.demand_misses::total 9970586 # number of demand (read+write) misses 738system.cpu.dcache.overall_misses::cpu.data 9970594 # number of overall misses 739system.cpu.dcache.overall_misses::total 9970594 # number of overall misses 740system.cpu.dcache.ReadReq_miss_latency::cpu.data 87008583027 # number of ReadReq miss cycles 741system.cpu.dcache.ReadReq_miss_latency::total 87008583027 # number of ReadReq miss cycles 742system.cpu.dcache.WriteReq_miss_latency::cpu.data 3975903343 # number of WriteReq miss cycles 743system.cpu.dcache.WriteReq_miss_latency::total 3975903343 # number of WriteReq miss cycles 744system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 269500 # number of LoadLockedReq miss cycles 745system.cpu.dcache.LoadLockedReq_miss_latency::total 269500 # number of LoadLockedReq miss cycles 746system.cpu.dcache.demand_miss_latency::cpu.data 90984486370 # number of demand (read+write) miss cycles 747system.cpu.dcache.demand_miss_latency::total 90984486370 # number of demand (read+write) miss cycles 748system.cpu.dcache.overall_miss_latency::cpu.data 90984486370 # number of overall miss cycles 749system.cpu.dcache.overall_miss_latency::total 90984486370 # number of overall miss cycles 750system.cpu.dcache.ReadReq_accesses::cpu.data 23498555 # number of ReadReq accesses(hits+misses) 751system.cpu.dcache.ReadReq_accesses::total 23498555 # number of ReadReq accesses(hits+misses) |
| 1059system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 1060system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 1061system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses) 1062system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses) 1063system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 1064system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 1065system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 1066system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) | 752system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 753system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 754system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses) 755system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses) 756system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 757system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 758system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 759system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) |
| 1067system.cpu.dcache.demand_accesses::cpu.data 28233104 # number of demand (read+write) accesses 1068system.cpu.dcache.demand_accesses::total 28233104 # number of demand (read+write) accesses 1069system.cpu.dcache.overall_accesses::cpu.data 28233634 # number of overall (read+write) accesses 1070system.cpu.dcache.overall_accesses::total 28233634 # number of overall (read+write) accesses 1071system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408221 # miss rate for ReadReq accesses 1072system.cpu.dcache.ReadReq_miss_rate::total 0.408221 # miss rate for ReadReq accesses 1073system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079757 # miss rate for WriteReq accesses 1074system.cpu.dcache.WriteReq_miss_rate::total 0.079757 # miss rate for WriteReq accesses | 760system.cpu.dcache.demand_accesses::cpu.data 28233536 # number of demand (read+write) accesses 761system.cpu.dcache.demand_accesses::total 28233536 # number of demand (read+write) accesses 762system.cpu.dcache.overall_accesses::cpu.data 28234066 # number of overall (read+write) accesses 763system.cpu.dcache.overall_accesses::total 28234066 # number of overall (read+write) accesses 764system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408235 # miss rate for ReadReq accesses 765system.cpu.dcache.ReadReq_miss_rate::total 0.408235 # miss rate for ReadReq accesses 766system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses 767system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses |
| 1075system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses 1076system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses | 768system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses 769system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses |
| 1077system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses 1078system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses 1079system.cpu.dcache.demand_miss_rate::cpu.data 0.353134 # miss rate for demand accesses 1080system.cpu.dcache.demand_miss_rate::total 0.353134 # miss rate for demand accesses 1081system.cpu.dcache.overall_miss_rate::cpu.data 0.353128 # miss rate for overall accesses 1082system.cpu.dcache.overall_miss_rate::total 0.353128 # miss rate for overall accesses 1083system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9073.389719 # average ReadReq miss latency 1084system.cpu.dcache.ReadReq_avg_miss_latency::total 9073.389719 # average ReadReq miss latency 1085system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10479.564718 # average WriteReq miss latency 1086system.cpu.dcache.WriteReq_avg_miss_latency::total 10479.564718 # average WriteReq miss latency 1087system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20232.142857 # average LoadLockedReq miss latency 1088system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20232.142857 # average LoadLockedReq miss latency 1089system.cpu.dcache.demand_avg_miss_latency::cpu.data 9126.652876 # average overall miss latency 1090system.cpu.dcache.demand_avg_miss_latency::total 9126.652876 # average overall miss latency 1091system.cpu.dcache.overall_avg_miss_latency::cpu.data 9126.645552 # average overall miss latency 1092system.cpu.dcache.overall_avg_miss_latency::total 9126.645552 # average overall miss latency 1093system.cpu.dcache.blocked_cycles::no_mshrs 301384 # number of cycles access was blocked 1094system.cpu.dcache.blocked_cycles::no_targets 67125 # number of cycles access was blocked 1095system.cpu.dcache.blocked::no_mshrs 120500 # number of cycles access was blocked 1096system.cpu.dcache.blocked::no_targets 12183 # number of cycles access was blocked 1097system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.501112 # average number of cycles each access was blocked 1098system.cpu.dcache.avg_blocked_cycles::no_targets 5.509727 # average number of cycles each access was blocked | 770system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses 771system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses 772system.cpu.dcache.demand_miss_rate::cpu.data 0.353147 # miss rate for demand accesses 773system.cpu.dcache.demand_miss_rate::total 0.353147 # miss rate for demand accesses 774system.cpu.dcache.overall_miss_rate::cpu.data 0.353141 # miss rate for overall accesses 775system.cpu.dcache.overall_miss_rate::total 0.353141 # miss rate for overall accesses 776system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9070.074742 # average ReadReq miss latency 777system.cpu.dcache.ReadReq_avg_miss_latency::total 9070.074742 # average ReadReq miss latency 778system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10527.815830 # average WriteReq miss latency 779system.cpu.dcache.WriteReq_avg_miss_latency::total 10527.815830 # average WriteReq miss latency 780system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17966.666667 # average LoadLockedReq miss latency 781system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17966.666667 # average LoadLockedReq miss latency 782system.cpu.dcache.demand_avg_miss_latency::cpu.data 9125.289764 # average overall miss latency 783system.cpu.dcache.demand_avg_miss_latency::total 9125.289764 # average overall miss latency 784system.cpu.dcache.overall_avg_miss_latency::cpu.data 9125.282443 # average overall miss latency 785system.cpu.dcache.overall_avg_miss_latency::total 9125.282443 # average overall miss latency 786system.cpu.dcache.blocked_cycles::no_mshrs 301798 # number of cycles access was blocked 787system.cpu.dcache.blocked_cycles::no_targets 69284 # number of cycles access was blocked 788system.cpu.dcache.blocked::no_mshrs 120550 # number of cycles access was blocked 789system.cpu.dcache.blocked::no_targets 12191 # number of cycles access was blocked 790system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.503509 # average number of cycles each access was blocked 791system.cpu.dcache.avg_blocked_cycles::no_targets 5.683209 # average number of cycles each access was blocked |
| 1099system.cpu.dcache.fast_writes 0 # number of fast writes performed 1100system.cpu.dcache.cache_copies 0 # number of cache copies performed | 792system.cpu.dcache.fast_writes 0 # number of fast writes performed 793system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1101system.cpu.dcache.writebacks::writebacks 5407164 # number of writebacks 1102system.cpu.dcache.writebacks::total 5407164 # number of writebacks 1103system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328464 # number of ReadReq MSHR hits 1104system.cpu.dcache.ReadReq_mshr_hits::total 4328464 # number of ReadReq MSHR hits 1105system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154855 # number of WriteReq MSHR hits 1106system.cpu.dcache.WriteReq_mshr_hits::total 154855 # number of WriteReq MSHR hits 1107system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits 1108system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits 1109system.cpu.dcache.demand_mshr_hits::cpu.data 4483319 # number of demand (read+write) MSHR hits 1110system.cpu.dcache.demand_mshr_hits::total 4483319 # number of demand (read+write) MSHR hits 1111system.cpu.dcache.overall_mshr_hits::cpu.data 4483319 # number of overall MSHR hits 1112system.cpu.dcache.overall_mshr_hits::total 4483319 # number of overall MSHR hits 1113system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263966 # number of ReadReq MSHR misses 1114system.cpu.dcache.ReadReq_mshr_misses::total 5263966 # number of ReadReq MSHR misses 1115system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222792 # number of WriteReq MSHR misses 1116system.cpu.dcache.WriteReq_mshr_misses::total 222792 # number of WriteReq MSHR misses | 794system.cpu.dcache.writebacks::writebacks 5460017 # number of writebacks 795system.cpu.dcache.writebacks::total 5460017 # number of writebacks 796system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328962 # number of ReadReq MSHR hits 797system.cpu.dcache.ReadReq_mshr_hits::total 4328962 # number of ReadReq MSHR hits 798system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154868 # number of WriteReq MSHR hits 799system.cpu.dcache.WriteReq_mshr_hits::total 154868 # number of WriteReq MSHR hits 800system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits 801system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits 802system.cpu.dcache.demand_mshr_hits::cpu.data 4483830 # number of demand (read+write) MSHR hits 803system.cpu.dcache.demand_mshr_hits::total 4483830 # number of demand (read+write) MSHR hits 804system.cpu.dcache.overall_mshr_hits::cpu.data 4483830 # number of overall MSHR hits 805system.cpu.dcache.overall_mshr_hits::total 4483830 # number of overall MSHR hits 806system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263967 # number of ReadReq MSHR misses 807system.cpu.dcache.ReadReq_mshr_misses::total 5263967 # number of ReadReq MSHR misses 808system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222789 # number of WriteReq MSHR misses 809system.cpu.dcache.WriteReq_mshr_misses::total 222789 # number of WriteReq MSHR misses |
| 1117system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses 1118system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses | 810system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses 811system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses |
| 1119system.cpu.dcache.demand_mshr_misses::cpu.data 5486758 # number of demand (read+write) MSHR misses 1120system.cpu.dcache.demand_mshr_misses::total 5486758 # number of demand (read+write) MSHR misses 1121system.cpu.dcache.overall_mshr_misses::cpu.data 5486763 # number of overall MSHR misses 1122system.cpu.dcache.overall_mshr_misses::total 5486763 # number of overall MSHR misses 1123system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38232328002 # number of ReadReq MSHR miss cycles 1124system.cpu.dcache.ReadReq_mshr_miss_latency::total 38232328002 # number of ReadReq MSHR miss cycles 1125system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2158774283 # number of WriteReq MSHR miss cycles 1126system.cpu.dcache.WriteReq_mshr_miss_latency::total 2158774283 # number of WriteReq MSHR miss cycles 1127system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 284500 # number of SoftPFReq MSHR miss cycles 1128system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 284500 # number of SoftPFReq MSHR miss cycles 1129system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40391102285 # number of demand (read+write) MSHR miss cycles 1130system.cpu.dcache.demand_mshr_miss_latency::total 40391102285 # number of demand (read+write) MSHR miss cycles 1131system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40391386785 # number of overall MSHR miss cycles 1132system.cpu.dcache.overall_mshr_miss_latency::total 40391386785 # number of overall MSHR miss cycles 1133system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224016 # mshr miss rate for ReadReq accesses 1134system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224016 # mshr miss rate for ReadReq accesses | 812system.cpu.dcache.demand_mshr_misses::cpu.data 5486756 # number of demand (read+write) MSHR misses 813system.cpu.dcache.demand_mshr_misses::total 5486756 # number of demand (read+write) MSHR misses 814system.cpu.dcache.overall_mshr_misses::cpu.data 5486761 # number of overall MSHR misses 815system.cpu.dcache.overall_mshr_misses::total 5486761 # number of overall MSHR misses 816system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38199288241 # number of ReadReq MSHR miss cycles 817system.cpu.dcache.ReadReq_mshr_miss_latency::total 38199288241 # number of ReadReq MSHR miss cycles 818system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2164503781 # number of WriteReq MSHR miss cycles 819system.cpu.dcache.WriteReq_mshr_miss_latency::total 2164503781 # number of WriteReq MSHR miss cycles 820system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 250500 # number of SoftPFReq MSHR miss cycles 821system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 250500 # number of SoftPFReq MSHR miss cycles 822system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40363792022 # number of demand (read+write) MSHR miss cycles 823system.cpu.dcache.demand_mshr_miss_latency::total 40363792022 # number of demand (read+write) MSHR miss cycles 824system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40364042522 # number of overall MSHR miss cycles 825system.cpu.dcache.overall_mshr_miss_latency::total 40364042522 # number of overall MSHR miss cycles 826system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224012 # mshr miss rate for ReadReq accesses 827system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224012 # mshr miss rate for ReadReq accesses |
| 1135system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses 1136system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses 1137system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses 1138system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses | 828system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses 829system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses 830system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses 831system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses |
| 1139system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194338 # mshr miss rate for demand accesses 1140system.cpu.dcache.demand_mshr_miss_rate::total 0.194338 # mshr miss rate for demand accesses 1141system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194334 # mshr miss rate for overall accesses 1142system.cpu.dcache.overall_mshr_miss_rate::total 0.194334 # mshr miss rate for overall accesses 1143system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7263.027155 # average ReadReq mshr miss latency 1144system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7263.027155 # average ReadReq mshr miss latency 1145system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9689.640036 # average WriteReq mshr miss latency 1146system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9689.640036 # average WriteReq mshr miss latency 1147system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56900 # average SoftPFReq mshr miss latency 1148system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56900 # average SoftPFReq mshr miss latency 1149system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7361.560740 # average overall mshr miss latency 1150system.cpu.dcache.demand_avg_mshr_miss_latency::total 7361.560740 # average overall mshr miss latency 1151system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7361.605884 # average overall mshr miss latency 1152system.cpu.dcache.overall_avg_mshr_miss_latency::total 7361.605884 # average overall mshr miss latency | 832system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194335 # mshr miss rate for demand accesses 833system.cpu.dcache.demand_mshr_miss_rate::total 0.194335 # mshr miss rate for demand accesses 834system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194331 # mshr miss rate for overall accesses 835system.cpu.dcache.overall_mshr_miss_rate::total 0.194331 # mshr miss rate for overall accesses 836system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7256.749186 # average ReadReq mshr miss latency 837system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7256.749186 # average ReadReq mshr miss latency 838system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9715.487663 # average WriteReq mshr miss latency 839system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9715.487663 # average WriteReq mshr miss latency 840system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50100 # average SoftPFReq mshr miss latency 841system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50100 # average SoftPFReq mshr miss latency 842system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7356.585936 # average overall mshr miss latency 843system.cpu.dcache.demand_avg_mshr_miss_latency::total 7356.585936 # average overall mshr miss latency 844system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7356.624887 # average overall mshr miss latency 845system.cpu.dcache.overall_avg_mshr_miss_latency::total 7356.624887 # average overall mshr miss latency |
| 1153system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 846system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 847system.cpu.icache.tags.replacements 447 # number of replacements 848system.cpu.icache.tags.tagsinuse 428.924531 # Cycle average of tags in use 849system.cpu.icache.tags.total_refs 32314402 # Total number of references to valid blocks. 850system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. 851system.cpu.icache.tags.avg_refs 35667.110375 # Average number of references to valid blocks. 852system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 853system.cpu.icache.tags.occ_blocks::cpu.inst 428.924531 # Average occupied blocks per requestor 854system.cpu.icache.tags.occ_percent::cpu.inst 0.837743 # Average percentage of cache occupancy 855system.cpu.icache.tags.occ_percent::total 0.837743 # Average percentage of cache occupancy 856system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id 857system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 858system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 859system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id 860system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id 861system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id 862system.cpu.icache.tags.tag_accesses 64631998 # Number of tag accesses 863system.cpu.icache.tags.data_accesses 64631998 # Number of data accesses 864system.cpu.icache.ReadReq_hits::cpu.inst 32314402 # number of ReadReq hits 865system.cpu.icache.ReadReq_hits::total 32314402 # number of ReadReq hits 866system.cpu.icache.demand_hits::cpu.inst 32314402 # number of demand (read+write) hits 867system.cpu.icache.demand_hits::total 32314402 # number of demand (read+write) hits 868system.cpu.icache.overall_hits::cpu.inst 32314402 # number of overall hits 869system.cpu.icache.overall_hits::total 32314402 # number of overall hits 870system.cpu.icache.ReadReq_misses::cpu.inst 1144 # number of ReadReq misses 871system.cpu.icache.ReadReq_misses::total 1144 # number of ReadReq misses 872system.cpu.icache.demand_misses::cpu.inst 1144 # number of demand (read+write) misses 873system.cpu.icache.demand_misses::total 1144 # number of demand (read+write) misses 874system.cpu.icache.overall_misses::cpu.inst 1144 # number of overall misses 875system.cpu.icache.overall_misses::total 1144 # number of overall misses 876system.cpu.icache.ReadReq_miss_latency::cpu.inst 55657984 # number of ReadReq miss cycles 877system.cpu.icache.ReadReq_miss_latency::total 55657984 # number of ReadReq miss cycles 878system.cpu.icache.demand_miss_latency::cpu.inst 55657984 # number of demand (read+write) miss cycles 879system.cpu.icache.demand_miss_latency::total 55657984 # number of demand (read+write) miss cycles 880system.cpu.icache.overall_miss_latency::cpu.inst 55657984 # number of overall miss cycles 881system.cpu.icache.overall_miss_latency::total 55657984 # number of overall miss cycles 882system.cpu.icache.ReadReq_accesses::cpu.inst 32315546 # number of ReadReq accesses(hits+misses) 883system.cpu.icache.ReadReq_accesses::total 32315546 # number of ReadReq accesses(hits+misses) 884system.cpu.icache.demand_accesses::cpu.inst 32315546 # number of demand (read+write) accesses 885system.cpu.icache.demand_accesses::total 32315546 # number of demand (read+write) accesses 886system.cpu.icache.overall_accesses::cpu.inst 32315546 # number of overall (read+write) accesses 887system.cpu.icache.overall_accesses::total 32315546 # number of overall (read+write) accesses 888system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses 889system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses 890system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses 891system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses 892system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses 893system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses 894system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48652.083916 # average ReadReq miss latency 895system.cpu.icache.ReadReq_avg_miss_latency::total 48652.083916 # average ReadReq miss latency 896system.cpu.icache.demand_avg_miss_latency::cpu.inst 48652.083916 # average overall miss latency 897system.cpu.icache.demand_avg_miss_latency::total 48652.083916 # average overall miss latency 898system.cpu.icache.overall_avg_miss_latency::cpu.inst 48652.083916 # average overall miss latency 899system.cpu.icache.overall_avg_miss_latency::total 48652.083916 # average overall miss latency 900system.cpu.icache.blocked_cycles::no_mshrs 17056 # number of cycles access was blocked 901system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked 902system.cpu.icache.blocked::no_mshrs 223 # number of cycles access was blocked 903system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 904system.cpu.icache.avg_blocked_cycles::no_mshrs 76.484305 # average number of cycles each access was blocked 905system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked 906system.cpu.icache.fast_writes 0 # number of fast writes performed 907system.cpu.icache.cache_copies 0 # number of cache copies performed 908system.cpu.icache.ReadReq_mshr_hits::cpu.inst 238 # number of ReadReq MSHR hits 909system.cpu.icache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits 910system.cpu.icache.demand_mshr_hits::cpu.inst 238 # number of demand (read+write) MSHR hits 911system.cpu.icache.demand_mshr_hits::total 238 # number of demand (read+write) MSHR hits 912system.cpu.icache.overall_mshr_hits::cpu.inst 238 # number of overall MSHR hits 913system.cpu.icache.overall_mshr_hits::total 238 # number of overall MSHR hits 914system.cpu.icache.ReadReq_mshr_misses::cpu.inst 906 # number of ReadReq MSHR misses 915system.cpu.icache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses 916system.cpu.icache.demand_mshr_misses::cpu.inst 906 # number of demand (read+write) MSHR misses 917system.cpu.icache.demand_mshr_misses::total 906 # number of demand (read+write) MSHR misses 918system.cpu.icache.overall_mshr_misses::cpu.inst 906 # number of overall MSHR misses 919system.cpu.icache.overall_mshr_misses::total 906 # number of overall MSHR misses 920system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44276742 # number of ReadReq MSHR miss cycles 921system.cpu.icache.ReadReq_mshr_miss_latency::total 44276742 # number of ReadReq MSHR miss cycles 922system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44276742 # number of demand (read+write) MSHR miss cycles 923system.cpu.icache.demand_mshr_miss_latency::total 44276742 # number of demand (read+write) MSHR miss cycles 924system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44276742 # number of overall MSHR miss cycles 925system.cpu.icache.overall_mshr_miss_latency::total 44276742 # number of overall MSHR miss cycles 926system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 927system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 928system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 929system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 930system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 931system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 932system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48870.576159 # average ReadReq mshr miss latency 933system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48870.576159 # average ReadReq mshr miss latency 934system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency 935system.cpu.icache.demand_avg_mshr_miss_latency::total 48870.576159 # average overall mshr miss latency 936system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency 937system.cpu.icache.overall_avg_mshr_miss_latency::total 48870.576159 # average overall mshr miss latency 938system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 939system.cpu.l2cache.prefetcher.num_hwpf_issued 4494242 # number of hwpf issued 940system.cpu.l2cache.prefetcher.pfIdentified 5296949 # number of prefetch candidates identified 941system.cpu.l2cache.prefetcher.pfBufferHit 693182 # number of redundant prefetches already in prefetch queue 942system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 943system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 944system.cpu.l2cache.prefetcher.pfSpanPage 14114027 # number of prefetches not generated due to page crossing 945system.cpu.l2cache.tags.replacements 432 # number of replacements 946system.cpu.l2cache.tags.tagsinuse 12071.451375 # Cycle average of tags in use 947system.cpu.l2cache.tags.total_refs 10694296 # Total number of references to valid blocks. 948system.cpu.l2cache.tags.sampled_refs 15874 # Sample count of references to valid blocks. 949system.cpu.l2cache.tags.avg_refs 673.698879 # Average number of references to valid blocks. 950system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 951system.cpu.l2cache.tags.occ_blocks::writebacks 11103.819168 # Average occupied blocks per requestor 952system.cpu.l2cache.tags.occ_blocks::cpu.inst 569.155490 # Average occupied blocks per requestor 953system.cpu.l2cache.tags.occ_blocks::cpu.data 195.974498 # Average occupied blocks per requestor 954system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 202.502218 # Average occupied blocks per requestor 955system.cpu.l2cache.tags.occ_percent::writebacks 0.677723 # Average percentage of cache occupancy 956system.cpu.l2cache.tags.occ_percent::cpu.inst 0.034738 # Average percentage of cache occupancy 957system.cpu.l2cache.tags.occ_percent::cpu.data 0.011961 # Average percentage of cache occupancy 958system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.012360 # Average percentage of cache occupancy 959system.cpu.l2cache.tags.occ_percent::total 0.736783 # Average percentage of cache occupancy 960system.cpu.l2cache.tags.occ_task_id_blocks::1022 240 # Occupied blocks per task id 961system.cpu.l2cache.tags.occ_task_id_blocks::1024 15202 # Occupied blocks per task id 962system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id 963system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 964system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id 965system.cpu.l2cache.tags.age_task_id_blocks_1022::3 5 # Occupied blocks per task id 966system.cpu.l2cache.tags.age_task_id_blocks_1022::4 214 # Occupied blocks per task id 967system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 968system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 969system.cpu.l2cache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id 970system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1059 # Occupied blocks per task id 971system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13108 # Occupied blocks per task id 972system.cpu.l2cache.tags.occ_task_id_percent::1022 0.014648 # Percentage of cache occupancy per task id 973system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927856 # Percentage of cache occupancy per task id 974system.cpu.l2cache.tags.tag_accesses 175404109 # Number of tag accesses 975system.cpu.l2cache.tags.data_accesses 175404109 # Number of data accesses 976system.cpu.l2cache.ReadReq_hits::cpu.inst 211 # number of ReadReq hits 977system.cpu.l2cache.ReadReq_hits::cpu.data 5261084 # number of ReadReq hits 978system.cpu.l2cache.ReadReq_hits::total 5261295 # number of ReadReq hits 979system.cpu.l2cache.Writeback_hits::writebacks 5460017 # number of Writeback hits 980system.cpu.l2cache.Writeback_hits::total 5460017 # number of Writeback hits 981system.cpu.l2cache.ReadExReq_hits::cpu.data 224780 # number of ReadExReq hits 982system.cpu.l2cache.ReadExReq_hits::total 224780 # number of ReadExReq hits 983system.cpu.l2cache.demand_hits::cpu.inst 211 # number of demand (read+write) hits 984system.cpu.l2cache.demand_hits::cpu.data 5485864 # number of demand (read+write) hits 985system.cpu.l2cache.demand_hits::total 5486075 # number of demand (read+write) hits 986system.cpu.l2cache.overall_hits::cpu.inst 211 # number of overall hits 987system.cpu.l2cache.overall_hits::cpu.data 5485864 # number of overall hits 988system.cpu.l2cache.overall_hits::total 5486075 # number of overall hits 989system.cpu.l2cache.ReadReq_misses::cpu.inst 695 # number of ReadReq misses 990system.cpu.l2cache.ReadReq_misses::cpu.data 386 # number of ReadReq misses 991system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses 992system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 993system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 994system.cpu.l2cache.ReadExReq_misses::cpu.data 509 # number of ReadExReq misses 995system.cpu.l2cache.ReadExReq_misses::total 509 # number of ReadExReq misses 996system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses 997system.cpu.l2cache.demand_misses::cpu.data 895 # number of demand (read+write) misses 998system.cpu.l2cache.demand_misses::total 1590 # number of demand (read+write) misses 999system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses 1000system.cpu.l2cache.overall_misses::cpu.data 895 # number of overall misses 1001system.cpu.l2cache.overall_misses::total 1590 # number of overall misses 1002system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42529250 # number of ReadReq miss cycles 1003system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21068985 # number of ReadReq miss cycles 1004system.cpu.l2cache.ReadReq_miss_latency::total 63598235 # number of ReadReq miss cycles 1005system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30498 # number of UpgradeReq miss cycles 1006system.cpu.l2cache.UpgradeReq_miss_latency::total 30498 # number of UpgradeReq miss cycles 1007system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 34497490 # number of ReadExReq miss cycles 1008system.cpu.l2cache.ReadExReq_miss_latency::total 34497490 # number of ReadExReq miss cycles 1009system.cpu.l2cache.demand_miss_latency::cpu.inst 42529250 # number of demand (read+write) miss cycles 1010system.cpu.l2cache.demand_miss_latency::cpu.data 55566475 # number of demand (read+write) miss cycles 1011system.cpu.l2cache.demand_miss_latency::total 98095725 # number of demand (read+write) miss cycles 1012system.cpu.l2cache.overall_miss_latency::cpu.inst 42529250 # number of overall miss cycles 1013system.cpu.l2cache.overall_miss_latency::cpu.data 55566475 # number of overall miss cycles 1014system.cpu.l2cache.overall_miss_latency::total 98095725 # number of overall miss cycles 1015system.cpu.l2cache.ReadReq_accesses::cpu.inst 906 # number of ReadReq accesses(hits+misses) 1016system.cpu.l2cache.ReadReq_accesses::cpu.data 5261470 # number of ReadReq accesses(hits+misses) 1017system.cpu.l2cache.ReadReq_accesses::total 5262376 # number of ReadReq accesses(hits+misses) 1018system.cpu.l2cache.Writeback_accesses::writebacks 5460017 # number of Writeback accesses(hits+misses) 1019system.cpu.l2cache.Writeback_accesses::total 5460017 # number of Writeback accesses(hits+misses) 1020system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 1021system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 1022system.cpu.l2cache.ReadExReq_accesses::cpu.data 225289 # number of ReadExReq accesses(hits+misses) 1023system.cpu.l2cache.ReadExReq_accesses::total 225289 # number of ReadExReq accesses(hits+misses) 1024system.cpu.l2cache.demand_accesses::cpu.inst 906 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.data 5486759 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::total 5487665 # number of demand (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.inst 906 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.data 5486759 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::total 5487665 # number of overall (read+write) accesses 1030system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.767108 # miss rate for ReadReq accesses 1031system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000073 # miss rate for ReadReq accesses 1032system.cpu.l2cache.ReadReq_miss_rate::total 0.000205 # miss rate for ReadReq accesses 1033system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1034system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1035system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002259 # miss rate for ReadExReq accesses 1036system.cpu.l2cache.ReadExReq_miss_rate::total 0.002259 # miss rate for ReadExReq accesses 1037system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767108 # miss rate for demand accesses 1038system.cpu.l2cache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses 1039system.cpu.l2cache.demand_miss_rate::total 0.000290 # miss rate for demand accesses 1040system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767108 # miss rate for overall accesses 1041system.cpu.l2cache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses 1042system.cpu.l2cache.overall_miss_rate::total 0.000290 # miss rate for overall accesses 1043system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61193.165468 # average ReadReq miss latency 1044system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54582.862694 # average ReadReq miss latency 1045system.cpu.l2cache.ReadReq_avg_miss_latency::total 58832.779833 # average ReadReq miss latency 1046system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15249 # average UpgradeReq miss latency 1047system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15249 # average UpgradeReq miss latency 1048system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67775.029470 # average ReadExReq miss latency 1049system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67775.029470 # average ReadExReq miss latency 1050system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61193.165468 # average overall miss latency 1051system.cpu.l2cache.demand_avg_miss_latency::cpu.data 62085.446927 # average overall miss latency 1052system.cpu.l2cache.demand_avg_miss_latency::total 61695.424528 # average overall miss latency 1053system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61193.165468 # average overall miss latency 1054system.cpu.l2cache.overall_avg_miss_latency::cpu.data 62085.446927 # average overall miss latency 1055system.cpu.l2cache.overall_avg_miss_latency::total 61695.424528 # average overall miss latency 1056system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1057system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1058system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1059system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1060system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1061system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1062system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1063system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1064system.cpu.l2cache.writebacks::writebacks 309 # number of writebacks 1065system.cpu.l2cache.writebacks::total 309 # number of writebacks 1066system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1067system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits 1068system.cpu.l2cache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits 1069system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 168 # number of ReadExReq MSHR hits 1070system.cpu.l2cache.ReadExReq_mshr_hits::total 168 # number of ReadExReq MSHR hits 1071system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1072system.cpu.l2cache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits 1073system.cpu.l2cache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits 1074system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1075system.cpu.l2cache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits 1076system.cpu.l2cache.overall_mshr_hits::total 214 # number of overall MSHR hits 1077system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 694 # number of ReadReq MSHR misses 1078system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 341 # number of ReadReq MSHR misses 1079system.cpu.l2cache.ReadReq_mshr_misses::total 1035 # number of ReadReq MSHR misses 1080system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20230 # number of HardPFReq MSHR misses 1081system.cpu.l2cache.HardPFReq_mshr_misses::total 20230 # number of HardPFReq MSHR misses 1082system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 1083system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 1084system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses 1085system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses 1086system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses 1087system.cpu.l2cache.demand_mshr_misses::cpu.data 682 # number of demand (read+write) MSHR misses 1088system.cpu.l2cache.demand_mshr_misses::total 1376 # number of demand (read+write) MSHR misses 1089system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses 1090system.cpu.l2cache.overall_mshr_misses::cpu.data 682 # number of overall MSHR misses 1091system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20230 # number of overall MSHR misses 1092system.cpu.l2cache.overall_mshr_misses::total 21606 # number of overall MSHR misses 1093system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36534500 # number of ReadReq MSHR miss cycles 1094system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16113750 # number of ReadReq MSHR miss cycles 1095system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52648250 # number of ReadReq MSHR miss cycles 1096system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of HardPFReq MSHR miss cycles 1097system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 777111161 # number of HardPFReq MSHR miss cycles 1098system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles 1099system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles 1100system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 22591778 # number of ReadExReq MSHR miss cycles 1101system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 22591778 # number of ReadExReq MSHR miss cycles 1102system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36534500 # number of demand (read+write) MSHR miss cycles 1103system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 38705528 # number of demand (read+write) MSHR miss cycles 1104system.cpu.l2cache.demand_mshr_miss_latency::total 75240028 # number of demand (read+write) MSHR miss cycles 1105system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36534500 # number of overall MSHR miss cycles 1106system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 38705528 # number of overall MSHR miss cycles 1107system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of overall MSHR miss cycles 1108system.cpu.l2cache.overall_mshr_miss_latency::total 852351189 # number of overall MSHR miss cycles 1109system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for ReadReq accesses 1110system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for ReadReq accesses 1111system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000197 # mshr miss rate for ReadReq accesses 1112system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1113system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1114system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1115system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1116system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses 1117system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses 1118system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for demand accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for demand accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::total 0.000251 # mshr miss rate for demand accesses 1121system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for overall accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for overall accesses 1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::total 0.003937 # mshr miss rate for overall accesses 1125system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52643.371758 # average ReadReq mshr miss latency 1126system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47254.398827 # average ReadReq mshr miss latency 1127system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50867.874396 # average ReadReq mshr miss latency 1128system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average HardPFReq mshr miss latency 1129system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38413.799357 # average HardPFReq mshr miss latency 1130system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 1131system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency 1132system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66251.548387 # average ReadExReq mshr miss latency 1133system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66251.548387 # average ReadExReq mshr miss latency 1134system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency 1135system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency 1136system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54680.252907 # average overall mshr miss latency 1137system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency 1138system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39449.744932 # average overall mshr miss latency 1141system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1142system.cpu.toL2Bus.trans_dist::ReadReq 5262376 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::ReadResp 5262376 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::Writeback 5460017 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::HardPFReq 22339 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 1147system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 1148system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 1149system.cpu.toL2Bus.trans_dist::ReadExReq 225289 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::ReadExResp 225289 # Transaction distribution 1151system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1812 # Packet count per connected master and slave (bytes) 1152system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16433541 # Packet count per connected master and slave (bytes) 1153system.cpu.toL2Bus.pkt_count::total 16435353 # Packet count per connected master and slave (bytes) 1154system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57984 # Cumulative packet size per connected master and slave (bytes) 1155system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700593792 # Cumulative packet size per connected master and slave (bytes) 1156system.cpu.toL2Bus.pkt_size::total 700651776 # Cumulative packet size per connected master and slave (bytes) 1157system.cpu.toL2Bus.snoops 22341 # Total snoops (count) 1158system.cpu.toL2Bus.snoop_fanout::samples 10970023 # Request fanout histogram 1159system.cpu.toL2Bus.snoop_fanout::mean 5.002036 # Request fanout histogram 1160system.cpu.toL2Bus.snoop_fanout::stdev 0.045080 # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1162system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1163system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::5 10947684 99.80% 99.80% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::6 22339 0.20% 100.00% # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::total 10970023 # Request fanout histogram 1173system.cpu.toL2Bus.reqLayer0.occupancy 10933859000 # Layer occupancy (ticks) 1174system.cpu.toL2Bus.reqLayer0.utilization 18.9 # Layer utilization (%) 1175system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) 1176system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1177system.cpu.toL2Bus.respLayer0.occupancy 1479748 # Layer occupancy (ticks) 1178system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1179system.cpu.toL2Bus.respLayer1.occupancy 8230187517 # Layer occupancy (ticks) 1180system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) 1181system.membus.trans_dist::ReadReq 15531 # Transaction distribution 1182system.membus.trans_dist::ReadResp 15531 # Transaction distribution 1183system.membus.trans_dist::Writeback 309 # Transaction distribution 1184system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 1185system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1186system.membus.trans_dist::ReadExReq 341 # Transaction distribution 1187system.membus.trans_dist::ReadExResp 341 # Transaction distribution 1188system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32057 # Packet count per connected master and slave (bytes) 1189system.membus.pkt_count::total 32057 # Packet count per connected master and slave (bytes) 1190system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1035584 # Cumulative packet size per connected master and slave (bytes) 1191system.membus.pkt_size::total 1035584 # Cumulative packet size per connected master and slave (bytes) 1192system.membus.snoops 0 # Total snoops (count) 1193system.membus.snoop_fanout::samples 16183 # Request fanout histogram 1194system.membus.snoop_fanout::mean 0 # Request fanout histogram 1195system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1196system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1197system.membus.snoop_fanout::0 16183 100.00% 100.00% # Request fanout histogram 1198system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1199system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1200system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1201system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1202system.membus.snoop_fanout::total 16183 # Request fanout histogram 1203system.membus.reqLayer0.occupancy 28002068 # Layer occupancy (ticks) 1204system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1205system.membus.respLayer1.occupancy 149256371 # Layer occupancy (ticks) 1206system.membus.respLayer1.utilization 0.3 # Layer utilization (%) |
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| 1154 1155---------- End Simulation Statistics ---------- | 1207 1208---------- End Simulation Statistics ---------- |