7,11c7,11
< host_inst_rate 184396 # Simulator instruction rate (inst/s)
< host_op_rate 185720 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 54518089 # Simulator tick rate (ticks/s)
< host_mem_usage 410024 # Number of bytes of host memory used
< host_seconds 491.33 # Real time elapsed on the host
---
> host_inst_rate 55091 # Simulator instruction rate (inst/s)
> host_op_rate 55487 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 16288150 # Simulator tick rate (ticks/s)
> host_mem_usage 365372 # Number of bytes of host memory used
> host_seconds 1644.53 # Real time elapsed on the host
73c73
< system.physmem.totGap 26786185500 # Total gap between requests
---
> system.physmem.totGap 26786186500 # Total gap between requests
167,168c167,168
< system.physmem.totQLat 45050979 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 279102979 # Sum of mem lat for all requests
---
> system.physmem.totQLat 45051479 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 279103479 # Sum of mem lat for all requests
171c171
< system.physmem.avgQLat 2904.27 # Average queueing delay per request
---
> system.physmem.avgQLat 2904.30 # Average queueing delay per request
174c174
< system.physmem.avgMemAccLat 17992.71 # Average memory access latency
---
> system.physmem.avgMemAccLat 17992.75 # Average memory access latency
187c187
< system.physmem.avgGap 1726804.12 # Average gap between requests
---
> system.physmem.avgGap 1726804.18 # Average gap between requests
242c242
< system.cpu.fetch.icacheStallCycles 14169802 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 14169803 # Number of cycles fetch is stalled on an Icache miss
248,249c248,249
< system.cpu.fetch.BlockedCycles 11256916 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.BlockedCycles 11256917 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
252,254c252,254
< system.cpu.fetch.CacheLines 13841949 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 329938 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 53360207 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 13841950 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 53360208 # Number of instructions fetched each cycle (Total)
258c258
< system.cpu.fetch.rateDist::0 29366337 55.03% 55.03% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 29366338 55.03% 55.03% # Number of instructions fetched each cycle (Total)
270c270
< system.cpu.fetch.rateDist::total 53360207 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 53360208 # Number of instructions fetched each cycle (Total)
274c274
< system.cpu.decode.BlockedCycles 9104448 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 9104449 # Number of cycles decode is blocked
286c286
< system.cpu.rename.RunCycles 21547168 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 21547169 # Number of cycles rename is running
288c288
< system.cpu.rename.RenamedInsts 123140443 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 123140444 # Number of instructions processed by rename
293,295c293,295
< system.cpu.rename.RenamedOperands 143600920 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 536395589 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 536390601 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 143600921 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 536395593 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 536390605 # Number of integer rename lookups
298c298
< system.cpu.rename.UndoneMaps 36171438 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 36171439 # Number of HB maps that are undone due to squashing
313c313
< system.cpu.iq.issued_per_cycle::samples 53360207 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 53360208 # Number of insts issued each cycle
317c317
< system.cpu.iq.issued_per_cycle::0 15336122 28.74% 28.74% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 15336123 28.74% 28.74% # Number of insts issued each cycle
329c329
< system.cpu.iq.issued_per_cycle::total 53360207 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 53360208 # Number of insts issued each cycle
402c402
< system.cpu.iq.int_inst_queue_reads 264421445 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 264421446 # Number of integer instruction queue reads
425c425
< system.cpu.iew.iewDispSquashedInsts 309093 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 309094 # Number of squashed instructions skipped by dispatch
487c487
< system.cpu.idleCycles 212523 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 212522 # Total number of cycles that the CPU has spent unscheduled due to idling
516,533c516,533
< system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses
< system.cpu.icache.overall_misses::total 983 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 48291499 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 48291499 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 48291499 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 48291499 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 48291499 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 48291499 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 13841948 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 13841948 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 13841948 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 13841948 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 13841948 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 13841948 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses
> system.cpu.icache.overall_misses::total 984 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 48362499 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 48362499 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 48362499 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 48362499 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 48362499 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 48362499 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 13841949 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 13841949 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 13841949 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 13841949 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 13841949 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 13841949 # number of overall (read+write) accesses
540,545c540,545
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49126.652085 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 49126.652085 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 49126.652085 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 49126.652085 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49148.881098 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 49148.881098 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 49148.881098 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 49148.881098 # average overall miss latency
554,559c554,559
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits
585,710d584
< system.cpu.dcache.replacements 943495 # number of replacements
< system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
< system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
< system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
< system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
< system.cpu.dcache.writebacks::total 942892 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
753,754c627,628
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14541500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 50282500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14542000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 50283000 # number of ReadReq miss cycles
758,759c632,633
< system.cpu.l2cache.demand_miss_latency::cpu.data 617353000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 653094000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 617353500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 653094500 # number of demand (read+write) miss cycles
761,762c635,636
< system.cpu.l2cache.overall_miss_latency::cpu.data 617353000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 653094000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 617353500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 653094500 # number of overall miss cycles
792,793c666,667
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52496.389892 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.223350 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52498.194946 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.730964 # average ReadReq miss latency
797,798c671,672
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 42072.666366 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 42072.698576 # average overall miss latency
800,801c674,675
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 42072.666366 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 42072.698576 # average overall miss latency
832c706
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819084 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819584 # number of ReadReq MSHR miss cycles
834c708
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602463 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602963 # number of ReadReq MSHR miss cycles
839c713
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819084 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819584 # number of demand (read+write) MSHR miss cycles
841,842c715,716
< system.cpu.l2cache.demand_mshr_miss_latency::total 458402805 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819084 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 458403305 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819584 # number of overall MSHR miss cycles
844c718
< system.cpu.l2cache.overall_mshr_miss_latency::total 458402805 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 458403305 # number of overall MSHR miss cycles
858c732
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37933.640736 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37934.347949 # average ReadReq mshr miss latency
860c734
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.224846 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.738193 # average ReadReq mshr miss latency
865c739
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
867,868c741,742
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
870c744
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency
871a746,871
> system.cpu.dcache.replacements 943495 # number of replacements
> system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
> system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
> system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
> system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880184000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 13880184000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 19250281404 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 19250281404 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 19250281404 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 19250281404 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782919 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782919 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14043.038478 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14043.038478 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
> system.cpu.dcache.writebacks::total 942892 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989578000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989578000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120952 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10947120952 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120952 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10947120952 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.342542 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.342542 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< host_inst_rate 184396 # Simulator instruction rate (inst/s)
< host_op_rate 185720 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 54518089 # Simulator tick rate (ticks/s)
< host_mem_usage 410024 # Number of bytes of host memory used
< host_seconds 491.33 # Real time elapsed on the host
---
> host_inst_rate 55091 # Simulator instruction rate (inst/s)
> host_op_rate 55487 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 16288150 # Simulator tick rate (ticks/s)
> host_mem_usage 365372 # Number of bytes of host memory used
> host_seconds 1644.53 # Real time elapsed on the host
73c73
< system.physmem.totGap 26786185500 # Total gap between requests
---
> system.physmem.totGap 26786186500 # Total gap between requests
167,168c167,168
< system.physmem.totQLat 45050979 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 279102979 # Sum of mem lat for all requests
---
> system.physmem.totQLat 45051479 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 279103479 # Sum of mem lat for all requests
171c171
< system.physmem.avgQLat 2904.27 # Average queueing delay per request
---
> system.physmem.avgQLat 2904.30 # Average queueing delay per request
174c174
< system.physmem.avgMemAccLat 17992.71 # Average memory access latency
---
> system.physmem.avgMemAccLat 17992.75 # Average memory access latency
187c187
< system.physmem.avgGap 1726804.12 # Average gap between requests
---
> system.physmem.avgGap 1726804.18 # Average gap between requests
242c242
< system.cpu.fetch.icacheStallCycles 14169802 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 14169803 # Number of cycles fetch is stalled on an Icache miss
248,249c248,249
< system.cpu.fetch.BlockedCycles 11256916 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.BlockedCycles 11256917 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
252,254c252,254
< system.cpu.fetch.CacheLines 13841949 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 329938 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 53360207 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 13841950 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 53360208 # Number of instructions fetched each cycle (Total)
258c258
< system.cpu.fetch.rateDist::0 29366337 55.03% 55.03% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 29366338 55.03% 55.03% # Number of instructions fetched each cycle (Total)
270c270
< system.cpu.fetch.rateDist::total 53360207 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 53360208 # Number of instructions fetched each cycle (Total)
274c274
< system.cpu.decode.BlockedCycles 9104448 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 9104449 # Number of cycles decode is blocked
286c286
< system.cpu.rename.RunCycles 21547168 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 21547169 # Number of cycles rename is running
288c288
< system.cpu.rename.RenamedInsts 123140443 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 123140444 # Number of instructions processed by rename
293,295c293,295
< system.cpu.rename.RenamedOperands 143600920 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 536395589 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 536390601 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 143600921 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 536395593 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 536390605 # Number of integer rename lookups
298c298
< system.cpu.rename.UndoneMaps 36171438 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 36171439 # Number of HB maps that are undone due to squashing
313c313
< system.cpu.iq.issued_per_cycle::samples 53360207 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 53360208 # Number of insts issued each cycle
317c317
< system.cpu.iq.issued_per_cycle::0 15336122 28.74% 28.74% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 15336123 28.74% 28.74% # Number of insts issued each cycle
329c329
< system.cpu.iq.issued_per_cycle::total 53360207 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 53360208 # Number of insts issued each cycle
402c402
< system.cpu.iq.int_inst_queue_reads 264421445 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 264421446 # Number of integer instruction queue reads
425c425
< system.cpu.iew.iewDispSquashedInsts 309093 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 309094 # Number of squashed instructions skipped by dispatch
487c487
< system.cpu.idleCycles 212523 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 212522 # Total number of cycles that the CPU has spent unscheduled due to idling
516,533c516,533
< system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses
< system.cpu.icache.overall_misses::total 983 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 48291499 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 48291499 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 48291499 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 48291499 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 48291499 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 48291499 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 13841948 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 13841948 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 13841948 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 13841948 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 13841948 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 13841948 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses
> system.cpu.icache.overall_misses::total 984 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 48362499 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 48362499 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 48362499 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 48362499 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 48362499 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 48362499 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 13841949 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 13841949 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 13841949 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 13841949 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 13841949 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 13841949 # number of overall (read+write) accesses
540,545c540,545
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49126.652085 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 49126.652085 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 49126.652085 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 49126.652085 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49148.881098 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 49148.881098 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 49148.881098 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 49148.881098 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 49148.881098 # average overall miss latency
554,559c554,559
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits
585,710d584
< system.cpu.dcache.replacements 943495 # number of replacements
< system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
< system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
< system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
< system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880183500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 13880183500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 19250280904 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 19250280904 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 19250280904 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 19250280904 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782492 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782492 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14043.038113 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
< system.cpu.dcache.writebacks::total 942892 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989577500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989577500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120452 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10947120452 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120452 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10947120452 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.341989 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.341989 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.530830 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.530830 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
753,754c627,628
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14541500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 50282500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14542000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 50283000 # number of ReadReq miss cycles
758,759c632,633
< system.cpu.l2cache.demand_miss_latency::cpu.data 617353000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 653094000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 617353500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 653094500 # number of demand (read+write) miss cycles
761,762c635,636
< system.cpu.l2cache.overall_miss_latency::cpu.data 617353000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 653094000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 617353500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 653094500 # number of overall miss cycles
792,793c666,667
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52496.389892 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.223350 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52498.194946 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 51048.730964 # average ReadReq miss latency
797,798c671,672
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 42072.666366 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 42072.698576 # average overall miss latency
800,801c674,675
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.806615 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 42072.666366 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41670.840364 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 42072.698576 # average overall miss latency
832c706
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819084 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26819584 # number of ReadReq MSHR miss cycles
834c708
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602463 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37602963 # number of ReadReq MSHR miss cycles
839c713
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819084 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26819584 # number of demand (read+write) MSHR miss cycles
841,842c715,716
< system.cpu.l2cache.demand_mshr_miss_latency::total 458402805 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819084 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 458403305 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26819584 # number of overall MSHR miss cycles
844c718
< system.cpu.l2cache.overall_mshr_miss_latency::total 458402805 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 458403305 # number of overall MSHR miss cycles
858c732
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37933.640736 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37934.347949 # average ReadReq mshr miss latency
860c734
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.224846 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.738193 # average ReadReq mshr miss latency
865c739
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
867,868c741,742
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37934.347949 # average overall mshr miss latency
870c744
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.528172 # average overall mshr miss latency
871a746,871
> system.cpu.dcache.replacements 943495 # number of replacements
> system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
> system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 23596473 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23596473 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4537302 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4537302 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 28133775 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 28133775 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 28133775 # number of overall hits
> system.cpu.dcache.overall_hits::total 28133775 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1173127 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1173127 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 197679 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 197679 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1370806 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1370806 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1370806 # number of overall misses
> system.cpu.dcache.overall_misses::total 1370806 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880184000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 13880184000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5370097404 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5370097404 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 19250281404 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 19250281404 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 19250281404 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 19250281404 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24769600 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24769600 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 29504581 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 29504581 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 29504581 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 29504581 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047362 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.047362 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041749 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.041749 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.046461 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.046461 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.046461 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.046461 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.782919 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.782919 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27165.745496 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 27165.745496 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14043.038478 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038478 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14043.038478 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 152379 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 23821 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.396835 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks
> system.cpu.dcache.writebacks::total 942892 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269039 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 269039 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154172 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 154172 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 423211 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 423211 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 423211 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 423211 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904088 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 904088 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43507 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 43507 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 947595 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 947595 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 947595 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 947595 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9989578000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9989578000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 957542952 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 957542952 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947120952 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10947120952 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947120952 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10947120952 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036500 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036500 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009188 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009188 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.032117 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032117 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.032117 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11049.342542 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11049.342542 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22008.939987 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22008.939987 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11552.531358 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11552.531358 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate