3,5c3,5
< sim_seconds 0.058675 # Number of seconds simulated
< sim_ticks 58675371500 # Number of ticks simulated
< final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.058681 # Number of seconds simulated
> sim_ticks 58681066500 # Number of ticks simulated
> final_tick 58681066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 241655 # Simulator instruction rate (inst/s)
< host_op_rate 242858 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 156520643 # Simulator tick rate (ticks/s)
< host_mem_usage 492304 # Number of bytes of host memory used
< host_seconds 374.87 # Real time elapsed on the host
---
> host_inst_rate 243006 # Simulator instruction rate (inst/s)
> host_op_rate 244216 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 157411271 # Simulator tick rate (ticks/s)
> host_mem_usage 492224 # Number of bytes of host memory used
> host_seconds 372.79 # Real time elapsed on the host
16,49c16,49
< system.physmem.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 218240 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 923072 # Number of bytes read from this memory
< system.physmem.bytes_read::total 1186048 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6656 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 3410 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 14423 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 18532 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 104 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 762432 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3719448 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 15731848 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 20213728 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 762432 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 762432 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 113438 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 113438 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 113438 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 762432 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3719448 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 15731848 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 20327166 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 18533 # Number of read requests accepted
< system.physmem.writeReqs 104 # Number of write requests accepted
< system.physmem.readBursts 18533 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 104 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 1180480 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 219520 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 922368 # Number of bytes read from this memory
> system.physmem.bytes_read::total 1186688 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6784 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6784 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 3430 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 14412 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 18542 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 106 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 106 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 763449 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3740900 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 15718324 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 20222673 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 763449 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 763449 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 115608 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 115608 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 115608 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 763449 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3740900 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 15718324 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 20338281 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 18543 # Number of read requests accepted
> system.physmem.writeReqs 106 # Number of write requests accepted
> system.physmem.readBursts 18543 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 106 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 1180544 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue
51,54c51,54
< system.physmem.bytesReadSys 1186112 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 6656 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bytesReadSys 1186752 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6784 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one
58c58
< system.physmem.perBankRdBursts::2 952 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 954 # Per bank write bursts
61,63c61,63
< system.physmem.perBankRdBursts::5 1118 # Per bank write bursts
< system.physmem.perBankRdBursts::6 1097 # Per bank write bursts
< system.physmem.perBankRdBursts::7 1096 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 1115 # Per bank write bursts
> system.physmem.perBankRdBursts::6 1093 # Per bank write bursts
> system.physmem.perBankRdBursts::7 1100 # Per bank write bursts
66c66
< system.physmem.perBankRdBursts::10 932 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 933 # Per bank write bursts
71,72c71,72
< system.physmem.perBankRdBursts::15 903 # Per bank write bursts
< system.physmem.perBankWrBursts::0 0 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 904 # Per bank write bursts
> system.physmem.perBankWrBursts::0 2 # Per bank write bursts
74,75c74,75
< system.physmem.perBankWrBursts::2 3 # Per bank write bursts
< system.physmem.perBankWrBursts::3 3 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 0 # Per bank write bursts
> system.physmem.perBankWrBursts::3 0 # Per bank write bursts
77,79c77,79
< system.physmem.perBankWrBursts::5 10 # Per bank write bursts
< system.physmem.perBankWrBursts::6 15 # Per bank write bursts
< system.physmem.perBankWrBursts::7 0 # Per bank write bursts
---
> system.physmem.perBankWrBursts::5 8 # Per bank write bursts
> system.physmem.perBankWrBursts::6 10 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7 # Per bank write bursts
83c83
< system.physmem.perBankWrBursts::11 3 # Per bank write bursts
---
> system.physmem.perBankWrBursts::11 0 # Per bank write bursts
86,87c86,87
< system.physmem.perBankWrBursts::14 7 # Per bank write bursts
< system.physmem.perBankWrBursts::15 0 # Per bank write bursts
---
> system.physmem.perBankWrBursts::14 8 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6 # Per bank write bursts
90c90
< system.physmem.totGap 58675363000 # Total gap between requests
---
> system.physmem.totGap 58681058000 # Total gap between requests
97c97
< system.physmem.readPktSize::6 18533 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 18543 # Read request sizes (log2)
104,114c104,114
< system.physmem.writePktSize::6 104 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 12556 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 3396 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 314 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 300 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 296 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 280 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 99 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 106 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 12536 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 3413 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 499 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 407 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 316 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 299 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 297 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 278 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 100 # What read queue length does an incoming req see
165c165
< system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see
201,214c201,214
< system.physmem.bytesPerActivate::samples 2974 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 397.815736 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 217.392167 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 406.651837 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 841 28.28% 28.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 992 33.36% 61.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 92 3.09% 64.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 59 1.98% 66.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 59 1.98% 68.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 62 2.08% 70.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 53 1.78% 72.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 59 1.98% 74.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 757 25.45% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 2974 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 2972 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 398.104980 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 217.970166 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 405.874685 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 839 28.23% 28.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 987 33.21% 61.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 89 2.99% 64.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 64 2.15% 66.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 64 2.15% 68.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 65 2.19% 70.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 54 1.82% 72.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 55 1.85% 74.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 755 25.40% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 2972 # Bytes accessed per row activation
216,218c216,218
< system.physmem.rdPerTurnAround::mean 4542 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 1434.998534 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 7438.956513 # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::mean 4544.500000 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 1447.547305 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 7502.381200 # Reads before turning the bus around for writes
228,231c228,231
< system.physmem.totQLat 819558662 # Total ticks spent queuing
< system.physmem.totMemAccLat 1165402412 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 92225000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 44432.57 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 829373528 # Total ticks spent queuing
> system.physmem.totMemAccLat 1175236028 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 92230000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 44962.24 # Average queueing delay per DRAM burst
233c233
< system.physmem.avgMemAccLat 63182.57 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 63712.24 # Average memory access latency per DRAM burst
236,237c236,237
< system.physmem.avgRdBWSys 20.21 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 0.11 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 20.22 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 0.12 # Average system write bandwidth in MiByte/s
242,293c242,293
< system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 17.01 # Average write queue length when enqueuing
< system.physmem.readRowHits 15523 # Number of row buffer hits during reads
< system.physmem.writeRowHits 12 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 84.16 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 11.88 # Row buffer hit rate for writes
< system.physmem.avgGap 3148326.61 # Average gap between requests
< system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 15986460 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 8481825 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 75141360 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 224460 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 1848222480.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 457291620 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 99494880 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 3995273070 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 3179264640 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 10079734425 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 19762775190 # Total energy per rank (pJ)
< system.physmem_0.averagePower 336.815504 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 57405272063 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 196297250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 786242000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 40364411250 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 8279321820 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 287560187 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 8761538993 # Time in different power states
< system.physmem_1.actEnergy 5305020 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2804505 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 56548800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 151380 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 250773120.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 129702360 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 13640160 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 769421340 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 250623360 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 13483521390 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 14962606875 # Total energy per rank (pJ)
< system.physmem_1.averagePower 255.006594 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 58353889098 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 22210250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 106530000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 56015166500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 652672389 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 191421152 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 1687371209 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 28234010 # Number of BP lookups
< system.cpu.branchPred.condPredicted 23266490 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 835433 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 11829728 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 11748003 # Number of BTB hits
---
> system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 19.34 # Average write queue length when enqueuing
> system.physmem.readRowHits 15527 # Number of row buffer hits during reads
> system.physmem.writeRowHits 11 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 84.18 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 11.00 # Row buffer hit rate for writes
> system.physmem.avgGap 3146606.15 # Average gap between requests
> system.physmem.pageHitRate 83.78 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 15943620 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 8459055 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 75134220 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 203580 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 1849451760.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 458311920 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 99516480 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 3997068570 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 3182851200 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 10077393330 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 19767987555 # Total energy per rank (pJ)
> system.physmem_0.averagePower 336.871642 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 57408712347 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 196273000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 786774000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 40354533250 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 8288648060 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 289307153 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 8765531037 # Time in different power states
> system.physmem_1.actEnergy 5333580 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2819685 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 56563080 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 172260 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 259378080.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 131548590 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 14205120 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 785395590 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 262919520 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 13470232590 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 14988765045 # Total energy per rank (pJ)
> system.physmem_1.averagePower 255.427603 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 58353780091 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 23548250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 110212000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 55948105250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 684663397 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 192205159 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 1722332444 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 28234239 # Number of BP lookups
> system.cpu.branchPred.condPredicted 23266690 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 835421 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 11829840 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 11748052 # Number of BTB hits
295,296c295,296
< system.cpu.branchPred.BTBHitPct 99.309156 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 74546 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 99.308630 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 74543 # Number of times the RAS was used to get a target.
298,300c298,300
< system.cpu.branchPred.indirectLookups 27219 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 25475 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 1744 # Number of indirect misses.
---
> system.cpu.branchPred.indirectLookups 27224 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 25476 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 1748 # Number of indirect misses.
303c303
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
333c333
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
363c363
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
393c393
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
424,425c424,425
< system.cpu.pwrStateResidencyTicks::ON 58675371500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 117350744 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 58681066500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 117362134 # number of cpu cycles simulated
428,440c428,440
< system.cpu.fetch.icacheStallCycles 746331 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 134908246 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 28234010 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 11848024 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 115699810 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1674291 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 849 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.IcacheWaitRetryStallCycles 926 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 32275670 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 568 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 117285061 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.155401 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.317679 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 746504 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 134908625 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 28234239 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 11848071 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 115710996 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1674249 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.IcacheWaitRetryStallCycles 948 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 32275841 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 117296446 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.155292 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.317650 # Number of instructions fetched each cycle (Total)
442,445c442,445
< system.cpu.fetch.rateDist::0 59749210 50.94% 50.94% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 13933958 11.88% 62.82% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 9228354 7.87% 70.69% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 34373539 29.31% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 59759710 50.95% 50.95% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 13934020 11.88% 62.83% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 9230571 7.87% 70.70% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 34372145 29.30% 100.00% # Number of instructions fetched each cycle (Total)
449,457c449,457
< system.cpu.fetch.rateDist::total 117285061 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.240595 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.149616 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 8835265 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 65049836 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 33012809 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 9561722 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 825429 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 4097911 # Number of times decode resolved a branch
---
> system.cpu.fetch.rateDist::total 117296446 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.240574 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.149507 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 8834504 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 65062525 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 33013030 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 9560979 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 825408 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 4097904 # Number of times decode resolved a branch
459,476c459,476
< system.cpu.decode.DecodedInsts 114395758 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 1985288 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 825429 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 15272092 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 50298480 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 112986 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 35409562 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 15366512 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 110872789 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 1412207 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 11133815 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 1555614 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 2094363 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 506230 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 129945991 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 483154289 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 119447702 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups
---
> system.cpu.decode.DecodedInsts 114396314 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1984657 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 825408 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 15270391 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 50319403 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 113009 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 35408802 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 15359433 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 110873352 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 1412133 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 11133960 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 1550028 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 2088318 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 507009 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 129946854 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 483157007 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 119448195 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups
478c478
< system.cpu.rename.UndoneMaps 22633072 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 22633935 # Number of HB maps that are undone due to squashing
481,486c481,486
< system.cpu.rename.skidInsts 21514760 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 26805262 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 5347320 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 521988 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 256188 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 109667585 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.rename.skidInsts 21513701 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 26805540 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 5347415 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 519015 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 253842 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 109668195 # Number of instructions added to the IQ (excludes non-spec)
488,491c488,491
< system.cpu.iq.iqInstsIssued 101366888 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 1074694 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 18634838 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 41670017 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 101366364 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 1074602 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 18635448 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 41675725 # Number of squashed operands that are examined and possibly removed from graph
493,495c493,495
< system.cpu.iq.issued_per_cycle::samples 117285061 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.864278 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.988233 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 117296446 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.864190 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.988217 # Number of insts issued each cycle
497,502c497,502
< system.cpu.iq.issued_per_cycle::0 55650042 47.45% 47.45% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 31364266 26.74% 74.19% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 22008003 18.76% 92.95% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 7064697 6.02% 98.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 1197740 1.02% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 55661536 47.45% 47.45% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 31364227 26.74% 74.19% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 22008293 18.76% 92.96% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 7064324 6.02% 98.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1197751 1.02% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 315 0.00% 100.00% # Number of insts issued each cycle
509c509
< system.cpu.iq.issued_per_cycle::total 117285061 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 117296446 # Number of insts issued each cycle
511,543c511,543
< system.cpu.iq.fu_full::IntAlu 9783493 48.67% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 9615891 47.83% 96.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 702910 3.50% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 9780929 48.66% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 50 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 9614642 47.84% 96.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 702971 3.50% 100.00% # attempts to use FU when none available
549c549
< system.cpu.iq.FU_type_0::IntAlu 71970995 71.00% 71.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 71970702 71.00% 71.00% # Type of FU issued
574c574
< system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatCvt 57 0.00% 71.01% # Type of FU issued
580,581c580,581
< system.cpu.iq.FU_type_0::MemRead 24337764 24.01% 95.02% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 5047220 4.98% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 24337480 24.01% 95.02% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 5047270 4.98% 100.00% # Type of FU issued
586,598c586,598
< system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued
< system.cpu.iq.rate 0.863794 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 20102384 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 467 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 247 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 101366364 # Type of FU issued
> system.cpu.iq.rate 0.863706 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 20098632 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.198277 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 341201935 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 128312613 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 99607782 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 473 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 121464746 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 288157 # Number of loads that had data forwarded from stores
600,603c600,603
< system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 602476 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 4329629 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 1502 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 1344 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 602571 # Number of stores squashed
607c607
< system.cpu.iew.lsq.thread0.cacheBlocked 130798 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 130792 # Number of times an access to memory failed due to the cache being blocked
609,612c609,612
< system.cpu.iew.iewSquashCycles 825429 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 8290686 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 768265 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 109688691 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 825408 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 8297291 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 773487 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 109689301 # Number of instructions dispatched to IQ
614,615c614,615
< system.cpu.iew.iewDispLoadInsts 26805262 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 5347320 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 26805540 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 5347415 # Number of dispatched store instructions
617,625c617,625
< system.cpu.iew.iewIQFullEvents 180386 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 424316 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 435090 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 412415 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 847505 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 100109953 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 23803133 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1256935 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewIQFullEvents 182523 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 427569 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 1344 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 435014 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 412394 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 847408 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 100110032 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 23803163 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1256332 # Number of squashed instructions skipped in execute
628,638c628,638
< system.cpu.iew.exec_refs 28718801 # number of memory reference insts executed
< system.cpu.iew.exec_branches 20621332 # Number of branches executed
< system.cpu.iew.exec_stores 4915668 # Number of stores executed
< system.cpu.iew.exec_rate 0.853083 # Inst execution rate
< system.cpu.iew.wb_sent 99693665 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 99608516 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 59691499 # num instructions producing a value
< system.cpu.iew.wb_consumers 95528314 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.848810 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.624857 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 17363350 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_refs 28718949 # number of memory reference insts executed
> system.cpu.iew.exec_branches 20621210 # Number of branches executed
> system.cpu.iew.exec_stores 4915786 # Number of stores executed
> system.cpu.iew.exec_rate 0.853001 # Inst execution rate
> system.cpu.iew.wb_sent 99693474 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 99607900 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 59692176 # num instructions producing a value
> system.cpu.iew.wb_consumers 95528763 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.848723 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.624861 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 17363908 # The number of squashed insts skipped by commit
640,643c640,643
< system.cpu.commit.branchMispredicts 823717 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 114597116 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.794554 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.732042 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 823705 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 114608461 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.794476 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.731976 # Number of insts commited each cycle
645,653c645,653
< system.cpu.commit.committed_per_cycle::0 78173194 68.22% 68.22% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 18611100 16.24% 84.46% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 7154015 6.24% 90.70% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 3469592 3.03% 93.73% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1644807 1.44% 95.16% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 541237 0.47% 95.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 703127 0.61% 96.25% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 178794 0.16% 96.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 4121250 3.60% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 78183874 68.22% 68.22% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 18612814 16.24% 84.46% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 7153278 6.24% 90.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 3469165 3.03% 93.73% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1644308 1.43% 95.16% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 541542 0.47% 95.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 703493 0.61% 96.25% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 179022 0.16% 96.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 4120965 3.60% 100.00% # Number of insts commited each cycle
657c657
< system.cpu.commit.committed_per_cycle::total 114597116 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 114608461 # Number of insts commited each cycle
707,711c707,711
< system.cpu.commit.bw_lim_events 4121250 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 218887121 # The number of ROB reads
< system.cpu.rob.rob_writes 219522508 # The number of ROB writes
< system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 65683 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 4120965 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 218899309 # The number of ROB reads
> system.cpu.rob.rob_writes 219523661 # The number of ROB writes
> system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 65688 # Total number of cycles that the CPU has spent unscheduled due to idling
714,719c714,719
< system.cpu.cpi 1.295408 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.295408 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.771958 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.771958 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 108097860 # number of integer regfile reads
< system.cpu.int_regfile_writes 58692141 # number of integer regfile writes
---
> system.cpu.cpi 1.295534 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.295534 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.771883 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.771883 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 108098001 # number of integer regfile reads
> system.cpu.int_regfile_writes 58691976 # number of integer regfile writes
721,724c721,724
< system.cpu.fp_regfile_writes 93 # number of floating regfile writes
< system.cpu.cc_regfile_reads 369004584 # number of cc regfile reads
< system.cpu.cc_regfile_writes 58686965 # number of cc regfile writes
< system.cpu.misc_regfile_reads 28409767 # number of misc regfile reads
---
> system.cpu.fp_regfile_writes 98 # number of floating regfile writes
> system.cpu.cc_regfile_reads 369004563 # number of cc regfile reads
> system.cpu.cc_regfile_writes 58686890 # number of cc regfile writes
> system.cpu.misc_regfile_reads 28409682 # number of misc regfile reads
726,733c726,733
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 5470621 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.769293 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 18249382 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 5471133 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 3.335576 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 38111500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.769293 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 5470632 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.769242 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 18249828 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 3.335651 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 38122500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.769242 # Average occupied blocks per requestor
737,738c737,738
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
740,746c740,746
< system.cpu.dcache.tags.tag_accesses 61907171 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 61907171 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 13887260 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13887260 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4353834 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4353834 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 61906996 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 61906996 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 13887361 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13887361 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4354163 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4354163 # number of WriteReq hits
753,760c753,760
< system.cpu.dcache.demand_hits::cpu.data 18241094 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 18241094 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 18241616 # number of overall hits
< system.cpu.dcache.overall_hits::total 18241616 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 9587475 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 9587475 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 381147 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 381147 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 18241524 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 18241524 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 18242046 # number of overall hits
> system.cpu.dcache.overall_hits::total 18242046 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 9587281 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 9587281 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 380818 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 380818 # number of WriteReq misses
765,772c765,772
< system.cpu.dcache.demand_misses::cpu.data 9968622 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9968622 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9968629 # number of overall misses
< system.cpu.dcache.overall_misses::total 9968629 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 89371349000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 89371349000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4092576700 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4092576700 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 9968099 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9968099 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9968106 # number of overall misses
> system.cpu.dcache.overall_misses::total 9968106 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 89375617500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 89375617500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4089956224 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4089956224 # number of WriteReq miss cycles
775,780c775,780
< system.cpu.dcache.demand_miss_latency::cpu.data 93463925700 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 93463925700 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 93463925700 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 93463925700 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23474735 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23474735 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 93465573724 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 93465573724 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 93465573724 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 93465573724 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23474642 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23474642 # number of ReadReq accesses(hits+misses)
789,796c789,796
< system.cpu.dcache.demand_accesses::cpu.data 28209716 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 28209716 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 28210245 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 28210245 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408417 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.408417 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 28209623 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 28209623 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 28210152 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 28210152 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080427 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.080427 # miss rate for WriteReq accesses
801,808c801,808
< system.cpu.dcache.demand_miss_rate::cpu.data 0.353375 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.353375 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.353369 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.353369 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9321.677397 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 9321.677397 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303 # average WriteReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.353358 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.353358 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.353352 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.353352 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.311248 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.311248 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10739.923596 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 10739.923596 # average WriteReq miss latency
811,817c811,817
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 9375.811993 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 9375.811993 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 9375.805409 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 9375.805409 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 331977 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 129797 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 121610 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 9376.469247 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 9376.469247 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 9376.462662 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 9376.462662 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 331655 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 128757 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 121530 # number of cycles access was blocked
819,826c819,826
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.729850 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 10.108801 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 5470621 # number of writebacks
< system.cpu.dcache.writebacks::total 5470621 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338830 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 4338830 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158660 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 158660 # number of WriteReq MSHR hits
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.728997 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 10.027804 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks
> system.cpu.dcache.writebacks::total 5470632 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338725 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 4338725 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158229 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 158229 # number of WriteReq MSHR hits
829,836c829,836
< system.cpu.dcache.demand_mshr_hits::cpu.data 4497490 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 4497490 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 4497490 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 4497490 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248645 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 5248645 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 4496954 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 4496954 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 4496954 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 4496954 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248556 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 5248556 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222589 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 222589 # number of WriteReq MSHR misses
839,846c839,846
< system.cpu.dcache.demand_mshr_misses::cpu.data 5471132 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 5471132 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 5471136 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 5471136 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817219500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817219500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2296823105 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2296823105 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43819499500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 43819499500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2297613115 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2297613115 # number of WriteReq MSHR miss cycles
849,856c849,856
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46114042605 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 46114042605 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46114278105 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 46114278105 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223587 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223587 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46117112615 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 46117112615 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46117348115 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 46117348115 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223584 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223584 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047009 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047009 # mshr miss rate for WriteReq accesses
859,866c859,866
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193945 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.193945 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193941 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.193941 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.291702 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.291702 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10323.403637 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10323.403637 # average WriteReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.867670 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.867670 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10322.222190 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10322.222190 # average WriteReq mshr miss latency
869,873c869,873
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8428.610862 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 8428.610862 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8428.647744 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 8428.647744 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.151963 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.151963 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.188844 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.188844 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
875,876c875,876
< system.cpu.icache.tags.tagsinuse 427.600534 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 32274508 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 427.601453 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 32274679 # Total number of references to valid blocks.
878c878
< system.cpu.icache.tags.avg_refs 35623.077263 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 35623.266004 # Average number of references to valid blocks.
880,882c880,882
< system.cpu.icache.tags.occ_blocks::cpu.inst 427.600534 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.835157 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.835157 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 427.601453 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.835159 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.835159 # Average percentage of cache occupancy
889,915c889,915
< system.cpu.icache.tags.tag_accesses 64552224 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 64552224 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 32274508 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 32274508 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 32274508 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 32274508 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 32274508 # number of overall hits
< system.cpu.icache.overall_hits::total 32274508 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1151 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1151 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1151 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1151 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1151 # number of overall misses
< system.cpu.icache.overall_misses::total 1151 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 79113980 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 79113980 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 79113980 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 79113980 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 79113980 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 79113980 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 32275659 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 32275659 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 32275659 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 32275659 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 32275659 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 32275659 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 64552564 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 64552564 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 32274679 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 32274679 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 32274679 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 32274679 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 32274679 # number of overall hits
> system.cpu.icache.overall_hits::total 32274679 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1150 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1150 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1150 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1150 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1150 # number of overall misses
> system.cpu.icache.overall_misses::total 1150 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 79102980 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 79102980 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 79102980 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 79102980 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 79102980 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 79102980 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 32275829 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 32275829 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 32275829 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 32275829 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 32275829 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 32275829 # number of overall (read+write) accesses
922,930c922,930
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68734.995656 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68734.995656 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68734.995656 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68734.995656 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 21173 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 759 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68785.200000 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 68785.200000 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 68785.200000 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 68785.200000 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 21255 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 760 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 230 # number of cycles access was blocked
932,933c932,933
< system.cpu.icache.avg_blocked_cycles::no_mshrs 94.102222 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 126.500000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 92.413043 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 126.666667 # average number of cycles each access was blocked
936,941c936,941
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits
948,953c948,953
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60405484 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 60405484 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60405484 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 60405484 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60405484 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 60405484 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60408984 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 60408984 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60408984 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 60408984 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60408984 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 60408984 # number of overall MSHR miss cycles
960,969c960,969
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66599.210584 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66599.210584 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 4988856 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 5295771 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 266816 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66603.069460 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66603.069460 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66603.069460 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 66603.069460 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66603.069460 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 66603.069460 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 4986166 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 5293297 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 266998 # number of redundant prefetches already in prefetch queue
972,978c972,978
< system.cpu.l2cache.prefetcher.pfSpanPage 14074045 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 140 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 11212.925557 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 5291618 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 14696 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 360.071992 # Average number of references to valid blocks.
---
> system.cpu.l2cache.prefetcher.pfSpanPage 14074663 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 148 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 11219.998633 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 5292017 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 14707 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 359.829809 # Average number of references to valid blocks.
980,992c980,992
< system.cpu.l2cache.tags.occ_blocks::writebacks 11154.278216 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 58.647341 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.680803 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003580 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.684383 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 60 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 477 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3389 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9672 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 11153.900503 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.098130 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.680780 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004034 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.684814 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 64 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 14495 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 55 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3398 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9680 # Occupied blocks per task id
994,1051c994,1051
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 839 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003662 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 180525801 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 180525801 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 5457281 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 5457281 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 10913 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 10913 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 226015 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 226015 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 206 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 206 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241513 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 5241513 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 206 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 5467528 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 5467734 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 206 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 5467528 # number of overall hits
< system.cpu.l2cache.overall_hits::total 5467734 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 505 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 505 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3100 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 3100 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 3605 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 4306 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 3605 # number of overall misses
< system.cpu.l2cache.overall_misses::total 4306 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 63500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 63500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64129500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 64129500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58109500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 58109500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 616309000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 616309000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 58109500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 680438500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 738548000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 58109500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 680438500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 738548000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457281 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 5457281 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 10913 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 10913 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 226520 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 226520 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 832 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003906 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884705 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 180526200 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 180526200 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 5457195 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 5457195 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 11011 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 11011 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 225669 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 225669 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 205 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 205 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241856 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 5241856 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 205 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 5467525 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 5467730 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 205 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 5467525 # number of overall hits
> system.cpu.l2cache.overall_hits::total 5467730 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 501 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 501 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 702 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 702 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3118 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 3118 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 702 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 3619 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 4321 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 702 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 3619 # number of overall misses
> system.cpu.l2cache.overall_misses::total 4321 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 106500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 106500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63936500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 63936500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58121500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 58121500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 619277500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 619277500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 58121500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 683214000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 741335500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 58121500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 683214000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 741335500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457195 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 5457195 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 11011 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 11011 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 226170 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 226170 # number of ReadExReq accesses(hits+misses)
1054,1055c1054,1055
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244613 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 5244613 # number of ReadSharedReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244974 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 5244974 # number of ReadSharedReq accesses(hits+misses)
1057,1058c1057,1058
< system.cpu.l2cache.demand_accesses::cpu.data 5471133 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 5472040 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 5471144 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses
1060,1061c1060,1061
< system.cpu.l2cache.overall_accesses::cpu.data 5471133 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 5472040 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.data 5471144 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses
1064,1089c1064,1089
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002229 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.002229 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772878 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772878 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000591 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000591 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772878 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.000659 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.000787 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772878 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.000659 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.000787 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21166.666667 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21166.666667 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126989.108911 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126989.108911 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82895.149786 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82895.149786 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198809.354839 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198809.354839 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 171516.024152 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 171516.024152 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002215 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.002215 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.773980 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.773980 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000594 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000594 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.773980 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.000661 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.000790 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.773980 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.000661 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21300 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21300 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127617.764471 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127617.764471 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82794.159544 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82794.159544 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198613.694676 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198613.694676 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82794.159544 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188785.299807 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 171565.725526 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82794.159544 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188785.299807 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 171565.725526 # average overall miss latency
1097,1100c1097,1100
< system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks
< system.cpu.l2cache.writebacks::total 104 # number of writebacks
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 106 # number of writebacks
> system.cpu.l2cache.writebacks::total 106 # number of writebacks
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits
1103,1104c1103,1104
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits
---
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 30 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits
1106,1107c1106,1107
< system.cpu.l2cache.demand_mshr_hits::cpu.data 194 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 195 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 188 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits
1109,1114c1109,1114
< system.cpu.l2cache.overall_mshr_hits::cpu.data 194 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 195 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316848 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 316848 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 188 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 189 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316628 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 316628 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
1117,1144c1117,1144
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3068 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3068 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 3411 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 4111 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 3411 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316848 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 320959 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1079223443 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45646000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45646000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53848500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53848500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 589212500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 589212500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53848500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 634858500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 688707000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53848500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 634858500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 1767930443 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 701 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 701 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3088 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3088 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 701 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 3431 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 4132 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 701 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 3431 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316628 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 320760 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1087453464 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1087453464 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45609000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45609000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53854500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53854500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 591148000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 591148000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53854500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 636757000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 690611500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53854500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 636757000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1087453464 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 1778064964 # number of overall MSHR miss cycles
1149,1159c1149,1159
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.771775 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000585 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000585 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.000751 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001517 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001517 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.772878 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000589 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000589 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.000755 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for overall accesses
1161,1183c1161,1183
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.058654 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3406.123577 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5508.275023 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 10943112 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471085 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 302425 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302424 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.058618 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3434.482939 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15300 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15300 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 132970.845481 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 132970.845481 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76825.249643 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76825.249643 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 191433.937824 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 191433.937824 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167137.342691 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5543.287704 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 10943136 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471098 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2874 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 302216 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302215 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1185,1195c1185,1195
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 5245519 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 5457385 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 13788 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 36 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 318720 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 226520 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 226520 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 5245880 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 5457301 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 13885 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 42 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 318509 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 226170 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 226170 # Transaction distribution
1197c1197
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244613 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244974 # Transaction distribution
1199,1200c1199,1200
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412897 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 16415158 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 16415197 # Packet count per connected master and slave (bytes)
1202,1208c1202,1208
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700272512 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 700359168 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 318864 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 6912 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 5790903 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.052723 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.223481 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 700360704 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 318663 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 7168 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 5790713 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.052689 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.223412 # Request fanout histogram
1210,1211c1210,1211
< system.cpu.toL2Bus.snoop_fanout::0 5485590 94.73% 94.73% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 305312 5.27% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 5485610 94.73% 94.73% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 305102 5.27% 100.00% # Request fanout histogram
1216,1217c1216,1217
< system.cpu.toL2Bus.snoop_fanout::total 5790903 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 10942625015 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 5790713 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 10942648026 # Layer occupancy (ticks)
1219c1219
< system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks)
1221c1221
< system.cpu.toL2Bus.respLayer0.occupancy 1360996 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1361495 # Layer occupancy (ticks)
1223c1223
< system.cpu.toL2Bus.respLayer1.occupancy 8206704493 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks)
1225,1226c1225,1226
< system.membus.snoop_filter.tot_requests 18677 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 3023 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.membus.snoop_filter.tot_requests 18697 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 3032 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1231,1235c1231,1235
< system.membus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 18190 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 104 # Transaction distribution
< system.membus.trans_dist::CleanEvict 36 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 18200 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 106 # Transaction distribution
> system.membus.trans_dist::CleanEvict 42 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 6 # Transaction distribution
1238,1242c1238,1242
< system.membus.trans_dist::ReadSharedReq 18191 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37209 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 37209 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192704 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 1192704 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 18201 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37239 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 37239 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1193472 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 1193472 # Cumulative packet size per connected master and slave (bytes)
1245c1245
< system.membus.snoop_fanout::samples 18537 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 18549 # Request fanout histogram
1249c1249
< system.membus.snoop_fanout::0 18537 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 18549 100.00% 100.00% # Request fanout histogram
1254,1255c1254,1255
< system.membus.snoop_fanout::total 18537 # Request fanout histogram
< system.membus.reqLayer0.occupancy 29625930 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 18549 # Request fanout histogram
> system.membus.reqLayer0.occupancy 29669004 # Layer occupancy (ticks)
1257c1257
< system.membus.respLayer1.occupancy 97326818 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 97336094 # Layer occupancy (ticks)