3,5c3,5
< sim_seconds 0.058199 # Number of seconds simulated
< sim_ticks 58199030500 # Number of ticks simulated
< final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.058328 # Number of seconds simulated
> sim_ticks 58328364500 # Number of ticks simulated
> final_tick 58328364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 122100 # Simulator instruction rate (inst/s)
< host_op_rate 122709 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 78442850 # Simulator tick rate (ticks/s)
< host_mem_usage 487108 # Number of bytes of host memory used
< host_seconds 741.93 # Real time elapsed on the host
---
> host_inst_rate 135523 # Simulator instruction rate (inst/s)
> host_op_rate 136198 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 87259482 # Simulator tick rate (ticks/s)
> host_mem_usage 492508 # Number of bytes of host memory used
> host_seconds 668.45 # Real time elapsed on the host
16,54c16,54
< system.physmem.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory
< system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory
< system.physmem.bytes_written::total 11200 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 693 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1369 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 14454 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 16516 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 175 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 762075 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1505455 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 15894698 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 18162227 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 762075 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 762075 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 192443 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 192443 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 192443 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 762075 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1505455 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 15894698 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 18354670 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 16517 # Number of read requests accepted
< system.physmem.writeReqs 175 # Number of write requests accepted
< system.physmem.readBursts 16517 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 1048320 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 1057088 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 218752 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 921408 # Number of bytes read from this memory
> system.physmem.bytes_read::total 1184896 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 5696 # Number of bytes written to this memory
> system.physmem.bytes_written::total 5696 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 3418 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 14397 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 18514 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 89 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 89 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 766968 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3750354 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 15796911 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 20314233 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 766968 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 766968 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 97654 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 97654 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 97654 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 766968 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3750354 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 15796911 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 20411887 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 18515 # Number of read requests accepted
> system.physmem.writeReqs 89 # Number of write requests accepted
> system.physmem.readBursts 18515 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 89 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 1179904 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue
> system.physmem.bytesWritten 4480 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 1184960 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 5696 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one
56,58c56,58
< system.physmem.perBankRdBursts::0 1166 # Per bank write bursts
< system.physmem.perBankRdBursts::1 920 # Per bank write bursts
< system.physmem.perBankRdBursts::2 953 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 3247 # Per bank write bursts
> system.physmem.perBankRdBursts::1 921 # Per bank write bursts
> system.physmem.perBankRdBursts::2 949 # Per bank write bursts
61,64c61,64
< system.physmem.perBankRdBursts::5 1122 # Per bank write bursts
< system.physmem.perBankRdBursts::6 1094 # Per bank write bursts
< system.physmem.perBankRdBursts::7 1089 # Per bank write bursts
< system.physmem.perBankRdBursts::8 1025 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 1117 # Per bank write bursts
> system.physmem.perBankRdBursts::6 1095 # Per bank write bursts
> system.physmem.perBankRdBursts::7 1097 # Per bank write bursts
> system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
66,72c66,72
< system.physmem.perBankRdBursts::10 933 # Per bank write bursts
< system.physmem.perBankRdBursts::11 900 # Per bank write bursts
< system.physmem.perBankRdBursts::12 903 # Per bank write bursts
< system.physmem.perBankRdBursts::13 900 # Per bank write bursts
< system.physmem.perBankRdBursts::14 1411 # Per bank write bursts
< system.physmem.perBankRdBursts::15 910 # Per bank write bursts
< system.physmem.perBankWrBursts::0 2 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 932 # Per bank write bursts
> system.physmem.perBankRdBursts::11 899 # Per bank write bursts
> system.physmem.perBankRdBursts::12 902 # Per bank write bursts
> system.physmem.perBankRdBursts::13 896 # Per bank write bursts
> system.physmem.perBankRdBursts::14 1399 # Per bank write bursts
> system.physmem.perBankRdBursts::15 904 # Per bank write bursts
> system.physmem.perBankWrBursts::0 0 # Per bank write bursts
74c74
< system.physmem.perBankWrBursts::2 6 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 2 # Per bank write bursts
76,79c76,79
< system.physmem.perBankWrBursts::4 3 # Per bank write bursts
< system.physmem.perBankWrBursts::5 16 # Per bank write bursts
< system.physmem.perBankWrBursts::6 40 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7 # Per bank write bursts
---
> system.physmem.perBankWrBursts::4 2 # Per bank write bursts
> system.physmem.perBankWrBursts::5 9 # Per bank write bursts
> system.physmem.perBankWrBursts::6 10 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8 # Per bank write bursts
82,83c82,83
< system.physmem.perBankWrBursts::10 2 # Per bank write bursts
< system.physmem.perBankWrBursts::11 2 # Per bank write bursts
---
> system.physmem.perBankWrBursts::10 3 # Per bank write bursts
> system.physmem.perBankWrBursts::11 3 # Per bank write bursts
85,87c85,87
< system.physmem.perBankWrBursts::13 17 # Per bank write bursts
< system.physmem.perBankWrBursts::14 37 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7 # Per bank write bursts
---
> system.physmem.perBankWrBursts::13 9 # Per bank write bursts
> system.physmem.perBankWrBursts::14 13 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6 # Per bank write bursts
90c90
< system.physmem.totGap 58199022000 # Total gap between requests
---
> system.physmem.totGap 58328356000 # Total gap between requests
97c97
< system.physmem.readPktSize::6 16517 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 18515 # Read request sizes (log2)
104,112c104,112
< system.physmem.writePktSize::6 175 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 11454 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2521 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 462 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 296 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 296 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 292 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 89 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 13470 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2526 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 477 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 307 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 310 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 283 # What read queue length does an incoming req see
114c114
< system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see
152,169c152,169
< system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see
201,230c201,234
< system.physmem.bytesPerActivate::samples 1812 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 582.746137 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 353.648277 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 424.722034 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 448 24.72% 24.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 213 11.75% 36.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 96 5.30% 41.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 72 3.97% 45.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 56 3.09% 48.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 67 3.70% 52.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 61 3.37% 55.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 48 2.65% 58.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 751 41.45% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1812 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 2016.250000 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 98.342741 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 5441.040729 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads
< system.physmem.totQLat 175730624 # Total ticks spent queuing
< system.physmem.totMemAccLat 482855624 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 81900000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10728.37 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 3107 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 380.704216 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 201.847183 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 402.867268 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 1088 35.02% 35.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 865 27.84% 62.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 94 3.03% 65.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 72 2.32% 68.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 65 2.09% 70.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 68 2.19% 72.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 56 1.80% 74.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 51 1.64% 75.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 748 24.07% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 3107 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 4608 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 1496.681558 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 7484.705695 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 1 25.00% 25.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-1023 1 25.00% 50.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.500000 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.477704 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 1 25.00% 25.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 3 75.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads
> system.physmem.totQLat 204802662 # Total ticks spent queuing
> system.physmem.totMemAccLat 550477662 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 92180000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 11108.84 # Average queueing delay per DRAM burst
232,236c236,240
< system.physmem.avgMemAccLat 29478.37 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 18.01 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 18.16 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 29858.84 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 20.23 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 20.32 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 0.10 # Average system write bandwidth in MiByte/s
238,239c242,243
< system.physmem.busUtil 0.14 # Data bus utilization in percentage
< system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 0.16 # Data bus utilization in percentage
> system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads
241,259c245,263
< system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing
< system.physmem.readRowHits 14651 # Number of row buffer hits during reads
< system.physmem.writeRowHits 51 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 29.82 # Row buffer hit rate for writes
< system.physmem.avgGap 3486641.62 # Average gap between requests
< system.physmem.pageHitRate 88.83 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 65512200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 486000 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 2714701095 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 32535498750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 39129012390 # Total energy per rank (pJ)
< system.physmem_0.averagePower 672.381118 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 54114607553 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1943240000 # Time in different power states
---
> system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 22.38 # Average write queue length when enqueuing
> system.physmem.readRowHits 15382 # Number of row buffer hits during reads
> system.physmem.writeRowHits 10 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 11.49 # Row buffer hit rate for writes
> system.physmem.avgGap 3135258.87 # Average gap between requests
> system.physmem.pageHitRate 83.10 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 17803800 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 9714375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 81876600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 162000 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 6575109030 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 29228595750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 39722884515 # Total energy per rank (pJ)
> system.physmem_0.averagePower 681.036990 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 48583441495 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1947660000 # Time in different power states
261c265
< system.physmem_0.memoryStateTime::ACT 2137743447 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 7795971005 # Time in different power states
263,273c267,277
< system.physmem_1.actEnergy 6017760 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3283500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 61916400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 447120 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 2480426820 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ)
< system.physmem_1.averagePower 671.780705 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states
---
> system.physmem_1.actEnergy 5609520 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3060750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 61760400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 187920 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2425538385 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 32868570000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 39174349935 # Total energy per rank (pJ)
> system.physmem_1.averagePower 671.632528 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 54671634140 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1947660000 # Time in different power states
275c279
< system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1708703360 # Time in different power states
277,282c281,286
< system.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 28233538 # Number of BP lookups
< system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits
---
> system.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 28233990 # Number of BP lookups
> system.cpu.branchPred.condPredicted 23266525 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 835401 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 11829630 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 11747896 # Number of BTB hits
284,287c288,291
< system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups.
---
> system.cpu.branchPred.BTBHitPct 99.309074 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 74550 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 27225 # Number of indirect predictor lookups.
289c293
< system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses.
---
> system.cpu.branchPred.indirectMisses 1747 # Number of indirect misses.
292c296
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
322c326
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
352c356
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
382c386
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
413,414c417,418
< system.cpu.pwrStateResidencyTicks::ON 58199030500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 116398062 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 58328364500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 116656730 # number of cpu cycles simulated
417,429c421,433
< system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1674187 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.IcacheWaitRetryStallCycles 805 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 32275055 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 562 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 116345779 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.164712 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.318875 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 746133 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 134907690 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 28233990 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 11847924 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 115018036 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1674227 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 32275439 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 555 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 116602964 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.162155 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.318550 # Number of instructions fetched each cycle (Total)
431,434c435,438
< system.cpu.fetch.rateDist::0 58810972 50.55% 50.55% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 13933527 11.98% 62.52% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 9228064 7.93% 70.46% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 34373216 29.54% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 59067374 50.66% 50.66% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 13933709 11.95% 62.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 9228635 7.91% 70.52% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 34373246 29.48% 100.00% # Number of instructions fetched each cycle (Total)
438,465c442,469
< system.cpu.fetch.rateDist::total 116345779 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.242560 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.159010 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 8834252 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 64111694 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 33013656 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 9560800 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 825377 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 4097950 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 114395383 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 1985420 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 825377 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 15270485 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 49952350 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 109536 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 35410349 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 14777682 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 110872417 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 1412237 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 11132933 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 1144918 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1526969 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 486977 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 129945519 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 483152587 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 119447216 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 116602964 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.242026 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.156450 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 8835100 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 64368120 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 33012562 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 9561783 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 825399 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 4097891 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 11814 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 114395515 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1985251 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 825399 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 15271601 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 50089085 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 110009 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 35409630 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 14897240 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 110872720 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 1412183 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 11133547 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 1231881 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1645196 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 486344 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 129945840 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 483153679 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 119447461 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 433 # Number of floating rename lookups
467c471
< system.cpu.rename.UndoneMaps 22632600 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 22632921 # Number of HB maps that are undone due to squashing
470,475c474,479
< system.cpu.rename.skidInsts 21510749 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 26805153 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 5347343 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 519410 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 254099 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 109667150 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.rename.skidInsts 21513680 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 26805319 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 5347286 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 522469 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 256366 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 109667529 # Number of instructions added to the IQ (excludes non-spec)
477,480c481,484
< system.cpu.iq.iqInstsIssued 101366848 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 1074801 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 18634403 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 41667039 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 101366370 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 1074686 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 18634782 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 41671490 # Number of squashed operands that are examined and possibly removed from graph
482,484c486,488
< system.cpu.iq.issued_per_cycle::samples 116345779 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.871255 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.989200 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 116602964 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.869329 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.988911 # Number of insts issued each cycle
486,490c490,494
< system.cpu.iq.issued_per_cycle::0 54714850 47.03% 47.03% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 31358235 26.95% 73.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 22007860 18.92% 92.90% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 7066756 6.07% 98.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 1197765 1.03% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 54969091 47.14% 47.14% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 31363076 26.90% 74.04% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 22007447 18.87% 92.91% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 7065313 6.06% 98.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1197724 1.03% 100.00% # Number of insts issued each cycle
498c502
< system.cpu.iq.issued_per_cycle::total 116345779 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 116602964 # Number of insts issued each cycle
500c504
< system.cpu.iq.fu_full::IntAlu 9784213 48.67% 48.67% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 9783594 48.67% 48.67% # attempts to use FU when none available
529,530c533,534
< system.cpu.iq.fu_full::MemRead 9614548 47.83% 96.50% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 702998 3.50% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 9615674 47.83% 96.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 702930 3.50% 100.00% # attempts to use FU when none available
534,535c538,539
< system.cpu.iq.FU_type_0::IntAlu 71970791 71.00% 71.00% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 10698 0.01% 71.01% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 71970691 71.00% 71.00% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued
559c563
< system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 71.01% # Type of FU issued
563,564c567,568
< system.cpu.iq.FU_type_0::MemRead 24337715 24.01% 95.02% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 5047462 4.98% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 24337594 24.01% 95.02% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 5047205 4.98% 100.00% # Type of FU issued
567,573c571,577
< system.cpu.iq.FU_type_0::total 101366848 # Type of FU issued
< system.cpu.iq.rate 0.870864 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 20101822 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.198308 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 340255638 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 128310520 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 99608490 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 101366370 # Type of FU issued
> system.cpu.iq.rate 0.868929 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 20102261 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 340512191 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 128311283 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 99607990 # Number of integer instruction queue wakeup accesses
575,579c579,583
< system.cpu.iq.fp_inst_queue_writes 624 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 121468430 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 288068 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 121468392 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 288047 # Number of loads that had data forwarded from stores
581,584c585,588
< system.cpu.iew.lsq.thread0.squashedLoads 4329242 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 1500 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 1342 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 602499 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 4329408 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 602442 # Number of stores squashed
587,588c591,592
< system.cpu.iew.lsq.thread0.rescheduledLoads 7579 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 130663 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 130712 # Number of times an access to memory failed due to the cache being blocked
590,593c594,597
< system.cpu.iew.iewSquashCycles 825377 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 8119454 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 685980 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 109688255 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 825399 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 8206553 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 706266 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 109688634 # Number of instructions dispatched to IQ
595,596c599,600
< system.cpu.iew.iewDispLoadInsts 26805153 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 5347343 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 26805319 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 5347286 # Number of dispatched store instructions
598,606c602,610
< system.cpu.iew.iewIQFullEvents 180270 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 342292 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 1342 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 435059 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 412404 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 847463 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 100109842 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 23803071 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1257006 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewIQFullEvents 180569 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 362078 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 435086 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 412401 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 847487 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 100109489 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 23802993 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1256881 # Number of squashed instructions skipped in execute
609,619c613,623
< system.cpu.iew.exec_refs 28718921 # number of memory reference insts executed
< system.cpu.iew.exec_branches 20621209 # Number of branches executed
< system.cpu.iew.exec_stores 4915850 # Number of stores executed
< system.cpu.iew.exec_rate 0.860065 # Inst execution rate
< system.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 99608605 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 59691637 # num instructions producing a value
< system.cpu.iew.wb_consumers 95527463 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.855758 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_refs 28718621 # number of memory reference insts executed
> system.cpu.iew.exec_branches 20621294 # Number of branches executed
> system.cpu.iew.exec_stores 4915628 # Number of stores executed
> system.cpu.iew.exec_rate 0.858154 # Inst execution rate
> system.cpu.iew.wb_sent 99693258 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 99608103 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 59691284 # num instructions producing a value
> system.cpu.iew.wb_consumers 95529167 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.853856 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.624849 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 17363279 # The number of squashed insts skipped by commit
621,624c625,628
< system.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 823687 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 113915056 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.799312 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.736114 # Number of insts commited each cycle
626,634c630,638
< system.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 77490817 68.03% 68.03% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 18611366 16.34% 84.36% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 7154135 6.28% 90.64% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 3469454 3.05% 93.69% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1644903 1.44% 95.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 541342 0.48% 95.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 703110 0.62% 96.23% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 178773 0.16% 96.38% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 4121156 3.62% 100.00% # Number of insts commited each cycle
638c642
< system.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 113915056 # Number of insts commited each cycle
684,688c688,692
< system.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 217947492 # The number of ROB reads
< system.cpu.rob.rob_writes 219521309 # The number of ROB writes
< system.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 4121156 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 218205084 # The number of ROB reads
> system.cpu.rob.rob_writes 219522331 # The number of ROB writes
> system.cpu.timesIdled 576 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 53766 # Total number of cycles that the CPU has spent unscheduled due to idling
691,701c695,705
< system.cpu.cpi 1.284891 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.778276 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 108097873 # number of integer regfile reads
< system.cpu.int_regfile_writes 58692304 # number of integer regfile writes
< system.cpu.fp_regfile_reads 59 # number of floating regfile reads
< system.cpu.fp_regfile_writes 96 # number of floating regfile writes
< system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads
< system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes
< system.cpu.misc_regfile_reads 28410105 # number of misc regfile reads
---
> system.cpu.cpi 1.287747 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.287747 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.776550 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.776550 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 108097252 # number of integer regfile reads
> system.cpu.int_regfile_writes 58691902 # number of integer regfile writes
> system.cpu.fp_regfile_reads 58 # number of floating regfile reads
> system.cpu.fp_regfile_writes 93 # number of floating regfile writes
> system.cpu.cc_regfile_reads 369002875 # number of cc regfile reads
> system.cpu.cc_regfile_writes 58686679 # number of cc regfile writes
> system.cpu.misc_regfile_reads 28409649 # number of misc regfile reads
703,712c707,716
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 5470634 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 5470636 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.779483 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 18249262 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 5471148 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 3.335545 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 36545500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.779483 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999569 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999569 # Average percentage of cache occupancy
714,715c718,719
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
717,723c721,727
< system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 61906894 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 61906894 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 13887138 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13887138 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4353836 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4353836 # number of WriteReq hits
726,727c730,731
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits
---
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits
730,737c734,741
< system.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits
< system.cpu.dcache.overall_hits::total 18241600 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 18240974 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 18240974 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 18241496 # number of overall hits
> system.cpu.dcache.overall_hits::total 18241496 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 9587451 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 9587451 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 381145 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 381145 # number of WriteReq misses
740,757c744,761
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses
< system.cpu.dcache.overall_misses::total 9968505 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 9968596 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9968596 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9968603 # number of overall misses
> system.cpu.dcache.overall_misses::total 9968603 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 88929958000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 88929958000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000514273 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4000514273 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 284000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 284000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 92930472273 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 92930472273 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 92930472273 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 92930472273 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23474589 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23474589 # number of ReadReq accesses(hits+misses)
766,773c770,777
< system.cpu.dcache.demand_accesses::cpu.data 28209576 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 28209576 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 28210105 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 28210105 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 28209570 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 28209570 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 28210099 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 28210099 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408418 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.408418 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses
776,794c780,798
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.353373 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.353373 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.353366 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.353366 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9259.500156 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 9259.500156 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19400 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19400 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 9306.724882 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 9306.724882 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked
---
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.353376 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.353376 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.353370 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.353370 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9275.662322 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 9275.662322 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10496.042905 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 10496.042905 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20285.714286 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20285.714286 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 9322.323051 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 9322.323051 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 9322.316504 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 9322.316504 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 330469 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 108734 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 121517 # number of cycles access was blocked
796,813c800,817
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks
< system.cpu.dcache.writebacks::total 5470634 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 4497353 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 4497353 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 4497353 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 4497353 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248661 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 5248661 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222484 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 222484 # number of WriteReq MSHR misses
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.719529 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 8.469699 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 5470636 # number of writebacks
> system.cpu.dcache.writebacks::total 5470636 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338792 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 4338792 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158657 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 158657 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 4497449 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 4497449 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 4497449 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 4497449 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248659 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 5248659 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222488 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 222488 # number of WriteReq MSHR misses
816,829c820,833
< system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43288788000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 43288788000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285573254 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285573254 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45574361254 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 45574361254 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45574575754 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 45574575754 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 5471147 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 5471147 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 5471151 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 5471151 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43429617000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 43429617000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285050165 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285050165 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 217500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 217500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45714667165 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 45714667165 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45714884665 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 45714884665 # number of overall MSHR miss cycles
832,833c836,837
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses
840,850c844,854
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8247.586956 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8247.586956 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8274.421524 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8274.421524 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.442294 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.442294 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54375 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54375 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8355.591097 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 8355.591097 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8355.624742 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 8355.624742 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
852,853c856,857
< system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 427.481000 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 32274286 # Total number of references to valid blocks.
855c859
< system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 35701.643805 # Average number of references to valid blocks.
857,859c861,863
< system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 427.481000 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.834924 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.834924 # Average percentage of cache occupancy
866,892c870,896
< system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits
< system.cpu.icache.overall_hits::total 32273898 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1145 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1145 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1145 # number of overall misses
< system.cpu.icache.overall_misses::total 1145 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 60302481 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 60302481 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 60302481 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 60302481 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 60302481 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 60302481 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 32275043 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 32275043 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 32275043 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 32275043 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 32275043 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 32275043 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 64551760 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 64551760 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 32274286 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 32274286 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 32274286 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 32274286 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 32274286 # number of overall hits
> system.cpu.icache.overall_hits::total 32274286 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1142 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1142 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1142 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1142 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1142 # number of overall misses
> system.cpu.icache.overall_misses::total 1142 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 61976480 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 61976480 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 61976480 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 61976480 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 61976480 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 61976480 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 32275428 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 32275428 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 32275428 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 32275428 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 32275428 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 32275428 # number of overall (read+write) accesses
899,906c903,910
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 52665.922271 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54270.122592 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54270.122592 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54270.122592 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54270.122592 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54270.122592 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54270.122592 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 19008 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked
909,910c913,914
< system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 86.794521 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 29.600000 # average number of cycles each access was blocked
913,918c917,922
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 237 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 237 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 237 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 237 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 237 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 237 # number of overall MSHR hits
925,930c929,934
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49734485 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 49734485 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49734485 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 49734485 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49734485 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 49734485 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50842984 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 50842984 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50842984 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 50842984 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50842984 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 50842984 # number of overall MSHR miss cycles
937,946c941,950
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56180.092818 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56180.092818 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56180.092818 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 56180.092818 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56180.092818 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 56180.092818 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 4982437 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 5296601 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 273114 # number of redundant prefetches already in prefetch queue
949,955c953,959
< system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 248 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks.
---
> system.cpu.l2cache.prefetcher.pfSpanPage 14074231 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 123 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 11197.361342 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 5291777 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 14677 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 360.548954 # Average number of references to valid blocks.
957,993c961,996
< system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.675141 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010639 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.685780 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 181 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 14486 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 168 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243562 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 5243562 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 210 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 5469581 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 5469791 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 210 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 5469581 # number of overall hits
< system.cpu.l2cache.overall_hits::total 5469791 # number of overall hits
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 11137.339599 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 60.021743 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.679769 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003663 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.683433 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 61 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 14493 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3478 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9594 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 837 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003723 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884583 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 180526187 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 180526187 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 5457780 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 5457780 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 10426 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 10426 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 226022 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 226022 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 204 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 204 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241527 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 5241527 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 204 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 5467549 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 5467753 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 204 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 5467549 # number of overall hits
> system.cpu.l2cache.overall_hits::total 5467753 # number of overall hits
996,1025c999,1028
< system.cpu.l2cache.ReadExReq_misses::cpu.data 500 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 500 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 695 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 695 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1065 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 1065 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1565 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 2260 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1565 # number of overall misses
< system.cpu.l2cache.overall_misses::total 2260 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 59500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 59500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41259500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 41259500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47414000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 47414000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71274500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 71274500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 47414000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 112534000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 159948000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 47414000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 112534000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 159948000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 5451171 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 5451171 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 17033 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 17033 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3100 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 3100 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 3599 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 4300 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 3599 # number of overall misses
> system.cpu.l2cache.overall_misses::total 4300 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 64500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 64500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41467500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 41467500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48564000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 48564000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 228575500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 228575500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 48564000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 270043000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 318607000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 48564000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 270043000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 318607000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457780 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 5457780 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 10426 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 10426 # number of WritebackClean accesses(hits+misses)
1028,1029c1031,1032
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 226521 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 226521 # number of ReadExReq accesses(hits+misses)
1035,1036c1038,1039
< system.cpu.l2cache.demand_accesses::cpu.data 5471146 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 5471148 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 5472053 # number of demand (read+write) accesses
1038,1039c1041,1042
< system.cpu.l2cache.overall_accesses::cpu.data 5471146 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.data 5471148 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 5472053 # number of overall (read+write) accesses
1042,1067c1045,1070
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002207 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.002207 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.767956 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.767956 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000203 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000203 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767956 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.000286 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.000413 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767956 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.000286 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.000413 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19833.333333 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19833.333333 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82519 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82519 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68221.582734 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68221.582734 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66924.413146 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66924.413146 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70773.451327 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002203 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.002203 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.774586 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.774586 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000591 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000591 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.774586 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.000658 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.000786 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.774586 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.000658 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.000786 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21500 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21500 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83101.202405 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83101.202405 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 69278.174037 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 69278.174037 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73734.032258 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73734.032258 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69278.174037 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75032.786885 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74094.651163 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69278.174037 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75032.786885 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74094.651163 # average overall miss latency
1074,1076c1077,1078
< system.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference
< system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks
< system.cpu.l2cache.writebacks::total 175 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 89 # number of writebacks
> system.cpu.l2cache.writebacks::total 89 # number of writebacks
1081,1082c1083,1084
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 37 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 37 # number of ReadSharedReq MSHR hits
---
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits
1084,1085c1086,1087
< system.cpu.l2cache.demand_mshr_hits::cpu.data 195 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 196 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 181 # number of demand (read+write) MSHR hits
1087,1090c1089,1092
< system.cpu.l2cache.overall_mshr_hits::cpu.data 195 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 196 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316084 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 316084 # number of HardPFReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 181 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316573 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 316573 # number of HardPFReq MSHR misses
1093,1122c1095,1124
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 342 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 342 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 694 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 694 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1028 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1028 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1370 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 2064 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1370 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316084 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 318148 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852614747 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 41500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 41500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32745000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32745000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43196500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43196500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63614500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63614500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43196500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96359500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 139556000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43196500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96359500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 992170747 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3078 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3078 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 3419 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 4119 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 3419 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316573 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 320692 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 866631987 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 866631987 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 46500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 46500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32627500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32627500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44309000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44309000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 208942500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 208942500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44309000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 241570000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 285879000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44309000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 241570000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 866631987 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 1152510987 # number of overall MSHR miss cycles
1127,1137c1129,1139
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.000377 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.773481 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000587 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.000753 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for overall accesses
1139,1158c1141,1160
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.058605 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2737.542327 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95681.818182 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95681.818182 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63298.571429 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63298.571429 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67882.553606 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67882.553606 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69404.952658 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3593.825187 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 10943139 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1160,1163c1162,1165
< system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 302176 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302175 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
1165,1168c1167,1170
< system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 5457869 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 13303 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 318447 # Transaction distribution
1172,1173c1174,1175
< system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 226521 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 226521 # Transaction distribution
1177,1178c1179,1180
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412942 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 16415198 # Packet count per connected master and slave (bytes)
1180,1186c1182,1188
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 319939 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 11456 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274432 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 700360896 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 318574 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 5952 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 5790626 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.052683 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.223400 # Request fanout histogram
1188,1190c1190,1192
< system.cpu.toL2Bus.snoop_fanout::0 5485738 94.71% 94.71% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 305466 5.27% 99.99% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 785 0.01% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 5485560 94.73% 94.73% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 305065 5.27% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
1194,1195c1196,1197
< system.cpu.toL2Bus.snoop_fanout::total 5791989 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 5790626 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 10942652515 # Layer occupancy (ticks)
1201c1203
< system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 8206727492 # Layer occupancy (ticks)
1203,1206c1205,1214
< system.membus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 16175 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 175 # Transaction distribution
< system.membus.trans_dist::CleanEvict 63 # Transaction distribution
---
> system.membus.snoop_filter.tot_requests 18642 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 3008 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 18174 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 89 # Transaction distribution
> system.membus.trans_dist::CleanEvict 34 # Transaction distribution
1208,1214c1216,1222
< system.membus.trans_dist::ReadExReq 341 # Transaction distribution
< system.membus.trans_dist::ReadExResp 341 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 33275 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadExReq 340 # Transaction distribution
> system.membus.trans_dist::ReadExResp 340 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 18175 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37156 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 37156 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1190592 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 1190592 # Cumulative packet size per connected master and slave (bytes)
1217c1225
< system.membus.snoop_fanout::samples 16759 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 18519 # Request fanout histogram
1221c1229
< system.membus.snoop_fanout::0 16759 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 18519 100.00% 100.00% # Request fanout histogram
1226,1230c1234,1238
< system.membus.snoop_fanout::total 16759 # Request fanout histogram
< system.membus.reqLayer0.occupancy 27529285 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 86434816 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---
> system.membus.snoop_fanout::total 18519 # Request fanout histogram
> system.membus.reqLayer0.occupancy 29524488 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer1.occupancy 97237655 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.2 # Layer utilization (%)