3,5c3,5
< sim_seconds 0.057719 # Number of seconds simulated
< sim_ticks 57719377000 # Number of ticks simulated
< final_tick 57719377000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.058203 # Number of seconds simulated
> sim_ticks 58202727500 # Number of ticks simulated
> final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 125223 # Simulator instruction rate (inst/s)
< host_op_rate 125847 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 79786059 # Simulator tick rate (ticks/s)
< host_mem_usage 443544 # Number of bytes of host memory used
< host_seconds 723.43 # Real time elapsed on the host
---
> host_inst_rate 129726 # Simulator instruction rate (inst/s)
> host_op_rate 130372 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 83346935 # Simulator tick rate (ticks/s)
> host_mem_usage 443628 # Number of bytes of host memory used
> host_seconds 698.32 # Real time elapsed on the host
16,53c16,53
< system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 43648 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 927744 # Number of bytes read from this memory
< system.physmem.bytes_read::total 1015808 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory
< system.physmem.bytes_written::total 19776 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 682 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 14496 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15872 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 309 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 769516 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 756211 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 16073354 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 17599081 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 769516 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 769516 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 342623 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 342623 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 342623 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 769516 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 756211 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 16073354 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17941704 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15872 # Number of read requests accepted
< system.physmem.writeReqs 309 # Number of write requests accepted
< system.physmem.readBursts 15872 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 1006016 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue
< system.physmem.bytesWritten 18432 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 1015808 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bytes_read::cpu.inst 44480 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 45376 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 930112 # Number of bytes read from this memory
> system.physmem.bytes_read::total 1019968 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 44480 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 44480 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 22912 # Number of bytes written to this memory
> system.physmem.bytes_written::total 22912 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 695 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 709 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 14533 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15937 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 358 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 358 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 764225 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 779620 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 15980557 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 17524402 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 764225 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 764225 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 393659 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 393659 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 393659 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 764225 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 779620 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 15980557 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 17918061 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15937 # Number of read requests accepted
> system.physmem.writeReqs 358 # Number of write requests accepted
> system.physmem.readBursts 15937 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 358 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 1010432 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue
> system.physmem.bytesWritten 21184 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 1019968 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 22912 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one
55c55
< system.physmem.perBankRdBursts::0 999 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 1009 # Per bank write bursts
57,58c57,58
< system.physmem.perBankRdBursts::2 956 # Per bank write bursts
< system.physmem.perBankRdBursts::3 1023 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 958 # Per bank write bursts
> system.physmem.perBankRdBursts::3 1024 # Per bank write bursts
60,63c60,63
< system.physmem.perBankRdBursts::5 1127 # Per bank write bursts
< system.physmem.perBankRdBursts::6 1115 # Per bank write bursts
< system.physmem.perBankRdBursts::7 1101 # Per bank write bursts
< system.physmem.perBankRdBursts::8 1033 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 1132 # Per bank write bursts
> system.physmem.perBankRdBursts::6 1124 # Per bank write bursts
> system.physmem.perBankRdBursts::7 1103 # Per bank write bursts
> system.physmem.perBankRdBursts::8 1046 # Per bank write bursts
67,71c67,71
< system.physmem.perBankRdBursts::12 910 # Per bank write bursts
< system.physmem.perBankRdBursts::13 886 # Per bank write bursts
< system.physmem.perBankRdBursts::14 919 # Per bank write bursts
< system.physmem.perBankRdBursts::15 912 # Per bank write bursts
< system.physmem.perBankWrBursts::0 23 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 909 # Per bank write bursts
> system.physmem.perBankRdBursts::13 889 # Per bank write bursts
> system.physmem.perBankRdBursts::14 926 # Per bank write bursts
> system.physmem.perBankRdBursts::15 930 # Per bank write bursts
> system.physmem.perBankWrBursts::0 30 # Per bank write bursts
73,75c73,75
< system.physmem.perBankWrBursts::2 4 # Per bank write bursts
< system.physmem.perBankWrBursts::3 0 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 8 # Per bank write bursts
> system.physmem.perBankWrBursts::3 1 # Per bank write bursts
> system.physmem.perBankWrBursts::4 10 # Per bank write bursts
77,79c77,79
< system.physmem.perBankWrBursts::6 62 # Per bank write bursts
< system.physmem.perBankWrBursts::7 30 # Per bank write bursts
< system.physmem.perBankWrBursts::8 15 # Per bank write bursts
---
> system.physmem.perBankWrBursts::6 69 # Per bank write bursts
> system.physmem.perBankWrBursts::7 31 # Per bank write bursts
> system.physmem.perBankWrBursts::8 36 # Per bank write bursts
81,83c81,83
< system.physmem.perBankWrBursts::10 10 # Per bank write bursts
< system.physmem.perBankWrBursts::11 1 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9 # Per bank write bursts
---
> system.physmem.perBankWrBursts::10 7 # Per bank write bursts
> system.physmem.perBankWrBursts::11 0 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7 # Per bank write bursts
85,86c85,86
< system.physmem.perBankWrBursts::14 48 # Per bank write bursts
< system.physmem.perBankWrBursts::15 21 # Per bank write bursts
---
> system.physmem.perBankWrBursts::14 45 # Per bank write bursts
> system.physmem.perBankWrBursts::15 31 # Per bank write bursts
89c89
< system.physmem.totGap 57719226000 # Total gap between requests
---
> system.physmem.totGap 58202569500 # Total gap between requests
96c96
< system.physmem.readPktSize::6 15872 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 15937 # Read request sizes (log2)
103,114c103,114
< system.physmem.writePktSize::6 309 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 10641 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2671 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 352 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 295 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 287 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 293 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 358 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 10945 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2405 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 349 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 310 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 297 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 305 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 289 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 304 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 62 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
151,162c151,162
< system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 17 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 20 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see
164,168c164,168
< system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 18 # What write queue length does an incoming req see
200,233c200,232
< system.physmem.bytesPerActivate::samples 1739 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 588.402530 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 354.168959 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 429.121053 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 443 25.47% 25.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 194 11.16% 36.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 91 5.23% 41.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 64 3.68% 45.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 57 3.28% 48.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 43 2.47% 51.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 46 2.65% 53.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 54 3.11% 57.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 747 42.96% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1739 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 981 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 40.634826 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 3762.941438 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 15 93.75% 93.75% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::14848-15359 1 6.25% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.975187 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.966092 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 11 68.75% 81.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 2 12.50% 93.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads
< system.physmem.totQLat 179464908 # Total ticks spent queuing
< system.physmem.totMemAccLat 474196158 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 78595000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 11417.07 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1871 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 551.268840 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 315.885566 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 433.770323 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 552 29.50% 29.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 218 11.65% 41.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 92 4.92% 46.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 57 3.05% 49.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 63 3.37% 52.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 44 2.35% 54.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 55 2.94% 57.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 42 2.24% 60.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 748 39.98% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1871 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 18 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 874.777778 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 39.760140 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 3541.219224 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 17 94.44% 94.44% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::14848-15359 1 5.56% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 18 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 18 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 18.388889 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.356746 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.195033 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 15 83.33% 83.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 2 11.11% 94.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 1 5.56% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 18 # Writes before turning the bus around for reads
> system.physmem.totQLat 172783990 # Total ticks spent queuing
> system.physmem.totMemAccLat 468808990 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 78940000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10944.01 # Average queueing delay per DRAM burst
235,239c234,238
< system.physmem.avgMemAccLat 30167.07 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 0.32 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 17.60 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 0.34 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 29694.01 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 17.36 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 0.36 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 17.52 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 0.39 # Average system write bandwidth in MiByte/s
244,262c243,261
< system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing
< system.physmem.readRowHits 14166 # Number of row buffer hits during reads
< system.physmem.writeRowHits 92 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 29.97 # Row buffer hit rate for writes
< system.physmem.avgGap 3567098.82 # Average gap between requests
< system.physmem.pageHitRate 88.97 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 7053480 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 3848625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 64162800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 959040 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 2338304445 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 32576022750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 38759797860 # Total energy per rank (pJ)
< system.physmem_0.averagePower 671.607894 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 54183699610 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states
---
> system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 16.15 # Average write queue length when enqueuing
> system.physmem.readRowHits 14154 # Number of row buffer hits during reads
> system.physmem.writeRowHits 93 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 26.20 # Row buffer hit rate for writes
> system.physmem.avgGap 3571805.43 # Average gap between requests
> system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 64638600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 1153440 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2451888630 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 32770707750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 39101711325 # Total energy per rank (pJ)
> system.physmem_0.averagePower 671.822097 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 54506616189 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1943500000 # Time in different power states
264c263
< system.physmem_0.memoryStateTime::ACT 1601139140 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1752376311 # Time in different power states
266,276c265,275
< system.physmem_1.actEnergy 6002640 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3275250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 58133400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 803520 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 2319744105 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 32592295500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 38749701135 # Total energy per rank (pJ)
< system.physmem_1.averagePower 671.433104 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 54217128450 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states
---
> system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 58484400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 991440 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2431326735 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 32788744500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 39091058805 # Total energy per rank (pJ)
> system.physmem_1.averagePower 671.639072 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 54537138662 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1943500000 # Time in different power states
278c277
< system.physmem_1.memoryStateTime::ACT 1573598050 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1721853838 # Time in different power states
280,284c279,283
< system.cpu.branchPred.lookups 28271166 # Number of BP lookups
< system.cpu.branchPred.condPredicted 23289258 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 837919 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 11857915 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 11789421 # Number of BTB hits
---
> system.cpu.branchPred.lookups 28259323 # Number of BP lookups
> system.cpu.branchPred.condPredicted 23281308 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 837964 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 11850778 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 11785443 # Number of BTB hits
286,288c285,287
< system.cpu.branchPred.BTBHitPct 99.422377 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 75707 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 99.448686 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 75758 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 89 # Number of incorrect RAS predictions.
407c406
< system.cpu.numCycles 115438755 # number of cpu cycles simulated
---
> system.cpu.numCycles 116405456 # number of cpu cycles simulated
410,422c409,421
< system.cpu.fetch.icacheStallCycles 750677 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 135029605 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 28271166 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 11865128 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 113801477 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1679415 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 1154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.IcacheWaitRetryStallCycles 715 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 32315558 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 115393730 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.175455 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.320715 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 749294 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 134993998 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 28259323 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 11861201 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 114761716 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1679249 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 1000 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.IcacheWaitRetryStallCycles 840 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 32304088 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 579 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 116352474 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.165469 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.319047 # Number of instructions fetched each cycle (Total)
424,427c423,426
< system.cpu.fetch.rateDist::0 57838402 50.12% 50.12% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 13925125 12.07% 62.19% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 9175651 7.95% 70.14% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 34454552 29.86% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 58780581 50.52% 50.52% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 13944559 11.98% 62.50% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 9221403 7.93% 70.43% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 34405931 29.57% 100.00% # Number of instructions fetched each cycle (Total)
431,458c430,457
< system.cpu.fetch.rateDist::total 115393730 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.244902 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.169708 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 8870766 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 63114849 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 33033969 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 9546674 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 827472 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 4101024 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 12335 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 114392732 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 1987220 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 827472 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 15224664 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 49207626 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 108919 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 35472493 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 14552556 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 110856042 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 1413744 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 11047079 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 1056491 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1457150 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 456315 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 129915292 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 483076638 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 119437218 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 116352474 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.242766 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.159688 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 8844184 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 64087377 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 33032699 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 9560836 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 827378 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 4101289 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 12349 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 114434840 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 1995518 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 827378 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 15306554 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 49837632 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 110028 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 35408205 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 14862677 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 110902804 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 1415247 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 11133046 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 1143083 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1515709 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 570063 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 129962368 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 483290389 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 119478713 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 424 # Number of floating rename lookups
460c459
< system.cpu.rename.UndoneMaps 22602373 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 22649449 # Number of HB maps that are undone due to squashing
463,477c462,476
< system.cpu.rename.skidInsts 21217869 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 26815015 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 5348915 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 559856 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 297304 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 109685726 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 101429576 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 1059441 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 18455382 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 41507392 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 115393730 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.878987 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.999963 # Number of insts issued each cycle
---
> system.cpu.rename.skidInsts 21572068 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 26814283 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 5349560 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 615072 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 351208 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 109694902 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 101389982 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 1073881 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 18465721 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 41703174 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 116352474 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.871404 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.988585 # Number of insts issued each cycle
479,483c478,482
< system.cpu.iq.issued_per_cycle::0 54518642 47.25% 47.25% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 30124755 26.11% 73.35% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 22142664 19.19% 92.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 7411500 6.42% 98.96% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 1195852 1.04% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 54656656 46.98% 46.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 31447896 27.03% 74.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 21997479 18.91% 92.91% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 7054961 6.06% 98.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1195165 1.03% 100.00% # Number of insts issued each cycle
491c490
< system.cpu.iq.issued_per_cycle::total 115393730 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 116352474 # Number of insts issued each cycle
493,523c492,522
< system.cpu.iq.fu_full::IntAlu 9750384 48.86% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 9494227 47.58% 96.44% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 710033 3.56% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 9796147 48.71% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 50 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 9605529 47.77% 96.48% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 708223 3.52% 100.00% # attempts to use FU when none available
527,557c526,556
< system.cpu.iq.FU_type_0::IntAlu 71988081 70.97% 70.97% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 55 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 24381590 24.04% 95.02% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 5049013 4.98% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 71985557 71.00% 71.00% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 24344215 24.01% 95.02% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 5049315 4.98% 100.00% # Type of FU issued
560,566c559,565
< system.cpu.iq.FU_type_0::total 101429576 # Type of FU issued
< system.cpu.iq.rate 0.878644 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 19954707 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.196735 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 339266571 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 128150140 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 99658235 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 101389982 # Type of FU issued
> system.cpu.iq.rate 0.871007 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 20109961 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.198343 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 340315821 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 128169527 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 99626078 # Number of integer instruction queue wakeup accesses
568,570c567,569
< system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 121384044 # Number of integer alu accesses
---
> system.cpu.iq.fp_inst_queue_writes 609 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 121499704 # Number of integer alu accesses
572c571
< system.cpu.iew.lsq.thread0.forwLoads 285219 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 282708 # Number of loads that had data forwarded from stores
574,577c573,576
< system.cpu.iew.lsq.thread0.squashedLoads 4339104 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 1483 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 1422 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 604071 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 4338372 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 1511 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 1302 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 604716 # Number of stores squashed
580,581c579,580
< system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 130466 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 7561 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 130367 # Number of times an access to memory failed due to the cache being blocked
583,586c582,585
< system.cpu.iew.iewSquashCycles 827472 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 8003638 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 730506 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 109706640 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 827378 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 8117043 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 661508 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 109715814 # Number of instructions dispatched to IQ
588,599c587,598
< system.cpu.iew.iewDispLoadInsts 26815015 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 5348915 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 187146 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 360894 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 1422 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 436340 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 849212 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 100146798 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 23824665 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1282778 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 26814283 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 5349560 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 4358 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 178487 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 319637 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 1302 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 436579 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 412967 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 849546 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 100128293 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 23807365 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1261689 # Number of squashed instructions skipped in execute
601,609c600,608
< system.cpu.iew.exec_nop 12667 # number of nop insts executed
< system.cpu.iew.exec_refs 28743608 # number of memory reference insts executed
< system.cpu.iew.exec_branches 20629236 # Number of branches executed
< system.cpu.iew.exec_stores 4918943 # Number of stores executed
< system.cpu.iew.exec_rate 0.867532 # Inst execution rate
< system.cpu.iew.wb_sent 99756620 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 99658354 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 59706662 # num instructions producing a value
< system.cpu.iew.wb_consumers 95558908 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 12666 # number of nop insts executed
> system.cpu.iew.exec_refs 28725194 # number of memory reference insts executed
> system.cpu.iew.exec_branches 20624883 # Number of branches executed
> system.cpu.iew.exec_stores 4917829 # Number of stores executed
> system.cpu.iew.exec_rate 0.860168 # Inst execution rate
> system.cpu.iew.wb_sent 99711182 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 99626193 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 59706016 # num instructions producing a value
> system.cpu.iew.wb_consumers 95562461 # num instructions consuming a value
611,612c610,611
< system.cpu.iew.wb_rate 0.863301 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.624815 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.855855 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.624785 # average fanout of values written-back
614c613
< system.cpu.commit.commitSquashedInsts 17391201 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 17390136 # The number of squashed insts skipped by commit
616,619c615,618
< system.cpu.commit.branchMispredicts 825684 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 112699801 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.807931 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.745752 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 825718 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 113659456 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.801109 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.737097 # Number of insts commited each cycle
621,629c620,628
< system.cpu.commit.committed_per_cycle::0 76441556 67.83% 67.83% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 18447200 16.37% 84.20% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 7119761 6.32% 90.51% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 3375676 3.00% 93.51% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1760831 1.56% 95.07% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 536786 0.48% 95.55% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 726119 0.64% 96.19% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 179056 0.16% 96.35% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 4112816 3.65% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 77211009 67.93% 67.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 18641585 16.40% 84.33% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 7152887 6.29% 90.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 3463018 3.05% 93.67% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1652627 1.45% 95.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 524640 0.46% 95.59% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 723684 0.64% 96.23% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 178635 0.16% 96.38% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 4111371 3.62% 100.00% # Number of insts commited each cycle
633c632
< system.cpu.commit.committed_per_cycle::total 112699801 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 113659456 # Number of insts commited each cycle
679c678
< system.cpu.commit.bw_lim_events 4112816 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached
681,684c680,683
< system.cpu.rob.rob_reads 217026090 # The number of ROB reads
< system.cpu.rob.rob_writes 219584249 # The number of ROB writes
< system.cpu.timesIdled 586 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 45025 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 217986125 # The number of ROB reads
> system.cpu.rob.rob_writes 219581178 # The number of ROB writes
> system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 52982 # Total number of cycles that the CPU has spent unscheduled due to idling
687,692c686,691
< system.cpu.cpi 1.274302 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.274302 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.784743 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.784743 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 108125012 # number of integer regfile reads
< system.cpu.int_regfile_writes 58739124 # number of integer regfile writes
---
> system.cpu.cpi 1.284973 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.284973 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.778226 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.778226 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 108112973 # number of integer regfile reads
> system.cpu.int_regfile_writes 58701982 # number of integer regfile writes
694,697c693,696
< system.cpu.fp_regfile_writes 99 # number of floating regfile writes
< system.cpu.cc_regfile_reads 369256929 # number of cc regfile reads
< system.cpu.cc_regfile_writes 58699332 # number of cc regfile writes
< system.cpu.misc_regfile_reads 28460693 # number of misc regfile reads
---
> system.cpu.fp_regfile_writes 95 # number of floating regfile writes
> system.cpu.cc_regfile_reads 369069288 # number of cc regfile reads
> system.cpu.cc_regfile_writes 58692619 # number of cc regfile writes
> system.cpu.misc_regfile_reads 28415446 # number of misc regfile reads
699,707c698,706
< system.cpu.dcache.tags.replacements 5486247 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.800439 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 18271247 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 5486759 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 3.330062 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 33236000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.800439 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999610 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999610 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.replacements 5469543 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.788616 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 18297454 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 5470055 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 3.345022 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 35157000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.788616 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999587 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999587 # Average percentage of cache occupancy
709,710c708,709
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
712,717c711,716
< system.cpu.dcache.tags.tag_accesses 61970439 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 61970439 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 13905626 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13905626 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4357324 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4357324 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 61924995 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 61924995 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 13934183 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13934183 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4354974 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4354974 # number of WriteReq hits
724,733c723,732
< system.cpu.dcache.demand_hits::cpu.data 18262950 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 18262950 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 18263472 # number of overall hits
< system.cpu.dcache.overall_hits::total 18263472 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 9592929 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 9592929 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 377657 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 377657 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 18289157 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 18289157 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 18289679 # number of overall hits
> system.cpu.dcache.overall_hits::total 18289679 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 9550003 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 9550003 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 380007 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 380007 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
736,751c735,750
< system.cpu.dcache.demand_misses::cpu.data 9970586 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9970586 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9970594 # number of overall misses
< system.cpu.dcache.overall_misses::total 9970594 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 87008583027 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 87008583027 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 3975903343 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 3975903343 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 269500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 269500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 90984486370 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 90984486370 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 90984486370 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 90984486370 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23498555 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23498555 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 9930010 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9930010 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9930017 # number of overall misses
> system.cpu.dcache.overall_misses::total 9930017 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 88443276736 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 88443276736 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 3962066244 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 3962066244 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 297000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 92405342980 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 92405342980 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 92405342980 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 92405342980 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23484186 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23484186 # number of ReadReq accesses(hits+misses)
754,755c753,754
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
760,769c759,768
< system.cpu.dcache.demand_accesses::cpu.data 28233536 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 28233536 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 28234066 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 28234066 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408235 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.408235 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 28219167 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 28219167 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 28219696 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 28219696 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.406657 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.406657 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080255 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.080255 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
772,791c771,790
< system.cpu.dcache.demand_miss_rate::cpu.data 0.353147 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.353147 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.353141 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.353141 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9070.074742 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 9070.074742 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10527.815830 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 10527.815830 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17966.666667 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17966.666667 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 9125.289764 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 9125.289764 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 9125.282443 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 9125.282443 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 301798 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 69284 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 120550 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 12191 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.503509 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 5.683209 # average number of cycles each access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.351889 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.351889 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.351882 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.351882 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9261.073189 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 9261.073189 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10426.298052 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 10426.298052 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19800 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19800 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 9305.664645 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 9305.664645 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 9305.658085 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 9305.658085 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 306020 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 36082 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 120709 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 2278 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.535188 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 15.839333 # average number of cycles each access was blocked
794,799c793,798
< system.cpu.dcache.writebacks::writebacks 5460017 # number of writebacks
< system.cpu.dcache.writebacks::total 5460017 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328962 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 4328962 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154868 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 154868 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 5439051 # number of writebacks
> system.cpu.dcache.writebacks::total 5439051 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4313021 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 4313021 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 146936 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 146936 # number of WriteReq MSHR hits
802,845c801,844
< system.cpu.dcache.demand_mshr_hits::cpu.data 4483830 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 4483830 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 4483830 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 4483830 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263967 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 5263967 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222789 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 222789 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 5486756 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 5486756 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 5486761 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 5486761 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38199288241 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 38199288241 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2164503781 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2164503781 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 250500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 250500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40363792022 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 40363792022 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40364042522 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 40364042522 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224012 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224012 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194335 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.194335 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194331 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.194331 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7256.749186 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7256.749186 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9715.487663 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9715.487663 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50100 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50100 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7356.585936 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 7356.585936 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7356.624887 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 7356.624887 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 4459957 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 4459957 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 4459957 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 4459957 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5236982 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 5236982 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 233071 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 233071 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 5470053 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 5470053 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 5470057 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 5470057 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40519086258 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 40519086258 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2295163471 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2295163471 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 213000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 213000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42814249729 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 42814249729 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42814462729 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 42814462729 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223000 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223000 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049223 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049223 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193842 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.193842 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193838 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.193838 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7737.106268 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7737.106268 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9847.486264 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9847.486264 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53250 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53250 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7827.026489 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 7827.026489 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7827.059705 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 7827.059705 # average overall mshr miss latency
847,851c846,850
< system.cpu.icache.tags.replacements 447 # number of replacements
< system.cpu.icache.tags.tagsinuse 428.924531 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 32314402 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 35667.110375 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 451 # number of replacements
> system.cpu.icache.tags.tagsinuse 428.263511 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 32302915 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 35497.708791 # Average number of references to valid blocks.
853,855c852,854
< system.cpu.icache.tags.occ_blocks::cpu.inst 428.924531 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.837743 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.837743 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 428.263511 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.836452 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.836452 # Average percentage of cache occupancy
862,905c861,904
< system.cpu.icache.tags.tag_accesses 64631998 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 64631998 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 32314402 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 32314402 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 32314402 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 32314402 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 32314402 # number of overall hits
< system.cpu.icache.overall_hits::total 32314402 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1144 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1144 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1144 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1144 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1144 # number of overall misses
< system.cpu.icache.overall_misses::total 1144 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 55657984 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 55657984 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 55657984 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 55657984 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 55657984 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 55657984 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 32315546 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 32315546 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 32315546 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 32315546 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 32315546 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 32315546 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48652.083916 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 48652.083916 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 48652.083916 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 48652.083916 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 48652.083916 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 48652.083916 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 17056 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 223 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 76.484305 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked
---
> system.cpu.icache.tags.tag_accesses 64609056 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 64609056 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 32302915 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 32302915 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 32302915 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 32302915 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 32302915 # number of overall hits
> system.cpu.icache.overall_hits::total 32302915 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses
> system.cpu.icache.overall_misses::total 1158 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 62669987 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 62669987 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 62669987 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 62669987 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 62669987 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 62669987 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 32304073 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 32304073 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 32304073 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 32304073 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 32304073 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 32304073 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54119.159758 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54119.159758 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54119.159758 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54119.159758 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 19414 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 134 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 238 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 81.571429 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 26.800000 # average number of cycles each access was blocked
908,925c907,924
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 238 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 238 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 238 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 238 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 238 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 906 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 906 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 906 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 906 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 906 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44276742 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 44276742 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44276742 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 44276742 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44276742 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 44276742 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50368733 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 50368733 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50368733 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 50368733 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50368733 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 50368733 # number of overall MSHR miss cycles
932,937c931,936
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48870.576159 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48870.576159 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 48870.576159 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 48870.576159 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55350.256044 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55350.256044 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55350.256044 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 55350.256044 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55350.256044 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 55350.256044 # average overall mshr miss latency
939,941c938,940
< system.cpu.l2cache.prefetcher.num_hwpf_issued 4494242 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 5296949 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 693182 # number of redundant prefetches already in prefetch queue
---
> system.cpu.l2cache.prefetcher.num_hwpf_issued 4495585 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 5292074 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 687825 # number of redundant prefetches already in prefetch queue
944,949c943,948
< system.cpu.l2cache.prefetcher.pfSpanPage 14114027 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.replacements 432 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 12071.451375 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 10694296 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 15874 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 673.698879 # Average number of references to valid blocks.
---
> system.cpu.l2cache.prefetcher.pfSpanPage 14072766 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.replacements 493 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 12074.856330 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 10653372 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 15934 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 668.593699 # Average number of references to valid blocks.
951,961c950,960
< system.cpu.l2cache.tags.occ_blocks::writebacks 11103.819168 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 569.155490 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 195.974498 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 202.502218 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.677723 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.034738 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.011961 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.012360 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.736783 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 240 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15202 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 11119.543661 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 571.365929 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 202.646634 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 181.300106 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.678683 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.034873 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.012369 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.011066 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.736991 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 216 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15225 # Occupied blocks per task id
964,991c963,990
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 5 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 214 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1059 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13108 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.014648 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927856 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 175404109 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 175404109 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 211 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 5261084 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 5261295 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 5460017 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 5460017 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 224780 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 224780 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 211 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 5485864 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 5486075 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 211 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 5485864 # number of overall hits
< system.cpu.l2cache.overall_hits::total 5486075 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 695 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 386 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 13 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 974 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1048 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13130 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.013184 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.929260 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 174809424 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 174809424 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 213 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 5236439 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 5236652 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 5439051 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 5439051 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 232688 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 232688 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 213 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 5469127 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 5469340 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 213 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 5469127 # number of overall hits
> system.cpu.l2cache.overall_hits::total 5469340 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 697 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 416 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 1113 # number of ReadReq misses
994,1019c993,1018
< system.cpu.l2cache.ReadExReq_misses::cpu.data 509 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 509 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 895 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1590 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 895 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1590 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42529250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21068985 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 63598235 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30498 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 30498 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 34497490 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 34497490 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 42529250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 55566475 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 98095725 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 42529250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 55566475 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 98095725 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 906 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 5261470 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 5262376 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 5460017 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 5460017 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 512 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 512 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 697 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 928 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1625 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 697 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 928 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1625 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48506493 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26932750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 75439243 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 46498 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 46498 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37042063 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 37042063 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 48506493 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 63974813 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 112481306 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 48506493 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 63974813 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 112481306 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 910 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 5236855 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 5237765 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 5439051 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 5439051 # number of Writeback accesses(hits+misses)
1022,1032c1021,1031
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 225289 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 225289 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 906 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 5486759 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 5487665 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 906 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 5486759 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 5487665 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.767108 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000073 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.000205 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 233200 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 233200 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 910 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 5470055 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 5470965 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 910 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 5470055 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 5470965 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.765934 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000079 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.000212 # miss rate for ReadReq accesses
1035,1055c1034,1054
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002259 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.002259 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767108 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.000290 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767108 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.000290 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61193.165468 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54582.862694 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 58832.779833 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15249 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15249 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67775.029470 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67775.029470 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61193.165468 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 62085.446927 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 61695.424528 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61193.165468 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 62085.446927 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 61695.424528 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002196 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.002196 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.765934 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.000170 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.000297 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.765934 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.000170 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.000297 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69593.246772 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64742.187500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 67780.092543 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23249 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23249 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72347.779297 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72347.779297 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69593.246772 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68938.376078 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 69219.265231 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69593.246772 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68938.376078 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 69219.265231 # average overall miss latency
1064,1081c1063,1080
< system.cpu.l2cache.writebacks::writebacks 309 # number of writebacks
< system.cpu.l2cache.writebacks::total 309 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 168 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 168 # number of ReadExReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 214 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 694 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 341 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 1035 # number of ReadReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20230 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 20230 # number of HardPFReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 358 # number of writebacks
> system.cpu.l2cache.writebacks::total 358 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 48 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 171 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 171 # number of ReadExReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 221 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 695 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 368 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 1063 # number of ReadReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20246 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 20246 # number of HardPFReq MSHR misses
1086,1111c1085,1110
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 682 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1376 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 682 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20230 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 21606 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36534500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16113750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52648250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 777111161 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 22591778 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 22591778 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36534500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 38705528 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 75240028 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36534500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 38705528 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 852351189 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000197 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 695 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 709 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1404 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 695 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 709 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20246 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 21650 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42518507 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21103750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63622257 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 830590289 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 25988008 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 25988008 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42518507 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47091758 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 89610265 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42518507 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47091758 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 920200554 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000070 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000203 # mshr miss rate for ReadReq accesses
1116,1122c1115,1121
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.000251 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001462 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001462 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.000257 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for overall accesses
1124,1140c1123,1139
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.003937 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52643.371758 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47254.398827 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50867.874396 # average ReadReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38413.799357 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66251.548387 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66251.548387 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54680.252907 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39449.744932 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.003957 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61177.707914 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57347.146739 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59851.605833 # average ReadReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41024.908081 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76211.167155 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76211.167155 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63824.975071 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.489792 # average overall mshr miss latency
1142,1145c1141,1144
< system.cpu.toL2Bus.trans_dist::ReadReq 5262376 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 5262376 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 5460017 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 22339 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 5237765 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 5237765 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 5439051 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 22132 # Transaction distribution
1149,1160c1148,1159
< system.cpu.toL2Bus.trans_dist::ReadExReq 225289 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 225289 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1812 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16433541 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 16435353 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57984 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700593792 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 700651776 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 22341 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 10970023 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.002036 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.045080 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 233200 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 233200 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1820 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16379167 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 16380987 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698182912 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 698241152 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 22134 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 10932150 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.002024 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.044949 # Request fanout histogram
1165,1168c1164,1165
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 10947684 99.80% 99.80% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 22339 0.20% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 10910018 99.80% 99.80% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 22132 0.20% 100.00% # Request fanout histogram
1170,1174c1167,1171
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 10970023 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 10933859000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 18.9 # Layer utilization (%)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 10932150 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 10894060998 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%)
1177c1174
< system.cpu.toL2Bus.respLayer0.occupancy 1479748 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1497004 # Layer occupancy (ticks)
1179,1183c1176,1180
< system.cpu.toL2Bus.respLayer1.occupancy 8230187517 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%)
< system.membus.trans_dist::ReadReq 15531 # Transaction distribution
< system.membus.trans_dist::ReadResp 15531 # Transaction distribution
< system.membus.trans_dist::Writeback 309 # Transaction distribution
---
> system.cpu.toL2Bus.respLayer1.occupancy 8205133181 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%)
> system.membus.trans_dist::ReadReq 15596 # Transaction distribution
> system.membus.trans_dist::ReadResp 15596 # Transaction distribution
> system.membus.trans_dist::Writeback 358 # Transaction distribution
1188,1191c1185,1188
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32057 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 32057 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1035584 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 1035584 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32236 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 32236 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1042880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 1042880 # Cumulative packet size per connected master and slave (bytes)
1193c1190
< system.membus.snoop_fanout::samples 16183 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 16297 # Request fanout histogram
1197c1194
< system.membus.snoop_fanout::0 16183 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 16297 100.00% 100.00% # Request fanout histogram
1202,1203c1199,1200
< system.membus.snoop_fanout::total 16183 # Request fanout histogram
< system.membus.reqLayer0.occupancy 28002068 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 16297 # Request fanout histogram
> system.membus.reqLayer0.occupancy 26854780 # Layer occupancy (ticks)
1205,1206c1202,1203
< system.membus.respLayer1.occupancy 149256371 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 83365318 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.1 # Layer utilization (%)