Cross Reference: /gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt

Deleted Added

sdiff udiff text old ( 11860:67dee11badea ) new ( 11955:1170d039b31e )

full compact

stats.txt (11860:67dee11badea)	stats.txt (11955:1170d039b31e)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058521 # Number of seconds simulated 4sim_ticks 58521086000 # Number of ticks simulated 5final_tick 58521086000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 243648 # Simulator instruction rate (inst/s) 8host_op_rate 244862 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 157397000 # Simulator tick rate (ticks/s) 10host_mem_usage 492140 # Number of bytes of host memory used 11host_seconds 371.81 # Real time elapsed on the host 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 220224 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 # Number of bytes read from this memory 20system.physmem.bytes_read::total 1186880 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 4736 # Number of bytes written to this memory 24system.physmem.bytes_written::total 4736 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 3441 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 14405 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 18545 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 74 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 74 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 764442 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 3763156 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 20281237 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 764442 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 764442 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 80928 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 80928 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 80928 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 764442 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 3763156 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 20362165 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 18546 # Number of read requests accepted 45system.physmem.writeReqs 74 # Number of write requests accepted 46system.physmem.readBursts 18546 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 74 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 1183360 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue 50system.physmem.bytesWritten 3328 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 1186944 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 4736 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 56system.physmem.perBankRdBursts::0 3297 # Per bank write bursts 57system.physmem.perBankRdBursts::1 920 # Per bank write bursts 58system.physmem.perBankRdBursts::2 949 # Per bank write bursts 59system.physmem.perBankRdBursts::3 1031 # Per bank write bursts 60system.physmem.perBankRdBursts::4 1067 # Per bank write bursts 61system.physmem.perBankRdBursts::5 1119 # Per bank write bursts 62system.physmem.perBankRdBursts::6 1093 # Per bank write bursts 63system.physmem.perBankRdBursts::7 1097 # Per bank write bursts 64system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 65system.physmem.perBankRdBursts::9 961 # Per bank write bursts 66system.physmem.perBankRdBursts::10 934 # Per bank write bursts 67system.physmem.perBankRdBursts::11 899 # Per bank write bursts 68system.physmem.perBankRdBursts::12 902 # Per bank write bursts 69system.physmem.perBankRdBursts::13 895 # Per bank write bursts 70system.physmem.perBankRdBursts::14 1399 # Per bank write bursts 71system.physmem.perBankRdBursts::15 903 # Per bank write bursts 72system.physmem.perBankWrBursts::0 1 # Per bank write bursts 73system.physmem.perBankWrBursts::1 0 # Per bank write bursts 74system.physmem.perBankWrBursts::2 2 # Per bank write bursts 75system.physmem.perBankWrBursts::3 0 # Per bank write bursts 76system.physmem.perBankWrBursts::4 1 # Per bank write bursts 77system.physmem.perBankWrBursts::5 14 # Per bank write bursts 78system.physmem.perBankWrBursts::6 9 # Per bank write bursts 79system.physmem.perBankWrBursts::7 3 # Per bank write bursts 80system.physmem.perBankWrBursts::8 1 # Per bank write bursts 81system.physmem.perBankWrBursts::9 0 # Per bank write bursts 82system.physmem.perBankWrBursts::10 2 # Per bank write bursts 83system.physmem.perBankWrBursts::11 0 # Per bank write bursts 84system.physmem.perBankWrBursts::12 1 # Per bank write bursts 85system.physmem.perBankWrBursts::13 12 # Per bank write bursts 86system.physmem.perBankWrBursts::14 5 # Per bank write bursts 87system.physmem.perBankWrBursts::15 1 # Per bank write bursts 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 90system.physmem.totGap 58521077500 # Total gap between requests 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) 97system.physmem.readPktSize::6 18546 # Read request sizes (log2) 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) 104system.physmem.writePktSize::6 74 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 12593 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 3390 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 500 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 319 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 299 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 279 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 103 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 137system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::15 3 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 3 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 3 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 3 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 3 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 3 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 3 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 3004 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 394.652463 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 214.589229 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 405.543781 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 3004 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 6161.333333 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::gmean 2123.401593 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::stdev 8586.829993 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 3 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 17.333333 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 17.306995 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 1.154701 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16 1 33.33% 33.33% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::18 2 66.67% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 3 # Writes before turning the bus around for reads 230system.physmem.totQLat 837911216 # Total ticks spent queuing 231system.physmem.totMemAccLat 1184598716 # Total ticks spent from burst creation until serviced by the DRAM 232system.physmem.totBusLat 92450000 # Total ticks spent in databus transfers 233system.physmem.avgQLat 45316.99 # Average queueing delay per DRAM burst 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 235system.physmem.avgMemAccLat 64066.99 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 20.22 # Average DRAM read bandwidth in MiByte/s 237system.physmem.avgWrBW 0.06 # Average achieved write bandwidth in MiByte/s 238system.physmem.avgRdBWSys 20.28 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 0.08 # Average system write bandwidth in MiByte/s 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 241system.physmem.busUtil 0.16 # Data bus utilization in percentage 242system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 244system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 245system.physmem.avgWrQLen 13.38 # Average write queue length when enqueuing 246system.physmem.readRowHits 15512 # Number of row buffer hits during reads 247system.physmem.writeRowHits 18 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 25.71 # Row buffer hit rate for writes 250system.physmem.avgGap 3142915.01 # Average gap between requests 251system.physmem.pageHitRate 83.67 # Row buffer hit rate, read and write combined 252system.physmem_0.actEnergy 16243500 # Energy for activate commands per rank (pJ) 253system.physmem_0.preEnergy 8614650 # Energy for precharge commands per rank (pJ) 254system.physmem_0.readEnergy 75484080 # Energy for read commands per rank (pJ) 255system.physmem_0.writeEnergy 156600 # Energy for write commands per rank (pJ) 256system.physmem_0.refreshEnergy 1895549760.000000 # Energy for refresh commands per rank (pJ) 257system.physmem_0.actBackEnergy 464945010 # Energy for active background per rank (pJ) 258system.physmem_0.preBackEnergy 99199680 # Energy for precharge background per rank (pJ) 259system.physmem_0.actPowerDownEnergy 4173482430 # Energy for active power-down per rank (pJ) 260system.physmem_0.prePowerDownEnergy 3272736480 # Energy for precharge power-down per rank (pJ) 261system.physmem_0.selfRefreshEnergy 9883191315 # Energy for self refresh per rank (pJ) 262system.physmem_0.totalEnergy 19894073865 # Total energy per rank (pJ) 263system.physmem_0.averagePower 339.947098 # Core power per rank (mW) 264system.physmem_0.totalIdleTime 57233116090 # Total Idle time Per DRAM Rank 265system.physmem_0.memoryStateTime::IDLE 194944250 # Time in different power states 266system.physmem_0.memoryStateTime::REF 806364000 # Time in different power states 267system.physmem_0.memoryStateTime::SREF 39558059500 # Time in different power states 268system.physmem_0.memoryStateTime::PRE_PDN 8522710566 # Time in different power states 269system.physmem_0.memoryStateTime::ACT 286661660 # Time in different power states 270system.physmem_0.memoryStateTime::ACT_PDN 9152346024 # Time in different power states 271system.physmem_1.actEnergy 5255040 # Energy for activate commands per rank (pJ) 272system.physmem_1.preEnergy 2785530 # Energy for precharge commands per rank (pJ) 273system.physmem_1.readEnergy 56527380 # Energy for read commands per rank (pJ) 274system.physmem_1.writeEnergy 114840 # Energy for write commands per rank (pJ) 275system.physmem_1.refreshEnergy 247699920.000000 # Energy for refresh commands per rank (pJ) 276system.physmem_1.actBackEnergy 125328180 # Energy for active background per rank (pJ) 277system.physmem_1.preBackEnergy 13397280 # Energy for precharge background per rank (pJ) 278system.physmem_1.actPowerDownEnergy 772336890 # Energy for active power-down per rank (pJ) 279system.physmem_1.prePowerDownEnergy 242624160 # Energy for precharge power-down per rank (pJ) 280system.physmem_1.selfRefreshEnergy 13451278005 # Energy for self refresh per rank (pJ) 281system.physmem_1.totalEnergy 14917407225 # Total energy per rank (pJ) 282system.physmem_1.averagePower 254.906533 # Core power per rank (mW) 283system.physmem_1.totalIdleTime 58211272096 # Total Idle time Per DRAM Rank 284system.physmem_1.memoryStateTime::IDLE 21634250 # Time in different power states 285system.physmem_1.memoryStateTime::REF 105218000 # Time in different power states 286system.physmem_1.memoryStateTime::SREF 55885668250 # Time in different power states 287system.physmem_1.memoryStateTime::PRE_PDN 631842954 # Time in different power states 288system.physmem_1.memoryStateTime::ACT 182961654 # Time in different power states 289system.physmem_1.memoryStateTime::ACT_PDN 1693760892 # Time in different power states 290system.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 291system.cpu.branchPred.lookups 28121660 # Number of BP lookups 292system.cpu.branchPred.condPredicted 23134709 # Number of conditional branches predicted 293system.cpu.branchPred.condIncorrect 844714 # Number of conditional branches incorrect 294system.cpu.branchPred.BTBLookups 11731332 # Number of BTB lookups 295system.cpu.branchPred.BTBHits 11630363 # Number of BTB hits 296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 297system.cpu.branchPred.BTBHitPct 99.139322 # BTB Hit Percentage 298system.cpu.branchPred.usedRAS 80725 # Number of times the RAS was used to get a target. 299system.cpu.branchPred.RASInCorrect 95 # Number of incorrect RAS predictions. 300system.cpu.branchPred.indirectLookups 28301 # Number of indirect predictor lookups. 301system.cpu.branchPred.indirectHits 25845 # Number of indirect target hits. 302system.cpu.branchPred.indirectMisses 2456 # Number of indirect misses. 303system.cpu.branchPredindirectMispredicted 243 # Number of mispredicted indirect branches. 304system.cpu_clk_domain.clock 500 # Clock period in ticks 305system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 306system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 315system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 316system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 317system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 318system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 319system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 322system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 323system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 324system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 325system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 326system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 327system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 328system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 329system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 330system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 331system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 332system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 333system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 334system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 335system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 336system.cpu.dtb.walker.walks 0 # Table walker walks requested 337system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.inst_hits 0 # ITB inst hits 345system.cpu.dtb.inst_misses 0 # ITB inst misses 346system.cpu.dtb.read_hits 0 # DTB read hits 347system.cpu.dtb.read_misses 0 # DTB read misses 348system.cpu.dtb.write_hits 0 # DTB write hits 349system.cpu.dtb.write_misses 0 # DTB write misses 350system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 351system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 352system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 353system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 354system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 355system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 356system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 357system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 358system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 359system.cpu.dtb.read_accesses 0 # DTB read accesses 360system.cpu.dtb.write_accesses 0 # DTB write accesses 361system.cpu.dtb.inst_accesses 0 # ITB inst accesses 362system.cpu.dtb.hits 0 # DTB hits 363system.cpu.dtb.misses 0 # DTB misses 364system.cpu.dtb.accesses 0 # DTB accesses 365system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 366system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 374system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 375system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 376system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 377system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 378system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 379system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 380system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 381system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 382system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 383system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 384system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 385system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 386system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 387system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 388system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 389system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 390system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 391system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 392system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 393system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 394system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 395system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 396system.cpu.itb.walker.walks 0 # Table walker walks requested 397system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.inst_hits 0 # ITB inst hits 405system.cpu.itb.inst_misses 0 # ITB inst misses 406system.cpu.itb.read_hits 0 # DTB read hits 407system.cpu.itb.read_misses 0 # DTB read misses 408system.cpu.itb.write_hits 0 # DTB write hits 409system.cpu.itb.write_misses 0 # DTB write misses 410system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 411system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 412system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 413system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 414system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 415system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 416system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 417system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 418system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 419system.cpu.itb.read_accesses 0 # DTB read accesses 420system.cpu.itb.write_accesses 0 # DTB write accesses 421system.cpu.itb.inst_accesses 0 # ITB inst accesses 422system.cpu.itb.hits 0 # DTB hits 423system.cpu.itb.misses 0 # DTB misses 424system.cpu.itb.accesses 0 # DTB accesses	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058521 # Number of seconds simulated 4sim_ticks 58521086000 # Number of ticks simulated 5final_tick 58521086000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 243648 # Simulator instruction rate (inst/s) 8host_op_rate 244862 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 157397000 # Simulator tick rate (ticks/s) 10host_mem_usage 492140 # Number of bytes of host memory used 11host_seconds 371.81 # Real time elapsed on the host 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 220224 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 # Number of bytes read from this memory 20system.physmem.bytes_read::total 1186880 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 4736 # Number of bytes written to this memory 24system.physmem.bytes_written::total 4736 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 3441 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 14405 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 18545 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 74 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 74 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 764442 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 3763156 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 20281237 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 764442 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 764442 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 80928 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 80928 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 80928 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 764442 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 3763156 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 20362165 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 18546 # Number of read requests accepted 45system.physmem.writeReqs 74 # Number of write requests accepted 46system.physmem.readBursts 18546 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 74 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 1183360 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue 50system.physmem.bytesWritten 3328 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 1186944 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 4736 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 56system.physmem.perBankRdBursts::0 3297 # Per bank write bursts 57system.physmem.perBankRdBursts::1 920 # Per bank write bursts 58system.physmem.perBankRdBursts::2 949 # Per bank write bursts 59system.physmem.perBankRdBursts::3 1031 # Per bank write bursts 60system.physmem.perBankRdBursts::4 1067 # Per bank write bursts 61system.physmem.perBankRdBursts::5 1119 # Per bank write bursts 62system.physmem.perBankRdBursts::6 1093 # Per bank write bursts 63system.physmem.perBankRdBursts::7 1097 # Per bank write bursts 64system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 65system.physmem.perBankRdBursts::9 961 # Per bank write bursts 66system.physmem.perBankRdBursts::10 934 # Per bank write bursts 67system.physmem.perBankRdBursts::11 899 # Per bank write bursts 68system.physmem.perBankRdBursts::12 902 # Per bank write bursts 69system.physmem.perBankRdBursts::13 895 # Per bank write bursts 70system.physmem.perBankRdBursts::14 1399 # Per bank write bursts 71system.physmem.perBankRdBursts::15 903 # Per bank write bursts 72system.physmem.perBankWrBursts::0 1 # Per bank write bursts 73system.physmem.perBankWrBursts::1 0 # Per bank write bursts 74system.physmem.perBankWrBursts::2 2 # Per bank write bursts 75system.physmem.perBankWrBursts::3 0 # Per bank write bursts 76system.physmem.perBankWrBursts::4 1 # Per bank write bursts 77system.physmem.perBankWrBursts::5 14 # Per bank write bursts 78system.physmem.perBankWrBursts::6 9 # Per bank write bursts 79system.physmem.perBankWrBursts::7 3 # Per bank write bursts 80system.physmem.perBankWrBursts::8 1 # Per bank write bursts 81system.physmem.perBankWrBursts::9 0 # Per bank write bursts 82system.physmem.perBankWrBursts::10 2 # Per bank write bursts 83system.physmem.perBankWrBursts::11 0 # Per bank write bursts 84system.physmem.perBankWrBursts::12 1 # Per bank write bursts 85system.physmem.perBankWrBursts::13 12 # Per bank write bursts 86system.physmem.perBankWrBursts::14 5 # Per bank write bursts 87system.physmem.perBankWrBursts::15 1 # Per bank write bursts 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 90system.physmem.totGap 58521077500 # Total gap between requests 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) 97system.physmem.readPktSize::6 18546 # Read request sizes (log2) 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) 104system.physmem.writePktSize::6 74 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 12593 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 3390 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 500 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 319 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 299 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 279 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 103 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 137system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::15 3 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 3 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 3 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 3 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 3 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 3 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 3 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 3004 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 394.652463 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 214.589229 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 405.543781 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 3004 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 6161.333333 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::gmean 2123.401593 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::stdev 8586.829993 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 3 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 17.333333 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 17.306995 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 1.154701 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16 1 33.33% 33.33% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::18 2 66.67% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 3 # Writes before turning the bus around for reads 230system.physmem.totQLat 837911216 # Total ticks spent queuing 231system.physmem.totMemAccLat 1184598716 # Total ticks spent from burst creation until serviced by the DRAM 232system.physmem.totBusLat 92450000 # Total ticks spent in databus transfers 233system.physmem.avgQLat 45316.99 # Average queueing delay per DRAM burst 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 235system.physmem.avgMemAccLat 64066.99 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 20.22 # Average DRAM read bandwidth in MiByte/s 237system.physmem.avgWrBW 0.06 # Average achieved write bandwidth in MiByte/s 238system.physmem.avgRdBWSys 20.28 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 0.08 # Average system write bandwidth in MiByte/s 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 241system.physmem.busUtil 0.16 # Data bus utilization in percentage 242system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 244system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 245system.physmem.avgWrQLen 13.38 # Average write queue length when enqueuing 246system.physmem.readRowHits 15512 # Number of row buffer hits during reads 247system.physmem.writeRowHits 18 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 25.71 # Row buffer hit rate for writes 250system.physmem.avgGap 3142915.01 # Average gap between requests 251system.physmem.pageHitRate 83.67 # Row buffer hit rate, read and write combined 252system.physmem_0.actEnergy 16243500 # Energy for activate commands per rank (pJ) 253system.physmem_0.preEnergy 8614650 # Energy for precharge commands per rank (pJ) 254system.physmem_0.readEnergy 75484080 # Energy for read commands per rank (pJ) 255system.physmem_0.writeEnergy 156600 # Energy for write commands per rank (pJ) 256system.physmem_0.refreshEnergy 1895549760.000000 # Energy for refresh commands per rank (pJ) 257system.physmem_0.actBackEnergy 464945010 # Energy for active background per rank (pJ) 258system.physmem_0.preBackEnergy 99199680 # Energy for precharge background per rank (pJ) 259system.physmem_0.actPowerDownEnergy 4173482430 # Energy for active power-down per rank (pJ) 260system.physmem_0.prePowerDownEnergy 3272736480 # Energy for precharge power-down per rank (pJ) 261system.physmem_0.selfRefreshEnergy 9883191315 # Energy for self refresh per rank (pJ) 262system.physmem_0.totalEnergy 19894073865 # Total energy per rank (pJ) 263system.physmem_0.averagePower 339.947098 # Core power per rank (mW) 264system.physmem_0.totalIdleTime 57233116090 # Total Idle time Per DRAM Rank 265system.physmem_0.memoryStateTime::IDLE 194944250 # Time in different power states 266system.physmem_0.memoryStateTime::REF 806364000 # Time in different power states 267system.physmem_0.memoryStateTime::SREF 39558059500 # Time in different power states 268system.physmem_0.memoryStateTime::PRE_PDN 8522710566 # Time in different power states 269system.physmem_0.memoryStateTime::ACT 286661660 # Time in different power states 270system.physmem_0.memoryStateTime::ACT_PDN 9152346024 # Time in different power states 271system.physmem_1.actEnergy 5255040 # Energy for activate commands per rank (pJ) 272system.physmem_1.preEnergy 2785530 # Energy for precharge commands per rank (pJ) 273system.physmem_1.readEnergy 56527380 # Energy for read commands per rank (pJ) 274system.physmem_1.writeEnergy 114840 # Energy for write commands per rank (pJ) 275system.physmem_1.refreshEnergy 247699920.000000 # Energy for refresh commands per rank (pJ) 276system.physmem_1.actBackEnergy 125328180 # Energy for active background per rank (pJ) 277system.physmem_1.preBackEnergy 13397280 # Energy for precharge background per rank (pJ) 278system.physmem_1.actPowerDownEnergy 772336890 # Energy for active power-down per rank (pJ) 279system.physmem_1.prePowerDownEnergy 242624160 # Energy for precharge power-down per rank (pJ) 280system.physmem_1.selfRefreshEnergy 13451278005 # Energy for self refresh per rank (pJ) 281system.physmem_1.totalEnergy 14917407225 # Total energy per rank (pJ) 282system.physmem_1.averagePower 254.906533 # Core power per rank (mW) 283system.physmem_1.totalIdleTime 58211272096 # Total Idle time Per DRAM Rank 284system.physmem_1.memoryStateTime::IDLE 21634250 # Time in different power states 285system.physmem_1.memoryStateTime::REF 105218000 # Time in different power states 286system.physmem_1.memoryStateTime::SREF 55885668250 # Time in different power states 287system.physmem_1.memoryStateTime::PRE_PDN 631842954 # Time in different power states 288system.physmem_1.memoryStateTime::ACT 182961654 # Time in different power states 289system.physmem_1.memoryStateTime::ACT_PDN 1693760892 # Time in different power states 290system.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 291system.cpu.branchPred.lookups 28121660 # Number of BP lookups 292system.cpu.branchPred.condPredicted 23134709 # Number of conditional branches predicted 293system.cpu.branchPred.condIncorrect 844714 # Number of conditional branches incorrect 294system.cpu.branchPred.BTBLookups 11731332 # Number of BTB lookups 295system.cpu.branchPred.BTBHits 11630363 # Number of BTB hits 296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 297system.cpu.branchPred.BTBHitPct 99.139322 # BTB Hit Percentage 298system.cpu.branchPred.usedRAS 80725 # Number of times the RAS was used to get a target. 299system.cpu.branchPred.RASInCorrect 95 # Number of incorrect RAS predictions. 300system.cpu.branchPred.indirectLookups 28301 # Number of indirect predictor lookups. 301system.cpu.branchPred.indirectHits 25845 # Number of indirect target hits. 302system.cpu.branchPred.indirectMisses 2456 # Number of indirect misses. 303system.cpu.branchPredindirectMispredicted 243 # Number of mispredicted indirect branches. 304system.cpu_clk_domain.clock 500 # Clock period in ticks 305system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 306system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 315system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 316system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 317system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 318system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 319system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 322system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 323system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 324system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 325system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 326system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 327system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 328system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 329system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 330system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 331system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 332system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 333system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 334system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 335system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 336system.cpu.dtb.walker.walks 0 # Table walker walks requested 337system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.inst_hits 0 # ITB inst hits 345system.cpu.dtb.inst_misses 0 # ITB inst misses 346system.cpu.dtb.read_hits 0 # DTB read hits 347system.cpu.dtb.read_misses 0 # DTB read misses 348system.cpu.dtb.write_hits 0 # DTB write hits 349system.cpu.dtb.write_misses 0 # DTB write misses 350system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 351system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 352system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 353system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 354system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 355system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 356system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 357system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 358system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 359system.cpu.dtb.read_accesses 0 # DTB read accesses 360system.cpu.dtb.write_accesses 0 # DTB write accesses 361system.cpu.dtb.inst_accesses 0 # ITB inst accesses 362system.cpu.dtb.hits 0 # DTB hits 363system.cpu.dtb.misses 0 # DTB misses 364system.cpu.dtb.accesses 0 # DTB accesses 365system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 366system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 374system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 375system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 376system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 377system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 378system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 379system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 380system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 381system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 382system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 383system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 384system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 385system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 386system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 387system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 388system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 389system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 390system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 391system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 392system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 393system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 394system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 395system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 396system.cpu.itb.walker.walks 0 # Table walker walks requested 397system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.inst_hits 0 # ITB inst hits 405system.cpu.itb.inst_misses 0 # ITB inst misses 406system.cpu.itb.read_hits 0 # DTB read hits 407system.cpu.itb.read_misses 0 # DTB read misses 408system.cpu.itb.write_hits 0 # DTB write hits 409system.cpu.itb.write_misses 0 # DTB write misses 410system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 411system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 412system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 413system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 414system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 415system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 416system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 417system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 418system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 419system.cpu.itb.read_accesses 0 # DTB read accesses 420system.cpu.itb.write_accesses 0 # DTB write accesses 421system.cpu.itb.inst_accesses 0 # ITB inst accesses 422system.cpu.itb.hits 0 # DTB hits 423system.cpu.itb.misses 0 # DTB misses 424system.cpu.itb.accesses 0 # DTB accesses
425system.cpu.workload.num_syscalls 442 # Number of system calls	425system.cpu.workload.numSyscalls 442 # Number of system calls
426system.cpu.pwrStateResidencyTicks::ON 58521086000 # Cumulative time (in ticks) in various power states 427system.cpu.numCycles 117042173 # number of cpu cycles simulated 428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 430system.cpu.fetch.icacheStallCycles 755365 # Number of cycles fetch is stalled on an Icache miss 431system.cpu.fetch.Insts 134380549 # Number of instructions fetch has processed 432system.cpu.fetch.Branches 28121660 # Number of branches that fetch encountered 433system.cpu.fetch.predictedBranches 11736933 # Number of branches that fetch has predicted taken 434system.cpu.fetch.Cycles 115370240 # Number of cycles fetch has run and was not squashing or blocked 435system.cpu.fetch.SquashCycles 1692793 # Number of cycles fetch has spent squashing 436system.cpu.fetch.MiscStallCycles 848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 437system.cpu.fetch.IcacheWaitRetryStallCycles 1033 # Number of stall cycles due to full MSHR 438system.cpu.fetch.CacheLines 32086744 # Number of cache lines fetched 439system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed 440system.cpu.fetch.rateDist::samples 116973882 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::mean 1.154260 # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::stdev 1.318237 # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::0 59688776 51.03% 51.03% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::1 13868271 11.86% 62.88% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::2 9100495 7.78% 70.66% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::3 34316340 29.34% 100.00% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::total 116973882 # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.branchRate 0.240269 # Number of branch fetches per cycle 453system.cpu.fetch.rate 1.148138 # Number of inst fetches per cycle 454system.cpu.decode.IdleCycles 8865418 # Number of cycles decode is idle 455system.cpu.decode.BlockedCycles 65026599 # Number of cycles decode is blocked 456system.cpu.decode.RunCycles 32710680 # Number of cycles decode is running 457system.cpu.decode.UnblockCycles 9589004 # Number of cycles decode is unblocking 458system.cpu.decode.SquashCycles 782181 # Number of cycles decode is squashing 459system.cpu.decode.BranchResolved 9831266 # Number of times decode resolved a branch 460system.cpu.decode.BranchMispred 64876 # Number of times decode detected a branch misprediction 461system.cpu.decode.DecodedInsts 113761457 # Number of instructions handled by decode 462system.cpu.decode.SquashedInsts 2108425 # Number of squashed instructions handled by decode 463system.cpu.rename.SquashCycles 782181 # Number of cycles rename is squashing 464system.cpu.rename.IdleCycles 15316274 # Number of cycles rename is idle 465system.cpu.rename.BlockCycles 50229704 # Number of cycles rename is blocking 466system.cpu.rename.serializeStallCycles 114341 # count of cycles rename stalled for serializing inst 467system.cpu.rename.RunCycles 35119945 # Number of cycles rename is running 468system.cpu.rename.UnblockCycles 15411437 # Number of cycles rename is unblocking 469system.cpu.rename.RenamedInsts 110456918 # Number of instructions processed by rename 470system.cpu.rename.SquashedInsts 1289549 # Number of squashed instructions processed by rename 471system.cpu.rename.ROBFullEvents 11149602 # Number of times rename has blocked due to ROB full 472system.cpu.rename.IQFullEvents 1576334 # Number of times rename has blocked due to IQ full 473system.cpu.rename.LQFullEvents 2138216 # Number of times rename has blocked due to LQ full 474system.cpu.rename.SQFullEvents 510190 # Number of times rename has blocked due to SQ full 475system.cpu.rename.RenamedOperands 129202611 # Number of destination operands rename has renamed 476system.cpu.rename.RenameLookups 481340709 # Number of register rename lookups that rename has made 477system.cpu.rename.int_rename_lookups 118978784 # Number of integer rename lookups 478system.cpu.rename.fp_rename_lookups 633 # Number of floating rename lookups 479system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed 480system.cpu.rename.UndoneMaps 21889692 # Number of HB maps that are undone due to squashing 481system.cpu.rename.serializingInsts 4408 # count of serializing insts renamed 482system.cpu.rename.tempSerializingInsts 4400 # count of temporary serializing insts renamed 483system.cpu.rename.skidInsts 21529051 # count of insts added to the skid buffer 484system.cpu.memDep0.insertedLoads 26813393 # Number of loads inserted to the mem dependence unit. 485system.cpu.memDep0.insertedStores 5308956 # Number of stores inserted to the mem dependence unit. 486system.cpu.memDep0.conflictingLoads 540635 # Number of conflicting loads. 487system.cpu.memDep0.conflictingStores 272789 # Number of conflicting stores. 488system.cpu.iq.iqInstsAdded 109383305 # Number of instructions added to the IQ (excludes non-spec) 489system.cpu.iq.iqNonSpecInstsAdded 8282 # Number of non-speculative instructions added to the IQ 490system.cpu.iq.iqInstsIssued 101253910 # Number of instructions issued 491system.cpu.iq.iqSquashedInstsIssued 993650 # Number of squashed instructions issued 492system.cpu.iq.iqSquashedInstsExamined 18350557 # Number of squashed instructions iterated over during squash; mainly for profiling 493system.cpu.iq.iqSquashedOperandsExamined 40868291 # Number of squashed operands that are examined and possibly removed from graph 494system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed 495system.cpu.iq.issued_per_cycle::samples 116973882 # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::mean 0.865611 # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::stdev 0.989909 # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::total 116973882 # Number of insts issued each cycle 512system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 513system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84% # attempts to use FU when none available 514system.cpu.iq.fu_full::IntMult 51 0.00% 48.84% # attempts to use FU when none available 515system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84% # attempts to use FU when none available 516system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84% # attempts to use FU when none available 517system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84% # attempts to use FU when none available 544system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54% # attempts to use FU when none available 545system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00% # attempts to use FU when none available 546system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available 547system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available 548system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 549system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 550system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 551system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93% # Type of FU issued 552system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94% # Type of FU issued 553system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94% # Type of FU issued 560system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94% # Type of FU issued 561system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94% # Type of FU issued 582system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99% # Type of FU issued 583system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00% # Type of FU issued 584system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued 585system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued 586system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 587system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 588system.cpu.iq.FU_type_0::total 101253910 # Type of FU issued 589system.cpu.iq.rate 0.865106 # Inst issue rate 590system.cpu.iq.fu_busy_cnt 20139291 # FU busy when requested 591system.cpu.iq.fu_busy_rate 0.198899 # FU busy rate (busy events/executed inst) 592system.cpu.iq.int_inst_queue_reads 340613998 # Number of integer instruction queue reads 593system.cpu.iq.int_inst_queue_writes 127742533 # Number of integer instruction queue writes 594system.cpu.iq.int_inst_queue_wakeup_accesses 99568159 # Number of integer instruction queue wakeup accesses 595system.cpu.iq.fp_inst_queue_reads 645 # Number of floating instruction queue reads 596system.cpu.iq.fp_inst_queue_writes 896 # Number of floating instruction queue writes 597system.cpu.iq.fp_inst_queue_wakeup_accesses 147 # Number of floating instruction queue wakeup accesses 598system.cpu.iq.int_alu_accesses 121392865 # Number of integer alu accesses 599system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses 600system.cpu.iew.lsq.thread0.forwLoads 289487 # Number of loads that had data forwarded from stores 601system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 602system.cpu.iew.lsq.thread0.squashedLoads 4337482 # Number of loads squashed 603system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed 604system.cpu.iew.lsq.thread0.memOrderViolation 1323 # Number of memory ordering violations 605system.cpu.iew.lsq.thread0.squashedStores 564112 # Number of stores squashed 606system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 607system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 608system.cpu.iew.lsq.thread0.rescheduledLoads 7586 # Number of loads that were rescheduled 609system.cpu.iew.lsq.thread0.cacheBlocked 131115 # Number of times an access to memory failed due to the cache being blocked 610system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 611system.cpu.iew.iewSquashCycles 782181 # Number of cycles IEW is squashing 612system.cpu.iew.iewBlockCycles 8303656 # Number of cycles IEW is blocking 613system.cpu.iew.iewUnblockCycles 706645 # Number of cycles IEW is unblocking 614system.cpu.iew.iewDispatchedInsts 109404410 # Number of instructions dispatched to IQ 615system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 616system.cpu.iew.iewDispLoadInsts 26813393 # Number of dispatched load instructions 617system.cpu.iew.iewDispStoreInsts 5308956 # Number of dispatched store instructions 618system.cpu.iew.iewDispNonSpecInsts 4394 # Number of dispatched non-speculative instructions 619system.cpu.iew.iewIQFullEvents 183005 # Number of times the IQ has become full, causing a stall 620system.cpu.iew.iewLSQFullEvents 362995 # Number of times the LSQ has become full, causing a stall 621system.cpu.iew.memOrderViolationEvents 1323 # Number of memory order violations 622system.cpu.iew.predictedTakenIncorrect 354101 # Number of branches that were predicted taken incorrectly 623system.cpu.iew.predictedNotTakenIncorrect 451870 # Number of branches that were predicted not taken incorrectly 624system.cpu.iew.branchMispredicts 805971 # Number of branch mispredicts detected at execute 625system.cpu.iew.iewExecutedInsts 100068536 # Number of executed instructions 626system.cpu.iew.iewExecLoadInsts 23799476 # Number of load instructions executed 627system.cpu.iew.iewExecSquashedInsts 1185374 # Number of squashed instructions skipped in execute 628system.cpu.iew.exec_swp 0 # number of swp insts executed 629system.cpu.iew.exec_nop 12823 # number of nop insts executed 630system.cpu.iew.exec_refs 28747002 # number of memory reference insts executed 631system.cpu.iew.exec_branches 20644390 # Number of branches executed 632system.cpu.iew.exec_stores 4947526 # Number of stores executed 633system.cpu.iew.exec_rate 0.854978 # Inst execution rate 634system.cpu.iew.wb_sent 99653444 # cumulative count of insts sent to commit 635system.cpu.iew.wb_count 99568306 # cumulative count of insts written-back 636system.cpu.iew.wb_producers 59603520 # num instructions producing a value 637system.cpu.iew.wb_consumers 95472454 # num instructions consuming a value 638system.cpu.iew.wb_rate 0.850705 # insts written-back per cycle 639system.cpu.iew.wb_fanout 0.624301 # average fanout of values written-back 640system.cpu.commit.commitSquashedInsts 17204380 # The number of squashed insts skipped by commit 641system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 642system.cpu.commit.branchMispredicts 780499 # The number of times a branch was mispredicted 643system.cpu.commit.committed_per_cycle::samples 114317449 # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::mean 0.796498 # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::stdev 1.736161 # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00% # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 658system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 659system.cpu.commit.committed_per_cycle::total 114317449 # Number of insts commited each cycle 660system.cpu.commit.committedInsts 90602408 # Number of instructions committed 661system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed 662system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 663system.cpu.commit.refs 27220755 # Number of memory references committed 664system.cpu.commit.loads 22475911 # Number of loads committed 665system.cpu.commit.membars 3888 # Number of memory barriers committed 666system.cpu.commit.branches 18732305 # Number of branches committed 667system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 668system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. 669system.cpu.commit.function_calls 56148 # Number of function calls committed. 670system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 671system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction 672system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 673system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 676system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 677system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 678system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction 679system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 680system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction 681system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 696system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 697system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 698system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 699system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 700system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 701system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 702system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction 703system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction 704system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction 705system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction 706system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 707system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 708system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction 709system.cpu.commit.bw_lim_events 4142947 # number cycles where commit BW limit reached 710system.cpu.rob.rob_reads 218426787 # The number of ROB reads 711system.cpu.rob.rob_writes 219173124 # The number of ROB writes 712system.cpu.timesIdled 593 # Number of times that the entire CPU went into an idle state and unscheduled itself 713system.cpu.idleCycles 68291 # Total number of cycles that the CPU has spent unscheduled due to idling 714system.cpu.committedInsts 90589799 # Number of Instructions Simulated 715system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated 716system.cpu.cpi 1.292002 # CPI: Cycles Per Instruction 717system.cpu.cpi_total 1.292002 # CPI: Total CPI of All Threads 718system.cpu.ipc 0.773993 # IPC: Instructions Per Cycle 719system.cpu.ipc_total 0.773993 # IPC: Total IPC of All Threads 720system.cpu.int_regfile_reads 108095256 # number of integer regfile reads 721system.cpu.int_regfile_writes 58597145 # number of integer regfile writes 722system.cpu.fp_regfile_reads 58 # number of floating regfile reads 723system.cpu.fp_regfile_writes 127 # number of floating regfile writes 724system.cpu.cc_regfile_reads 368871207 # number of cc regfile reads 725system.cpu.cc_regfile_writes 58517884 # number of cc regfile writes 726system.cpu.misc_regfile_reads 28439348 # number of misc regfile reads 727system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 728system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 729system.cpu.dcache.tags.replacements 5470632 # number of replacements 730system.cpu.dcache.tags.tagsinuse 511.768178 # Cycle average of tags in use 731system.cpu.dcache.tags.total_refs 18243100 # Total number of references to valid blocks. 732system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks. 733system.cpu.dcache.tags.avg_refs 3.334421 # Average number of references to valid blocks. 734system.cpu.dcache.tags.warmup_cycle 38187500 # Cycle when the warmup percentage was hit. 735system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178 # Average occupied blocks per requestor 736system.cpu.dcache.tags.occ_percent::cpu.data 0.999547 # Average percentage of cache occupancy 737system.cpu.dcache.tags.occ_percent::total 0.999547 # Average percentage of cache occupancy 738system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 739system.cpu.dcache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id 740system.cpu.dcache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id 741system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 742system.cpu.dcache.tags.tag_accesses 61896540 # Number of tag accesses 743system.cpu.dcache.tags.data_accesses 61896540 # Number of data accesses 744system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 745system.cpu.dcache.ReadReq_hits::cpu.data 13880582 # number of ReadReq hits 746system.cpu.dcache.ReadReq_hits::total 13880582 # number of ReadReq hits 747system.cpu.dcache.WriteReq_hits::cpu.data 4354214 # number of WriteReq hits 748system.cpu.dcache.WriteReq_hits::total 4354214 # number of WriteReq hits 749system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 750system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 751system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits 752system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits 753system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 754system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 755system.cpu.dcache.demand_hits::cpu.data 18234796 # number of demand (read+write) hits 756system.cpu.dcache.demand_hits::total 18234796 # number of demand (read+write) hits 757system.cpu.dcache.overall_hits::cpu.data 18235318 # number of overall hits 758system.cpu.dcache.overall_hits::total 18235318 # number of overall hits 759system.cpu.dcache.ReadReq_misses::cpu.data 9588832 # number of ReadReq misses 760system.cpu.dcache.ReadReq_misses::total 9588832 # number of ReadReq misses 761system.cpu.dcache.WriteReq_misses::cpu.data 380767 # number of WriteReq misses 762system.cpu.dcache.WriteReq_misses::total 380767 # number of WriteReq misses 763system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses 764system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses 765system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses 766system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses 767system.cpu.dcache.demand_misses::cpu.data 9969599 # number of demand (read+write) misses 768system.cpu.dcache.demand_misses::total 9969599 # number of demand (read+write) misses 769system.cpu.dcache.overall_misses::cpu.data 9969606 # number of overall misses 770system.cpu.dcache.overall_misses::total 9969606 # number of overall misses 771system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500 # number of ReadReq miss cycles 772system.cpu.dcache.ReadReq_miss_latency::total 89393317500 # number of ReadReq miss cycles 773system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083 # number of WriteReq miss cycles 774system.cpu.dcache.WriteReq_miss_latency::total 4103772083 # number of WriteReq miss cycles 775system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles 776system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles 777system.cpu.dcache.demand_miss_latency::cpu.data 93497089583 # number of demand (read+write) miss cycles 778system.cpu.dcache.demand_miss_latency::total 93497089583 # number of demand (read+write) miss cycles 779system.cpu.dcache.overall_miss_latency::cpu.data 93497089583 # number of overall miss cycles 780system.cpu.dcache.overall_miss_latency::total 93497089583 # number of overall miss cycles 781system.cpu.dcache.ReadReq_accesses::cpu.data 23469414 # number of ReadReq accesses(hits+misses) 782system.cpu.dcache.ReadReq_accesses::total 23469414 # number of ReadReq accesses(hits+misses) 783system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 784system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 785system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) 786system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) 787system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 788system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 789system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 790system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 791system.cpu.dcache.demand_accesses::cpu.data 28204395 # number of demand (read+write) accesses 792system.cpu.dcache.demand_accesses::total 28204395 # number of demand (read+write) accesses 793system.cpu.dcache.overall_accesses::cpu.data 28204924 # number of overall (read+write) accesses 794system.cpu.dcache.overall_accesses::total 28204924 # number of overall (read+write) accesses 795system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567 # miss rate for ReadReq accesses 796system.cpu.dcache.ReadReq_miss_rate::total 0.408567 # miss rate for ReadReq accesses 797system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416 # miss rate for WriteReq accesses 798system.cpu.dcache.WriteReq_miss_rate::total 0.080416 # miss rate for WriteReq accesses 799system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses 800system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses 801system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses 802system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses 803system.cpu.dcache.demand_miss_rate::cpu.data 0.353477 # miss rate for demand accesses 804system.cpu.dcache.demand_miss_rate::total 0.353477 # miss rate for demand accesses 805system.cpu.dcache.overall_miss_rate::cpu.data 0.353470 # miss rate for overall accesses 806system.cpu.dcache.overall_miss_rate::total 0.353470 # miss rate for overall accesses 807system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255 # average ReadReq miss latency 808system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255 # average ReadReq miss latency 809system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390 # average WriteReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390 # average WriteReq miss latency 811system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency 812system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency 813system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684 # average overall miss latency 814system.cpu.dcache.demand_avg_miss_latency::total 9378.219684 # average overall miss latency 815system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099 # average overall miss latency 816system.cpu.dcache.overall_avg_miss_latency::total 9378.213099 # average overall miss latency 817system.cpu.dcache.blocked_cycles::no_mshrs 331670 # number of cycles access was blocked 818system.cpu.dcache.blocked_cycles::no_targets 131340 # number of cycles access was blocked 819system.cpu.dcache.blocked::no_mshrs 121646 # number of cycles access was blocked 820system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked 821system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518 # average number of cycles each access was blocked 822system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566 # average number of cycles each access was blocked 823system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks 824system.cpu.dcache.writebacks::total 5470632 # number of writebacks 825system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269 # number of ReadReq MSHR hits 826system.cpu.dcache.ReadReq_mshr_hits::total 4340269 # number of ReadReq MSHR hits 827system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185 # number of WriteReq MSHR hits 828system.cpu.dcache.WriteReq_mshr_hits::total 158185 # number of WriteReq MSHR hits 829system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits 830system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits 831system.cpu.dcache.demand_mshr_hits::cpu.data 4498454 # number of demand (read+write) MSHR hits 832system.cpu.dcache.demand_mshr_hits::total 4498454 # number of demand (read+write) MSHR hits 833system.cpu.dcache.overall_mshr_hits::cpu.data 4498454 # number of overall MSHR hits 834system.cpu.dcache.overall_mshr_hits::total 4498454 # number of overall MSHR hits 835system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563 # number of ReadReq MSHR misses 836system.cpu.dcache.ReadReq_mshr_misses::total 5248563 # number of ReadReq MSHR misses 837system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582 # number of WriteReq MSHR misses 838system.cpu.dcache.WriteReq_mshr_misses::total 222582 # number of WriteReq MSHR misses 839system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses 840system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses 841system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses 842system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses 843system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses 844system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses 845system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500 # number of ReadReq MSHR miss cycles 846system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500 # number of ReadReq MSHR miss cycles 847system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483 # number of WriteReq MSHR miss cycles 848system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483 # number of WriteReq MSHR miss cycles 849system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles 850system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles 851system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983 # number of demand (read+write) MSHR miss cycles 852system.cpu.dcache.demand_mshr_miss_latency::total 46120568983 # number of demand (read+write) MSHR miss cycles 853system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483 # number of overall MSHR miss cycles 854system.cpu.dcache.overall_mshr_miss_latency::total 46120804483 # number of overall MSHR miss cycles 855system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634 # mshr miss rate for ReadReq accesses 856system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634 # mshr miss rate for ReadReq accesses 857system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008 # mshr miss rate for WriteReq accesses 858system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008 # mshr miss rate for WriteReq accesses 859system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses 860system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses 861system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982 # mshr miss rate for demand accesses 862system.cpu.dcache.demand_mshr_miss_rate::total 0.193982 # mshr miss rate for demand accesses 863system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979 # mshr miss rate for overall accesses 864system.cpu.dcache.overall_mshr_miss_rate::total 0.193979 # mshr miss rate for overall accesses 865system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446 # average ReadReq mshr miss latency 866system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446 # average ReadReq mshr miss latency 867system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061 # average WriteReq mshr miss latency 868system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061 # average WriteReq mshr miss latency 869system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency 870system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency 871system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708 # average overall mshr miss latency 872system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708 # average overall mshr miss latency 873system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589 # average overall mshr miss latency 874system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589 # average overall mshr miss latency 875system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 876system.cpu.icache.tags.replacements 449 # number of replacements 877system.cpu.icache.tags.tagsinuse 426.857560 # Cycle average of tags in use 878system.cpu.icache.tags.total_refs 32085580 # Total number of references to valid blocks. 879system.cpu.icache.tags.sampled_refs 907 # Sample count of references to valid blocks. 880system.cpu.icache.tags.avg_refs 35375.501654 # Average number of references to valid blocks. 881system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 882system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560 # Average occupied blocks per requestor 883system.cpu.icache.tags.occ_percent::cpu.inst 0.833706 # Average percentage of cache occupancy 884system.cpu.icache.tags.occ_percent::total 0.833706 # Average percentage of cache occupancy 885system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id 886system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 887system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id 888system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id 889system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id 890system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id 891system.cpu.icache.tags.tag_accesses 64174375 # Number of tag accesses 892system.cpu.icache.tags.data_accesses 64174375 # Number of data accesses 893system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 894system.cpu.icache.ReadReq_hits::cpu.inst 32085580 # number of ReadReq hits 895system.cpu.icache.ReadReq_hits::total 32085580 # number of ReadReq hits 896system.cpu.icache.demand_hits::cpu.inst 32085580 # number of demand (read+write) hits 897system.cpu.icache.demand_hits::total 32085580 # number of demand (read+write) hits 898system.cpu.icache.overall_hits::cpu.inst 32085580 # number of overall hits 899system.cpu.icache.overall_hits::total 32085580 # number of overall hits 900system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses 901system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses 902system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses 903system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses 904system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses 905system.cpu.icache.overall_misses::total 1154 # number of overall misses 906system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480 # number of ReadReq miss cycles 907system.cpu.icache.ReadReq_miss_latency::total 81624480 # number of ReadReq miss cycles 908system.cpu.icache.demand_miss_latency::cpu.inst 81624480 # number of demand (read+write) miss cycles 909system.cpu.icache.demand_miss_latency::total 81624480 # number of demand (read+write) miss cycles 910system.cpu.icache.overall_miss_latency::cpu.inst 81624480 # number of overall miss cycles 911system.cpu.icache.overall_miss_latency::total 81624480 # number of overall miss cycles 912system.cpu.icache.ReadReq_accesses::cpu.inst 32086734 # number of ReadReq accesses(hits+misses) 913system.cpu.icache.ReadReq_accesses::total 32086734 # number of ReadReq accesses(hits+misses) 914system.cpu.icache.demand_accesses::cpu.inst 32086734 # number of demand (read+write) accesses 915system.cpu.icache.demand_accesses::total 32086734 # number of demand (read+write) accesses 916system.cpu.icache.overall_accesses::cpu.inst 32086734 # number of overall (read+write) accesses 917system.cpu.icache.overall_accesses::total 32086734 # number of overall (read+write) accesses 918system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses 919system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses 920system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses 921system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses 922system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses 923system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses 924system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095 # average ReadReq miss latency 925system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095 # average ReadReq miss latency 926system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency 927system.cpu.icache.demand_avg_miss_latency::total 70731.785095 # average overall miss latency 928system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency 929system.cpu.icache.overall_avg_miss_latency::total 70731.785095 # average overall miss latency 930system.cpu.icache.blocked_cycles::no_mshrs 21770 # number of cycles access was blocked 931system.cpu.icache.blocked_cycles::no_targets 1853 # number of cycles access was blocked 932system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked 933system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked 934system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502 # average number of cycles each access was blocked 935system.cpu.icache.avg_blocked_cycles::no_targets 264.714286 # average number of cycles each access was blocked 936system.cpu.icache.writebacks::writebacks 449 # number of writebacks 937system.cpu.icache.writebacks::total 449 # number of writebacks 938system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits 939system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits 940system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits 941system.cpu.icache.demand_mshr_hits::total 246 # number of demand (read+write) MSHR hits 942system.cpu.icache.overall_mshr_hits::cpu.inst 246 # number of overall MSHR hits 943system.cpu.icache.overall_mshr_hits::total 246 # number of overall MSHR hits 944system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses 945system.cpu.icache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses 946system.cpu.icache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses 947system.cpu.icache.demand_mshr_misses::total 908 # number of demand (read+write) MSHR misses 948system.cpu.icache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses 949system.cpu.icache.overall_mshr_misses::total 908 # number of overall MSHR misses 950system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61609984 # number of ReadReq MSHR miss cycles 951system.cpu.icache.ReadReq_mshr_miss_latency::total 61609984 # number of ReadReq MSHR miss cycles 952system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61609984 # number of demand (read+write) MSHR miss cycles 953system.cpu.icache.demand_mshr_miss_latency::total 61609984 # number of demand (read+write) MSHR miss cycles 954system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984 # number of overall MSHR miss cycles 955system.cpu.icache.overall_mshr_miss_latency::total 61609984 # number of overall MSHR miss cycles 956system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 957system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 958system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 959system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 960system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 961system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 962system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67852.405286 # average ReadReq mshr miss latency 963system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286 # average ReadReq mshr miss latency 964system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency 965system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency 966system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency 967system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency 968system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 969system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667 # number of hwpf issued 970system.cpu.l2cache.prefetcher.pfIdentified 5295978 # number of prefetch candidates identified 971system.cpu.l2cache.prefetcher.pfBufferHit 268023 # number of redundant prefetches already in prefetch queue 972system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 973system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 974system.cpu.l2cache.prefetcher.pfSpanPage 14076270 # number of prefetches not generated due to page crossing 975system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 976system.cpu.l2cache.tags.replacements 99 # number of replacements 977system.cpu.l2cache.tags.tagsinuse 11218.637670 # Cycle average of tags in use 978system.cpu.l2cache.tags.total_refs 5292117 # Total number of references to valid blocks. 979system.cpu.l2cache.tags.sampled_refs 14656 # Sample count of references to valid blocks. 980system.cpu.l2cache.tags.avg_refs 361.088769 # Average number of references to valid blocks. 981system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 982system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658 # Average occupied blocks per requestor 983system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012 # Average occupied blocks per requestor 984system.cpu.l2cache.tags.occ_percent::writebacks 0.680659 # Average percentage of cache occupancy 985system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004072 # Average percentage of cache occupancy 986system.cpu.l2cache.tags.occ_percent::total 0.684731 # Average percentage of cache occupancy 987system.cpu.l2cache.tags.occ_task_id_blocks::1022 67 # Occupied blocks per task id 988system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642 # Occupied blocks per task id 995system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120 # Occupied blocks per task id 996system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834 # Occupied blocks per task id 997system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089 # Percentage of cache occupancy per task id 998system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399 # Percentage of cache occupancy per task id 999system.cpu.l2cache.tags.tag_accesses 180525307 # Number of tag accesses 1000system.cpu.l2cache.tags.data_accesses 180525307 # Number of data accesses 1001system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 1002system.cpu.l2cache.WritebackDirty_hits::writebacks 5460197 # number of WritebackDirty hits 1003system.cpu.l2cache.WritebackDirty_hits::total 5460197 # number of WritebackDirty hits 1004system.cpu.l2cache.WritebackClean_hits::writebacks 7956 # number of WritebackClean hits 1005system.cpu.l2cache.WritebackClean_hits::total 7956 # number of WritebackClean hits 1006system.cpu.l2cache.ReadExReq_hits::cpu.data 225753 # number of ReadExReq hits 1007system.cpu.l2cache.ReadExReq_hits::total 225753 # number of ReadExReq hits 1008system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 207 # number of ReadCleanReq hits 1009system.cpu.l2cache.ReadCleanReq_hits::total 207 # number of ReadCleanReq hits 1010system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241769 # number of ReadSharedReq hits 1011system.cpu.l2cache.ReadSharedReq_hits::total 5241769 # number of ReadSharedReq hits 1012system.cpu.l2cache.demand_hits::cpu.inst 207 # number of demand (read+write) hits 1013system.cpu.l2cache.demand_hits::cpu.data 5467522 # number of demand (read+write) hits 1014system.cpu.l2cache.demand_hits::total 5467729 # number of demand (read+write) hits 1015system.cpu.l2cache.overall_hits::cpu.inst 207 # number of overall hits 1016system.cpu.l2cache.overall_hits::cpu.data 5467522 # number of overall hits 1017system.cpu.l2cache.overall_hits::total 5467729 # number of overall hits 1018system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 1019system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses 1020system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses 1021system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses 1022system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses 1023system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses 1024system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123 # number of ReadSharedReq misses 1025system.cpu.l2cache.ReadSharedReq_misses::total 3123 # number of ReadSharedReq misses 1026system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses 1027system.cpu.l2cache.demand_misses::cpu.data 3622 # number of demand (read+write) misses 1028system.cpu.l2cache.demand_misses::total 4323 # number of demand (read+write) misses 1029system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses 1030system.cpu.l2cache.overall_misses::cpu.data 3622 # number of overall misses 1031system.cpu.l2cache.overall_misses::total 4323 # number of overall misses 1032system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 105500 # number of UpgradeReq miss cycles 1033system.cpu.l2cache.UpgradeReq_miss_latency::total 105500 # number of UpgradeReq miss cycles 1034system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66196000 # number of ReadExReq miss cycles 1035system.cpu.l2cache.ReadExReq_miss_latency::total 66196000 # number of ReadExReq miss cycles 1036system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59307500 # number of ReadCleanReq miss cycles 1037system.cpu.l2cache.ReadCleanReq_miss_latency::total 59307500 # number of ReadCleanReq miss cycles 1038system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 617300000 # number of ReadSharedReq miss cycles 1039system.cpu.l2cache.ReadSharedReq_miss_latency::total 617300000 # number of ReadSharedReq miss cycles 1040system.cpu.l2cache.demand_miss_latency::cpu.inst 59307500 # number of demand (read+write) miss cycles 1041system.cpu.l2cache.demand_miss_latency::cpu.data 683496000 # number of demand (read+write) miss cycles 1042system.cpu.l2cache.demand_miss_latency::total 742803500 # number of demand (read+write) miss cycles 1043system.cpu.l2cache.overall_miss_latency::cpu.inst 59307500 # number of overall miss cycles 1044system.cpu.l2cache.overall_miss_latency::cpu.data 683496000 # number of overall miss cycles 1045system.cpu.l2cache.overall_miss_latency::total 742803500 # number of overall miss cycles 1046system.cpu.l2cache.WritebackDirty_accesses::writebacks 5460197 # number of WritebackDirty accesses(hits+misses) 1047system.cpu.l2cache.WritebackDirty_accesses::total 5460197 # number of WritebackDirty accesses(hits+misses) 1048system.cpu.l2cache.WritebackClean_accesses::writebacks 7956 # number of WritebackClean accesses(hits+misses) 1049system.cpu.l2cache.WritebackClean_accesses::total 7956 # number of WritebackClean accesses(hits+misses) 1050system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) 1051system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) 1052system.cpu.l2cache.ReadExReq_accesses::cpu.data 226252 # number of ReadExReq accesses(hits+misses) 1053system.cpu.l2cache.ReadExReq_accesses::total 226252 # number of ReadExReq accesses(hits+misses) 1054system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 908 # number of ReadCleanReq accesses(hits+misses) 1055system.cpu.l2cache.ReadCleanReq_accesses::total 908 # number of ReadCleanReq accesses(hits+misses) 1056system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244892 # number of ReadSharedReq accesses(hits+misses) 1057system.cpu.l2cache.ReadSharedReq_accesses::total 5244892 # number of ReadSharedReq accesses(hits+misses) 1058system.cpu.l2cache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses 1059system.cpu.l2cache.demand_accesses::cpu.data 5471144 # number of demand (read+write) accesses 1060system.cpu.l2cache.demand_accesses::total 5472052 # number of demand (read+write) accesses 1061system.cpu.l2cache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses 1062system.cpu.l2cache.overall_accesses::cpu.data 5471144 # number of overall (read+write) accesses 1063system.cpu.l2cache.overall_accesses::total 5472052 # number of overall (read+write) accesses 1064system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1065system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1066system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002206 # miss rate for ReadExReq accesses 1067system.cpu.l2cache.ReadExReq_miss_rate::total 0.002206 # miss rate for ReadExReq accesses 1068system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772026 # miss rate for ReadCleanReq accesses 1069system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772026 # miss rate for ReadCleanReq accesses 1070system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000595 # miss rate for ReadSharedReq accesses 1071system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000595 # miss rate for ReadSharedReq accesses 1072system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772026 # miss rate for demand accesses 1073system.cpu.l2cache.demand_miss_rate::cpu.data 0.000662 # miss rate for demand accesses 1074system.cpu.l2cache.demand_miss_rate::total 0.000790 # miss rate for demand accesses 1075system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026 # miss rate for overall accesses 1076system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662 # miss rate for overall accesses 1077system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses 1078system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21100 # average UpgradeReq miss latency 1079system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21100 # average UpgradeReq miss latency 1080system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.314629 # average ReadExReq miss latency 1081system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.314629 # average ReadExReq miss latency 1082system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947 # average ReadCleanReq miss latency 1083system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947 # average ReadCleanReq miss latency 1084system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003 # average ReadSharedReq miss latency 1085system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003 # average ReadSharedReq miss latency 1086system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency 1087system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency 1088system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066 # average overall miss latency 1089system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency 1090system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency 1091system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066 # average overall miss latency 1092system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1093system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1094system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1095system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1096system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1097system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1098system.cpu.l2cache.unused_prefetches 1 # number of HardPF blocks evicted w/o reference 1099system.cpu.l2cache.writebacks::writebacks 74 # number of writebacks 1100system.cpu.l2cache.writebacks::total 74 # number of writebacks 1101system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits 1102system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits 1103system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1104system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1105system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits 1106system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits 1107system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1108system.cpu.l2cache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits 1109system.cpu.l2cache.demand_mshr_hits::total 181 # number of demand (read+write) MSHR hits 1110system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1111system.cpu.l2cache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits 1112system.cpu.l2cache.overall_mshr_hits::total 181 # number of overall MSHR hits 1113system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332 # number of HardPFReq MSHR misses 1114system.cpu.l2cache.HardPFReq_mshr_misses::total 316332 # number of HardPFReq MSHR misses 1115system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses 1116system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses 1117system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses 1118system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses 1119system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses 1120system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses 1121system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101 # number of ReadSharedReq MSHR misses 1122system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101 # number of ReadSharedReq MSHR misses 1123system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses 1124system.cpu.l2cache.demand_mshr_misses::cpu.data 3442 # number of demand (read+write) MSHR misses 1125system.cpu.l2cache.demand_mshr_misses::total 4142 # number of demand (read+write) MSHR misses 1126system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses 1127system.cpu.l2cache.overall_mshr_misses::cpu.data 3442 # number of overall MSHR misses 1128system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332 # number of overall MSHR misses 1129system.cpu.l2cache.overall_mshr_misses::total 320474 # number of overall MSHR misses 1130system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of HardPFReq MSHR miss cycles 1131system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507 # number of HardPFReq MSHR miss cycles 1132system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500 # number of UpgradeReq MSHR miss cycles 1133system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500 # number of UpgradeReq MSHR miss cycles 1134system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500 # number of ReadExReq MSHR miss cycles 1135system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500 # number of ReadExReq MSHR miss cycles 1136system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500 # number of ReadCleanReq MSHR miss cycles 1137system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500 # number of ReadCleanReq MSHR miss cycles 1138system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000 # number of ReadSharedReq MSHR miss cycles 1139system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000 # number of ReadSharedReq MSHR miss cycles 1140system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500 # number of demand (read+write) MSHR miss cycles 1141system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500 # number of demand (read+write) MSHR miss cycles 1142system.cpu.l2cache.demand_mshr_miss_latency::total 692500000 # number of demand (read+write) MSHR miss cycles 1143system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500 # number of overall MSHR miss cycles 1144system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500 # number of overall MSHR miss cycles 1145system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of overall MSHR miss cycles 1146system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507 # number of overall MSHR miss cycles 1147system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1148system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1149system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1150system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1151system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507 # mshr miss rate for ReadExReq accesses 1152system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadExReq accesses 1153system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for ReadCleanReq accesses 1154system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925 # mshr miss rate for ReadCleanReq accesses 1155system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591 # mshr miss rate for ReadSharedReq accesses 1156system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591 # mshr miss rate for ReadSharedReq accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for demand accesses 1158system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for demand accesses 1159system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757 # mshr miss rate for demand accesses 1160system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for overall accesses 1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for overall accesses 1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1163system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566 # mshr miss rate for overall accesses 1164system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average HardPFReq mshr miss latency 1165system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372 # average HardPFReq mshr miss latency 1166system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100 # average UpgradeReq mshr miss latency 1167system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100 # average UpgradeReq mshr miss latency 1168system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534 # average ReadExReq mshr miss latency 1169system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534 # average ReadExReq mshr miss latency 1170system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143 # average ReadCleanReq mshr miss latency 1171system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143 # average ReadCleanReq mshr miss latency 1172system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884 # average ReadSharedReq mshr miss latency 1173system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884 # average ReadSharedReq mshr miss latency 1174system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441 # average overall mshr miss latency 1181system.cpu.toL2Bus.snoop_filter.tot_requests 10943138 # Total number of requests made to the snoop filter. 1182system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1183system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1184system.cpu.toL2Bus.snoop_filter.tot_snoops 301927 # Total number of snoops made to the snoop filter. 1185system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1186system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1187system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 1188system.cpu.toL2Bus.trans_dist::ReadResp 5245799 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::WritebackClean 10884 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::CleanEvict 25 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::HardPFReq 318221 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::ReadExReq 226252 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::ReadExResp 226252 # Transaction distribution 1198system.cpu.toL2Bus.trans_dist::ReadCleanReq 908 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892 # Transaction distribution 1200system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264 # Packet count per connected master and slave (bytes) 1201system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) 1202system.cpu.toL2Bus.pkt_count::total 16415200 # Packet count per connected master and slave (bytes) 1203system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784 # Cumulative packet size per connected master and slave (bytes) 1204system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes) 1205system.cpu.toL2Bus.pkt_size::total 700360832 # Cumulative packet size per connected master and slave (bytes) 1206system.cpu.toL2Bus.snoops 318326 # Total snoops (count) 1207system.cpu.toL2Bus.snoopTraffic 5120 # Total snoop traffic (bytes) 1208system.cpu.toL2Bus.snoop_fanout::samples 5790377 # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::mean 0.052651 # Request fanout histogram 1210system.cpu.toL2Bus.snoop_fanout::stdev 0.223337 # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73% # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00% # Request fanout histogram 1214system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1215system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1216system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1217system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1218system.cpu.toL2Bus.snoop_fanout::total 5790377 # Request fanout histogram 1219system.cpu.toL2Bus.reqLayer0.occupancy 10942650026 # Layer occupancy (ticks) 1220system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) 1221system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks) 1222system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1223system.cpu.toL2Bus.respLayer0.occupancy 1362995 # Layer occupancy (ticks) 1224system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1225system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks) 1226system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) 1227system.membus.snoop_filter.tot_requests 18651 # Total number of requests made to the snoop filter. 1228system.membus.snoop_filter.hit_single_requests 3037 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1229system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1230system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1231system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1232system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1233system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 1234system.membus.trans_dist::ReadResp 18205 # Transaction distribution 1235system.membus.trans_dist::WritebackDirty 74 # Transaction distribution 1236system.membus.trans_dist::CleanEvict 25 # Transaction distribution 1237system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 1238system.membus.trans_dist::ReadExReq 340 # Transaction distribution 1239system.membus.trans_dist::ReadExResp 340 # Transaction distribution 1240system.membus.trans_dist::ReadSharedReq 18206 # Transaction distribution 1241system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196 # Packet count per connected master and slave (bytes) 1242system.membus.pkt_count::total 37196 # Packet count per connected master and slave (bytes) 1243system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616 # Cumulative packet size per connected master and slave (bytes) 1244system.membus.pkt_size::total 1191616 # Cumulative packet size per connected master and slave (bytes) 1245system.membus.snoops 0 # Total snoops (count) 1246system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1247system.membus.snoop_fanout::samples 18552 # Request fanout histogram 1248system.membus.snoop_fanout::mean 0 # Request fanout histogram 1249system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1250system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1251system.membus.snoop_fanout::0 18552 100.00% 100.00% # Request fanout histogram 1252system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1253system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1254system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1255system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1256system.membus.snoop_fanout::total 18552 # Request fanout histogram 1257system.membus.reqLayer0.occupancy 29380556 # Layer occupancy (ticks) 1258system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 1259system.membus.respLayer1.occupancy 97369032 # Layer occupancy (ticks) 1260system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1261 1262---------- End Simulation Statistics ----------	426system.cpu.pwrStateResidencyTicks::ON 58521086000 # Cumulative time (in ticks) in various power states 427system.cpu.numCycles 117042173 # number of cpu cycles simulated 428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 430system.cpu.fetch.icacheStallCycles 755365 # Number of cycles fetch is stalled on an Icache miss 431system.cpu.fetch.Insts 134380549 # Number of instructions fetch has processed 432system.cpu.fetch.Branches 28121660 # Number of branches that fetch encountered 433system.cpu.fetch.predictedBranches 11736933 # Number of branches that fetch has predicted taken 434system.cpu.fetch.Cycles 115370240 # Number of cycles fetch has run and was not squashing or blocked 435system.cpu.fetch.SquashCycles 1692793 # Number of cycles fetch has spent squashing 436system.cpu.fetch.MiscStallCycles 848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 437system.cpu.fetch.IcacheWaitRetryStallCycles 1033 # Number of stall cycles due to full MSHR 438system.cpu.fetch.CacheLines 32086744 # Number of cache lines fetched 439system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed 440system.cpu.fetch.rateDist::samples 116973882 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::mean 1.154260 # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::stdev 1.318237 # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::0 59688776 51.03% 51.03% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::1 13868271 11.86% 62.88% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::2 9100495 7.78% 70.66% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::3 34316340 29.34% 100.00% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::total 116973882 # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.branchRate 0.240269 # Number of branch fetches per cycle 453system.cpu.fetch.rate 1.148138 # Number of inst fetches per cycle 454system.cpu.decode.IdleCycles 8865418 # Number of cycles decode is idle 455system.cpu.decode.BlockedCycles 65026599 # Number of cycles decode is blocked 456system.cpu.decode.RunCycles 32710680 # Number of cycles decode is running 457system.cpu.decode.UnblockCycles 9589004 # Number of cycles decode is unblocking 458system.cpu.decode.SquashCycles 782181 # Number of cycles decode is squashing 459system.cpu.decode.BranchResolved 9831266 # Number of times decode resolved a branch 460system.cpu.decode.BranchMispred 64876 # Number of times decode detected a branch misprediction 461system.cpu.decode.DecodedInsts 113761457 # Number of instructions handled by decode 462system.cpu.decode.SquashedInsts 2108425 # Number of squashed instructions handled by decode 463system.cpu.rename.SquashCycles 782181 # Number of cycles rename is squashing 464system.cpu.rename.IdleCycles 15316274 # Number of cycles rename is idle 465system.cpu.rename.BlockCycles 50229704 # Number of cycles rename is blocking 466system.cpu.rename.serializeStallCycles 114341 # count of cycles rename stalled for serializing inst 467system.cpu.rename.RunCycles 35119945 # Number of cycles rename is running 468system.cpu.rename.UnblockCycles 15411437 # Number of cycles rename is unblocking 469system.cpu.rename.RenamedInsts 110456918 # Number of instructions processed by rename 470system.cpu.rename.SquashedInsts 1289549 # Number of squashed instructions processed by rename 471system.cpu.rename.ROBFullEvents 11149602 # Number of times rename has blocked due to ROB full 472system.cpu.rename.IQFullEvents 1576334 # Number of times rename has blocked due to IQ full 473system.cpu.rename.LQFullEvents 2138216 # Number of times rename has blocked due to LQ full 474system.cpu.rename.SQFullEvents 510190 # Number of times rename has blocked due to SQ full 475system.cpu.rename.RenamedOperands 129202611 # Number of destination operands rename has renamed 476system.cpu.rename.RenameLookups 481340709 # Number of register rename lookups that rename has made 477system.cpu.rename.int_rename_lookups 118978784 # Number of integer rename lookups 478system.cpu.rename.fp_rename_lookups 633 # Number of floating rename lookups 479system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed 480system.cpu.rename.UndoneMaps 21889692 # Number of HB maps that are undone due to squashing 481system.cpu.rename.serializingInsts 4408 # count of serializing insts renamed 482system.cpu.rename.tempSerializingInsts 4400 # count of temporary serializing insts renamed 483system.cpu.rename.skidInsts 21529051 # count of insts added to the skid buffer 484system.cpu.memDep0.insertedLoads 26813393 # Number of loads inserted to the mem dependence unit. 485system.cpu.memDep0.insertedStores 5308956 # Number of stores inserted to the mem dependence unit. 486system.cpu.memDep0.conflictingLoads 540635 # Number of conflicting loads. 487system.cpu.memDep0.conflictingStores 272789 # Number of conflicting stores. 488system.cpu.iq.iqInstsAdded 109383305 # Number of instructions added to the IQ (excludes non-spec) 489system.cpu.iq.iqNonSpecInstsAdded 8282 # Number of non-speculative instructions added to the IQ 490system.cpu.iq.iqInstsIssued 101253910 # Number of instructions issued 491system.cpu.iq.iqSquashedInstsIssued 993650 # Number of squashed instructions issued 492system.cpu.iq.iqSquashedInstsExamined 18350557 # Number of squashed instructions iterated over during squash; mainly for profiling 493system.cpu.iq.iqSquashedOperandsExamined 40868291 # Number of squashed operands that are examined and possibly removed from graph 494system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed 495system.cpu.iq.issued_per_cycle::samples 116973882 # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::mean 0.865611 # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::stdev 0.989909 # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::total 116973882 # Number of insts issued each cycle 512system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 513system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84% # attempts to use FU when none available 514system.cpu.iq.fu_full::IntMult 51 0.00% 48.84% # attempts to use FU when none available 515system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84% # attempts to use FU when none available 516system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84% # attempts to use FU when none available 517system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84% # attempts to use FU when none available 544system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54% # attempts to use FU when none available 545system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00% # attempts to use FU when none available 546system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available 547system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available 548system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 549system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 550system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 551system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93% # Type of FU issued 552system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94% # Type of FU issued 553system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94% # Type of FU issued 560system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94% # Type of FU issued 561system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94% # Type of FU issued 582system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99% # Type of FU issued 583system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00% # Type of FU issued 584system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued 585system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued 586system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 587system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 588system.cpu.iq.FU_type_0::total 101253910 # Type of FU issued 589system.cpu.iq.rate 0.865106 # Inst issue rate 590system.cpu.iq.fu_busy_cnt 20139291 # FU busy when requested 591system.cpu.iq.fu_busy_rate 0.198899 # FU busy rate (busy events/executed inst) 592system.cpu.iq.int_inst_queue_reads 340613998 # Number of integer instruction queue reads 593system.cpu.iq.int_inst_queue_writes 127742533 # Number of integer instruction queue writes 594system.cpu.iq.int_inst_queue_wakeup_accesses 99568159 # Number of integer instruction queue wakeup accesses 595system.cpu.iq.fp_inst_queue_reads 645 # Number of floating instruction queue reads 596system.cpu.iq.fp_inst_queue_writes 896 # Number of floating instruction queue writes 597system.cpu.iq.fp_inst_queue_wakeup_accesses 147 # Number of floating instruction queue wakeup accesses 598system.cpu.iq.int_alu_accesses 121392865 # Number of integer alu accesses 599system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses 600system.cpu.iew.lsq.thread0.forwLoads 289487 # Number of loads that had data forwarded from stores 601system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 602system.cpu.iew.lsq.thread0.squashedLoads 4337482 # Number of loads squashed 603system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed 604system.cpu.iew.lsq.thread0.memOrderViolation 1323 # Number of memory ordering violations 605system.cpu.iew.lsq.thread0.squashedStores 564112 # Number of stores squashed 606system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 607system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 608system.cpu.iew.lsq.thread0.rescheduledLoads 7586 # Number of loads that were rescheduled 609system.cpu.iew.lsq.thread0.cacheBlocked 131115 # Number of times an access to memory failed due to the cache being blocked 610system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 611system.cpu.iew.iewSquashCycles 782181 # Number of cycles IEW is squashing 612system.cpu.iew.iewBlockCycles 8303656 # Number of cycles IEW is blocking 613system.cpu.iew.iewUnblockCycles 706645 # Number of cycles IEW is unblocking 614system.cpu.iew.iewDispatchedInsts 109404410 # Number of instructions dispatched to IQ 615system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 616system.cpu.iew.iewDispLoadInsts 26813393 # Number of dispatched load instructions 617system.cpu.iew.iewDispStoreInsts 5308956 # Number of dispatched store instructions 618system.cpu.iew.iewDispNonSpecInsts 4394 # Number of dispatched non-speculative instructions 619system.cpu.iew.iewIQFullEvents 183005 # Number of times the IQ has become full, causing a stall 620system.cpu.iew.iewLSQFullEvents 362995 # Number of times the LSQ has become full, causing a stall 621system.cpu.iew.memOrderViolationEvents 1323 # Number of memory order violations 622system.cpu.iew.predictedTakenIncorrect 354101 # Number of branches that were predicted taken incorrectly 623system.cpu.iew.predictedNotTakenIncorrect 451870 # Number of branches that were predicted not taken incorrectly 624system.cpu.iew.branchMispredicts 805971 # Number of branch mispredicts detected at execute 625system.cpu.iew.iewExecutedInsts 100068536 # Number of executed instructions 626system.cpu.iew.iewExecLoadInsts 23799476 # Number of load instructions executed 627system.cpu.iew.iewExecSquashedInsts 1185374 # Number of squashed instructions skipped in execute 628system.cpu.iew.exec_swp 0 # number of swp insts executed 629system.cpu.iew.exec_nop 12823 # number of nop insts executed 630system.cpu.iew.exec_refs 28747002 # number of memory reference insts executed 631system.cpu.iew.exec_branches 20644390 # Number of branches executed 632system.cpu.iew.exec_stores 4947526 # Number of stores executed 633system.cpu.iew.exec_rate 0.854978 # Inst execution rate 634system.cpu.iew.wb_sent 99653444 # cumulative count of insts sent to commit 635system.cpu.iew.wb_count 99568306 # cumulative count of insts written-back 636system.cpu.iew.wb_producers 59603520 # num instructions producing a value 637system.cpu.iew.wb_consumers 95472454 # num instructions consuming a value 638system.cpu.iew.wb_rate 0.850705 # insts written-back per cycle 639system.cpu.iew.wb_fanout 0.624301 # average fanout of values written-back 640system.cpu.commit.commitSquashedInsts 17204380 # The number of squashed insts skipped by commit 641system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 642system.cpu.commit.branchMispredicts 780499 # The number of times a branch was mispredicted 643system.cpu.commit.committed_per_cycle::samples 114317449 # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::mean 0.796498 # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::stdev 1.736161 # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00% # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 658system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 659system.cpu.commit.committed_per_cycle::total 114317449 # Number of insts commited each cycle 660system.cpu.commit.committedInsts 90602408 # Number of instructions committed 661system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed 662system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 663system.cpu.commit.refs 27220755 # Number of memory references committed 664system.cpu.commit.loads 22475911 # Number of loads committed 665system.cpu.commit.membars 3888 # Number of memory barriers committed 666system.cpu.commit.branches 18732305 # Number of branches committed 667system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 668system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. 669system.cpu.commit.function_calls 56148 # Number of function calls committed. 670system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 671system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction 672system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 673system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 676system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 677system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 678system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction 679system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 680system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction 681system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 696system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 697system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 698system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 699system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 700system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 701system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 702system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction 703system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction 704system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction 705system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction 706system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 707system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 708system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction 709system.cpu.commit.bw_lim_events 4142947 # number cycles where commit BW limit reached 710system.cpu.rob.rob_reads 218426787 # The number of ROB reads 711system.cpu.rob.rob_writes 219173124 # The number of ROB writes 712system.cpu.timesIdled 593 # Number of times that the entire CPU went into an idle state and unscheduled itself 713system.cpu.idleCycles 68291 # Total number of cycles that the CPU has spent unscheduled due to idling 714system.cpu.committedInsts 90589799 # Number of Instructions Simulated 715system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated 716system.cpu.cpi 1.292002 # CPI: Cycles Per Instruction 717system.cpu.cpi_total 1.292002 # CPI: Total CPI of All Threads 718system.cpu.ipc 0.773993 # IPC: Instructions Per Cycle 719system.cpu.ipc_total 0.773993 # IPC: Total IPC of All Threads 720system.cpu.int_regfile_reads 108095256 # number of integer regfile reads 721system.cpu.int_regfile_writes 58597145 # number of integer regfile writes 722system.cpu.fp_regfile_reads 58 # number of floating regfile reads 723system.cpu.fp_regfile_writes 127 # number of floating regfile writes 724system.cpu.cc_regfile_reads 368871207 # number of cc regfile reads 725system.cpu.cc_regfile_writes 58517884 # number of cc regfile writes 726system.cpu.misc_regfile_reads 28439348 # number of misc regfile reads 727system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 728system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 729system.cpu.dcache.tags.replacements 5470632 # number of replacements 730system.cpu.dcache.tags.tagsinuse 511.768178 # Cycle average of tags in use 731system.cpu.dcache.tags.total_refs 18243100 # Total number of references to valid blocks. 732system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks. 733system.cpu.dcache.tags.avg_refs 3.334421 # Average number of references to valid blocks. 734system.cpu.dcache.tags.warmup_cycle 38187500 # Cycle when the warmup percentage was hit. 735system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178 # Average occupied blocks per requestor 736system.cpu.dcache.tags.occ_percent::cpu.data 0.999547 # Average percentage of cache occupancy 737system.cpu.dcache.tags.occ_percent::total 0.999547 # Average percentage of cache occupancy 738system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 739system.cpu.dcache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id 740system.cpu.dcache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id 741system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 742system.cpu.dcache.tags.tag_accesses 61896540 # Number of tag accesses 743system.cpu.dcache.tags.data_accesses 61896540 # Number of data accesses 744system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 745system.cpu.dcache.ReadReq_hits::cpu.data 13880582 # number of ReadReq hits 746system.cpu.dcache.ReadReq_hits::total 13880582 # number of ReadReq hits 747system.cpu.dcache.WriteReq_hits::cpu.data 4354214 # number of WriteReq hits 748system.cpu.dcache.WriteReq_hits::total 4354214 # number of WriteReq hits 749system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 750system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 751system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits 752system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits 753system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 754system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 755system.cpu.dcache.demand_hits::cpu.data 18234796 # number of demand (read+write) hits 756system.cpu.dcache.demand_hits::total 18234796 # number of demand (read+write) hits 757system.cpu.dcache.overall_hits::cpu.data 18235318 # number of overall hits 758system.cpu.dcache.overall_hits::total 18235318 # number of overall hits 759system.cpu.dcache.ReadReq_misses::cpu.data 9588832 # number of ReadReq misses 760system.cpu.dcache.ReadReq_misses::total 9588832 # number of ReadReq misses 761system.cpu.dcache.WriteReq_misses::cpu.data 380767 # number of WriteReq misses 762system.cpu.dcache.WriteReq_misses::total 380767 # number of WriteReq misses 763system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses 764system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses 765system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses 766system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses 767system.cpu.dcache.demand_misses::cpu.data 9969599 # number of demand (read+write) misses 768system.cpu.dcache.demand_misses::total 9969599 # number of demand (read+write) misses 769system.cpu.dcache.overall_misses::cpu.data 9969606 # number of overall misses 770system.cpu.dcache.overall_misses::total 9969606 # number of overall misses 771system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500 # number of ReadReq miss cycles 772system.cpu.dcache.ReadReq_miss_latency::total 89393317500 # number of ReadReq miss cycles 773system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083 # number of WriteReq miss cycles 774system.cpu.dcache.WriteReq_miss_latency::total 4103772083 # number of WriteReq miss cycles 775system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles 776system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles 777system.cpu.dcache.demand_miss_latency::cpu.data 93497089583 # number of demand (read+write) miss cycles 778system.cpu.dcache.demand_miss_latency::total 93497089583 # number of demand (read+write) miss cycles 779system.cpu.dcache.overall_miss_latency::cpu.data 93497089583 # number of overall miss cycles 780system.cpu.dcache.overall_miss_latency::total 93497089583 # number of overall miss cycles 781system.cpu.dcache.ReadReq_accesses::cpu.data 23469414 # number of ReadReq accesses(hits+misses) 782system.cpu.dcache.ReadReq_accesses::total 23469414 # number of ReadReq accesses(hits+misses) 783system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 784system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 785system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) 786system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) 787system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 788system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 789system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 790system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 791system.cpu.dcache.demand_accesses::cpu.data 28204395 # number of demand (read+write) accesses 792system.cpu.dcache.demand_accesses::total 28204395 # number of demand (read+write) accesses 793system.cpu.dcache.overall_accesses::cpu.data 28204924 # number of overall (read+write) accesses 794system.cpu.dcache.overall_accesses::total 28204924 # number of overall (read+write) accesses 795system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567 # miss rate for ReadReq accesses 796system.cpu.dcache.ReadReq_miss_rate::total 0.408567 # miss rate for ReadReq accesses 797system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416 # miss rate for WriteReq accesses 798system.cpu.dcache.WriteReq_miss_rate::total 0.080416 # miss rate for WriteReq accesses 799system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses 800system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses 801system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses 802system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses 803system.cpu.dcache.demand_miss_rate::cpu.data 0.353477 # miss rate for demand accesses 804system.cpu.dcache.demand_miss_rate::total 0.353477 # miss rate for demand accesses 805system.cpu.dcache.overall_miss_rate::cpu.data 0.353470 # miss rate for overall accesses 806system.cpu.dcache.overall_miss_rate::total 0.353470 # miss rate for overall accesses 807system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255 # average ReadReq miss latency 808system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255 # average ReadReq miss latency 809system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390 # average WriteReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390 # average WriteReq miss latency 811system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency 812system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency 813system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684 # average overall miss latency 814system.cpu.dcache.demand_avg_miss_latency::total 9378.219684 # average overall miss latency 815system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099 # average overall miss latency 816system.cpu.dcache.overall_avg_miss_latency::total 9378.213099 # average overall miss latency 817system.cpu.dcache.blocked_cycles::no_mshrs 331670 # number of cycles access was blocked 818system.cpu.dcache.blocked_cycles::no_targets 131340 # number of cycles access was blocked 819system.cpu.dcache.blocked::no_mshrs 121646 # number of cycles access was blocked 820system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked 821system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518 # average number of cycles each access was blocked 822system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566 # average number of cycles each access was blocked 823system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks 824system.cpu.dcache.writebacks::total 5470632 # number of writebacks 825system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269 # number of ReadReq MSHR hits 826system.cpu.dcache.ReadReq_mshr_hits::total 4340269 # number of ReadReq MSHR hits 827system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185 # number of WriteReq MSHR hits 828system.cpu.dcache.WriteReq_mshr_hits::total 158185 # number of WriteReq MSHR hits 829system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits 830system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits 831system.cpu.dcache.demand_mshr_hits::cpu.data 4498454 # number of demand (read+write) MSHR hits 832system.cpu.dcache.demand_mshr_hits::total 4498454 # number of demand (read+write) MSHR hits 833system.cpu.dcache.overall_mshr_hits::cpu.data 4498454 # number of overall MSHR hits 834system.cpu.dcache.overall_mshr_hits::total 4498454 # number of overall MSHR hits 835system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563 # number of ReadReq MSHR misses 836system.cpu.dcache.ReadReq_mshr_misses::total 5248563 # number of ReadReq MSHR misses 837system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582 # number of WriteReq MSHR misses 838system.cpu.dcache.WriteReq_mshr_misses::total 222582 # number of WriteReq MSHR misses 839system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses 840system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses 841system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses 842system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses 843system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses 844system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses 845system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500 # number of ReadReq MSHR miss cycles 846system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500 # number of ReadReq MSHR miss cycles 847system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483 # number of WriteReq MSHR miss cycles 848system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483 # number of WriteReq MSHR miss cycles 849system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles 850system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles 851system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983 # number of demand (read+write) MSHR miss cycles 852system.cpu.dcache.demand_mshr_miss_latency::total 46120568983 # number of demand (read+write) MSHR miss cycles 853system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483 # number of overall MSHR miss cycles 854system.cpu.dcache.overall_mshr_miss_latency::total 46120804483 # number of overall MSHR miss cycles 855system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634 # mshr miss rate for ReadReq accesses 856system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634 # mshr miss rate for ReadReq accesses 857system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008 # mshr miss rate for WriteReq accesses 858system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008 # mshr miss rate for WriteReq accesses 859system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses 860system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses 861system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982 # mshr miss rate for demand accesses 862system.cpu.dcache.demand_mshr_miss_rate::total 0.193982 # mshr miss rate for demand accesses 863system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979 # mshr miss rate for overall accesses 864system.cpu.dcache.overall_mshr_miss_rate::total 0.193979 # mshr miss rate for overall accesses 865system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446 # average ReadReq mshr miss latency 866system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446 # average ReadReq mshr miss latency 867system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061 # average WriteReq mshr miss latency 868system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061 # average WriteReq mshr miss latency 869system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency 870system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency 871system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708 # average overall mshr miss latency 872system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708 # average overall mshr miss latency 873system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589 # average overall mshr miss latency 874system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589 # average overall mshr miss latency 875system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 876system.cpu.icache.tags.replacements 449 # number of replacements 877system.cpu.icache.tags.tagsinuse 426.857560 # Cycle average of tags in use 878system.cpu.icache.tags.total_refs 32085580 # Total number of references to valid blocks. 879system.cpu.icache.tags.sampled_refs 907 # Sample count of references to valid blocks. 880system.cpu.icache.tags.avg_refs 35375.501654 # Average number of references to valid blocks. 881system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 882system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560 # Average occupied blocks per requestor 883system.cpu.icache.tags.occ_percent::cpu.inst 0.833706 # Average percentage of cache occupancy 884system.cpu.icache.tags.occ_percent::total 0.833706 # Average percentage of cache occupancy 885system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id 886system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 887system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id 888system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id 889system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id 890system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id 891system.cpu.icache.tags.tag_accesses 64174375 # Number of tag accesses 892system.cpu.icache.tags.data_accesses 64174375 # Number of data accesses 893system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 894system.cpu.icache.ReadReq_hits::cpu.inst 32085580 # number of ReadReq hits 895system.cpu.icache.ReadReq_hits::total 32085580 # number of ReadReq hits 896system.cpu.icache.demand_hits::cpu.inst 32085580 # number of demand (read+write) hits 897system.cpu.icache.demand_hits::total 32085580 # number of demand (read+write) hits 898system.cpu.icache.overall_hits::cpu.inst 32085580 # number of overall hits 899system.cpu.icache.overall_hits::total 32085580 # number of overall hits 900system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses 901system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses 902system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses 903system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses 904system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses 905system.cpu.icache.overall_misses::total 1154 # number of overall misses 906system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480 # number of ReadReq miss cycles 907system.cpu.icache.ReadReq_miss_latency::total 81624480 # number of ReadReq miss cycles 908system.cpu.icache.demand_miss_latency::cpu.inst 81624480 # number of demand (read+write) miss cycles 909system.cpu.icache.demand_miss_latency::total 81624480 # number of demand (read+write) miss cycles 910system.cpu.icache.overall_miss_latency::cpu.inst 81624480 # number of overall miss cycles 911system.cpu.icache.overall_miss_latency::total 81624480 # number of overall miss cycles 912system.cpu.icache.ReadReq_accesses::cpu.inst 32086734 # number of ReadReq accesses(hits+misses) 913system.cpu.icache.ReadReq_accesses::total 32086734 # number of ReadReq accesses(hits+misses) 914system.cpu.icache.demand_accesses::cpu.inst 32086734 # number of demand (read+write) accesses 915system.cpu.icache.demand_accesses::total 32086734 # number of demand (read+write) accesses 916system.cpu.icache.overall_accesses::cpu.inst 32086734 # number of overall (read+write) accesses 917system.cpu.icache.overall_accesses::total 32086734 # number of overall (read+write) accesses 918system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses 919system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses 920system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses 921system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses 922system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses 923system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses 924system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095 # average ReadReq miss latency 925system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095 # average ReadReq miss latency 926system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency 927system.cpu.icache.demand_avg_miss_latency::total 70731.785095 # average overall miss latency 928system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency 929system.cpu.icache.overall_avg_miss_latency::total 70731.785095 # average overall miss latency 930system.cpu.icache.blocked_cycles::no_mshrs 21770 # number of cycles access was blocked 931system.cpu.icache.blocked_cycles::no_targets 1853 # number of cycles access was blocked 932system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked 933system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked 934system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502 # average number of cycles each access was blocked 935system.cpu.icache.avg_blocked_cycles::no_targets 264.714286 # average number of cycles each access was blocked 936system.cpu.icache.writebacks::writebacks 449 # number of writebacks 937system.cpu.icache.writebacks::total 449 # number of writebacks 938system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits 939system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits 940system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits 941system.cpu.icache.demand_mshr_hits::total 246 # number of demand (read+write) MSHR hits 942system.cpu.icache.overall_mshr_hits::cpu.inst 246 # number of overall MSHR hits 943system.cpu.icache.overall_mshr_hits::total 246 # number of overall MSHR hits 944system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses 945system.cpu.icache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses 946system.cpu.icache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses 947system.cpu.icache.demand_mshr_misses::total 908 # number of demand (read+write) MSHR misses 948system.cpu.icache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses 949system.cpu.icache.overall_mshr_misses::total 908 # number of overall MSHR misses 950system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61609984 # number of ReadReq MSHR miss cycles 951system.cpu.icache.ReadReq_mshr_miss_latency::total 61609984 # number of ReadReq MSHR miss cycles 952system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61609984 # number of demand (read+write) MSHR miss cycles 953system.cpu.icache.demand_mshr_miss_latency::total 61609984 # number of demand (read+write) MSHR miss cycles 954system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984 # number of overall MSHR miss cycles 955system.cpu.icache.overall_mshr_miss_latency::total 61609984 # number of overall MSHR miss cycles 956system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 957system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 958system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 959system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 960system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 961system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 962system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67852.405286 # average ReadReq mshr miss latency 963system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286 # average ReadReq mshr miss latency 964system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency 965system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency 966system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency 967system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency 968system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 969system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667 # number of hwpf issued 970system.cpu.l2cache.prefetcher.pfIdentified 5295978 # number of prefetch candidates identified 971system.cpu.l2cache.prefetcher.pfBufferHit 268023 # number of redundant prefetches already in prefetch queue 972system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 973system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 974system.cpu.l2cache.prefetcher.pfSpanPage 14076270 # number of prefetches not generated due to page crossing 975system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 976system.cpu.l2cache.tags.replacements 99 # number of replacements 977system.cpu.l2cache.tags.tagsinuse 11218.637670 # Cycle average of tags in use 978system.cpu.l2cache.tags.total_refs 5292117 # Total number of references to valid blocks. 979system.cpu.l2cache.tags.sampled_refs 14656 # Sample count of references to valid blocks. 980system.cpu.l2cache.tags.avg_refs 361.088769 # Average number of references to valid blocks. 981system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 982system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658 # Average occupied blocks per requestor 983system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012 # Average occupied blocks per requestor 984system.cpu.l2cache.tags.occ_percent::writebacks 0.680659 # Average percentage of cache occupancy 985system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004072 # Average percentage of cache occupancy 986system.cpu.l2cache.tags.occ_percent::total 0.684731 # Average percentage of cache occupancy 987system.cpu.l2cache.tags.occ_task_id_blocks::1022 67 # Occupied blocks per task id 988system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642 # Occupied blocks per task id 995system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120 # Occupied blocks per task id 996system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834 # Occupied blocks per task id 997system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089 # Percentage of cache occupancy per task id 998system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399 # Percentage of cache occupancy per task id 999system.cpu.l2cache.tags.tag_accesses 180525307 # Number of tag accesses 1000system.cpu.l2cache.tags.data_accesses 180525307 # Number of data accesses 1001system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 1002system.cpu.l2cache.WritebackDirty_hits::writebacks 5460197 # number of WritebackDirty hits 1003system.cpu.l2cache.WritebackDirty_hits::total 5460197 # number of WritebackDirty hits 1004system.cpu.l2cache.WritebackClean_hits::writebacks 7956 # number of WritebackClean hits 1005system.cpu.l2cache.WritebackClean_hits::total 7956 # number of WritebackClean hits 1006system.cpu.l2cache.ReadExReq_hits::cpu.data 225753 # number of ReadExReq hits 1007system.cpu.l2cache.ReadExReq_hits::total 225753 # number of ReadExReq hits 1008system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 207 # number of ReadCleanReq hits 1009system.cpu.l2cache.ReadCleanReq_hits::total 207 # number of ReadCleanReq hits 1010system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241769 # number of ReadSharedReq hits 1011system.cpu.l2cache.ReadSharedReq_hits::total 5241769 # number of ReadSharedReq hits 1012system.cpu.l2cache.demand_hits::cpu.inst 207 # number of demand (read+write) hits 1013system.cpu.l2cache.demand_hits::cpu.data 5467522 # number of demand (read+write) hits 1014system.cpu.l2cache.demand_hits::total 5467729 # number of demand (read+write) hits 1015system.cpu.l2cache.overall_hits::cpu.inst 207 # number of overall hits 1016system.cpu.l2cache.overall_hits::cpu.data 5467522 # number of overall hits 1017system.cpu.l2cache.overall_hits::total 5467729 # number of overall hits 1018system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 1019system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses 1020system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses 1021system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses 1022system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses 1023system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses 1024system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123 # number of ReadSharedReq misses 1025system.cpu.l2cache.ReadSharedReq_misses::total 3123 # number of ReadSharedReq misses 1026system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses 1027system.cpu.l2cache.demand_misses::cpu.data 3622 # number of demand (read+write) misses 1028system.cpu.l2cache.demand_misses::total 4323 # number of demand (read+write) misses 1029system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses 1030system.cpu.l2cache.overall_misses::cpu.data 3622 # number of overall misses 1031system.cpu.l2cache.overall_misses::total 4323 # number of overall misses 1032system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 105500 # number of UpgradeReq miss cycles 1033system.cpu.l2cache.UpgradeReq_miss_latency::total 105500 # number of UpgradeReq miss cycles 1034system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66196000 # number of ReadExReq miss cycles 1035system.cpu.l2cache.ReadExReq_miss_latency::total 66196000 # number of ReadExReq miss cycles 1036system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59307500 # number of ReadCleanReq miss cycles 1037system.cpu.l2cache.ReadCleanReq_miss_latency::total 59307500 # number of ReadCleanReq miss cycles 1038system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 617300000 # number of ReadSharedReq miss cycles 1039system.cpu.l2cache.ReadSharedReq_miss_latency::total 617300000 # number of ReadSharedReq miss cycles 1040system.cpu.l2cache.demand_miss_latency::cpu.inst 59307500 # number of demand (read+write) miss cycles 1041system.cpu.l2cache.demand_miss_latency::cpu.data 683496000 # number of demand (read+write) miss cycles 1042system.cpu.l2cache.demand_miss_latency::total 742803500 # number of demand (read+write) miss cycles 1043system.cpu.l2cache.overall_miss_latency::cpu.inst 59307500 # number of overall miss cycles 1044system.cpu.l2cache.overall_miss_latency::cpu.data 683496000 # number of overall miss cycles 1045system.cpu.l2cache.overall_miss_latency::total 742803500 # number of overall miss cycles 1046system.cpu.l2cache.WritebackDirty_accesses::writebacks 5460197 # number of WritebackDirty accesses(hits+misses) 1047system.cpu.l2cache.WritebackDirty_accesses::total 5460197 # number of WritebackDirty accesses(hits+misses) 1048system.cpu.l2cache.WritebackClean_accesses::writebacks 7956 # number of WritebackClean accesses(hits+misses) 1049system.cpu.l2cache.WritebackClean_accesses::total 7956 # number of WritebackClean accesses(hits+misses) 1050system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) 1051system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) 1052system.cpu.l2cache.ReadExReq_accesses::cpu.data 226252 # number of ReadExReq accesses(hits+misses) 1053system.cpu.l2cache.ReadExReq_accesses::total 226252 # number of ReadExReq accesses(hits+misses) 1054system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 908 # number of ReadCleanReq accesses(hits+misses) 1055system.cpu.l2cache.ReadCleanReq_accesses::total 908 # number of ReadCleanReq accesses(hits+misses) 1056system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244892 # number of ReadSharedReq accesses(hits+misses) 1057system.cpu.l2cache.ReadSharedReq_accesses::total 5244892 # number of ReadSharedReq accesses(hits+misses) 1058system.cpu.l2cache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses 1059system.cpu.l2cache.demand_accesses::cpu.data 5471144 # number of demand (read+write) accesses 1060system.cpu.l2cache.demand_accesses::total 5472052 # number of demand (read+write) accesses 1061system.cpu.l2cache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses 1062system.cpu.l2cache.overall_accesses::cpu.data 5471144 # number of overall (read+write) accesses 1063system.cpu.l2cache.overall_accesses::total 5472052 # number of overall (read+write) accesses 1064system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1065system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1066system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002206 # miss rate for ReadExReq accesses 1067system.cpu.l2cache.ReadExReq_miss_rate::total 0.002206 # miss rate for ReadExReq accesses 1068system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772026 # miss rate for ReadCleanReq accesses 1069system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772026 # miss rate for ReadCleanReq accesses 1070system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000595 # miss rate for ReadSharedReq accesses 1071system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000595 # miss rate for ReadSharedReq accesses 1072system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772026 # miss rate for demand accesses 1073system.cpu.l2cache.demand_miss_rate::cpu.data 0.000662 # miss rate for demand accesses 1074system.cpu.l2cache.demand_miss_rate::total 0.000790 # miss rate for demand accesses 1075system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026 # miss rate for overall accesses 1076system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662 # miss rate for overall accesses 1077system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses 1078system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21100 # average UpgradeReq miss latency 1079system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21100 # average UpgradeReq miss latency 1080system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.314629 # average ReadExReq miss latency 1081system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.314629 # average ReadExReq miss latency 1082system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947 # average ReadCleanReq miss latency 1083system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947 # average ReadCleanReq miss latency 1084system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003 # average ReadSharedReq miss latency 1085system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003 # average ReadSharedReq miss latency 1086system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency 1087system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency 1088system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066 # average overall miss latency 1089system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency 1090system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency 1091system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066 # average overall miss latency 1092system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1093system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1094system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1095system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1096system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1097system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1098system.cpu.l2cache.unused_prefetches 1 # number of HardPF blocks evicted w/o reference 1099system.cpu.l2cache.writebacks::writebacks 74 # number of writebacks 1100system.cpu.l2cache.writebacks::total 74 # number of writebacks 1101system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits 1102system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits 1103system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1104system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1105system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits 1106system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits 1107system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1108system.cpu.l2cache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits 1109system.cpu.l2cache.demand_mshr_hits::total 181 # number of demand (read+write) MSHR hits 1110system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1111system.cpu.l2cache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits 1112system.cpu.l2cache.overall_mshr_hits::total 181 # number of overall MSHR hits 1113system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332 # number of HardPFReq MSHR misses 1114system.cpu.l2cache.HardPFReq_mshr_misses::total 316332 # number of HardPFReq MSHR misses 1115system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses 1116system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses 1117system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses 1118system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses 1119system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses 1120system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses 1121system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101 # number of ReadSharedReq MSHR misses 1122system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101 # number of ReadSharedReq MSHR misses 1123system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses 1124system.cpu.l2cache.demand_mshr_misses::cpu.data 3442 # number of demand (read+write) MSHR misses 1125system.cpu.l2cache.demand_mshr_misses::total 4142 # number of demand (read+write) MSHR misses 1126system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses 1127system.cpu.l2cache.overall_mshr_misses::cpu.data 3442 # number of overall MSHR misses 1128system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332 # number of overall MSHR misses 1129system.cpu.l2cache.overall_mshr_misses::total 320474 # number of overall MSHR misses 1130system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of HardPFReq MSHR miss cycles 1131system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507 # number of HardPFReq MSHR miss cycles 1132system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500 # number of UpgradeReq MSHR miss cycles 1133system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500 # number of UpgradeReq MSHR miss cycles 1134system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500 # number of ReadExReq MSHR miss cycles 1135system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500 # number of ReadExReq MSHR miss cycles 1136system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500 # number of ReadCleanReq MSHR miss cycles 1137system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500 # number of ReadCleanReq MSHR miss cycles 1138system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000 # number of ReadSharedReq MSHR miss cycles 1139system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000 # number of ReadSharedReq MSHR miss cycles 1140system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500 # number of demand (read+write) MSHR miss cycles 1141system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500 # number of demand (read+write) MSHR miss cycles 1142system.cpu.l2cache.demand_mshr_miss_latency::total 692500000 # number of demand (read+write) MSHR miss cycles 1143system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500 # number of overall MSHR miss cycles 1144system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500 # number of overall MSHR miss cycles 1145system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of overall MSHR miss cycles 1146system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507 # number of overall MSHR miss cycles 1147system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1148system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1149system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1150system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1151system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507 # mshr miss rate for ReadExReq accesses 1152system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadExReq accesses 1153system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for ReadCleanReq accesses 1154system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925 # mshr miss rate for ReadCleanReq accesses 1155system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591 # mshr miss rate for ReadSharedReq accesses 1156system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591 # mshr miss rate for ReadSharedReq accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for demand accesses 1158system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for demand accesses 1159system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757 # mshr miss rate for demand accesses 1160system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for overall accesses 1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for overall accesses 1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1163system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566 # mshr miss rate for overall accesses 1164system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average HardPFReq mshr miss latency 1165system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372 # average HardPFReq mshr miss latency 1166system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100 # average UpgradeReq mshr miss latency 1167system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100 # average UpgradeReq mshr miss latency 1168system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534 # average ReadExReq mshr miss latency 1169system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534 # average ReadExReq mshr miss latency 1170system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143 # average ReadCleanReq mshr miss latency 1171system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143 # average ReadCleanReq mshr miss latency 1172system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884 # average ReadSharedReq mshr miss latency 1173system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884 # average ReadSharedReq mshr miss latency 1174system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441 # average overall mshr miss latency 1181system.cpu.toL2Bus.snoop_filter.tot_requests 10943138 # Total number of requests made to the snoop filter. 1182system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1183system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1184system.cpu.toL2Bus.snoop_filter.tot_snoops 301927 # Total number of snoops made to the snoop filter. 1185system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1186system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1187system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 1188system.cpu.toL2Bus.trans_dist::ReadResp 5245799 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::WritebackClean 10884 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::CleanEvict 25 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::HardPFReq 318221 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::ReadExReq 226252 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::ReadExResp 226252 # Transaction distribution 1198system.cpu.toL2Bus.trans_dist::ReadCleanReq 908 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892 # Transaction distribution 1200system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264 # Packet count per connected master and slave (bytes) 1201system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) 1202system.cpu.toL2Bus.pkt_count::total 16415200 # Packet count per connected master and slave (bytes) 1203system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784 # Cumulative packet size per connected master and slave (bytes) 1204system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes) 1205system.cpu.toL2Bus.pkt_size::total 700360832 # Cumulative packet size per connected master and slave (bytes) 1206system.cpu.toL2Bus.snoops 318326 # Total snoops (count) 1207system.cpu.toL2Bus.snoopTraffic 5120 # Total snoop traffic (bytes) 1208system.cpu.toL2Bus.snoop_fanout::samples 5790377 # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::mean 0.052651 # Request fanout histogram 1210system.cpu.toL2Bus.snoop_fanout::stdev 0.223337 # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73% # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00% # Request fanout histogram 1214system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1215system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1216system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1217system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1218system.cpu.toL2Bus.snoop_fanout::total 5790377 # Request fanout histogram 1219system.cpu.toL2Bus.reqLayer0.occupancy 10942650026 # Layer occupancy (ticks) 1220system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) 1221system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks) 1222system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1223system.cpu.toL2Bus.respLayer0.occupancy 1362995 # Layer occupancy (ticks) 1224system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1225system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks) 1226system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) 1227system.membus.snoop_filter.tot_requests 18651 # Total number of requests made to the snoop filter. 1228system.membus.snoop_filter.hit_single_requests 3037 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1229system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1230system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1231system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1232system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1233system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states 1234system.membus.trans_dist::ReadResp 18205 # Transaction distribution 1235system.membus.trans_dist::WritebackDirty 74 # Transaction distribution 1236system.membus.trans_dist::CleanEvict 25 # Transaction distribution 1237system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 1238system.membus.trans_dist::ReadExReq 340 # Transaction distribution 1239system.membus.trans_dist::ReadExResp 340 # Transaction distribution 1240system.membus.trans_dist::ReadSharedReq 18206 # Transaction distribution 1241system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196 # Packet count per connected master and slave (bytes) 1242system.membus.pkt_count::total 37196 # Packet count per connected master and slave (bytes) 1243system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616 # Cumulative packet size per connected master and slave (bytes) 1244system.membus.pkt_size::total 1191616 # Cumulative packet size per connected master and slave (bytes) 1245system.membus.snoops 0 # Total snoops (count) 1246system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1247system.membus.snoop_fanout::samples 18552 # Request fanout histogram 1248system.membus.snoop_fanout::mean 0 # Request fanout histogram 1249system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1250system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1251system.membus.snoop_fanout::0 18552 100.00% 100.00% # Request fanout histogram 1252system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1253system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1254system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1255system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1256system.membus.snoop_fanout::total 18552 # Request fanout histogram 1257system.membus.reqLayer0.occupancy 29380556 # Layer occupancy (ticks) 1258system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 1259system.membus.respLayer1.occupancy 97369032 # Layer occupancy (ticks) 1260system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1261 1262---------- End Simulation Statistics ----------