| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058203 # Number of seconds simulated 4sim_ticks 58202727500 # Number of ticks simulated 5final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 129726 # Simulator instruction rate (inst/s) 8host_op_rate 130372 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 83346935 # Simulator tick rate (ticks/s) 10host_mem_usage 443628 # Number of bytes of host memory used 11host_seconds 698.32 # Real time elapsed on the host 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91041029 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 44480 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 45376 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 930112 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1019968 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 44480 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 44480 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 22912 # Number of bytes written to this memory 23system.physmem.bytes_written::total 22912 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 695 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 709 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 14533 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 15937 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 358 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 358 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 764225 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 779620 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 15980557 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 17524402 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 764225 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 764225 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 393659 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 393659 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 393659 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 764225 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 779620 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 15980557 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17918061 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 15937 # Number of read requests accepted 44system.physmem.writeReqs 358 # Number of write requests accepted 45system.physmem.readBursts 15937 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 358 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 1010432 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue 49system.physmem.bytesWritten 21184 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 1019968 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 22912 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 1009 # Per bank write bursts 56system.physmem.perBankRdBursts::1 876 # Per bank write bursts 57system.physmem.perBankRdBursts::2 958 # Per bank write bursts 58system.physmem.perBankRdBursts::3 1024 # Per bank write bursts 59system.physmem.perBankRdBursts::4 1064 # Per bank write bursts 60system.physmem.perBankRdBursts::5 1132 # Per bank write bursts 61system.physmem.perBankRdBursts::6 1124 # Per bank write bursts 62system.physmem.perBankRdBursts::7 1103 # Per bank write bursts 63system.physmem.perBankRdBursts::8 1046 # Per bank write bursts 64system.physmem.perBankRdBursts::9 962 # Per bank write bursts 65system.physmem.perBankRdBursts::10 937 # Per bank write bursts 66system.physmem.perBankRdBursts::11 899 # Per bank write bursts 67system.physmem.perBankRdBursts::12 909 # Per bank write bursts 68system.physmem.perBankRdBursts::13 889 # Per bank write bursts 69system.physmem.perBankRdBursts::14 926 # Per bank write bursts 70system.physmem.perBankRdBursts::15 930 # Per bank write bursts 71system.physmem.perBankWrBursts::0 30 # Per bank write bursts 72system.physmem.perBankWrBursts::1 0 # Per bank write bursts 73system.physmem.perBankWrBursts::2 8 # Per bank write bursts 74system.physmem.perBankWrBursts::3 1 # Per bank write bursts 75system.physmem.perBankWrBursts::4 10 # Per bank write bursts 76system.physmem.perBankWrBursts::5 29 # Per bank write bursts 77system.physmem.perBankWrBursts::6 69 # Per bank write bursts 78system.physmem.perBankWrBursts::7 31 # Per bank write bursts 79system.physmem.perBankWrBursts::8 36 # Per bank write bursts 80system.physmem.perBankWrBursts::9 0 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7 # Per bank write bursts 82system.physmem.perBankWrBursts::11 0 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7 # Per bank write bursts 84system.physmem.perBankWrBursts::13 27 # Per bank write bursts 85system.physmem.perBankWrBursts::14 45 # Per bank write bursts 86system.physmem.perBankWrBursts::15 31 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 58202569500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 15937 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 358 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 10945 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 2405 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 349 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 310 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 297 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 305 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 289 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 304 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 62 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 19 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 19 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 19 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 19 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 19 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 19 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 19 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 20 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 18 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 18 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 1871 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 551.268840 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 315.885566 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 433.770323 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 552 29.50% 29.50% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 218 11.65% 41.15% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 92 4.92% 46.07% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 57 3.05% 49.12% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 63 3.37% 52.49% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 44 2.35% 54.84% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 55 2.94% 57.78% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 42 2.24% 60.02% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 748 39.98% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 1871 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 18 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 874.777778 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 39.760140 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 3541.219224 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 17 94.44% 94.44% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::14848-15359 1 5.56% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 18 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 18 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 18.388889 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 18.356746 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 1.195033 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 15 83.33% 83.33% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 2 11.11% 94.44% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::23 1 5.56% 100.00% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::total 18 # Writes before turning the bus around for reads 229system.physmem.totQLat 172783990 # Total ticks spent queuing 230system.physmem.totMemAccLat 468808990 # Total ticks spent from burst creation until serviced by the DRAM 231system.physmem.totBusLat 78940000 # Total ticks spent in databus transfers 232system.physmem.avgQLat 10944.01 # Average queueing delay per DRAM burst 233system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 234system.physmem.avgMemAccLat 29694.01 # Average memory access latency per DRAM burst 235system.physmem.avgRdBW 17.36 # Average DRAM read bandwidth in MiByte/s 236system.physmem.avgWrBW 0.36 # Average achieved write bandwidth in MiByte/s 237system.physmem.avgRdBWSys 17.52 # Average system read bandwidth in MiByte/s 238system.physmem.avgWrBWSys 0.39 # Average system write bandwidth in MiByte/s 239system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 240system.physmem.busUtil 0.14 # Data bus utilization in percentage 241system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads 242system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 243system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing 244system.physmem.avgWrQLen 16.15 # Average write queue length when enqueuing 245system.physmem.readRowHits 14154 # Number of row buffer hits during reads 246system.physmem.writeRowHits 93 # Number of row buffer hits during writes 247system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads 248system.physmem.writeRowHitRate 26.20 # Row buffer hit rate for writes 249system.physmem.avgGap 3571805.43 # Average gap between requests 250system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined 251system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) 252system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) 253system.physmem_0.readEnergy 64638600 # Energy for read commands per rank (pJ) 254system.physmem_0.writeEnergy 1153440 # Energy for write commands per rank (pJ) 255system.physmem_0.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) 256system.physmem_0.actBackEnergy 2451888630 # Energy for active background per rank (pJ) 257system.physmem_0.preBackEnergy 32770707750 # Energy for precharge background per rank (pJ) 258system.physmem_0.totalEnergy 39101711325 # Total energy per rank (pJ) 259system.physmem_0.averagePower 671.822097 # Core power per rank (mW) 260system.physmem_0.memoryStateTime::IDLE 54506616189 # Time in different power states 261system.physmem_0.memoryStateTime::REF 1943500000 # Time in different power states 262system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 263system.physmem_0.memoryStateTime::ACT 1752376311 # Time in different power states 264system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 265system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) 266system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) 267system.physmem_1.readEnergy 58484400 # Energy for read commands per rank (pJ) 268system.physmem_1.writeEnergy 991440 # Energy for write commands per rank (pJ) 269system.physmem_1.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) 270system.physmem_1.actBackEnergy 2431326735 # Energy for active background per rank (pJ) 271system.physmem_1.preBackEnergy 32788744500 # Energy for precharge background per rank (pJ) 272system.physmem_1.totalEnergy 39091058805 # Total energy per rank (pJ) 273system.physmem_1.averagePower 671.639072 # Core power per rank (mW) 274system.physmem_1.memoryStateTime::IDLE 54537138662 # Time in different power states 275system.physmem_1.memoryStateTime::REF 1943500000 # Time in different power states 276system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 277system.physmem_1.memoryStateTime::ACT 1721853838 # Time in different power states 278system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 279system.cpu.branchPred.lookups 28259323 # Number of BP lookups 280system.cpu.branchPred.condPredicted 23281308 # Number of conditional branches predicted 281system.cpu.branchPred.condIncorrect 837964 # Number of conditional branches incorrect 282system.cpu.branchPred.BTBLookups 11850778 # Number of BTB lookups 283system.cpu.branchPred.BTBHits 11785443 # Number of BTB hits 284system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 285system.cpu.branchPred.BTBHitPct 99.448686 # BTB Hit Percentage 286system.cpu.branchPred.usedRAS 75758 # Number of times the RAS was used to get a target. 287system.cpu.branchPred.RASInCorrect 89 # Number of incorrect RAS predictions. 288system.cpu_clk_domain.clock 500 # Clock period in ticks 289system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 298system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 299system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 300system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 301system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 302system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 303system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 304system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 305system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 306system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 307system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 308system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 309system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 310system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 311system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 312system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 313system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 314system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 315system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 316system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 317system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 318system.cpu.dtb.walker.walks 0 # Table walker walks requested 319system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.inst_hits 0 # ITB inst hits 327system.cpu.dtb.inst_misses 0 # ITB inst misses 328system.cpu.dtb.read_hits 0 # DTB read hits 329system.cpu.dtb.read_misses 0 # DTB read misses 330system.cpu.dtb.write_hits 0 # DTB write hits 331system.cpu.dtb.write_misses 0 # DTB write misses 332system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 333system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 334system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 335system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 336system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 337system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 338system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 339system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 340system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 341system.cpu.dtb.read_accesses 0 # DTB read accesses 342system.cpu.dtb.write_accesses 0 # DTB write accesses 343system.cpu.dtb.inst_accesses 0 # ITB inst accesses 344system.cpu.dtb.hits 0 # DTB hits 345system.cpu.dtb.misses 0 # DTB misses 346system.cpu.dtb.accesses 0 # DTB accesses 347system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 356system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 357system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 358system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 359system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 360system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 361system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 362system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 363system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 364system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 365system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 366system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 367system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 368system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 369system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 370system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 371system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 372system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 373system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 374system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 375system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 376system.cpu.itb.walker.walks 0 # Table walker walks requested 377system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 384system.cpu.itb.inst_hits 0 # ITB inst hits 385system.cpu.itb.inst_misses 0 # ITB inst misses 386system.cpu.itb.read_hits 0 # DTB read hits 387system.cpu.itb.read_misses 0 # DTB read misses 388system.cpu.itb.write_hits 0 # DTB write hits 389system.cpu.itb.write_misses 0 # DTB write misses 390system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 391system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 392system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 393system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 394system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 395system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 396system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 397system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 398system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 399system.cpu.itb.read_accesses 0 # DTB read accesses 400system.cpu.itb.write_accesses 0 # DTB write accesses 401system.cpu.itb.inst_accesses 0 # ITB inst accesses 402system.cpu.itb.hits 0 # DTB hits 403system.cpu.itb.misses 0 # DTB misses 404system.cpu.itb.accesses 0 # DTB accesses 405system.cpu.workload.num_syscalls 442 # Number of system calls 406system.cpu.numCycles 116405456 # number of cpu cycles simulated 407system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 408system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 409system.cpu.fetch.icacheStallCycles 749294 # Number of cycles fetch is stalled on an Icache miss 410system.cpu.fetch.Insts 134993998 # Number of instructions fetch has processed 411system.cpu.fetch.Branches 28259323 # Number of branches that fetch encountered 412system.cpu.fetch.predictedBranches 11861201 # Number of branches that fetch has predicted taken 413system.cpu.fetch.Cycles 114761716 # Number of cycles fetch has run and was not squashing or blocked 414system.cpu.fetch.SquashCycles 1679249 # Number of cycles fetch has spent squashing 415system.cpu.fetch.MiscStallCycles 1000 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 416system.cpu.fetch.IcacheWaitRetryStallCycles 840 # Number of stall cycles due to full MSHR 417system.cpu.fetch.CacheLines 32304088 # Number of cache lines fetched 418system.cpu.fetch.IcacheSquashes 579 # Number of outstanding Icache misses that were squashed 419system.cpu.fetch.rateDist::samples 116352474 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::mean 1.165469 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::stdev 1.319047 # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 423system.cpu.fetch.rateDist::0 58780581 50.52% 50.52% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::1 13944559 11.98% 62.50% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::2 9221403 7.93% 70.43% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::3 34405931 29.57% 100.00% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::total 116352474 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.branchRate 0.242766 # Number of branch fetches per cycle 432system.cpu.fetch.rate 1.159688 # Number of inst fetches per cycle 433system.cpu.decode.IdleCycles 8844184 # Number of cycles decode is idle 434system.cpu.decode.BlockedCycles 64087377 # Number of cycles decode is blocked 435system.cpu.decode.RunCycles 33032699 # Number of cycles decode is running 436system.cpu.decode.UnblockCycles 9560836 # Number of cycles decode is unblocking 437system.cpu.decode.SquashCycles 827378 # Number of cycles decode is squashing 438system.cpu.decode.BranchResolved 4101289 # Number of times decode resolved a branch 439system.cpu.decode.BranchMispred 12349 # Number of times decode detected a branch misprediction 440system.cpu.decode.DecodedInsts 114434840 # Number of instructions handled by decode 441system.cpu.decode.SquashedInsts 1995518 # Number of squashed instructions handled by decode 442system.cpu.rename.SquashCycles 827378 # Number of cycles rename is squashing 443system.cpu.rename.IdleCycles 15306554 # Number of cycles rename is idle 444system.cpu.rename.BlockCycles 49837632 # Number of cycles rename is blocking 445system.cpu.rename.serializeStallCycles 110028 # count of cycles rename stalled for serializing inst 446system.cpu.rename.RunCycles 35408205 # Number of cycles rename is running 447system.cpu.rename.UnblockCycles 14862677 # Number of cycles rename is unblocking 448system.cpu.rename.RenamedInsts 110902804 # Number of instructions processed by rename 449system.cpu.rename.SquashedInsts 1415247 # Number of squashed instructions processed by rename 450system.cpu.rename.ROBFullEvents 11133046 # Number of times rename has blocked due to ROB full 451system.cpu.rename.IQFullEvents 1143083 # Number of times rename has blocked due to IQ full 452system.cpu.rename.LQFullEvents 1515709 # Number of times rename has blocked due to LQ full 453system.cpu.rename.SQFullEvents 570063 # Number of times rename has blocked due to SQ full 454system.cpu.rename.RenamedOperands 129962368 # Number of destination operands rename has renamed 455system.cpu.rename.RenameLookups 483290389 # Number of register rename lookups that rename has made 456system.cpu.rename.int_rename_lookups 119478713 # Number of integer rename lookups 457system.cpu.rename.fp_rename_lookups 424 # Number of floating rename lookups 458system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed 459system.cpu.rename.UndoneMaps 22649449 # Number of HB maps that are undone due to squashing 460system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed 461system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed 462system.cpu.rename.skidInsts 21572068 # count of insts added to the skid buffer 463system.cpu.memDep0.insertedLoads 26814283 # Number of loads inserted to the mem dependence unit. 464system.cpu.memDep0.insertedStores 5349560 # Number of stores inserted to the mem dependence unit. 465system.cpu.memDep0.conflictingLoads 615072 # Number of conflicting loads. 466system.cpu.memDep0.conflictingStores 351208 # Number of conflicting stores. 467system.cpu.iq.iqInstsAdded 109694902 # Number of instructions added to the IQ (excludes non-spec) 468system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ 469system.cpu.iq.iqInstsIssued 101389982 # Number of instructions issued 470system.cpu.iq.iqSquashedInstsIssued 1073881 # Number of squashed instructions issued 471system.cpu.iq.iqSquashedInstsExamined 18465721 # Number of squashed instructions iterated over during squash; mainly for profiling 472system.cpu.iq.iqSquashedOperandsExamined 41703174 # Number of squashed operands that are examined and possibly removed from graph 473system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed 474system.cpu.iq.issued_per_cycle::samples 116352474 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::mean 0.871404 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::stdev 0.988585 # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::0 54656656 46.98% 46.98% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::1 31447896 27.03% 74.00% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::2 21997479 18.91% 92.91% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::3 7054961 6.06% 98.97% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::4 1195165 1.03% 100.00% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::total 116352474 # Number of insts issued each cycle 491system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 492system.cpu.iq.fu_full::IntAlu 9796147 48.71% 48.71% # attempts to use FU when none available 493system.cpu.iq.fu_full::IntMult 50 0.00% 48.71% # attempts to use FU when none available 494system.cpu.iq.fu_full::IntDiv 0 0.00% 48.71% # attempts to use FU when none available 495system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.71% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.71% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.71% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatMult 0 0.00% 48.71% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.71% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.71% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.71% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.71% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.71% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.71% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.71% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.71% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdMult 0 0.00% 48.71% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.71% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdShift 0 0.00% 48.71% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.71% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.71% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.71% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.71% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.71% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 48.71% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.71% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.71% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.71% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.71% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.71% # attempts to use FU when none available 521system.cpu.iq.fu_full::MemRead 9605529 47.77% 96.48% # attempts to use FU when none available 522system.cpu.iq.fu_full::MemWrite 708223 3.52% 100.00% # attempts to use FU when none available 523system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 524system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 525system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 526system.cpu.iq.FU_type_0::IntAlu 71985557 71.00% 71.00% # Type of FU issued 527system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued 528system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued 529system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued 530system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued 531system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued 532system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued 534system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 71.01% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued 555system.cpu.iq.FU_type_0::MemRead 24344215 24.01% 95.02% # Type of FU issued 556system.cpu.iq.FU_type_0::MemWrite 5049315 4.98% 100.00% # Type of FU issued 557system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 558system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 559system.cpu.iq.FU_type_0::total 101389982 # Type of FU issued 560system.cpu.iq.rate 0.871007 # Inst issue rate 561system.cpu.iq.fu_busy_cnt 20109961 # FU busy when requested 562system.cpu.iq.fu_busy_rate 0.198343 # FU busy rate (busy events/executed inst) 563system.cpu.iq.int_inst_queue_reads 340315821 # Number of integer instruction queue reads 564system.cpu.iq.int_inst_queue_writes 128169527 # Number of integer instruction queue writes 565system.cpu.iq.int_inst_queue_wakeup_accesses 99626078 # Number of integer instruction queue wakeup accesses 566system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads 567system.cpu.iq.fp_inst_queue_writes 609 # Number of floating instruction queue writes 568system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses 569system.cpu.iq.int_alu_accesses 121499704 # Number of integer alu accesses 570system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses 571system.cpu.iew.lsq.thread0.forwLoads 282708 # Number of loads that had data forwarded from stores 572system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 573system.cpu.iew.lsq.thread0.squashedLoads 4338372 # Number of loads squashed 574system.cpu.iew.lsq.thread0.ignoredResponses 1511 # Number of memory responses ignored because the instruction is squashed 575system.cpu.iew.lsq.thread0.memOrderViolation 1302 # Number of memory ordering violations 576system.cpu.iew.lsq.thread0.squashedStores 604716 # Number of stores squashed 577system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 578system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 579system.cpu.iew.lsq.thread0.rescheduledLoads 7561 # Number of loads that were rescheduled 580system.cpu.iew.lsq.thread0.cacheBlocked 130367 # Number of times an access to memory failed due to the cache being blocked 581system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 582system.cpu.iew.iewSquashCycles 827378 # Number of cycles IEW is squashing 583system.cpu.iew.iewBlockCycles 8117043 # Number of cycles IEW is blocking 584system.cpu.iew.iewUnblockCycles 661508 # Number of cycles IEW is unblocking 585system.cpu.iew.iewDispatchedInsts 109715814 # Number of instructions dispatched to IQ 586system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 587system.cpu.iew.iewDispLoadInsts 26814283 # Number of dispatched load instructions 588system.cpu.iew.iewDispStoreInsts 5349560 # Number of dispatched store instructions 589system.cpu.iew.iewDispNonSpecInsts 4358 # Number of dispatched non-speculative instructions 590system.cpu.iew.iewIQFullEvents 178487 # Number of times the IQ has become full, causing a stall 591system.cpu.iew.iewLSQFullEvents 319637 # Number of times the LSQ has become full, causing a stall 592system.cpu.iew.memOrderViolationEvents 1302 # Number of memory order violations 593system.cpu.iew.predictedTakenIncorrect 436579 # Number of branches that were predicted taken incorrectly 594system.cpu.iew.predictedNotTakenIncorrect 412967 # Number of branches that were predicted not taken incorrectly 595system.cpu.iew.branchMispredicts 849546 # Number of branch mispredicts detected at execute 596system.cpu.iew.iewExecutedInsts 100128293 # Number of executed instructions 597system.cpu.iew.iewExecLoadInsts 23807365 # Number of load instructions executed 598system.cpu.iew.iewExecSquashedInsts 1261689 # Number of squashed instructions skipped in execute 599system.cpu.iew.exec_swp 0 # number of swp insts executed 600system.cpu.iew.exec_nop 12666 # number of nop insts executed 601system.cpu.iew.exec_refs 28725194 # number of memory reference insts executed 602system.cpu.iew.exec_branches 20624883 # Number of branches executed 603system.cpu.iew.exec_stores 4917829 # Number of stores executed 604system.cpu.iew.exec_rate 0.860168 # Inst execution rate 605system.cpu.iew.wb_sent 99711182 # cumulative count of insts sent to commit 606system.cpu.iew.wb_count 99626193 # cumulative count of insts written-back 607system.cpu.iew.wb_producers 59706016 # num instructions producing a value 608system.cpu.iew.wb_consumers 95562461 # num instructions consuming a value 609system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 610system.cpu.iew.wb_rate 0.855855 # insts written-back per cycle 611system.cpu.iew.wb_fanout 0.624785 # average fanout of values written-back 612system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 613system.cpu.commit.commitSquashedInsts 17390136 # The number of squashed insts skipped by commit 614system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 615system.cpu.commit.branchMispredicts 825718 # The number of times a branch was mispredicted 616system.cpu.commit.committed_per_cycle::samples 113659456 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::mean 0.801109 # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::stdev 1.737097 # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::0 77211009 67.93% 67.93% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::1 18641585 16.40% 84.33% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::2 7152887 6.29% 90.63% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::3 3463018 3.05% 93.67% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::4 1652627 1.45% 95.13% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::5 524640 0.46% 95.59% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::6 723684 0.64% 96.23% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::7 178635 0.16% 96.38% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::8 4111371 3.62% 100.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::total 113659456 # Number of insts commited each cycle 633system.cpu.commit.committedInsts 90602407 # Number of instructions committed 634system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed 635system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 636system.cpu.commit.refs 27220755 # Number of memory references committed 637system.cpu.commit.loads 22475911 # Number of loads committed 638system.cpu.commit.membars 3888 # Number of memory barriers committed 639system.cpu.commit.branches 18732304 # Number of branches committed 640system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 641system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. 642system.cpu.commit.function_calls 56148 # Number of function calls committed. 643system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 644system.cpu.commit.op_class_0::IntAlu 63822386 70.09% 70.09% # Class of committed instruction 645system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 646system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 647system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 648system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 649system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 650system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 651system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 652system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 658system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 673system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 674system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 675system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 676system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 677system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction 678system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058203 # Number of seconds simulated 4sim_ticks 58202727500 # Number of ticks simulated 5final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 129726 # Simulator instruction rate (inst/s) 8host_op_rate 130372 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 83346935 # Simulator tick rate (ticks/s) 10host_mem_usage 443628 # Number of bytes of host memory used 11host_seconds 698.32 # Real time elapsed on the host 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91041029 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 44480 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 45376 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 930112 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1019968 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 44480 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 44480 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 22912 # Number of bytes written to this memory 23system.physmem.bytes_written::total 22912 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 695 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 709 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 14533 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 15937 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 358 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 358 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 764225 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 779620 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 15980557 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 17524402 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 764225 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 764225 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 393659 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 393659 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 393659 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 764225 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 779620 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 15980557 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17918061 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 15937 # Number of read requests accepted 44system.physmem.writeReqs 358 # Number of write requests accepted 45system.physmem.readBursts 15937 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 358 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 1010432 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue 49system.physmem.bytesWritten 21184 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 1019968 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 22912 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 1009 # Per bank write bursts 56system.physmem.perBankRdBursts::1 876 # Per bank write bursts 57system.physmem.perBankRdBursts::2 958 # Per bank write bursts 58system.physmem.perBankRdBursts::3 1024 # Per bank write bursts 59system.physmem.perBankRdBursts::4 1064 # Per bank write bursts 60system.physmem.perBankRdBursts::5 1132 # Per bank write bursts 61system.physmem.perBankRdBursts::6 1124 # Per bank write bursts 62system.physmem.perBankRdBursts::7 1103 # Per bank write bursts 63system.physmem.perBankRdBursts::8 1046 # Per bank write bursts 64system.physmem.perBankRdBursts::9 962 # Per bank write bursts 65system.physmem.perBankRdBursts::10 937 # Per bank write bursts 66system.physmem.perBankRdBursts::11 899 # Per bank write bursts 67system.physmem.perBankRdBursts::12 909 # Per bank write bursts 68system.physmem.perBankRdBursts::13 889 # Per bank write bursts 69system.physmem.perBankRdBursts::14 926 # Per bank write bursts 70system.physmem.perBankRdBursts::15 930 # Per bank write bursts 71system.physmem.perBankWrBursts::0 30 # Per bank write bursts 72system.physmem.perBankWrBursts::1 0 # Per bank write bursts 73system.physmem.perBankWrBursts::2 8 # Per bank write bursts 74system.physmem.perBankWrBursts::3 1 # Per bank write bursts 75system.physmem.perBankWrBursts::4 10 # Per bank write bursts 76system.physmem.perBankWrBursts::5 29 # Per bank write bursts 77system.physmem.perBankWrBursts::6 69 # Per bank write bursts 78system.physmem.perBankWrBursts::7 31 # Per bank write bursts 79system.physmem.perBankWrBursts::8 36 # Per bank write bursts 80system.physmem.perBankWrBursts::9 0 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7 # Per bank write bursts 82system.physmem.perBankWrBursts::11 0 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7 # Per bank write bursts 84system.physmem.perBankWrBursts::13 27 # Per bank write bursts 85system.physmem.perBankWrBursts::14 45 # Per bank write bursts 86system.physmem.perBankWrBursts::15 31 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 58202569500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 15937 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 358 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 10945 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 2405 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 349 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 310 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 297 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 305 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 289 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 304 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 62 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 19 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 19 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 19 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 19 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 19 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 19 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 19 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 20 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 18 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 18 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 1871 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 551.268840 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 315.885566 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 433.770323 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 552 29.50% 29.50% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 218 11.65% 41.15% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 92 4.92% 46.07% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 57 3.05% 49.12% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 63 3.37% 52.49% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 44 2.35% 54.84% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 55 2.94% 57.78% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 42 2.24% 60.02% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 748 39.98% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 1871 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 18 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 874.777778 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 39.760140 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 3541.219224 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 17 94.44% 94.44% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::14848-15359 1 5.56% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 18 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 18 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 18.388889 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 18.356746 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 1.195033 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 15 83.33% 83.33% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 2 11.11% 94.44% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::23 1 5.56% 100.00% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::total 18 # Writes before turning the bus around for reads 229system.physmem.totQLat 172783990 # Total ticks spent queuing 230system.physmem.totMemAccLat 468808990 # Total ticks spent from burst creation until serviced by the DRAM 231system.physmem.totBusLat 78940000 # Total ticks spent in databus transfers 232system.physmem.avgQLat 10944.01 # Average queueing delay per DRAM burst 233system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 234system.physmem.avgMemAccLat 29694.01 # Average memory access latency per DRAM burst 235system.physmem.avgRdBW 17.36 # Average DRAM read bandwidth in MiByte/s 236system.physmem.avgWrBW 0.36 # Average achieved write bandwidth in MiByte/s 237system.physmem.avgRdBWSys 17.52 # Average system read bandwidth in MiByte/s 238system.physmem.avgWrBWSys 0.39 # Average system write bandwidth in MiByte/s 239system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 240system.physmem.busUtil 0.14 # Data bus utilization in percentage 241system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads 242system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 243system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing 244system.physmem.avgWrQLen 16.15 # Average write queue length when enqueuing 245system.physmem.readRowHits 14154 # Number of row buffer hits during reads 246system.physmem.writeRowHits 93 # Number of row buffer hits during writes 247system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads 248system.physmem.writeRowHitRate 26.20 # Row buffer hit rate for writes 249system.physmem.avgGap 3571805.43 # Average gap between requests 250system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined 251system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) 252system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) 253system.physmem_0.readEnergy 64638600 # Energy for read commands per rank (pJ) 254system.physmem_0.writeEnergy 1153440 # Energy for write commands per rank (pJ) 255system.physmem_0.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) 256system.physmem_0.actBackEnergy 2451888630 # Energy for active background per rank (pJ) 257system.physmem_0.preBackEnergy 32770707750 # Energy for precharge background per rank (pJ) 258system.physmem_0.totalEnergy 39101711325 # Total energy per rank (pJ) 259system.physmem_0.averagePower 671.822097 # Core power per rank (mW) 260system.physmem_0.memoryStateTime::IDLE 54506616189 # Time in different power states 261system.physmem_0.memoryStateTime::REF 1943500000 # Time in different power states 262system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 263system.physmem_0.memoryStateTime::ACT 1752376311 # Time in different power states 264system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 265system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) 266system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) 267system.physmem_1.readEnergy 58484400 # Energy for read commands per rank (pJ) 268system.physmem_1.writeEnergy 991440 # Energy for write commands per rank (pJ) 269system.physmem_1.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) 270system.physmem_1.actBackEnergy 2431326735 # Energy for active background per rank (pJ) 271system.physmem_1.preBackEnergy 32788744500 # Energy for precharge background per rank (pJ) 272system.physmem_1.totalEnergy 39091058805 # Total energy per rank (pJ) 273system.physmem_1.averagePower 671.639072 # Core power per rank (mW) 274system.physmem_1.memoryStateTime::IDLE 54537138662 # Time in different power states 275system.physmem_1.memoryStateTime::REF 1943500000 # Time in different power states 276system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 277system.physmem_1.memoryStateTime::ACT 1721853838 # Time in different power states 278system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 279system.cpu.branchPred.lookups 28259323 # Number of BP lookups 280system.cpu.branchPred.condPredicted 23281308 # Number of conditional branches predicted 281system.cpu.branchPred.condIncorrect 837964 # Number of conditional branches incorrect 282system.cpu.branchPred.BTBLookups 11850778 # Number of BTB lookups 283system.cpu.branchPred.BTBHits 11785443 # Number of BTB hits 284system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 285system.cpu.branchPred.BTBHitPct 99.448686 # BTB Hit Percentage 286system.cpu.branchPred.usedRAS 75758 # Number of times the RAS was used to get a target. 287system.cpu.branchPred.RASInCorrect 89 # Number of incorrect RAS predictions. 288system.cpu_clk_domain.clock 500 # Clock period in ticks 289system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 298system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 299system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 300system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 301system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 302system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 303system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 304system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 305system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 306system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 307system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 308system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 309system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 310system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 311system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 312system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 313system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 314system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 315system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 316system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 317system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 318system.cpu.dtb.walker.walks 0 # Table walker walks requested 319system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.inst_hits 0 # ITB inst hits 327system.cpu.dtb.inst_misses 0 # ITB inst misses 328system.cpu.dtb.read_hits 0 # DTB read hits 329system.cpu.dtb.read_misses 0 # DTB read misses 330system.cpu.dtb.write_hits 0 # DTB write hits 331system.cpu.dtb.write_misses 0 # DTB write misses 332system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 333system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 334system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 335system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 336system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 337system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 338system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 339system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 340system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 341system.cpu.dtb.read_accesses 0 # DTB read accesses 342system.cpu.dtb.write_accesses 0 # DTB write accesses 343system.cpu.dtb.inst_accesses 0 # ITB inst accesses 344system.cpu.dtb.hits 0 # DTB hits 345system.cpu.dtb.misses 0 # DTB misses 346system.cpu.dtb.accesses 0 # DTB accesses 347system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 356system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 357system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 358system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 359system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 360system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 361system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 362system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 363system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 364system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 365system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 366system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 367system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 368system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 369system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 370system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 371system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 372system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 373system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 374system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 375system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 376system.cpu.itb.walker.walks 0 # Table walker walks requested 377system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 384system.cpu.itb.inst_hits 0 # ITB inst hits 385system.cpu.itb.inst_misses 0 # ITB inst misses 386system.cpu.itb.read_hits 0 # DTB read hits 387system.cpu.itb.read_misses 0 # DTB read misses 388system.cpu.itb.write_hits 0 # DTB write hits 389system.cpu.itb.write_misses 0 # DTB write misses 390system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 391system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 392system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 393system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 394system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 395system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 396system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 397system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 398system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 399system.cpu.itb.read_accesses 0 # DTB read accesses 400system.cpu.itb.write_accesses 0 # DTB write accesses 401system.cpu.itb.inst_accesses 0 # ITB inst accesses 402system.cpu.itb.hits 0 # DTB hits 403system.cpu.itb.misses 0 # DTB misses 404system.cpu.itb.accesses 0 # DTB accesses 405system.cpu.workload.num_syscalls 442 # Number of system calls 406system.cpu.numCycles 116405456 # number of cpu cycles simulated 407system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 408system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 409system.cpu.fetch.icacheStallCycles 749294 # Number of cycles fetch is stalled on an Icache miss 410system.cpu.fetch.Insts 134993998 # Number of instructions fetch has processed 411system.cpu.fetch.Branches 28259323 # Number of branches that fetch encountered 412system.cpu.fetch.predictedBranches 11861201 # Number of branches that fetch has predicted taken 413system.cpu.fetch.Cycles 114761716 # Number of cycles fetch has run and was not squashing or blocked 414system.cpu.fetch.SquashCycles 1679249 # Number of cycles fetch has spent squashing 415system.cpu.fetch.MiscStallCycles 1000 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 416system.cpu.fetch.IcacheWaitRetryStallCycles 840 # Number of stall cycles due to full MSHR 417system.cpu.fetch.CacheLines 32304088 # Number of cache lines fetched 418system.cpu.fetch.IcacheSquashes 579 # Number of outstanding Icache misses that were squashed 419system.cpu.fetch.rateDist::samples 116352474 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::mean 1.165469 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::stdev 1.319047 # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 423system.cpu.fetch.rateDist::0 58780581 50.52% 50.52% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::1 13944559 11.98% 62.50% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::2 9221403 7.93% 70.43% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::3 34405931 29.57% 100.00% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::total 116352474 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.branchRate 0.242766 # Number of branch fetches per cycle 432system.cpu.fetch.rate 1.159688 # Number of inst fetches per cycle 433system.cpu.decode.IdleCycles 8844184 # Number of cycles decode is idle 434system.cpu.decode.BlockedCycles 64087377 # Number of cycles decode is blocked 435system.cpu.decode.RunCycles 33032699 # Number of cycles decode is running 436system.cpu.decode.UnblockCycles 9560836 # Number of cycles decode is unblocking 437system.cpu.decode.SquashCycles 827378 # Number of cycles decode is squashing 438system.cpu.decode.BranchResolved 4101289 # Number of times decode resolved a branch 439system.cpu.decode.BranchMispred 12349 # Number of times decode detected a branch misprediction 440system.cpu.decode.DecodedInsts 114434840 # Number of instructions handled by decode 441system.cpu.decode.SquashedInsts 1995518 # Number of squashed instructions handled by decode 442system.cpu.rename.SquashCycles 827378 # Number of cycles rename is squashing 443system.cpu.rename.IdleCycles 15306554 # Number of cycles rename is idle 444system.cpu.rename.BlockCycles 49837632 # Number of cycles rename is blocking 445system.cpu.rename.serializeStallCycles 110028 # count of cycles rename stalled for serializing inst 446system.cpu.rename.RunCycles 35408205 # Number of cycles rename is running 447system.cpu.rename.UnblockCycles 14862677 # Number of cycles rename is unblocking 448system.cpu.rename.RenamedInsts 110902804 # Number of instructions processed by rename 449system.cpu.rename.SquashedInsts 1415247 # Number of squashed instructions processed by rename 450system.cpu.rename.ROBFullEvents 11133046 # Number of times rename has blocked due to ROB full 451system.cpu.rename.IQFullEvents 1143083 # Number of times rename has blocked due to IQ full 452system.cpu.rename.LQFullEvents 1515709 # Number of times rename has blocked due to LQ full 453system.cpu.rename.SQFullEvents 570063 # Number of times rename has blocked due to SQ full 454system.cpu.rename.RenamedOperands 129962368 # Number of destination operands rename has renamed 455system.cpu.rename.RenameLookups 483290389 # Number of register rename lookups that rename has made 456system.cpu.rename.int_rename_lookups 119478713 # Number of integer rename lookups 457system.cpu.rename.fp_rename_lookups 424 # Number of floating rename lookups 458system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed 459system.cpu.rename.UndoneMaps 22649449 # Number of HB maps that are undone due to squashing 460system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed 461system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed 462system.cpu.rename.skidInsts 21572068 # count of insts added to the skid buffer 463system.cpu.memDep0.insertedLoads 26814283 # Number of loads inserted to the mem dependence unit. 464system.cpu.memDep0.insertedStores 5349560 # Number of stores inserted to the mem dependence unit. 465system.cpu.memDep0.conflictingLoads 615072 # Number of conflicting loads. 466system.cpu.memDep0.conflictingStores 351208 # Number of conflicting stores. 467system.cpu.iq.iqInstsAdded 109694902 # Number of instructions added to the IQ (excludes non-spec) 468system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ 469system.cpu.iq.iqInstsIssued 101389982 # Number of instructions issued 470system.cpu.iq.iqSquashedInstsIssued 1073881 # Number of squashed instructions issued 471system.cpu.iq.iqSquashedInstsExamined 18465721 # Number of squashed instructions iterated over during squash; mainly for profiling 472system.cpu.iq.iqSquashedOperandsExamined 41703174 # Number of squashed operands that are examined and possibly removed from graph 473system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed 474system.cpu.iq.issued_per_cycle::samples 116352474 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::mean 0.871404 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::stdev 0.988585 # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::0 54656656 46.98% 46.98% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::1 31447896 27.03% 74.00% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::2 21997479 18.91% 92.91% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::3 7054961 6.06% 98.97% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::4 1195165 1.03% 100.00% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::total 116352474 # Number of insts issued each cycle 491system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 492system.cpu.iq.fu_full::IntAlu 9796147 48.71% 48.71% # attempts to use FU when none available 493system.cpu.iq.fu_full::IntMult 50 0.00% 48.71% # attempts to use FU when none available 494system.cpu.iq.fu_full::IntDiv 0 0.00% 48.71% # attempts to use FU when none available 495system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.71% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.71% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.71% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatMult 0 0.00% 48.71% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.71% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.71% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.71% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.71% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.71% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.71% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.71% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.71% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdMult 0 0.00% 48.71% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.71% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdShift 0 0.00% 48.71% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.71% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.71% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.71% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.71% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.71% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 48.71% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.71% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.71% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.71% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.71% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.71% # attempts to use FU when none available 521system.cpu.iq.fu_full::MemRead 9605529 47.77% 96.48% # attempts to use FU when none available 522system.cpu.iq.fu_full::MemWrite 708223 3.52% 100.00% # attempts to use FU when none available 523system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 524system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 525system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 526system.cpu.iq.FU_type_0::IntAlu 71985557 71.00% 71.00% # Type of FU issued 527system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued 528system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued 529system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued 530system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued 531system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued 532system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued 534system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 71.01% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued 555system.cpu.iq.FU_type_0::MemRead 24344215 24.01% 95.02% # Type of FU issued 556system.cpu.iq.FU_type_0::MemWrite 5049315 4.98% 100.00% # Type of FU issued 557system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 558system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 559system.cpu.iq.FU_type_0::total 101389982 # Type of FU issued 560system.cpu.iq.rate 0.871007 # Inst issue rate 561system.cpu.iq.fu_busy_cnt 20109961 # FU busy when requested 562system.cpu.iq.fu_busy_rate 0.198343 # FU busy rate (busy events/executed inst) 563system.cpu.iq.int_inst_queue_reads 340315821 # Number of integer instruction queue reads 564system.cpu.iq.int_inst_queue_writes 128169527 # Number of integer instruction queue writes 565system.cpu.iq.int_inst_queue_wakeup_accesses 99626078 # Number of integer instruction queue wakeup accesses 566system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads 567system.cpu.iq.fp_inst_queue_writes 609 # Number of floating instruction queue writes 568system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses 569system.cpu.iq.int_alu_accesses 121499704 # Number of integer alu accesses 570system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses 571system.cpu.iew.lsq.thread0.forwLoads 282708 # Number of loads that had data forwarded from stores 572system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 573system.cpu.iew.lsq.thread0.squashedLoads 4338372 # Number of loads squashed 574system.cpu.iew.lsq.thread0.ignoredResponses 1511 # Number of memory responses ignored because the instruction is squashed 575system.cpu.iew.lsq.thread0.memOrderViolation 1302 # Number of memory ordering violations 576system.cpu.iew.lsq.thread0.squashedStores 604716 # Number of stores squashed 577system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 578system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 579system.cpu.iew.lsq.thread0.rescheduledLoads 7561 # Number of loads that were rescheduled 580system.cpu.iew.lsq.thread0.cacheBlocked 130367 # Number of times an access to memory failed due to the cache being blocked 581system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 582system.cpu.iew.iewSquashCycles 827378 # Number of cycles IEW is squashing 583system.cpu.iew.iewBlockCycles 8117043 # Number of cycles IEW is blocking 584system.cpu.iew.iewUnblockCycles 661508 # Number of cycles IEW is unblocking 585system.cpu.iew.iewDispatchedInsts 109715814 # Number of instructions dispatched to IQ 586system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 587system.cpu.iew.iewDispLoadInsts 26814283 # Number of dispatched load instructions 588system.cpu.iew.iewDispStoreInsts 5349560 # Number of dispatched store instructions 589system.cpu.iew.iewDispNonSpecInsts 4358 # Number of dispatched non-speculative instructions 590system.cpu.iew.iewIQFullEvents 178487 # Number of times the IQ has become full, causing a stall 591system.cpu.iew.iewLSQFullEvents 319637 # Number of times the LSQ has become full, causing a stall 592system.cpu.iew.memOrderViolationEvents 1302 # Number of memory order violations 593system.cpu.iew.predictedTakenIncorrect 436579 # Number of branches that were predicted taken incorrectly 594system.cpu.iew.predictedNotTakenIncorrect 412967 # Number of branches that were predicted not taken incorrectly 595system.cpu.iew.branchMispredicts 849546 # Number of branch mispredicts detected at execute 596system.cpu.iew.iewExecutedInsts 100128293 # Number of executed instructions 597system.cpu.iew.iewExecLoadInsts 23807365 # Number of load instructions executed 598system.cpu.iew.iewExecSquashedInsts 1261689 # Number of squashed instructions skipped in execute 599system.cpu.iew.exec_swp 0 # number of swp insts executed 600system.cpu.iew.exec_nop 12666 # number of nop insts executed 601system.cpu.iew.exec_refs 28725194 # number of memory reference insts executed 602system.cpu.iew.exec_branches 20624883 # Number of branches executed 603system.cpu.iew.exec_stores 4917829 # Number of stores executed 604system.cpu.iew.exec_rate 0.860168 # Inst execution rate 605system.cpu.iew.wb_sent 99711182 # cumulative count of insts sent to commit 606system.cpu.iew.wb_count 99626193 # cumulative count of insts written-back 607system.cpu.iew.wb_producers 59706016 # num instructions producing a value 608system.cpu.iew.wb_consumers 95562461 # num instructions consuming a value 609system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 610system.cpu.iew.wb_rate 0.855855 # insts written-back per cycle 611system.cpu.iew.wb_fanout 0.624785 # average fanout of values written-back 612system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 613system.cpu.commit.commitSquashedInsts 17390136 # The number of squashed insts skipped by commit 614system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 615system.cpu.commit.branchMispredicts 825718 # The number of times a branch was mispredicted 616system.cpu.commit.committed_per_cycle::samples 113659456 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::mean 0.801109 # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::stdev 1.737097 # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::0 77211009 67.93% 67.93% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::1 18641585 16.40% 84.33% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::2 7152887 6.29% 90.63% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::3 3463018 3.05% 93.67% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::4 1652627 1.45% 95.13% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::5 524640 0.46% 95.59% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::6 723684 0.64% 96.23% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::7 178635 0.16% 96.38% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::8 4111371 3.62% 100.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::total 113659456 # Number of insts commited each cycle 633system.cpu.commit.committedInsts 90602407 # Number of instructions committed 634system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed 635system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 636system.cpu.commit.refs 27220755 # Number of memory references committed 637system.cpu.commit.loads 22475911 # Number of loads committed 638system.cpu.commit.membars 3888 # Number of memory barriers committed 639system.cpu.commit.branches 18732304 # Number of branches committed 640system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 641system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. 642system.cpu.commit.function_calls 56148 # Number of function calls committed. 643system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 644system.cpu.commit.op_class_0::IntAlu 63822386 70.09% 70.09% # Class of committed instruction 645system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 646system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 647system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 648system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 649system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 650system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 651system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 652system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 658system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 673system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 674system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 675system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 676system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 677system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction 678system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached |
| 679system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 680system.cpu.rob.rob_reads 217986125 # The number of ROB reads 681system.cpu.rob.rob_writes 219581178 # The number of ROB writes 682system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself 683system.cpu.idleCycles 52982 # Total number of cycles that the CPU has spent unscheduled due to idling 684system.cpu.committedInsts 90589798 # Number of Instructions Simulated 685system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated 686system.cpu.cpi 1.284973 # CPI: Cycles Per Instruction 687system.cpu.cpi_total 1.284973 # CPI: Total CPI of All Threads 688system.cpu.ipc 0.778226 # IPC: Instructions Per Cycle 689system.cpu.ipc_total 0.778226 # IPC: Total IPC of All Threads 690system.cpu.int_regfile_reads 108112973 # number of integer regfile reads 691system.cpu.int_regfile_writes 58701982 # number of integer regfile writes 692system.cpu.fp_regfile_reads 58 # number of floating regfile reads 693system.cpu.fp_regfile_writes 95 # number of floating regfile writes 694system.cpu.cc_regfile_reads 369069288 # number of cc regfile reads 695system.cpu.cc_regfile_writes 58692619 # number of cc regfile writes 696system.cpu.misc_regfile_reads 28415446 # number of misc regfile reads 697system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 698system.cpu.dcache.tags.replacements 5469543 # number of replacements 699system.cpu.dcache.tags.tagsinuse 511.788616 # Cycle average of tags in use 700system.cpu.dcache.tags.total_refs 18297454 # Total number of references to valid blocks. 701system.cpu.dcache.tags.sampled_refs 5470055 # Sample count of references to valid blocks. 702system.cpu.dcache.tags.avg_refs 3.345022 # Average number of references to valid blocks. 703system.cpu.dcache.tags.warmup_cycle 35157000 # Cycle when the warmup percentage was hit. 704system.cpu.dcache.tags.occ_blocks::cpu.data 511.788616 # Average occupied blocks per requestor 705system.cpu.dcache.tags.occ_percent::cpu.data 0.999587 # Average percentage of cache occupancy 706system.cpu.dcache.tags.occ_percent::total 0.999587 # Average percentage of cache occupancy 707system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 708system.cpu.dcache.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id 709system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 710system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 711system.cpu.dcache.tags.tag_accesses 61924995 # Number of tag accesses 712system.cpu.dcache.tags.data_accesses 61924995 # Number of data accesses 713system.cpu.dcache.ReadReq_hits::cpu.data 13934183 # number of ReadReq hits 714system.cpu.dcache.ReadReq_hits::total 13934183 # number of ReadReq hits 715system.cpu.dcache.WriteReq_hits::cpu.data 4354974 # number of WriteReq hits 716system.cpu.dcache.WriteReq_hits::total 4354974 # number of WriteReq hits 717system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 718system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 719system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits 720system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits 721system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 722system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 723system.cpu.dcache.demand_hits::cpu.data 18289157 # number of demand (read+write) hits 724system.cpu.dcache.demand_hits::total 18289157 # number of demand (read+write) hits 725system.cpu.dcache.overall_hits::cpu.data 18289679 # number of overall hits 726system.cpu.dcache.overall_hits::total 18289679 # number of overall hits 727system.cpu.dcache.ReadReq_misses::cpu.data 9550003 # number of ReadReq misses 728system.cpu.dcache.ReadReq_misses::total 9550003 # number of ReadReq misses 729system.cpu.dcache.WriteReq_misses::cpu.data 380007 # number of WriteReq misses 730system.cpu.dcache.WriteReq_misses::total 380007 # number of WriteReq misses 731system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses 732system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses 733system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses 734system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses 735system.cpu.dcache.demand_misses::cpu.data 9930010 # number of demand (read+write) misses 736system.cpu.dcache.demand_misses::total 9930010 # number of demand (read+write) misses 737system.cpu.dcache.overall_misses::cpu.data 9930017 # number of overall misses 738system.cpu.dcache.overall_misses::total 9930017 # number of overall misses 739system.cpu.dcache.ReadReq_miss_latency::cpu.data 88443276736 # number of ReadReq miss cycles 740system.cpu.dcache.ReadReq_miss_latency::total 88443276736 # number of ReadReq miss cycles 741system.cpu.dcache.WriteReq_miss_latency::cpu.data 3962066244 # number of WriteReq miss cycles 742system.cpu.dcache.WriteReq_miss_latency::total 3962066244 # number of WriteReq miss cycles 743system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297000 # number of LoadLockedReq miss cycles 744system.cpu.dcache.LoadLockedReq_miss_latency::total 297000 # number of LoadLockedReq miss cycles 745system.cpu.dcache.demand_miss_latency::cpu.data 92405342980 # number of demand (read+write) miss cycles 746system.cpu.dcache.demand_miss_latency::total 92405342980 # number of demand (read+write) miss cycles 747system.cpu.dcache.overall_miss_latency::cpu.data 92405342980 # number of overall miss cycles 748system.cpu.dcache.overall_miss_latency::total 92405342980 # number of overall miss cycles 749system.cpu.dcache.ReadReq_accesses::cpu.data 23484186 # number of ReadReq accesses(hits+misses) 750system.cpu.dcache.ReadReq_accesses::total 23484186 # number of ReadReq accesses(hits+misses) 751system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 752system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 753system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) 754system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) 755system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 756system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 757system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 758system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 759system.cpu.dcache.demand_accesses::cpu.data 28219167 # number of demand (read+write) accesses 760system.cpu.dcache.demand_accesses::total 28219167 # number of demand (read+write) accesses 761system.cpu.dcache.overall_accesses::cpu.data 28219696 # number of overall (read+write) accesses 762system.cpu.dcache.overall_accesses::total 28219696 # number of overall (read+write) accesses 763system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.406657 # miss rate for ReadReq accesses 764system.cpu.dcache.ReadReq_miss_rate::total 0.406657 # miss rate for ReadReq accesses 765system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080255 # miss rate for WriteReq accesses 766system.cpu.dcache.WriteReq_miss_rate::total 0.080255 # miss rate for WriteReq accesses 767system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses 768system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses 769system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses 770system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses 771system.cpu.dcache.demand_miss_rate::cpu.data 0.351889 # miss rate for demand accesses 772system.cpu.dcache.demand_miss_rate::total 0.351889 # miss rate for demand accesses 773system.cpu.dcache.overall_miss_rate::cpu.data 0.351882 # miss rate for overall accesses 774system.cpu.dcache.overall_miss_rate::total 0.351882 # miss rate for overall accesses 775system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9261.073189 # average ReadReq miss latency 776system.cpu.dcache.ReadReq_avg_miss_latency::total 9261.073189 # average ReadReq miss latency 777system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10426.298052 # average WriteReq miss latency 778system.cpu.dcache.WriteReq_avg_miss_latency::total 10426.298052 # average WriteReq miss latency 779system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19800 # average LoadLockedReq miss latency 780system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19800 # average LoadLockedReq miss latency 781system.cpu.dcache.demand_avg_miss_latency::cpu.data 9305.664645 # average overall miss latency 782system.cpu.dcache.demand_avg_miss_latency::total 9305.664645 # average overall miss latency 783system.cpu.dcache.overall_avg_miss_latency::cpu.data 9305.658085 # average overall miss latency 784system.cpu.dcache.overall_avg_miss_latency::total 9305.658085 # average overall miss latency 785system.cpu.dcache.blocked_cycles::no_mshrs 306020 # number of cycles access was blocked 786system.cpu.dcache.blocked_cycles::no_targets 36082 # number of cycles access was blocked 787system.cpu.dcache.blocked::no_mshrs 120709 # number of cycles access was blocked 788system.cpu.dcache.blocked::no_targets 2278 # number of cycles access was blocked 789system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.535188 # average number of cycles each access was blocked 790system.cpu.dcache.avg_blocked_cycles::no_targets 15.839333 # average number of cycles each access was blocked 791system.cpu.dcache.fast_writes 0 # number of fast writes performed 792system.cpu.dcache.cache_copies 0 # number of cache copies performed 793system.cpu.dcache.writebacks::writebacks 5439051 # number of writebacks 794system.cpu.dcache.writebacks::total 5439051 # number of writebacks 795system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4313021 # number of ReadReq MSHR hits 796system.cpu.dcache.ReadReq_mshr_hits::total 4313021 # number of ReadReq MSHR hits 797system.cpu.dcache.WriteReq_mshr_hits::cpu.data 146936 # number of WriteReq MSHR hits 798system.cpu.dcache.WriteReq_mshr_hits::total 146936 # number of WriteReq MSHR hits 799system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits 800system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits 801system.cpu.dcache.demand_mshr_hits::cpu.data 4459957 # number of demand (read+write) MSHR hits 802system.cpu.dcache.demand_mshr_hits::total 4459957 # number of demand (read+write) MSHR hits 803system.cpu.dcache.overall_mshr_hits::cpu.data 4459957 # number of overall MSHR hits 804system.cpu.dcache.overall_mshr_hits::total 4459957 # number of overall MSHR hits 805system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5236982 # number of ReadReq MSHR misses 806system.cpu.dcache.ReadReq_mshr_misses::total 5236982 # number of ReadReq MSHR misses 807system.cpu.dcache.WriteReq_mshr_misses::cpu.data 233071 # number of WriteReq MSHR misses 808system.cpu.dcache.WriteReq_mshr_misses::total 233071 # number of WriteReq MSHR misses 809system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses 810system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses 811system.cpu.dcache.demand_mshr_misses::cpu.data 5470053 # number of demand (read+write) MSHR misses 812system.cpu.dcache.demand_mshr_misses::total 5470053 # number of demand (read+write) MSHR misses 813system.cpu.dcache.overall_mshr_misses::cpu.data 5470057 # number of overall MSHR misses 814system.cpu.dcache.overall_mshr_misses::total 5470057 # number of overall MSHR misses 815system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40519086258 # number of ReadReq MSHR miss cycles 816system.cpu.dcache.ReadReq_mshr_miss_latency::total 40519086258 # number of ReadReq MSHR miss cycles 817system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2295163471 # number of WriteReq MSHR miss cycles 818system.cpu.dcache.WriteReq_mshr_miss_latency::total 2295163471 # number of WriteReq MSHR miss cycles 819system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 213000 # number of SoftPFReq MSHR miss cycles 820system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 213000 # number of SoftPFReq MSHR miss cycles 821system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42814249729 # number of demand (read+write) MSHR miss cycles 822system.cpu.dcache.demand_mshr_miss_latency::total 42814249729 # number of demand (read+write) MSHR miss cycles 823system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42814462729 # number of overall MSHR miss cycles 824system.cpu.dcache.overall_mshr_miss_latency::total 42814462729 # number of overall MSHR miss cycles 825system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223000 # mshr miss rate for ReadReq accesses 826system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223000 # mshr miss rate for ReadReq accesses 827system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049223 # mshr miss rate for WriteReq accesses 828system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049223 # mshr miss rate for WriteReq accesses 829system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses 830system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses 831system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193842 # mshr miss rate for demand accesses 832system.cpu.dcache.demand_mshr_miss_rate::total 0.193842 # mshr miss rate for demand accesses 833system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193838 # mshr miss rate for overall accesses 834system.cpu.dcache.overall_mshr_miss_rate::total 0.193838 # mshr miss rate for overall accesses 835system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7737.106268 # average ReadReq mshr miss latency 836system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7737.106268 # average ReadReq mshr miss latency 837system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9847.486264 # average WriteReq mshr miss latency 838system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9847.486264 # average WriteReq mshr miss latency 839system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53250 # average SoftPFReq mshr miss latency 840system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53250 # average SoftPFReq mshr miss latency 841system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7827.026489 # average overall mshr miss latency 842system.cpu.dcache.demand_avg_mshr_miss_latency::total 7827.026489 # average overall mshr miss latency 843system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7827.059705 # average overall mshr miss latency 844system.cpu.dcache.overall_avg_mshr_miss_latency::total 7827.059705 # average overall mshr miss latency 845system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 846system.cpu.icache.tags.replacements 451 # number of replacements 847system.cpu.icache.tags.tagsinuse 428.263511 # Cycle average of tags in use 848system.cpu.icache.tags.total_refs 32302915 # Total number of references to valid blocks. 849system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. 850system.cpu.icache.tags.avg_refs 35497.708791 # Average number of references to valid blocks. 851system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 852system.cpu.icache.tags.occ_blocks::cpu.inst 428.263511 # Average occupied blocks per requestor 853system.cpu.icache.tags.occ_percent::cpu.inst 0.836452 # Average percentage of cache occupancy 854system.cpu.icache.tags.occ_percent::total 0.836452 # Average percentage of cache occupancy 855system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id 856system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 857system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 858system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id 859system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id 860system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id 861system.cpu.icache.tags.tag_accesses 64609056 # Number of tag accesses 862system.cpu.icache.tags.data_accesses 64609056 # Number of data accesses 863system.cpu.icache.ReadReq_hits::cpu.inst 32302915 # number of ReadReq hits 864system.cpu.icache.ReadReq_hits::total 32302915 # number of ReadReq hits 865system.cpu.icache.demand_hits::cpu.inst 32302915 # number of demand (read+write) hits 866system.cpu.icache.demand_hits::total 32302915 # number of demand (read+write) hits 867system.cpu.icache.overall_hits::cpu.inst 32302915 # number of overall hits 868system.cpu.icache.overall_hits::total 32302915 # number of overall hits 869system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses 870system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses 871system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses 872system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses 873system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses 874system.cpu.icache.overall_misses::total 1158 # number of overall misses 875system.cpu.icache.ReadReq_miss_latency::cpu.inst 62669987 # number of ReadReq miss cycles 876system.cpu.icache.ReadReq_miss_latency::total 62669987 # number of ReadReq miss cycles 877system.cpu.icache.demand_miss_latency::cpu.inst 62669987 # number of demand (read+write) miss cycles 878system.cpu.icache.demand_miss_latency::total 62669987 # number of demand (read+write) miss cycles 879system.cpu.icache.overall_miss_latency::cpu.inst 62669987 # number of overall miss cycles 880system.cpu.icache.overall_miss_latency::total 62669987 # number of overall miss cycles 881system.cpu.icache.ReadReq_accesses::cpu.inst 32304073 # number of ReadReq accesses(hits+misses) 882system.cpu.icache.ReadReq_accesses::total 32304073 # number of ReadReq accesses(hits+misses) 883system.cpu.icache.demand_accesses::cpu.inst 32304073 # number of demand (read+write) accesses 884system.cpu.icache.demand_accesses::total 32304073 # number of demand (read+write) accesses 885system.cpu.icache.overall_accesses::cpu.inst 32304073 # number of overall (read+write) accesses 886system.cpu.icache.overall_accesses::total 32304073 # number of overall (read+write) accesses 887system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses 888system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses 889system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses 890system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses 891system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses 892system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses 893system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54119.159758 # average ReadReq miss latency 894system.cpu.icache.ReadReq_avg_miss_latency::total 54119.159758 # average ReadReq miss latency 895system.cpu.icache.demand_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency 896system.cpu.icache.demand_avg_miss_latency::total 54119.159758 # average overall miss latency 897system.cpu.icache.overall_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency 898system.cpu.icache.overall_avg_miss_latency::total 54119.159758 # average overall miss latency 899system.cpu.icache.blocked_cycles::no_mshrs 19414 # number of cycles access was blocked 900system.cpu.icache.blocked_cycles::no_targets 134 # number of cycles access was blocked 901system.cpu.icache.blocked::no_mshrs 238 # number of cycles access was blocked 902system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 903system.cpu.icache.avg_blocked_cycles::no_mshrs 81.571429 # average number of cycles each access was blocked 904system.cpu.icache.avg_blocked_cycles::no_targets 26.800000 # average number of cycles each access was blocked 905system.cpu.icache.fast_writes 0 # number of fast writes performed 906system.cpu.icache.cache_copies 0 # number of cache copies performed 907system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits 908system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits 909system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits 910system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 911system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits 912system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits 913system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses 914system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses 915system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses 916system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses 917system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses 918system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses 919system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50368733 # number of ReadReq MSHR miss cycles 920system.cpu.icache.ReadReq_mshr_miss_latency::total 50368733 # number of ReadReq MSHR miss cycles 921system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50368733 # number of demand (read+write) MSHR miss cycles 922system.cpu.icache.demand_mshr_miss_latency::total 50368733 # number of demand (read+write) MSHR miss cycles 923system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50368733 # number of overall MSHR miss cycles 924system.cpu.icache.overall_mshr_miss_latency::total 50368733 # number of overall MSHR miss cycles 925system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 926system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 927system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 928system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 929system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 930system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 931system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55350.256044 # average ReadReq mshr miss latency 932system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55350.256044 # average ReadReq mshr miss latency 933system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55350.256044 # average overall mshr miss latency 934system.cpu.icache.demand_avg_mshr_miss_latency::total 55350.256044 # average overall mshr miss latency 935system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55350.256044 # average overall mshr miss latency 936system.cpu.icache.overall_avg_mshr_miss_latency::total 55350.256044 # average overall mshr miss latency 937system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 938system.cpu.l2cache.prefetcher.num_hwpf_issued 4495585 # number of hwpf issued 939system.cpu.l2cache.prefetcher.pfIdentified 5292074 # number of prefetch candidates identified 940system.cpu.l2cache.prefetcher.pfBufferHit 687825 # number of redundant prefetches already in prefetch queue 941system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 942system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 943system.cpu.l2cache.prefetcher.pfSpanPage 14072766 # number of prefetches not generated due to page crossing 944system.cpu.l2cache.tags.replacements 493 # number of replacements 945system.cpu.l2cache.tags.tagsinuse 12074.856330 # Cycle average of tags in use 946system.cpu.l2cache.tags.total_refs 10653372 # Total number of references to valid blocks. 947system.cpu.l2cache.tags.sampled_refs 15934 # Sample count of references to valid blocks. 948system.cpu.l2cache.tags.avg_refs 668.593699 # Average number of references to valid blocks. 949system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 950system.cpu.l2cache.tags.occ_blocks::writebacks 11119.543661 # Average occupied blocks per requestor 951system.cpu.l2cache.tags.occ_blocks::cpu.inst 571.365929 # Average occupied blocks per requestor 952system.cpu.l2cache.tags.occ_blocks::cpu.data 202.646634 # Average occupied blocks per requestor 953system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 181.300106 # Average occupied blocks per requestor 954system.cpu.l2cache.tags.occ_percent::writebacks 0.678683 # Average percentage of cache occupancy 955system.cpu.l2cache.tags.occ_percent::cpu.inst 0.034873 # Average percentage of cache occupancy 956system.cpu.l2cache.tags.occ_percent::cpu.data 0.012369 # Average percentage of cache occupancy 957system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.011066 # Average percentage of cache occupancy 958system.cpu.l2cache.tags.occ_percent::total 0.736991 # Average percentage of cache occupancy 959system.cpu.l2cache.tags.occ_task_id_blocks::1022 216 # Occupied blocks per task id 960system.cpu.l2cache.tags.occ_task_id_blocks::1024 15225 # Occupied blocks per task id 961system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id 962system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 963system.cpu.l2cache.tags.age_task_id_blocks_1022::2 13 # Occupied blocks per task id 964system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id 965system.cpu.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id 966system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 967system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 968system.cpu.l2cache.tags.age_task_id_blocks_1024::2 974 # Occupied blocks per task id 969system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1048 # Occupied blocks per task id 970system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13130 # Occupied blocks per task id 971system.cpu.l2cache.tags.occ_task_id_percent::1022 0.013184 # Percentage of cache occupancy per task id 972system.cpu.l2cache.tags.occ_task_id_percent::1024 0.929260 # Percentage of cache occupancy per task id 973system.cpu.l2cache.tags.tag_accesses 174809424 # Number of tag accesses 974system.cpu.l2cache.tags.data_accesses 174809424 # Number of data accesses 975system.cpu.l2cache.ReadReq_hits::cpu.inst 213 # number of ReadReq hits 976system.cpu.l2cache.ReadReq_hits::cpu.data 5236439 # number of ReadReq hits 977system.cpu.l2cache.ReadReq_hits::total 5236652 # number of ReadReq hits 978system.cpu.l2cache.Writeback_hits::writebacks 5439051 # number of Writeback hits 979system.cpu.l2cache.Writeback_hits::total 5439051 # number of Writeback hits 980system.cpu.l2cache.ReadExReq_hits::cpu.data 232688 # number of ReadExReq hits 981system.cpu.l2cache.ReadExReq_hits::total 232688 # number of ReadExReq hits 982system.cpu.l2cache.demand_hits::cpu.inst 213 # number of demand (read+write) hits 983system.cpu.l2cache.demand_hits::cpu.data 5469127 # number of demand (read+write) hits 984system.cpu.l2cache.demand_hits::total 5469340 # number of demand (read+write) hits 985system.cpu.l2cache.overall_hits::cpu.inst 213 # number of overall hits 986system.cpu.l2cache.overall_hits::cpu.data 5469127 # number of overall hits 987system.cpu.l2cache.overall_hits::total 5469340 # number of overall hits 988system.cpu.l2cache.ReadReq_misses::cpu.inst 697 # number of ReadReq misses 989system.cpu.l2cache.ReadReq_misses::cpu.data 416 # number of ReadReq misses 990system.cpu.l2cache.ReadReq_misses::total 1113 # number of ReadReq misses 991system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 992system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 993system.cpu.l2cache.ReadExReq_misses::cpu.data 512 # number of ReadExReq misses 994system.cpu.l2cache.ReadExReq_misses::total 512 # number of ReadExReq misses 995system.cpu.l2cache.demand_misses::cpu.inst 697 # number of demand (read+write) misses 996system.cpu.l2cache.demand_misses::cpu.data 928 # number of demand (read+write) misses 997system.cpu.l2cache.demand_misses::total 1625 # number of demand (read+write) misses 998system.cpu.l2cache.overall_misses::cpu.inst 697 # number of overall misses 999system.cpu.l2cache.overall_misses::cpu.data 928 # number of overall misses 1000system.cpu.l2cache.overall_misses::total 1625 # number of overall misses 1001system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48506493 # number of ReadReq miss cycles 1002system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26932750 # number of ReadReq miss cycles 1003system.cpu.l2cache.ReadReq_miss_latency::total 75439243 # number of ReadReq miss cycles 1004system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 46498 # number of UpgradeReq miss cycles 1005system.cpu.l2cache.UpgradeReq_miss_latency::total 46498 # number of UpgradeReq miss cycles 1006system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37042063 # number of ReadExReq miss cycles 1007system.cpu.l2cache.ReadExReq_miss_latency::total 37042063 # number of ReadExReq miss cycles 1008system.cpu.l2cache.demand_miss_latency::cpu.inst 48506493 # number of demand (read+write) miss cycles 1009system.cpu.l2cache.demand_miss_latency::cpu.data 63974813 # number of demand (read+write) miss cycles 1010system.cpu.l2cache.demand_miss_latency::total 112481306 # number of demand (read+write) miss cycles 1011system.cpu.l2cache.overall_miss_latency::cpu.inst 48506493 # number of overall miss cycles 1012system.cpu.l2cache.overall_miss_latency::cpu.data 63974813 # number of overall miss cycles 1013system.cpu.l2cache.overall_miss_latency::total 112481306 # number of overall miss cycles 1014system.cpu.l2cache.ReadReq_accesses::cpu.inst 910 # number of ReadReq accesses(hits+misses) 1015system.cpu.l2cache.ReadReq_accesses::cpu.data 5236855 # number of ReadReq accesses(hits+misses) 1016system.cpu.l2cache.ReadReq_accesses::total 5237765 # number of ReadReq accesses(hits+misses) 1017system.cpu.l2cache.Writeback_accesses::writebacks 5439051 # number of Writeback accesses(hits+misses) 1018system.cpu.l2cache.Writeback_accesses::total 5439051 # number of Writeback accesses(hits+misses) 1019system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 1020system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 1021system.cpu.l2cache.ReadExReq_accesses::cpu.data 233200 # number of ReadExReq accesses(hits+misses) 1022system.cpu.l2cache.ReadExReq_accesses::total 233200 # number of ReadExReq accesses(hits+misses) 1023system.cpu.l2cache.demand_accesses::cpu.inst 910 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::cpu.data 5470055 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::total 5470965 # number of demand (read+write) accesses 1026system.cpu.l2cache.overall_accesses::cpu.inst 910 # number of overall (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.data 5470055 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::total 5470965 # number of overall (read+write) accesses 1029system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.765934 # miss rate for ReadReq accesses 1030system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000079 # miss rate for ReadReq accesses 1031system.cpu.l2cache.ReadReq_miss_rate::total 0.000212 # miss rate for ReadReq accesses 1032system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1033system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1034system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002196 # miss rate for ReadExReq accesses 1035system.cpu.l2cache.ReadExReq_miss_rate::total 0.002196 # miss rate for ReadExReq accesses 1036system.cpu.l2cache.demand_miss_rate::cpu.inst 0.765934 # miss rate for demand accesses 1037system.cpu.l2cache.demand_miss_rate::cpu.data 0.000170 # miss rate for demand accesses 1038system.cpu.l2cache.demand_miss_rate::total 0.000297 # miss rate for demand accesses 1039system.cpu.l2cache.overall_miss_rate::cpu.inst 0.765934 # miss rate for overall accesses 1040system.cpu.l2cache.overall_miss_rate::cpu.data 0.000170 # miss rate for overall accesses 1041system.cpu.l2cache.overall_miss_rate::total 0.000297 # miss rate for overall accesses 1042system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69593.246772 # average ReadReq miss latency 1043system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64742.187500 # average ReadReq miss latency 1044system.cpu.l2cache.ReadReq_avg_miss_latency::total 67780.092543 # average ReadReq miss latency 1045system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23249 # average UpgradeReq miss latency 1046system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23249 # average UpgradeReq miss latency 1047system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72347.779297 # average ReadExReq miss latency 1048system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72347.779297 # average ReadExReq miss latency 1049system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69593.246772 # average overall miss latency 1050system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68938.376078 # average overall miss latency 1051system.cpu.l2cache.demand_avg_miss_latency::total 69219.265231 # average overall miss latency 1052system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69593.246772 # average overall miss latency 1053system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68938.376078 # average overall miss latency 1054system.cpu.l2cache.overall_avg_miss_latency::total 69219.265231 # average overall miss latency 1055system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1056system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1057system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1058system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1059system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1060system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1061system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1062system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1063system.cpu.l2cache.writebacks::writebacks 358 # number of writebacks 1064system.cpu.l2cache.writebacks::total 358 # number of writebacks 1065system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 1066system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 48 # number of ReadReq MSHR hits 1067system.cpu.l2cache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits 1068system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 171 # number of ReadExReq MSHR hits 1069system.cpu.l2cache.ReadExReq_mshr_hits::total 171 # number of ReadExReq MSHR hits 1070system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 1071system.cpu.l2cache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits 1072system.cpu.l2cache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits 1073system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 1074system.cpu.l2cache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits 1075system.cpu.l2cache.overall_mshr_hits::total 221 # number of overall MSHR hits 1076system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 695 # number of ReadReq MSHR misses 1077system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 368 # number of ReadReq MSHR misses 1078system.cpu.l2cache.ReadReq_mshr_misses::total 1063 # number of ReadReq MSHR misses 1079system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20246 # number of HardPFReq MSHR misses 1080system.cpu.l2cache.HardPFReq_mshr_misses::total 20246 # number of HardPFReq MSHR misses 1081system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 1082system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 1083system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses 1084system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses 1085system.cpu.l2cache.demand_mshr_misses::cpu.inst 695 # number of demand (read+write) MSHR misses 1086system.cpu.l2cache.demand_mshr_misses::cpu.data 709 # number of demand (read+write) MSHR misses 1087system.cpu.l2cache.demand_mshr_misses::total 1404 # number of demand (read+write) MSHR misses 1088system.cpu.l2cache.overall_mshr_misses::cpu.inst 695 # number of overall MSHR misses 1089system.cpu.l2cache.overall_mshr_misses::cpu.data 709 # number of overall MSHR misses 1090system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20246 # number of overall MSHR misses 1091system.cpu.l2cache.overall_mshr_misses::total 21650 # number of overall MSHR misses 1092system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42518507 # number of ReadReq MSHR miss cycles 1093system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21103750 # number of ReadReq MSHR miss cycles 1094system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63622257 # number of ReadReq MSHR miss cycles 1095system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of HardPFReq MSHR miss cycles 1096system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 830590289 # number of HardPFReq MSHR miss cycles 1097system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles 1098system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles 1099system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 25988008 # number of ReadExReq MSHR miss cycles 1100system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 25988008 # number of ReadExReq MSHR miss cycles 1101system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42518507 # number of demand (read+write) MSHR miss cycles 1102system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47091758 # number of demand (read+write) MSHR miss cycles 1103system.cpu.l2cache.demand_mshr_miss_latency::total 89610265 # number of demand (read+write) MSHR miss cycles 1104system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42518507 # number of overall MSHR miss cycles 1105system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47091758 # number of overall MSHR miss cycles 1106system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of overall MSHR miss cycles 1107system.cpu.l2cache.overall_mshr_miss_latency::total 920200554 # number of overall MSHR miss cycles 1108system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for ReadReq accesses 1109system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000070 # mshr miss rate for ReadReq accesses 1110system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000203 # mshr miss rate for ReadReq accesses 1111system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1112system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1113system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1114system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1115system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001462 # mshr miss rate for ReadExReq accesses 1116system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001462 # mshr miss rate for ReadExReq accesses 1117system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for demand accesses 1118system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for demand accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::total 0.000257 # mshr miss rate for demand accesses 1120system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for overall accesses 1121system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for overall accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1123system.cpu.l2cache.overall_mshr_miss_rate::total 0.003957 # mshr miss rate for overall accesses 1124system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61177.707914 # average ReadReq mshr miss latency 1125system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57347.146739 # average ReadReq mshr miss latency 1126system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59851.605833 # average ReadReq mshr miss latency 1127system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average HardPFReq mshr miss latency 1128system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41024.908081 # average HardPFReq mshr miss latency 1129system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency 1130system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency 1131system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76211.167155 # average ReadExReq mshr miss latency 1132system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76211.167155 # average ReadExReq mshr miss latency 1133system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency 1134system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency 1135system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63824.975071 # average overall mshr miss latency 1136system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency 1137system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency 1138system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.489792 # average overall mshr miss latency 1140system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.cpu.toL2Bus.trans_dist::ReadReq 5237765 # Transaction distribution 1142system.cpu.toL2Bus.trans_dist::ReadResp 5237765 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::Writeback 5439051 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::HardPFReq 22132 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 1147system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 1148system.cpu.toL2Bus.trans_dist::ReadExReq 233200 # Transaction distribution 1149system.cpu.toL2Bus.trans_dist::ReadExResp 233200 # Transaction distribution 1150system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1820 # Packet count per connected master and slave (bytes) 1151system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16379167 # Packet count per connected master and slave (bytes) 1152system.cpu.toL2Bus.pkt_count::total 16380987 # Packet count per connected master and slave (bytes) 1153system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) 1154system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698182912 # Cumulative packet size per connected master and slave (bytes) 1155system.cpu.toL2Bus.pkt_size::total 698241152 # Cumulative packet size per connected master and slave (bytes) 1156system.cpu.toL2Bus.snoops 22134 # Total snoops (count) 1157system.cpu.toL2Bus.snoop_fanout::samples 10932150 # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::mean 3.002024 # Request fanout histogram 1159system.cpu.toL2Bus.snoop_fanout::stdev 0.044949 # Request fanout histogram 1160system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1162system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1163system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::3 10910018 99.80% 99.80% # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::4 22132 0.20% 100.00% # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::total 10932150 # Request fanout histogram 1170system.cpu.toL2Bus.reqLayer0.occupancy 10894060998 # Layer occupancy (ticks) 1171system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) 1172system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) 1173system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1174system.cpu.toL2Bus.respLayer0.occupancy 1497004 # Layer occupancy (ticks) 1175system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1176system.cpu.toL2Bus.respLayer1.occupancy 8205133181 # Layer occupancy (ticks) 1177system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) 1178system.membus.trans_dist::ReadReq 15596 # Transaction distribution 1179system.membus.trans_dist::ReadResp 15596 # Transaction distribution 1180system.membus.trans_dist::Writeback 358 # Transaction distribution 1181system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 1182system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1183system.membus.trans_dist::ReadExReq 341 # Transaction distribution 1184system.membus.trans_dist::ReadExResp 341 # Transaction distribution 1185system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32236 # Packet count per connected master and slave (bytes) 1186system.membus.pkt_count::total 32236 # Packet count per connected master and slave (bytes) 1187system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1042880 # Cumulative packet size per connected master and slave (bytes) 1188system.membus.pkt_size::total 1042880 # Cumulative packet size per connected master and slave (bytes) 1189system.membus.snoops 0 # Total snoops (count) 1190system.membus.snoop_fanout::samples 16297 # Request fanout histogram 1191system.membus.snoop_fanout::mean 0 # Request fanout histogram 1192system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1193system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1194system.membus.snoop_fanout::0 16297 100.00% 100.00% # Request fanout histogram 1195system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1196system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1197system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1198system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1199system.membus.snoop_fanout::total 16297 # Request fanout histogram 1200system.membus.reqLayer0.occupancy 26854780 # Layer occupancy (ticks) 1201system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1202system.membus.respLayer1.occupancy 83365318 # Layer occupancy (ticks) 1203system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1204 1205---------- End Simulation Statistics ---------- | 679system.cpu.rob.rob_reads 217986125 # The number of ROB reads 680system.cpu.rob.rob_writes 219581178 # The number of ROB writes 681system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself 682system.cpu.idleCycles 52982 # Total number of cycles that the CPU has spent unscheduled due to idling 683system.cpu.committedInsts 90589798 # Number of Instructions Simulated 684system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated 685system.cpu.cpi 1.284973 # CPI: Cycles Per Instruction 686system.cpu.cpi_total 1.284973 # CPI: Total CPI of All Threads 687system.cpu.ipc 0.778226 # IPC: Instructions Per Cycle 688system.cpu.ipc_total 0.778226 # IPC: Total IPC of All Threads 689system.cpu.int_regfile_reads 108112973 # number of integer regfile reads 690system.cpu.int_regfile_writes 58701982 # number of integer regfile writes 691system.cpu.fp_regfile_reads 58 # number of floating regfile reads 692system.cpu.fp_regfile_writes 95 # number of floating regfile writes 693system.cpu.cc_regfile_reads 369069288 # number of cc regfile reads 694system.cpu.cc_regfile_writes 58692619 # number of cc regfile writes 695system.cpu.misc_regfile_reads 28415446 # number of misc regfile reads 696system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 697system.cpu.dcache.tags.replacements 5469543 # number of replacements 698system.cpu.dcache.tags.tagsinuse 511.788616 # Cycle average of tags in use 699system.cpu.dcache.tags.total_refs 18297454 # Total number of references to valid blocks. 700system.cpu.dcache.tags.sampled_refs 5470055 # Sample count of references to valid blocks. 701system.cpu.dcache.tags.avg_refs 3.345022 # Average number of references to valid blocks. 702system.cpu.dcache.tags.warmup_cycle 35157000 # Cycle when the warmup percentage was hit. 703system.cpu.dcache.tags.occ_blocks::cpu.data 511.788616 # Average occupied blocks per requestor 704system.cpu.dcache.tags.occ_percent::cpu.data 0.999587 # Average percentage of cache occupancy 705system.cpu.dcache.tags.occ_percent::total 0.999587 # Average percentage of cache occupancy 706system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 707system.cpu.dcache.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id 708system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 709system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 710system.cpu.dcache.tags.tag_accesses 61924995 # Number of tag accesses 711system.cpu.dcache.tags.data_accesses 61924995 # Number of data accesses 712system.cpu.dcache.ReadReq_hits::cpu.data 13934183 # number of ReadReq hits 713system.cpu.dcache.ReadReq_hits::total 13934183 # number of ReadReq hits 714system.cpu.dcache.WriteReq_hits::cpu.data 4354974 # number of WriteReq hits 715system.cpu.dcache.WriteReq_hits::total 4354974 # number of WriteReq hits 716system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 717system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 718system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits 719system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits 720system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 721system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 722system.cpu.dcache.demand_hits::cpu.data 18289157 # number of demand (read+write) hits 723system.cpu.dcache.demand_hits::total 18289157 # number of demand (read+write) hits 724system.cpu.dcache.overall_hits::cpu.data 18289679 # number of overall hits 725system.cpu.dcache.overall_hits::total 18289679 # number of overall hits 726system.cpu.dcache.ReadReq_misses::cpu.data 9550003 # number of ReadReq misses 727system.cpu.dcache.ReadReq_misses::total 9550003 # number of ReadReq misses 728system.cpu.dcache.WriteReq_misses::cpu.data 380007 # number of WriteReq misses 729system.cpu.dcache.WriteReq_misses::total 380007 # number of WriteReq misses 730system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses 731system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses 732system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses 733system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses 734system.cpu.dcache.demand_misses::cpu.data 9930010 # number of demand (read+write) misses 735system.cpu.dcache.demand_misses::total 9930010 # number of demand (read+write) misses 736system.cpu.dcache.overall_misses::cpu.data 9930017 # number of overall misses 737system.cpu.dcache.overall_misses::total 9930017 # number of overall misses 738system.cpu.dcache.ReadReq_miss_latency::cpu.data 88443276736 # number of ReadReq miss cycles 739system.cpu.dcache.ReadReq_miss_latency::total 88443276736 # number of ReadReq miss cycles 740system.cpu.dcache.WriteReq_miss_latency::cpu.data 3962066244 # number of WriteReq miss cycles 741system.cpu.dcache.WriteReq_miss_latency::total 3962066244 # number of WriteReq miss cycles 742system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297000 # number of LoadLockedReq miss cycles 743system.cpu.dcache.LoadLockedReq_miss_latency::total 297000 # number of LoadLockedReq miss cycles 744system.cpu.dcache.demand_miss_latency::cpu.data 92405342980 # number of demand (read+write) miss cycles 745system.cpu.dcache.demand_miss_latency::total 92405342980 # number of demand (read+write) miss cycles 746system.cpu.dcache.overall_miss_latency::cpu.data 92405342980 # number of overall miss cycles 747system.cpu.dcache.overall_miss_latency::total 92405342980 # number of overall miss cycles 748system.cpu.dcache.ReadReq_accesses::cpu.data 23484186 # number of ReadReq accesses(hits+misses) 749system.cpu.dcache.ReadReq_accesses::total 23484186 # number of ReadReq accesses(hits+misses) 750system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 751system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 752system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) 753system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) 754system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 755system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 756system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 757system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 758system.cpu.dcache.demand_accesses::cpu.data 28219167 # number of demand (read+write) accesses 759system.cpu.dcache.demand_accesses::total 28219167 # number of demand (read+write) accesses 760system.cpu.dcache.overall_accesses::cpu.data 28219696 # number of overall (read+write) accesses 761system.cpu.dcache.overall_accesses::total 28219696 # number of overall (read+write) accesses 762system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.406657 # miss rate for ReadReq accesses 763system.cpu.dcache.ReadReq_miss_rate::total 0.406657 # miss rate for ReadReq accesses 764system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080255 # miss rate for WriteReq accesses 765system.cpu.dcache.WriteReq_miss_rate::total 0.080255 # miss rate for WriteReq accesses 766system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses 767system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses 768system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses 769system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses 770system.cpu.dcache.demand_miss_rate::cpu.data 0.351889 # miss rate for demand accesses 771system.cpu.dcache.demand_miss_rate::total 0.351889 # miss rate for demand accesses 772system.cpu.dcache.overall_miss_rate::cpu.data 0.351882 # miss rate for overall accesses 773system.cpu.dcache.overall_miss_rate::total 0.351882 # miss rate for overall accesses 774system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9261.073189 # average ReadReq miss latency 775system.cpu.dcache.ReadReq_avg_miss_latency::total 9261.073189 # average ReadReq miss latency 776system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10426.298052 # average WriteReq miss latency 777system.cpu.dcache.WriteReq_avg_miss_latency::total 10426.298052 # average WriteReq miss latency 778system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19800 # average LoadLockedReq miss latency 779system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19800 # average LoadLockedReq miss latency 780system.cpu.dcache.demand_avg_miss_latency::cpu.data 9305.664645 # average overall miss latency 781system.cpu.dcache.demand_avg_miss_latency::total 9305.664645 # average overall miss latency 782system.cpu.dcache.overall_avg_miss_latency::cpu.data 9305.658085 # average overall miss latency 783system.cpu.dcache.overall_avg_miss_latency::total 9305.658085 # average overall miss latency 784system.cpu.dcache.blocked_cycles::no_mshrs 306020 # number of cycles access was blocked 785system.cpu.dcache.blocked_cycles::no_targets 36082 # number of cycles access was blocked 786system.cpu.dcache.blocked::no_mshrs 120709 # number of cycles access was blocked 787system.cpu.dcache.blocked::no_targets 2278 # number of cycles access was blocked 788system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.535188 # average number of cycles each access was blocked 789system.cpu.dcache.avg_blocked_cycles::no_targets 15.839333 # average number of cycles each access was blocked 790system.cpu.dcache.fast_writes 0 # number of fast writes performed 791system.cpu.dcache.cache_copies 0 # number of cache copies performed 792system.cpu.dcache.writebacks::writebacks 5439051 # number of writebacks 793system.cpu.dcache.writebacks::total 5439051 # number of writebacks 794system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4313021 # number of ReadReq MSHR hits 795system.cpu.dcache.ReadReq_mshr_hits::total 4313021 # number of ReadReq MSHR hits 796system.cpu.dcache.WriteReq_mshr_hits::cpu.data 146936 # number of WriteReq MSHR hits 797system.cpu.dcache.WriteReq_mshr_hits::total 146936 # number of WriteReq MSHR hits 798system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits 799system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits 800system.cpu.dcache.demand_mshr_hits::cpu.data 4459957 # number of demand (read+write) MSHR hits 801system.cpu.dcache.demand_mshr_hits::total 4459957 # number of demand (read+write) MSHR hits 802system.cpu.dcache.overall_mshr_hits::cpu.data 4459957 # number of overall MSHR hits 803system.cpu.dcache.overall_mshr_hits::total 4459957 # number of overall MSHR hits 804system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5236982 # number of ReadReq MSHR misses 805system.cpu.dcache.ReadReq_mshr_misses::total 5236982 # number of ReadReq MSHR misses 806system.cpu.dcache.WriteReq_mshr_misses::cpu.data 233071 # number of WriteReq MSHR misses 807system.cpu.dcache.WriteReq_mshr_misses::total 233071 # number of WriteReq MSHR misses 808system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses 809system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses 810system.cpu.dcache.demand_mshr_misses::cpu.data 5470053 # number of demand (read+write) MSHR misses 811system.cpu.dcache.demand_mshr_misses::total 5470053 # number of demand (read+write) MSHR misses 812system.cpu.dcache.overall_mshr_misses::cpu.data 5470057 # number of overall MSHR misses 813system.cpu.dcache.overall_mshr_misses::total 5470057 # number of overall MSHR misses 814system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40519086258 # number of ReadReq MSHR miss cycles 815system.cpu.dcache.ReadReq_mshr_miss_latency::total 40519086258 # number of ReadReq MSHR miss cycles 816system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2295163471 # number of WriteReq MSHR miss cycles 817system.cpu.dcache.WriteReq_mshr_miss_latency::total 2295163471 # number of WriteReq MSHR miss cycles 818system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 213000 # number of SoftPFReq MSHR miss cycles 819system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 213000 # number of SoftPFReq MSHR miss cycles 820system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42814249729 # number of demand (read+write) MSHR miss cycles 821system.cpu.dcache.demand_mshr_miss_latency::total 42814249729 # number of demand (read+write) MSHR miss cycles 822system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42814462729 # number of overall MSHR miss cycles 823system.cpu.dcache.overall_mshr_miss_latency::total 42814462729 # number of overall MSHR miss cycles 824system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223000 # mshr miss rate for ReadReq accesses 825system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223000 # mshr miss rate for ReadReq accesses 826system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049223 # mshr miss rate for WriteReq accesses 827system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049223 # mshr miss rate for WriteReq accesses 828system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses 829system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses 830system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193842 # mshr miss rate for demand accesses 831system.cpu.dcache.demand_mshr_miss_rate::total 0.193842 # mshr miss rate for demand accesses 832system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193838 # mshr miss rate for overall accesses 833system.cpu.dcache.overall_mshr_miss_rate::total 0.193838 # mshr miss rate for overall accesses 834system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7737.106268 # average ReadReq mshr miss latency 835system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7737.106268 # average ReadReq mshr miss latency 836system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9847.486264 # average WriteReq mshr miss latency 837system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9847.486264 # average WriteReq mshr miss latency 838system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53250 # average SoftPFReq mshr miss latency 839system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53250 # average SoftPFReq mshr miss latency 840system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7827.026489 # average overall mshr miss latency 841system.cpu.dcache.demand_avg_mshr_miss_latency::total 7827.026489 # average overall mshr miss latency 842system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7827.059705 # average overall mshr miss latency 843system.cpu.dcache.overall_avg_mshr_miss_latency::total 7827.059705 # average overall mshr miss latency 844system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 845system.cpu.icache.tags.replacements 451 # number of replacements 846system.cpu.icache.tags.tagsinuse 428.263511 # Cycle average of tags in use 847system.cpu.icache.tags.total_refs 32302915 # Total number of references to valid blocks. 848system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. 849system.cpu.icache.tags.avg_refs 35497.708791 # Average number of references to valid blocks. 850system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 851system.cpu.icache.tags.occ_blocks::cpu.inst 428.263511 # Average occupied blocks per requestor 852system.cpu.icache.tags.occ_percent::cpu.inst 0.836452 # Average percentage of cache occupancy 853system.cpu.icache.tags.occ_percent::total 0.836452 # Average percentage of cache occupancy 854system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id 855system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 856system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 857system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id 858system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id 859system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id 860system.cpu.icache.tags.tag_accesses 64609056 # Number of tag accesses 861system.cpu.icache.tags.data_accesses 64609056 # Number of data accesses 862system.cpu.icache.ReadReq_hits::cpu.inst 32302915 # number of ReadReq hits 863system.cpu.icache.ReadReq_hits::total 32302915 # number of ReadReq hits 864system.cpu.icache.demand_hits::cpu.inst 32302915 # number of demand (read+write) hits 865system.cpu.icache.demand_hits::total 32302915 # number of demand (read+write) hits 866system.cpu.icache.overall_hits::cpu.inst 32302915 # number of overall hits 867system.cpu.icache.overall_hits::total 32302915 # number of overall hits 868system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses 869system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses 870system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses 871system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses 872system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses 873system.cpu.icache.overall_misses::total 1158 # number of overall misses 874system.cpu.icache.ReadReq_miss_latency::cpu.inst 62669987 # number of ReadReq miss cycles 875system.cpu.icache.ReadReq_miss_latency::total 62669987 # number of ReadReq miss cycles 876system.cpu.icache.demand_miss_latency::cpu.inst 62669987 # number of demand (read+write) miss cycles 877system.cpu.icache.demand_miss_latency::total 62669987 # number of demand (read+write) miss cycles 878system.cpu.icache.overall_miss_latency::cpu.inst 62669987 # number of overall miss cycles 879system.cpu.icache.overall_miss_latency::total 62669987 # number of overall miss cycles 880system.cpu.icache.ReadReq_accesses::cpu.inst 32304073 # number of ReadReq accesses(hits+misses) 881system.cpu.icache.ReadReq_accesses::total 32304073 # number of ReadReq accesses(hits+misses) 882system.cpu.icache.demand_accesses::cpu.inst 32304073 # number of demand (read+write) accesses 883system.cpu.icache.demand_accesses::total 32304073 # number of demand (read+write) accesses 884system.cpu.icache.overall_accesses::cpu.inst 32304073 # number of overall (read+write) accesses 885system.cpu.icache.overall_accesses::total 32304073 # number of overall (read+write) accesses 886system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses 887system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses 888system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses 889system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses 890system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses 891system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses 892system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54119.159758 # average ReadReq miss latency 893system.cpu.icache.ReadReq_avg_miss_latency::total 54119.159758 # average ReadReq miss latency 894system.cpu.icache.demand_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency 895system.cpu.icache.demand_avg_miss_latency::total 54119.159758 # average overall miss latency 896system.cpu.icache.overall_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency 897system.cpu.icache.overall_avg_miss_latency::total 54119.159758 # average overall miss latency 898system.cpu.icache.blocked_cycles::no_mshrs 19414 # number of cycles access was blocked 899system.cpu.icache.blocked_cycles::no_targets 134 # number of cycles access was blocked 900system.cpu.icache.blocked::no_mshrs 238 # number of cycles access was blocked 901system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 902system.cpu.icache.avg_blocked_cycles::no_mshrs 81.571429 # average number of cycles each access was blocked 903system.cpu.icache.avg_blocked_cycles::no_targets 26.800000 # average number of cycles each access was blocked 904system.cpu.icache.fast_writes 0 # number of fast writes performed 905system.cpu.icache.cache_copies 0 # number of cache copies performed 906system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits 907system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits 908system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits 909system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 910system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits 911system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits 912system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses 913system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses 914system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses 915system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses 916system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses 917system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses 918system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50368733 # number of ReadReq MSHR miss cycles 919system.cpu.icache.ReadReq_mshr_miss_latency::total 50368733 # number of ReadReq MSHR miss cycles 920system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50368733 # number of demand (read+write) MSHR miss cycles 921system.cpu.icache.demand_mshr_miss_latency::total 50368733 # number of demand (read+write) MSHR miss cycles 922system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50368733 # number of overall MSHR miss cycles 923system.cpu.icache.overall_mshr_miss_latency::total 50368733 # number of overall MSHR miss cycles 924system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 925system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 926system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 927system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 928system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 929system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 930system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55350.256044 # average ReadReq mshr miss latency 931system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55350.256044 # average ReadReq mshr miss latency 932system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55350.256044 # average overall mshr miss latency 933system.cpu.icache.demand_avg_mshr_miss_latency::total 55350.256044 # average overall mshr miss latency 934system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55350.256044 # average overall mshr miss latency 935system.cpu.icache.overall_avg_mshr_miss_latency::total 55350.256044 # average overall mshr miss latency 936system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 937system.cpu.l2cache.prefetcher.num_hwpf_issued 4495585 # number of hwpf issued 938system.cpu.l2cache.prefetcher.pfIdentified 5292074 # number of prefetch candidates identified 939system.cpu.l2cache.prefetcher.pfBufferHit 687825 # number of redundant prefetches already in prefetch queue 940system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 941system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 942system.cpu.l2cache.prefetcher.pfSpanPage 14072766 # number of prefetches not generated due to page crossing 943system.cpu.l2cache.tags.replacements 493 # number of replacements 944system.cpu.l2cache.tags.tagsinuse 12074.856330 # Cycle average of tags in use 945system.cpu.l2cache.tags.total_refs 10653372 # Total number of references to valid blocks. 946system.cpu.l2cache.tags.sampled_refs 15934 # Sample count of references to valid blocks. 947system.cpu.l2cache.tags.avg_refs 668.593699 # Average number of references to valid blocks. 948system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 949system.cpu.l2cache.tags.occ_blocks::writebacks 11119.543661 # Average occupied blocks per requestor 950system.cpu.l2cache.tags.occ_blocks::cpu.inst 571.365929 # Average occupied blocks per requestor 951system.cpu.l2cache.tags.occ_blocks::cpu.data 202.646634 # Average occupied blocks per requestor 952system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 181.300106 # Average occupied blocks per requestor 953system.cpu.l2cache.tags.occ_percent::writebacks 0.678683 # Average percentage of cache occupancy 954system.cpu.l2cache.tags.occ_percent::cpu.inst 0.034873 # Average percentage of cache occupancy 955system.cpu.l2cache.tags.occ_percent::cpu.data 0.012369 # Average percentage of cache occupancy 956system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.011066 # Average percentage of cache occupancy 957system.cpu.l2cache.tags.occ_percent::total 0.736991 # Average percentage of cache occupancy 958system.cpu.l2cache.tags.occ_task_id_blocks::1022 216 # Occupied blocks per task id 959system.cpu.l2cache.tags.occ_task_id_blocks::1024 15225 # Occupied blocks per task id 960system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id 961system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 962system.cpu.l2cache.tags.age_task_id_blocks_1022::2 13 # Occupied blocks per task id 963system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id 964system.cpu.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id 965system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 966system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 967system.cpu.l2cache.tags.age_task_id_blocks_1024::2 974 # Occupied blocks per task id 968system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1048 # Occupied blocks per task id 969system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13130 # Occupied blocks per task id 970system.cpu.l2cache.tags.occ_task_id_percent::1022 0.013184 # Percentage of cache occupancy per task id 971system.cpu.l2cache.tags.occ_task_id_percent::1024 0.929260 # Percentage of cache occupancy per task id 972system.cpu.l2cache.tags.tag_accesses 174809424 # Number of tag accesses 973system.cpu.l2cache.tags.data_accesses 174809424 # Number of data accesses 974system.cpu.l2cache.ReadReq_hits::cpu.inst 213 # number of ReadReq hits 975system.cpu.l2cache.ReadReq_hits::cpu.data 5236439 # number of ReadReq hits 976system.cpu.l2cache.ReadReq_hits::total 5236652 # number of ReadReq hits 977system.cpu.l2cache.Writeback_hits::writebacks 5439051 # number of Writeback hits 978system.cpu.l2cache.Writeback_hits::total 5439051 # number of Writeback hits 979system.cpu.l2cache.ReadExReq_hits::cpu.data 232688 # number of ReadExReq hits 980system.cpu.l2cache.ReadExReq_hits::total 232688 # number of ReadExReq hits 981system.cpu.l2cache.demand_hits::cpu.inst 213 # number of demand (read+write) hits 982system.cpu.l2cache.demand_hits::cpu.data 5469127 # number of demand (read+write) hits 983system.cpu.l2cache.demand_hits::total 5469340 # number of demand (read+write) hits 984system.cpu.l2cache.overall_hits::cpu.inst 213 # number of overall hits 985system.cpu.l2cache.overall_hits::cpu.data 5469127 # number of overall hits 986system.cpu.l2cache.overall_hits::total 5469340 # number of overall hits 987system.cpu.l2cache.ReadReq_misses::cpu.inst 697 # number of ReadReq misses 988system.cpu.l2cache.ReadReq_misses::cpu.data 416 # number of ReadReq misses 989system.cpu.l2cache.ReadReq_misses::total 1113 # number of ReadReq misses 990system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 991system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 992system.cpu.l2cache.ReadExReq_misses::cpu.data 512 # number of ReadExReq misses 993system.cpu.l2cache.ReadExReq_misses::total 512 # number of ReadExReq misses 994system.cpu.l2cache.demand_misses::cpu.inst 697 # number of demand (read+write) misses 995system.cpu.l2cache.demand_misses::cpu.data 928 # number of demand (read+write) misses 996system.cpu.l2cache.demand_misses::total 1625 # number of demand (read+write) misses 997system.cpu.l2cache.overall_misses::cpu.inst 697 # number of overall misses 998system.cpu.l2cache.overall_misses::cpu.data 928 # number of overall misses 999system.cpu.l2cache.overall_misses::total 1625 # number of overall misses 1000system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48506493 # number of ReadReq miss cycles 1001system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26932750 # number of ReadReq miss cycles 1002system.cpu.l2cache.ReadReq_miss_latency::total 75439243 # number of ReadReq miss cycles 1003system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 46498 # number of UpgradeReq miss cycles 1004system.cpu.l2cache.UpgradeReq_miss_latency::total 46498 # number of UpgradeReq miss cycles 1005system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37042063 # number of ReadExReq miss cycles 1006system.cpu.l2cache.ReadExReq_miss_latency::total 37042063 # number of ReadExReq miss cycles 1007system.cpu.l2cache.demand_miss_latency::cpu.inst 48506493 # number of demand (read+write) miss cycles 1008system.cpu.l2cache.demand_miss_latency::cpu.data 63974813 # number of demand (read+write) miss cycles 1009system.cpu.l2cache.demand_miss_latency::total 112481306 # number of demand (read+write) miss cycles 1010system.cpu.l2cache.overall_miss_latency::cpu.inst 48506493 # number of overall miss cycles 1011system.cpu.l2cache.overall_miss_latency::cpu.data 63974813 # number of overall miss cycles 1012system.cpu.l2cache.overall_miss_latency::total 112481306 # number of overall miss cycles 1013system.cpu.l2cache.ReadReq_accesses::cpu.inst 910 # number of ReadReq accesses(hits+misses) 1014system.cpu.l2cache.ReadReq_accesses::cpu.data 5236855 # number of ReadReq accesses(hits+misses) 1015system.cpu.l2cache.ReadReq_accesses::total 5237765 # number of ReadReq accesses(hits+misses) 1016system.cpu.l2cache.Writeback_accesses::writebacks 5439051 # number of Writeback accesses(hits+misses) 1017system.cpu.l2cache.Writeback_accesses::total 5439051 # number of Writeback accesses(hits+misses) 1018system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 1019system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 1020system.cpu.l2cache.ReadExReq_accesses::cpu.data 233200 # number of ReadExReq accesses(hits+misses) 1021system.cpu.l2cache.ReadExReq_accesses::total 233200 # number of ReadExReq accesses(hits+misses) 1022system.cpu.l2cache.demand_accesses::cpu.inst 910 # number of demand (read+write) accesses 1023system.cpu.l2cache.demand_accesses::cpu.data 5470055 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::total 5470965 # number of demand (read+write) accesses 1025system.cpu.l2cache.overall_accesses::cpu.inst 910 # number of overall (read+write) accesses 1026system.cpu.l2cache.overall_accesses::cpu.data 5470055 # number of overall (read+write) accesses 1027system.cpu.l2cache.overall_accesses::total 5470965 # number of overall (read+write) accesses 1028system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.765934 # miss rate for ReadReq accesses 1029system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000079 # miss rate for ReadReq accesses 1030system.cpu.l2cache.ReadReq_miss_rate::total 0.000212 # miss rate for ReadReq accesses 1031system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1032system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1033system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002196 # miss rate for ReadExReq accesses 1034system.cpu.l2cache.ReadExReq_miss_rate::total 0.002196 # miss rate for ReadExReq accesses 1035system.cpu.l2cache.demand_miss_rate::cpu.inst 0.765934 # miss rate for demand accesses 1036system.cpu.l2cache.demand_miss_rate::cpu.data 0.000170 # miss rate for demand accesses 1037system.cpu.l2cache.demand_miss_rate::total 0.000297 # miss rate for demand accesses 1038system.cpu.l2cache.overall_miss_rate::cpu.inst 0.765934 # miss rate for overall accesses 1039system.cpu.l2cache.overall_miss_rate::cpu.data 0.000170 # miss rate for overall accesses 1040system.cpu.l2cache.overall_miss_rate::total 0.000297 # miss rate for overall accesses 1041system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69593.246772 # average ReadReq miss latency 1042system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64742.187500 # average ReadReq miss latency 1043system.cpu.l2cache.ReadReq_avg_miss_latency::total 67780.092543 # average ReadReq miss latency 1044system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23249 # average UpgradeReq miss latency 1045system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23249 # average UpgradeReq miss latency 1046system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72347.779297 # average ReadExReq miss latency 1047system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72347.779297 # average ReadExReq miss latency 1048system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69593.246772 # average overall miss latency 1049system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68938.376078 # average overall miss latency 1050system.cpu.l2cache.demand_avg_miss_latency::total 69219.265231 # average overall miss latency 1051system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69593.246772 # average overall miss latency 1052system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68938.376078 # average overall miss latency 1053system.cpu.l2cache.overall_avg_miss_latency::total 69219.265231 # average overall miss latency 1054system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1055system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1056system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1057system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1058system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1059system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1060system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1061system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1062system.cpu.l2cache.writebacks::writebacks 358 # number of writebacks 1063system.cpu.l2cache.writebacks::total 358 # number of writebacks 1064system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 1065system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 48 # number of ReadReq MSHR hits 1066system.cpu.l2cache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits 1067system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 171 # number of ReadExReq MSHR hits 1068system.cpu.l2cache.ReadExReq_mshr_hits::total 171 # number of ReadExReq MSHR hits 1069system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 1070system.cpu.l2cache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits 1071system.cpu.l2cache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits 1072system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 1073system.cpu.l2cache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits 1074system.cpu.l2cache.overall_mshr_hits::total 221 # number of overall MSHR hits 1075system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 695 # number of ReadReq MSHR misses 1076system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 368 # number of ReadReq MSHR misses 1077system.cpu.l2cache.ReadReq_mshr_misses::total 1063 # number of ReadReq MSHR misses 1078system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20246 # number of HardPFReq MSHR misses 1079system.cpu.l2cache.HardPFReq_mshr_misses::total 20246 # number of HardPFReq MSHR misses 1080system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 1081system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 1082system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses 1083system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses 1084system.cpu.l2cache.demand_mshr_misses::cpu.inst 695 # number of demand (read+write) MSHR misses 1085system.cpu.l2cache.demand_mshr_misses::cpu.data 709 # number of demand (read+write) MSHR misses 1086system.cpu.l2cache.demand_mshr_misses::total 1404 # number of demand (read+write) MSHR misses 1087system.cpu.l2cache.overall_mshr_misses::cpu.inst 695 # number of overall MSHR misses 1088system.cpu.l2cache.overall_mshr_misses::cpu.data 709 # number of overall MSHR misses 1089system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20246 # number of overall MSHR misses 1090system.cpu.l2cache.overall_mshr_misses::total 21650 # number of overall MSHR misses 1091system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42518507 # number of ReadReq MSHR miss cycles 1092system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21103750 # number of ReadReq MSHR miss cycles 1093system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63622257 # number of ReadReq MSHR miss cycles 1094system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of HardPFReq MSHR miss cycles 1095system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 830590289 # number of HardPFReq MSHR miss cycles 1096system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles 1097system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles 1098system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 25988008 # number of ReadExReq MSHR miss cycles 1099system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 25988008 # number of ReadExReq MSHR miss cycles 1100system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42518507 # number of demand (read+write) MSHR miss cycles 1101system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47091758 # number of demand (read+write) MSHR miss cycles 1102system.cpu.l2cache.demand_mshr_miss_latency::total 89610265 # number of demand (read+write) MSHR miss cycles 1103system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42518507 # number of overall MSHR miss cycles 1104system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47091758 # number of overall MSHR miss cycles 1105system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of overall MSHR miss cycles 1106system.cpu.l2cache.overall_mshr_miss_latency::total 920200554 # number of overall MSHR miss cycles 1107system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for ReadReq accesses 1108system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000070 # mshr miss rate for ReadReq accesses 1109system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000203 # mshr miss rate for ReadReq accesses 1110system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1111system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1112system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1113system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1114system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001462 # mshr miss rate for ReadExReq accesses 1115system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001462 # mshr miss rate for ReadExReq accesses 1116system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for demand accesses 1117system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for demand accesses 1118system.cpu.l2cache.demand_mshr_miss_rate::total 0.000257 # mshr miss rate for demand accesses 1119system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for overall accesses 1120system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for overall accesses 1121system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::total 0.003957 # mshr miss rate for overall accesses 1123system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61177.707914 # average ReadReq mshr miss latency 1124system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57347.146739 # average ReadReq mshr miss latency 1125system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59851.605833 # average ReadReq mshr miss latency 1126system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average HardPFReq mshr miss latency 1127system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41024.908081 # average HardPFReq mshr miss latency 1128system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency 1129system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency 1130system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76211.167155 # average ReadExReq mshr miss latency 1131system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76211.167155 # average ReadExReq mshr miss latency 1132system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency 1133system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency 1134system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63824.975071 # average overall mshr miss latency 1135system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency 1136system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency 1137system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average overall mshr miss latency 1138system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.489792 # average overall mshr miss latency 1139system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1140system.cpu.toL2Bus.trans_dist::ReadReq 5237765 # Transaction distribution 1141system.cpu.toL2Bus.trans_dist::ReadResp 5237765 # Transaction distribution 1142system.cpu.toL2Bus.trans_dist::Writeback 5439051 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::HardPFReq 22132 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 1147system.cpu.toL2Bus.trans_dist::ReadExReq 233200 # Transaction distribution 1148system.cpu.toL2Bus.trans_dist::ReadExResp 233200 # Transaction distribution 1149system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1820 # Packet count per connected master and slave (bytes) 1150system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16379167 # Packet count per connected master and slave (bytes) 1151system.cpu.toL2Bus.pkt_count::total 16380987 # Packet count per connected master and slave (bytes) 1152system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) 1153system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698182912 # Cumulative packet size per connected master and slave (bytes) 1154system.cpu.toL2Bus.pkt_size::total 698241152 # Cumulative packet size per connected master and slave (bytes) 1155system.cpu.toL2Bus.snoops 22134 # Total snoops (count) 1156system.cpu.toL2Bus.snoop_fanout::samples 10932150 # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::mean 3.002024 # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::stdev 0.044949 # Request fanout histogram 1159system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1160system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1162system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1163system.cpu.toL2Bus.snoop_fanout::3 10910018 99.80% 99.80% # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::4 22132 0.20% 100.00% # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::total 10932150 # Request fanout histogram 1169system.cpu.toL2Bus.reqLayer0.occupancy 10894060998 # Layer occupancy (ticks) 1170system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) 1171system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) 1172system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1173system.cpu.toL2Bus.respLayer0.occupancy 1497004 # Layer occupancy (ticks) 1174system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1175system.cpu.toL2Bus.respLayer1.occupancy 8205133181 # Layer occupancy (ticks) 1176system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) 1177system.membus.trans_dist::ReadReq 15596 # Transaction distribution 1178system.membus.trans_dist::ReadResp 15596 # Transaction distribution 1179system.membus.trans_dist::Writeback 358 # Transaction distribution 1180system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 1181system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1182system.membus.trans_dist::ReadExReq 341 # Transaction distribution 1183system.membus.trans_dist::ReadExResp 341 # Transaction distribution 1184system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32236 # Packet count per connected master and slave (bytes) 1185system.membus.pkt_count::total 32236 # Packet count per connected master and slave (bytes) 1186system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1042880 # Cumulative packet size per connected master and slave (bytes) 1187system.membus.pkt_size::total 1042880 # Cumulative packet size per connected master and slave (bytes) 1188system.membus.snoops 0 # Total snoops (count) 1189system.membus.snoop_fanout::samples 16297 # Request fanout histogram 1190system.membus.snoop_fanout::mean 0 # Request fanout histogram 1191system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1192system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1193system.membus.snoop_fanout::0 16297 100.00% 100.00% # Request fanout histogram 1194system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1195system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1196system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1197system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1198system.membus.snoop_fanout::total 16297 # Request fanout histogram 1199system.membus.reqLayer0.occupancy 26854780 # Layer occupancy (ticks) 1200system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1201system.membus.respLayer1.occupancy 83365318 # Layer occupancy (ticks) 1202system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1203 1204---------- End Simulation Statistics ---------- |