1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.026923 # Number of seconds simulated
4sim_ticks 26922512500 # Number of ticks simulated
5final_tick 26922512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 143955 # Simulator instruction rate (inst/s)
8host_op_rate 144989 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 42782119 # Simulator tick rate (ticks/s)
10host_mem_usage 446112 # Number of bytes of host memory used
11host_seconds 629.29 # Real time elapsed on the host
12sim_insts 90589798 # Number of instructions simulated
13sim_ops 91240351 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory
18system.physmem.bytes_read::total 992896 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 1680675 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 35199092 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 36879767 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 1680675 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 1680675 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 1680675 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 35199092 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 36879767 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 15514 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 988 # Per bank write bursts
45system.physmem.perBankRdBursts::1 886 # Per bank write bursts
46system.physmem.perBankRdBursts::2 942 # Per bank write bursts
47system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
48system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
49system.physmem.perBankRdBursts::5 1105 # Per bank write bursts
50system.physmem.perBankRdBursts::6 1078 # Per bank write bursts
51system.physmem.perBankRdBursts::7 1078 # Per bank write bursts
52system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
53system.physmem.perBankRdBursts::9 956 # Per bank write bursts
54system.physmem.perBankRdBursts::10 938 # Per bank write bursts
55system.physmem.perBankRdBursts::11 899 # Per bank write bursts
56system.physmem.perBankRdBursts::12 904 # Per bank write bursts
57system.physmem.perBankRdBursts::13 865 # Per bank write bursts
58system.physmem.perBankRdBursts::14 877 # Per bank write bursts
59system.physmem.perBankRdBursts::15 896 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts

--- 5 unchanged lines hidden (view full) ---

70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 26922312500 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 15514 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 10767 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 4517 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see

--- 76 unchanged lines hidden (view full) ---

181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 880 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 935.927273 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 827.602742 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 262.440032 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 41 4.66% 4.66% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 26 2.95% 7.61% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 13 1.48% 9.09% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 4 0.45% 9.55% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 5 0.57% 10.11% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 2 0.23% 10.34% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 2 0.23% 10.57% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 1 0.11% 10.68% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 786 89.32% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 880 # Bytes accessed per row activation
203system.physmem.totQLat 108095000 # Total ticks spent queuing
204system.physmem.totMemAccLat 369557500 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers
206system.physmem.totBankLat 183892500 # Total ticks spent accessing banks
207system.physmem.avgQLat 6967.58 # Average queueing delay per DRAM burst
208system.physmem.avgBankLat 11853.33 # Average bank access latency per DRAM burst
209system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
210system.physmem.avgMemAccLat 23820.90 # Average memory access latency per DRAM burst
211system.physmem.avgRdBW 36.88 # Average DRAM read bandwidth in MiByte/s
212system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
213system.physmem.avgRdBWSys 36.88 # Average system read bandwidth in MiByte/s
214system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
215system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
216system.physmem.busUtil 0.29 # Data bus utilization in percentage
217system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
218system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
219system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
220system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
221system.physmem.readRowHits 14141 # Number of row buffer hits during reads
222system.physmem.writeRowHits 0 # Number of row buffer hits during writes
223system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads
224system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
225system.physmem.avgGap 1735355.97 # Average gap between requests
226system.physmem.pageHitRate 91.15 # Row buffer hit rate, read and write combined
227system.physmem.prechargeAllPercent 1.09 # Percentage of time for which DRAM has all the banks in precharge state
228system.membus.throughput 36879767 # Throughput (bytes/s)
229system.membus.trans_dist::ReadReq 976 # Transaction distribution
230system.membus.trans_dist::ReadResp 976 # Transaction distribution
231system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
232system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
233system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
234system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31030 # Packet count per connected master and slave (bytes)
236system.membus.pkt_count::total 31030 # Packet count per connected master and slave (bytes)
237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes)
238system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes)
239system.membus.data_through_bus 992896 # Total data (bytes)
240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
241system.membus.reqLayer0.occupancy 19225500 # Layer occupancy (ticks)
242system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
243system.membus.respLayer1.occupancy 144897999 # Layer occupancy (ticks)
244system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
245system.cpu_clk_domain.clock 500 # Clock period in ticks
246system.cpu.branchPred.lookups 26688187 # Number of BP lookups
247system.cpu.branchPred.condPredicted 22005801 # Number of conditional branches predicted
248system.cpu.branchPred.condIncorrect 842567 # Number of conditional branches incorrect
249system.cpu.branchPred.BTBLookups 11378681 # Number of BTB lookups
250system.cpu.branchPred.BTBHits 11285656 # Number of BTB hits
251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
252system.cpu.branchPred.BTBHitPct 99.182462 # BTB Hit Percentage
253system.cpu.branchPred.usedRAS 69960 # Number of times the RAS was used to get a target.
254system.cpu.branchPred.RASInCorrect 176 # Number of incorrect RAS predictions.
255system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
256system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
257system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
258system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
259system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
260system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
262system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 69 unchanged lines hidden (view full) ---

332system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
333system.cpu.itb.read_accesses 0 # DTB read accesses
334system.cpu.itb.write_accesses 0 # DTB write accesses
335system.cpu.itb.inst_accesses 0 # ITB inst accesses
336system.cpu.itb.hits 0 # DTB hits
337system.cpu.itb.misses 0 # DTB misses
338system.cpu.itb.accesses 0 # DTB accesses
339system.cpu.workload.num_syscalls 442 # Number of system calls
340system.cpu.numCycles 53845026 # number of cpu cycles simulated
341system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
342system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
343system.cpu.fetch.icacheStallCycles 14173388 # Number of cycles fetch is stalled on an Icache miss
344system.cpu.fetch.Insts 127901014 # Number of instructions fetch has processed
345system.cpu.fetch.Branches 26688187 # Number of branches that fetch encountered
346system.cpu.fetch.predictedBranches 11355616 # Number of branches that fetch has predicted taken
347system.cpu.fetch.Cycles 24038968 # Number of cycles fetch has run and was not squashing or blocked
348system.cpu.fetch.SquashCycles 4766662 # Number of cycles fetch has spent squashing
349system.cpu.fetch.BlockedCycles 11320590 # Number of cycles fetch has spent blocked
350system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
351system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps
352system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
353system.cpu.fetch.CacheLines 13845523 # Number of cache lines fetched
354system.cpu.fetch.IcacheSquashes 330018 # Number of outstanding Icache misses that were squashed
355system.cpu.fetch.rateDist::samples 53440501 # Number of instructions fetched each cycle (Total)
356system.cpu.fetch.rateDist::mean 2.409803 # Number of instructions fetched each cycle (Total)
357system.cpu.fetch.rateDist::stdev 3.214653 # Number of instructions fetched each cycle (Total)
358system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
359system.cpu.fetch.rateDist::0 29439765 55.09% 55.09% # Number of instructions fetched each cycle (Total)
360system.cpu.fetch.rateDist::1 3390250 6.34% 61.43% # Number of instructions fetched each cycle (Total)
361system.cpu.fetch.rateDist::2 2029247 3.80% 65.23% # Number of instructions fetched each cycle (Total)
362system.cpu.fetch.rateDist::3 1554755 2.91% 68.14% # Number of instructions fetched each cycle (Total)
363system.cpu.fetch.rateDist::4 1667292 3.12% 71.26% # Number of instructions fetched each cycle (Total)
364system.cpu.fetch.rateDist::5 2920236 5.46% 76.72% # Number of instructions fetched each cycle (Total)
365system.cpu.fetch.rateDist::6 1512043 2.83% 79.55% # Number of instructions fetched each cycle (Total)
366system.cpu.fetch.rateDist::7 1089860 2.04% 81.59% # Number of instructions fetched each cycle (Total)
367system.cpu.fetch.rateDist::8 9837053 18.41% 100.00% # Number of instructions fetched each cycle (Total)
368system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
369system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
370system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
371system.cpu.fetch.rateDist::total 53440501 # Number of instructions fetched each cycle (Total)
372system.cpu.fetch.branchRate 0.495648 # Number of branch fetches per cycle
373system.cpu.fetch.rate 2.375354 # Number of inst fetches per cycle
374system.cpu.decode.IdleCycles 16937222 # Number of cycles decode is idle
375system.cpu.decode.BlockedCycles 9166719 # Number of cycles decode is blocked
376system.cpu.decode.RunCycles 22408314 # Number of cycles decode is running
377system.cpu.decode.UnblockCycles 1029433 # Number of cycles decode is unblocking
378system.cpu.decode.SquashCycles 3898813 # Number of cycles decode is squashing
379system.cpu.decode.BranchResolved 4444354 # Number of times decode resolved a branch
380system.cpu.decode.BranchMispred 8681 # Number of times decode detected a branch misprediction
381system.cpu.decode.DecodedInsts 126084070 # Number of instructions handled by decode
382system.cpu.decode.SquashedInsts 42675 # Number of squashed instructions handled by decode
383system.cpu.rename.SquashCycles 3898813 # Number of cycles rename is squashing
384system.cpu.rename.IdleCycles 18718559 # Number of cycles rename is idle
385system.cpu.rename.BlockCycles 3593311 # Number of cycles rename is blocking
386system.cpu.rename.serializeStallCycles 188330 # count of cycles rename stalled for serializing inst
387system.cpu.rename.RunCycles 21554671 # Number of cycles rename is running
388system.cpu.rename.UnblockCycles 5486817 # Number of cycles rename is unblocking
389system.cpu.rename.RenamedInsts 123168222 # Number of instructions processed by rename
390system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
391system.cpu.rename.IQFullEvents 424808 # Number of times rename has blocked due to IQ full
392system.cpu.rename.LSQFullEvents 4599857 # Number of times rename has blocked due to LSQ full
393system.cpu.rename.FullRegisterEvents 1460 # Number of times there has been no free registers
394system.cpu.rename.RenamedOperands 143625263 # Number of destination operands rename has renamed
395system.cpu.rename.RenameLookups 536555031 # Number of register rename lookups that rename has made
396system.cpu.rename.int_rename_lookups 500037832 # Number of integer rename lookups
397system.cpu.rename.fp_rename_lookups 718 # Number of floating rename lookups
398system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
399system.cpu.rename.UndoneMaps 36211077 # Number of HB maps that are undone due to squashing
400system.cpu.rename.serializingInsts 4609 # count of serializing insts renamed
401system.cpu.rename.tempSerializingInsts 4607 # count of temporary serializing insts renamed
402system.cpu.rename.skidInsts 12545622 # count of insts added to the skid buffer
403system.cpu.memDep0.insertedLoads 29481569 # Number of loads inserted to the mem dependence unit.
404system.cpu.memDep0.insertedStores 5520172 # Number of stores inserted to the mem dependence unit.
405system.cpu.memDep0.conflictingLoads 2131780 # Number of conflicting loads.
406system.cpu.memDep0.conflictingStores 1278964 # Number of conflicting stores.
407system.cpu.iq.iqInstsAdded 118183319 # Number of instructions added to the IQ (excludes non-spec)
408system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ
409system.cpu.iq.iqInstsIssued 105169429 # Number of instructions issued
410system.cpu.iq.iqSquashedInstsIssued 79348 # Number of squashed instructions issued
411system.cpu.iq.iqSquashedInstsExamined 26754797 # Number of squashed instructions iterated over during squash; mainly for profiling
412system.cpu.iq.iqSquashedOperandsExamined 65616265 # Number of squashed operands that are examined and possibly removed from graph
413system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed
414system.cpu.iq.issued_per_cycle::samples 53440501 # Number of insts issued each cycle
415system.cpu.iq.issued_per_cycle::mean 1.967972 # Number of insts issued each cycle
416system.cpu.iq.issued_per_cycle::stdev 1.909350 # Number of insts issued each cycle
417system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
418system.cpu.iq.issued_per_cycle::0 15384800 28.79% 28.79% # Number of insts issued each cycle
419system.cpu.iq.issued_per_cycle::1 11651642 21.80% 50.59% # Number of insts issued each cycle
420system.cpu.iq.issued_per_cycle::2 8259769 15.46% 66.05% # Number of insts issued each cycle
421system.cpu.iq.issued_per_cycle::3 6813523 12.75% 78.80% # Number of insts issued each cycle
422system.cpu.iq.issued_per_cycle::4 4933870 9.23% 88.03% # Number of insts issued each cycle
423system.cpu.iq.issued_per_cycle::5 2968386 5.55% 93.58% # Number of insts issued each cycle
424system.cpu.iq.issued_per_cycle::6 2461371 4.61% 98.19% # Number of insts issued each cycle
425system.cpu.iq.issued_per_cycle::7 525076 0.98% 99.17% # Number of insts issued each cycle
426system.cpu.iq.issued_per_cycle::8 442064 0.83% 100.00% # Number of insts issued each cycle
427system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
428system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
429system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
430system.cpu.iq.issued_per_cycle::total 53440501 # Number of insts issued each cycle
431system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
432system.cpu.iq.fu_full::IntAlu 46222 6.98% 6.98% # attempts to use FU when none available
433system.cpu.iq.fu_full::IntMult 26 0.00% 6.98% # attempts to use FU when none available
434system.cpu.iq.fu_full::IntDiv 0 0.00% 6.98% # attempts to use FU when none available
435system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.98% # attempts to use FU when none available
436system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.98% # attempts to use FU when none available
437system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.98% # attempts to use FU when none available
438system.cpu.iq.fu_full::FloatMult 0 0.00% 6.98% # attempts to use FU when none available
439system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.98% # attempts to use FU when none available
440system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.98% # attempts to use FU when none available
441system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.98% # attempts to use FU when none available
442system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.98% # attempts to use FU when none available
443system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.98% # attempts to use FU when none available
444system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.98% # attempts to use FU when none available
445system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.98% # attempts to use FU when none available
446system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.98% # attempts to use FU when none available
447system.cpu.iq.fu_full::SimdMult 0 0.00% 6.98% # attempts to use FU when none available
448system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.98% # attempts to use FU when none available
449system.cpu.iq.fu_full::SimdShift 0 0.00% 6.98% # attempts to use FU when none available
450system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.98% # attempts to use FU when none available
451system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.98% # attempts to use FU when none available
452system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.98% # attempts to use FU when none available
453system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.98% # attempts to use FU when none available
454system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.98% # attempts to use FU when none available
455system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.98% # attempts to use FU when none available
456system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.98% # attempts to use FU when none available
457system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.98% # attempts to use FU when none available
458system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.98% # attempts to use FU when none available
459system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.98% # attempts to use FU when none available
460system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.98% # attempts to use FU when none available
461system.cpu.iq.fu_full::MemRead 339934 51.34% 58.33% # attempts to use FU when none available
462system.cpu.iq.fu_full::MemWrite 275932 41.67% 100.00% # attempts to use FU when none available
463system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
464system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
465system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
466system.cpu.iq.FU_type_0::IntAlu 74431142 70.77% 70.77% # Type of FU issued
467system.cpu.iq.FU_type_0::IntMult 10980 0.01% 70.78% # Type of FU issued
468system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
469system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
470system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
471system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
472system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
473system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
474system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
476system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
477system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
478system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
479system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
480system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
481system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
482system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
483system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
484system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
485system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
486system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
487system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
488system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
489system.cpu.iq.FU_type_0::SimdFloatCvt 132 0.00% 70.78% # Type of FU issued
490system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
491system.cpu.iq.FU_type_0::SimdFloatMisc 172 0.00% 70.78% # Type of FU issued
492system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
493system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued
494system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
495system.cpu.iq.FU_type_0::MemRead 25611933 24.35% 95.14% # Type of FU issued
496system.cpu.iq.FU_type_0::MemWrite 5115067 4.86% 100.00% # Type of FU issued
497system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
498system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
499system.cpu.iq.FU_type_0::total 105169429 # Type of FU issued
500system.cpu.iq.rate 1.953187 # Inst issue rate
501system.cpu.iq.fu_busy_cnt 662114 # FU busy when requested
502system.cpu.iq.fu_busy_rate 0.006296 # FU busy rate (busy events/executed inst)
503system.cpu.iq.int_inst_queue_reads 264520145 # Number of integer instruction queue reads
504system.cpu.iq.int_inst_queue_writes 144951370 # Number of integer instruction queue writes
505system.cpu.iq.int_inst_queue_wakeup_accesses 102696867 # Number of integer instruction queue wakeup accesses
506system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads
507system.cpu.iq.fp_inst_queue_writes 925 # Number of floating instruction queue writes
508system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses
509system.cpu.iq.int_alu_accesses 105831206 # Number of integer alu accesses
510system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses
511system.cpu.iew.lsq.thread0.forwLoads 441415 # Number of loads that had data forwarded from stores
512system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
513system.cpu.iew.lsq.thread0.squashedLoads 6907603 # Number of loads squashed
514system.cpu.iew.lsq.thread0.ignoredResponses 6432 # Number of memory responses ignored because the instruction is squashed
515system.cpu.iew.lsq.thread0.memOrderViolation 6446 # Number of memory ordering violations
516system.cpu.iew.lsq.thread0.squashedStores 775328 # Number of stores squashed
517system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
518system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
519system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
520system.cpu.iew.lsq.thread0.cacheBlocked 31602 # Number of times an access to memory failed due to the cache being blocked
521system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
522system.cpu.iew.iewSquashCycles 3898813 # Number of cycles IEW is squashing
523system.cpu.iew.iewBlockCycles 959371 # Number of cycles IEW is blocking
524system.cpu.iew.iewUnblockCycles 127029 # Number of cycles IEW is unblocking
525system.cpu.iew.iewDispatchedInsts 118204490 # Number of instructions dispatched to IQ
526system.cpu.iew.iewDispSquashedInsts 309594 # Number of squashed instructions skipped by dispatch
527system.cpu.iew.iewDispLoadInsts 29481569 # Number of dispatched load instructions
528system.cpu.iew.iewDispStoreInsts 5520172 # Number of dispatched store instructions
529system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions
530system.cpu.iew.iewIQFullEvents 66074 # Number of times the IQ has become full, causing a stall
531system.cpu.iew.iewLSQFullEvents 6711 # Number of times the LSQ has become full, causing a stall
532system.cpu.iew.memOrderViolationEvents 6446 # Number of memory order violations
533system.cpu.iew.predictedTakenIncorrect 446623 # Number of branches that were predicted taken incorrectly
534system.cpu.iew.predictedNotTakenIncorrect 445838 # Number of branches that were predicted not taken incorrectly
535system.cpu.iew.branchMispredicts 892461 # Number of branch mispredicts detected at execute
536system.cpu.iew.iewExecutedInsts 104194994 # Number of executed instructions
537system.cpu.iew.iewExecLoadInsts 25292197 # Number of load instructions executed
538system.cpu.iew.iewExecSquashedInsts 974435 # Number of squashed instructions skipped in execute
539system.cpu.iew.exec_swp 0 # number of swp insts executed
540system.cpu.iew.exec_nop 12694 # number of nop insts executed
541system.cpu.iew.exec_refs 30350924 # number of memory reference insts executed
542system.cpu.iew.exec_branches 21328461 # Number of branches executed
543system.cpu.iew.exec_stores 5058727 # Number of stores executed
544system.cpu.iew.exec_rate 1.935090 # Inst execution rate
545system.cpu.iew.wb_sent 102975092 # cumulative count of insts sent to commit
546system.cpu.iew.wb_count 102697154 # cumulative count of insts written-back
547system.cpu.iew.wb_producers 62242577 # num instructions producing a value
548system.cpu.iew.wb_consumers 104291686 # num instructions consuming a value
549system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
550system.cpu.iew.wb_rate 1.907273 # insts written-back per cycle
551system.cpu.iew.wb_fanout 0.596812 # average fanout of values written-back
552system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
553system.cpu.commit.commitSquashedInsts 26954537 # The number of squashed insts skipped by commit
554system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
555system.cpu.commit.branchMispredicts 833969 # The number of times a branch was mispredicted
556system.cpu.commit.committed_per_cycle::samples 49541688 # Number of insts commited each cycle
557system.cpu.commit.committed_per_cycle::mean 1.841943 # Number of insts commited each cycle
558system.cpu.commit.committed_per_cycle::stdev 2.539958 # Number of insts commited each cycle
559system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
560system.cpu.commit.committed_per_cycle::0 20036957 40.44% 40.44% # Number of insts commited each cycle
561system.cpu.commit.committed_per_cycle::1 13159597 26.56% 67.01% # Number of insts commited each cycle
562system.cpu.commit.committed_per_cycle::2 4169965 8.42% 75.42% # Number of insts commited each cycle
563system.cpu.commit.committed_per_cycle::3 3431804 6.93% 82.35% # Number of insts commited each cycle
564system.cpu.commit.committed_per_cycle::4 1536139 3.10% 85.45% # Number of insts commited each cycle
565system.cpu.commit.committed_per_cycle::5 734203 1.48% 86.93% # Number of insts commited each cycle
566system.cpu.commit.committed_per_cycle::6 944467 1.91% 88.84% # Number of insts commited each cycle
567system.cpu.commit.committed_per_cycle::7 252800 0.51% 89.35% # Number of insts commited each cycle
568system.cpu.commit.committed_per_cycle::8 5275756 10.65% 100.00% # Number of insts commited each cycle
569system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
570system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
571system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
572system.cpu.commit.committed_per_cycle::total 49541688 # Number of insts commited each cycle
573system.cpu.commit.committedInsts 90602407 # Number of instructions committed
574system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
575system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
576system.cpu.commit.refs 27318810 # Number of memory references committed
577system.cpu.commit.loads 22573966 # Number of loads committed
578system.cpu.commit.membars 3888 # Number of memory barriers committed
579system.cpu.commit.branches 18732304 # Number of branches committed
580system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
581system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
582system.cpu.commit.function_calls 56148 # Number of function calls committed.
583system.cpu.commit.bw_lim_events 5275756 # number cycles where commit BW limit reached
584system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
585system.cpu.rob.rob_reads 162467695 # The number of ROB reads
586system.cpu.rob.rob_writes 240333520 # The number of ROB writes
587system.cpu.timesIdled 46195 # Number of times that the entire CPU went into an idle state and unscheduled itself
588system.cpu.idleCycles 404525 # Total number of cycles that the CPU has spent unscheduled due to idling
589system.cpu.committedInsts 90589798 # Number of Instructions Simulated
590system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
591system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
592system.cpu.cpi 0.594383 # CPI: Cycles Per Instruction
593system.cpu.cpi_total 0.594383 # CPI: Total CPI of All Threads
594system.cpu.ipc 1.682417 # IPC: Instructions Per Cycle
595system.cpu.ipc_total 1.682417 # IPC: Total IPC of All Threads
596system.cpu.int_regfile_reads 495621667 # number of integer regfile reads
597system.cpu.int_regfile_writes 120557380 # number of integer regfile writes
598system.cpu.fp_regfile_reads 149 # number of floating regfile reads
599system.cpu.fp_regfile_writes 361 # number of floating regfile writes
600system.cpu.misc_regfile_reads 29211256 # number of misc regfile reads
601system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
602system.cpu.toL2Bus.throughput 4495994050 # Throughput (bytes/s)
603system.cpu.toL2Bus.trans_dist::ReadReq 904654 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::ReadResp 904654 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::Writeback 942932 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::ReadExReq 43718 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::ReadExResp 43718 # Transaction distribution
610system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1467 # Packet count per connected master and slave (bytes)
611system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838210 # Packet count per connected master and slave (bytes)
612system.cpu.toL2Bus.pkt_count::total 2839677 # Packet count per connected master and slave (bytes)
613system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46912 # Cumulative packet size per connected master and slave (bytes)
614system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120996480 # Cumulative packet size per connected master and slave (bytes)
615system.cpu.toL2Bus.tot_pkt_size::total 121043392 # Cumulative packet size per connected master and slave (bytes)
616system.cpu.toL2Bus.data_through_bus 121043392 # Total data (bytes)
617system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes)
618system.cpu.toL2Bus.reqLayer0.occupancy 1888584500 # Layer occupancy (ticks)
619system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
620system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks)
621system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
622system.cpu.toL2Bus.respLayer1.occupancy 1423941741 # Layer occupancy (ticks)
623system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
624system.cpu.icache.tags.replacements 3 # number of replacements
625system.cpu.icache.tags.tagsinuse 632.458088 # Cycle average of tags in use
626system.cpu.icache.tags.total_refs 13844537 # Total number of references to valid blocks.
627system.cpu.icache.tags.sampled_refs 733 # Sample count of references to valid blocks.
628system.cpu.icache.tags.avg_refs 18887.499318 # Average number of references to valid blocks.
629system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
630system.cpu.icache.tags.occ_blocks::cpu.inst 632.458088 # Average occupied blocks per requestor
631system.cpu.icache.tags.occ_percent::cpu.inst 0.308817 # Average percentage of cache occupancy
632system.cpu.icache.tags.occ_percent::total 0.308817 # Average percentage of cache occupancy
633system.cpu.icache.tags.occ_task_id_blocks::1024 730 # Occupied blocks per task id
634system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
635system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
636system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
637system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id
638system.cpu.icache.tags.occ_task_id_percent::1024 0.356445 # Percentage of cache occupancy per task id
639system.cpu.icache.tags.tag_accesses 27691778 # Number of tag accesses
640system.cpu.icache.tags.data_accesses 27691778 # Number of data accesses
641system.cpu.icache.ReadReq_hits::cpu.inst 13844537 # number of ReadReq hits
642system.cpu.icache.ReadReq_hits::total 13844537 # number of ReadReq hits
643system.cpu.icache.demand_hits::cpu.inst 13844537 # number of demand (read+write) hits
644system.cpu.icache.demand_hits::total 13844537 # number of demand (read+write) hits
645system.cpu.icache.overall_hits::cpu.inst 13844537 # number of overall hits
646system.cpu.icache.overall_hits::total 13844537 # number of overall hits
647system.cpu.icache.ReadReq_misses::cpu.inst 985 # number of ReadReq misses
648system.cpu.icache.ReadReq_misses::total 985 # number of ReadReq misses
649system.cpu.icache.demand_misses::cpu.inst 985 # number of demand (read+write) misses
650system.cpu.icache.demand_misses::total 985 # number of demand (read+write) misses
651system.cpu.icache.overall_misses::cpu.inst 985 # number of overall misses
652system.cpu.icache.overall_misses::total 985 # number of overall misses
653system.cpu.icache.ReadReq_miss_latency::cpu.inst 65965748 # number of ReadReq miss cycles
654system.cpu.icache.ReadReq_miss_latency::total 65965748 # number of ReadReq miss cycles
655system.cpu.icache.demand_miss_latency::cpu.inst 65965748 # number of demand (read+write) miss cycles
656system.cpu.icache.demand_miss_latency::total 65965748 # number of demand (read+write) miss cycles
657system.cpu.icache.overall_miss_latency::cpu.inst 65965748 # number of overall miss cycles
658system.cpu.icache.overall_miss_latency::total 65965748 # number of overall miss cycles
659system.cpu.icache.ReadReq_accesses::cpu.inst 13845522 # number of ReadReq accesses(hits+misses)
660system.cpu.icache.ReadReq_accesses::total 13845522 # number of ReadReq accesses(hits+misses)
661system.cpu.icache.demand_accesses::cpu.inst 13845522 # number of demand (read+write) accesses
662system.cpu.icache.demand_accesses::total 13845522 # number of demand (read+write) accesses
663system.cpu.icache.overall_accesses::cpu.inst 13845522 # number of overall (read+write) accesses
664system.cpu.icache.overall_accesses::total 13845522 # number of overall (read+write) accesses
665system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
666system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
667system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
668system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
669system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
670system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
671system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66970.302538 # average ReadReq miss latency
672system.cpu.icache.ReadReq_avg_miss_latency::total 66970.302538 # average ReadReq miss latency
673system.cpu.icache.demand_avg_miss_latency::cpu.inst 66970.302538 # average overall miss latency
674system.cpu.icache.demand_avg_miss_latency::total 66970.302538 # average overall miss latency
675system.cpu.icache.overall_avg_miss_latency::cpu.inst 66970.302538 # average overall miss latency
676system.cpu.icache.overall_avg_miss_latency::total 66970.302538 # average overall miss latency
677system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked
678system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
679system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
680system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
681system.cpu.icache.avg_blocked_cycles::no_mshrs 49.666667 # average number of cycles each access was blocked
682system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
683system.cpu.icache.fast_writes 0 # number of fast writes performed
684system.cpu.icache.cache_copies 0 # number of cache copies performed
685system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits
686system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits
687system.cpu.icache.demand_mshr_hits::cpu.inst 251 # number of demand (read+write) MSHR hits
688system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits
689system.cpu.icache.overall_mshr_hits::cpu.inst 251 # number of overall MSHR hits
690system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits
691system.cpu.icache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses
692system.cpu.icache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses
693system.cpu.icache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses
694system.cpu.icache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses
695system.cpu.icache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses
696system.cpu.icache.overall_mshr_misses::total 734 # number of overall MSHR misses
697system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51030750 # number of ReadReq MSHR miss cycles
698system.cpu.icache.ReadReq_mshr_miss_latency::total 51030750 # number of ReadReq MSHR miss cycles
699system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51030750 # number of demand (read+write) MSHR miss cycles
700system.cpu.icache.demand_mshr_miss_latency::total 51030750 # number of demand (read+write) MSHR miss cycles
701system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51030750 # number of overall MSHR miss cycles
702system.cpu.icache.overall_mshr_miss_latency::total 51030750 # number of overall MSHR miss cycles
703system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
704system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
705system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
706system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
707system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
708system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
709system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69524.182561 # average ReadReq mshr miss latency
710system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69524.182561 # average ReadReq mshr miss latency
711system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69524.182561 # average overall mshr miss latency
712system.cpu.icache.demand_avg_mshr_miss_latency::total 69524.182561 # average overall mshr miss latency
713system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69524.182561 # average overall mshr miss latency
714system.cpu.icache.overall_avg_mshr_miss_latency::total 69524.182561 # average overall mshr miss latency
715system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
716system.cpu.l2cache.tags.replacements 0 # number of replacements
717system.cpu.l2cache.tags.tagsinuse 10726.796939 # Cycle average of tags in use
718system.cpu.l2cache.tags.total_refs 1831454 # Total number of references to valid blocks.
719system.cpu.l2cache.tags.sampled_refs 15497 # Sample count of references to valid blocks.
720system.cpu.l2cache.tags.avg_refs 118.181196 # Average number of references to valid blocks.
721system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
722system.cpu.l2cache.tags.occ_blocks::writebacks 9879.688406 # Average occupied blocks per requestor
723system.cpu.l2cache.tags.occ_blocks::cpu.inst 618.475949 # Average occupied blocks per requestor
724system.cpu.l2cache.tags.occ_blocks::cpu.data 228.632584 # Average occupied blocks per requestor
725system.cpu.l2cache.tags.occ_percent::writebacks 0.301504 # Average percentage of cache occupancy
726system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018874 # Average percentage of cache occupancy
727system.cpu.l2cache.tags.occ_percent::cpu.data 0.006977 # Average percentage of cache occupancy
728system.cpu.l2cache.tags.occ_percent::total 0.327356 # Average percentage of cache occupancy
729system.cpu.l2cache.tags.occ_task_id_blocks::1024 15497 # Occupied blocks per task id
730system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
731system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
732system.cpu.l2cache.tags.age_task_id_blocks_1024::2 514 # Occupied blocks per task id
733system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1300 # Occupied blocks per task id
734system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13616 # Occupied blocks per task id
735system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472931 # Percentage of cache occupancy per task id
736system.cpu.l2cache.tags.tag_accesses 15189647 # Number of tag accesses
737system.cpu.l2cache.tags.data_accesses 15189647 # Number of data accesses
738system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits
739system.cpu.l2cache.ReadReq_hits::cpu.data 903641 # number of ReadReq hits
740system.cpu.l2cache.ReadReq_hits::total 903666 # number of ReadReq hits
741system.cpu.l2cache.Writeback_hits::writebacks 942932 # number of Writeback hits
742system.cpu.l2cache.Writeback_hits::total 942932 # number of Writeback hits
743system.cpu.l2cache.ReadExReq_hits::cpu.data 29180 # number of ReadExReq hits
744system.cpu.l2cache.ReadExReq_hits::total 29180 # number of ReadExReq hits
745system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits
746system.cpu.l2cache.demand_hits::cpu.data 932821 # number of demand (read+write) hits
747system.cpu.l2cache.demand_hits::total 932846 # number of demand (read+write) hits
748system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits
749system.cpu.l2cache.overall_hits::cpu.data 932821 # number of overall hits
750system.cpu.l2cache.overall_hits::total 932846 # number of overall hits
751system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses
752system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses
753system.cpu.l2cache.ReadReq_misses::total 987 # number of ReadReq misses
754system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
755system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
756system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
757system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
758system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses
759system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses
760system.cpu.l2cache.demand_misses::total 15525 # number of demand (read+write) misses
761system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses
762system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses
763system.cpu.l2cache.overall_misses::total 15525 # number of overall misses
764system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50040500 # number of ReadReq miss cycles
765system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21343000 # number of ReadReq miss cycles
766system.cpu.l2cache.ReadReq_miss_latency::total 71383500 # number of ReadReq miss cycles
767system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 975716500 # number of ReadExReq miss cycles
768system.cpu.l2cache.ReadExReq_miss_latency::total 975716500 # number of ReadExReq miss cycles
769system.cpu.l2cache.demand_miss_latency::cpu.inst 50040500 # number of demand (read+write) miss cycles
770system.cpu.l2cache.demand_miss_latency::cpu.data 997059500 # number of demand (read+write) miss cycles
771system.cpu.l2cache.demand_miss_latency::total 1047100000 # number of demand (read+write) miss cycles
772system.cpu.l2cache.overall_miss_latency::cpu.inst 50040500 # number of overall miss cycles
773system.cpu.l2cache.overall_miss_latency::cpu.data 997059500 # number of overall miss cycles
774system.cpu.l2cache.overall_miss_latency::total 1047100000 # number of overall miss cycles
775system.cpu.l2cache.ReadReq_accesses::cpu.inst 733 # number of ReadReq accesses(hits+misses)
776system.cpu.l2cache.ReadReq_accesses::cpu.data 903920 # number of ReadReq accesses(hits+misses)
777system.cpu.l2cache.ReadReq_accesses::total 904653 # number of ReadReq accesses(hits+misses)
778system.cpu.l2cache.Writeback_accesses::writebacks 942932 # number of Writeback accesses(hits+misses)
779system.cpu.l2cache.Writeback_accesses::total 942932 # number of Writeback accesses(hits+misses)
780system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
781system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
782system.cpu.l2cache.ReadExReq_accesses::cpu.data 43718 # number of ReadExReq accesses(hits+misses)
783system.cpu.l2cache.ReadExReq_accesses::total 43718 # number of ReadExReq accesses(hits+misses)
784system.cpu.l2cache.demand_accesses::cpu.inst 733 # number of demand (read+write) accesses
785system.cpu.l2cache.demand_accesses::cpu.data 947638 # number of demand (read+write) accesses
786system.cpu.l2cache.demand_accesses::total 948371 # number of demand (read+write) accesses
787system.cpu.l2cache.overall_accesses::cpu.inst 733 # number of overall (read+write) accesses
788system.cpu.l2cache.overall_accesses::cpu.data 947638 # number of overall (read+write) accesses
789system.cpu.l2cache.overall_accesses::total 948371 # number of overall (read+write) accesses
790system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965894 # miss rate for ReadReq accesses
791system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses
792system.cpu.l2cache.ReadReq_miss_rate::total 0.001091 # miss rate for ReadReq accesses
793system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
794system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
795system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332540 # miss rate for ReadExReq accesses
796system.cpu.l2cache.ReadExReq_miss_rate::total 0.332540 # miss rate for ReadExReq accesses
797system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965894 # miss rate for demand accesses
798system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses
799system.cpu.l2cache.demand_miss_rate::total 0.016370 # miss rate for demand accesses
800system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965894 # miss rate for overall accesses
801system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses
802system.cpu.l2cache.overall_miss_rate::total 0.016370 # miss rate for overall accesses
803system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70678.672316 # average ReadReq miss latency
804system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76498.207885 # average ReadReq miss latency
805system.cpu.l2cache.ReadReq_avg_miss_latency::total 72323.708207 # average ReadReq miss latency
806system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67114.905764 # average ReadExReq miss latency
807system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67114.905764 # average ReadExReq miss latency
808system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70678.672316 # average overall miss latency
809system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67291.590740 # average overall miss latency
810system.cpu.l2cache.demand_avg_miss_latency::total 67446.054750 # average overall miss latency
811system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70678.672316 # average overall miss latency
812system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67291.590740 # average overall miss latency
813system.cpu.l2cache.overall_avg_miss_latency::total 67446.054750 # average overall miss latency
814system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
815system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
816system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
817system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
818system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
819system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
820system.cpu.l2cache.fast_writes 0 # number of fast writes performed
821system.cpu.l2cache.cache_copies 0 # number of cache copies performed
822system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
823system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
824system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
825system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
826system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
827system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
828system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
829system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
830system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
831system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses
832system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses
833system.cpu.l2cache.ReadReq_mshr_misses::total 976 # number of ReadReq MSHR misses
834system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
835system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
836system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
837system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
838system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses
839system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses
840system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses
841system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses
842system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses
843system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses
844system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41129750 # number of ReadReq MSHR miss cycles
845system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17372750 # number of ReadReq MSHR miss cycles
846system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58502500 # number of ReadReq MSHR miss cycles
847system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles
848system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles
849system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 793837000 # number of ReadExReq MSHR miss cycles
850system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 793837000 # number of ReadExReq MSHR miss cycles
851system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41129750 # number of demand (read+write) MSHR miss cycles
852system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 811209750 # number of demand (read+write) MSHR miss cycles
853system.cpu.l2cache.demand_mshr_miss_latency::total 852339500 # number of demand (read+write) MSHR miss cycles
854system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41129750 # number of overall MSHR miss cycles
855system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 811209750 # number of overall MSHR miss cycles
856system.cpu.l2cache.overall_mshr_miss_latency::total 852339500 # number of overall MSHR miss cycles
857system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for ReadReq accesses
858system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses
859system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001079 # mshr miss rate for ReadReq accesses
860system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
861system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
862system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332540 # mshr miss rate for ReadExReq accesses
863system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332540 # mshr miss rate for ReadExReq accesses
864system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for demand accesses
865system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses
866system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses
867system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for overall accesses
868system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses
869system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses
870system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58175.035361 # average ReadReq mshr miss latency
871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64582.713755 # average ReadReq mshr miss latency
872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59941.086066 # average ReadReq mshr miss latency
873system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
874system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
875system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54604.278443 # average ReadExReq mshr miss latency
876system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54604.278443 # average ReadExReq mshr miss latency
877system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58175.035361 # average overall mshr miss latency
878system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54785.557507 # average overall mshr miss latency
879system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54940.021916 # average overall mshr miss latency
880system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58175.035361 # average overall mshr miss latency
881system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54785.557507 # average overall mshr miss latency
882system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54940.021916 # average overall mshr miss latency
883system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
884system.cpu.dcache.tags.replacements 943542 # number of replacements
885system.cpu.dcache.tags.tagsinuse 3671.682953 # Cycle average of tags in use
886system.cpu.dcache.tags.total_refs 28143982 # Total number of references to valid blocks.
887system.cpu.dcache.tags.sampled_refs 947638 # Sample count of references to valid blocks.
888system.cpu.dcache.tags.avg_refs 29.699086 # Average number of references to valid blocks.
889system.cpu.dcache.tags.warmup_cycle 8008531250 # Cycle when the warmup percentage was hit.
890system.cpu.dcache.tags.occ_blocks::cpu.data 3671.682953 # Average occupied blocks per requestor
891system.cpu.dcache.tags.occ_percent::cpu.data 0.896407 # Average percentage of cache occupancy
892system.cpu.dcache.tags.occ_percent::total 0.896407 # Average percentage of cache occupancy
893system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
894system.cpu.dcache.tags.age_task_id_blocks_1024::0 464 # Occupied blocks per task id
895system.cpu.dcache.tags.age_task_id_blocks_1024::1 3129 # Occupied blocks per task id
896system.cpu.dcache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id
897system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
898system.cpu.dcache.tags.tag_accesses 59988388 # Number of tag accesses
899system.cpu.dcache.tags.data_accesses 59988388 # Number of data accesses
900system.cpu.dcache.ReadReq_hits::cpu.data 23603660 # number of ReadReq hits
901system.cpu.dcache.ReadReq_hits::total 23603660 # number of ReadReq hits
902system.cpu.dcache.WriteReq_hits::cpu.data 4532519 # number of WriteReq hits
903system.cpu.dcache.WriteReq_hits::total 4532519 # number of WriteReq hits
904system.cpu.dcache.LoadLockedReq_hits::cpu.data 3912 # number of LoadLockedReq hits
905system.cpu.dcache.LoadLockedReq_hits::total 3912 # number of LoadLockedReq hits
906system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
907system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
908system.cpu.dcache.demand_hits::cpu.data 28136179 # number of demand (read+write) hits
909system.cpu.dcache.demand_hits::total 28136179 # number of demand (read+write) hits
910system.cpu.dcache.overall_hits::cpu.data 28136179 # number of overall hits
911system.cpu.dcache.overall_hits::total 28136179 # number of overall hits
912system.cpu.dcache.ReadReq_misses::cpu.data 1173928 # number of ReadReq misses
913system.cpu.dcache.ReadReq_misses::total 1173928 # number of ReadReq misses
914system.cpu.dcache.WriteReq_misses::cpu.data 202462 # number of WriteReq misses
915system.cpu.dcache.WriteReq_misses::total 202462 # number of WriteReq misses
916system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
917system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
918system.cpu.dcache.demand_misses::cpu.data 1376390 # number of demand (read+write) misses
919system.cpu.dcache.demand_misses::total 1376390 # number of demand (read+write) misses
920system.cpu.dcache.overall_misses::cpu.data 1376390 # number of overall misses
921system.cpu.dcache.overall_misses::total 1376390 # number of overall misses
922system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893768230 # number of ReadReq miss cycles
923system.cpu.dcache.ReadReq_miss_latency::total 13893768230 # number of ReadReq miss cycles
924system.cpu.dcache.WriteReq_miss_latency::cpu.data 8571552365 # number of WriteReq miss cycles
925system.cpu.dcache.WriteReq_miss_latency::total 8571552365 # number of WriteReq miss cycles
926system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles
927system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles
928system.cpu.dcache.demand_miss_latency::cpu.data 22465320595 # number of demand (read+write) miss cycles
929system.cpu.dcache.demand_miss_latency::total 22465320595 # number of demand (read+write) miss cycles
930system.cpu.dcache.overall_miss_latency::cpu.data 22465320595 # number of overall miss cycles
931system.cpu.dcache.overall_miss_latency::total 22465320595 # number of overall miss cycles
932system.cpu.dcache.ReadReq_accesses::cpu.data 24777588 # number of ReadReq accesses(hits+misses)
933system.cpu.dcache.ReadReq_accesses::total 24777588 # number of ReadReq accesses(hits+misses)
934system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
935system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
936system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919 # number of LoadLockedReq accesses(hits+misses)
937system.cpu.dcache.LoadLockedReq_accesses::total 3919 # number of LoadLockedReq accesses(hits+misses)
938system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
939system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
940system.cpu.dcache.demand_accesses::cpu.data 29512569 # number of demand (read+write) accesses
941system.cpu.dcache.demand_accesses::total 29512569 # number of demand (read+write) accesses
942system.cpu.dcache.overall_accesses::cpu.data 29512569 # number of overall (read+write) accesses
943system.cpu.dcache.overall_accesses::total 29512569 # number of overall (read+write) accesses
944system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047379 # miss rate for ReadReq accesses
945system.cpu.dcache.ReadReq_miss_rate::total 0.047379 # miss rate for ReadReq accesses
946system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042759 # miss rate for WriteReq accesses
947system.cpu.dcache.WriteReq_miss_rate::total 0.042759 # miss rate for WriteReq accesses
948system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses
949system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses
950system.cpu.dcache.demand_miss_rate::cpu.data 0.046637 # miss rate for demand accesses
951system.cpu.dcache.demand_miss_rate::total 0.046637 # miss rate for demand accesses
952system.cpu.dcache.overall_miss_rate::cpu.data 0.046637 # miss rate for overall accesses
953system.cpu.dcache.overall_miss_rate::total 0.046637 # miss rate for overall accesses
954system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.281406 # average ReadReq miss latency
955system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.281406 # average ReadReq miss latency
956system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42336.598300 # average WriteReq miss latency
957system.cpu.dcache.WriteReq_avg_miss_latency::total 42336.598300 # average WriteReq miss latency
958system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency
959system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency
960system.cpu.dcache.demand_avg_miss_latency::cpu.data 16321.915006 # average overall miss latency
961system.cpu.dcache.demand_avg_miss_latency::total 16321.915006 # average overall miss latency
962system.cpu.dcache.overall_avg_miss_latency::cpu.data 16321.915006 # average overall miss latency
963system.cpu.dcache.overall_avg_miss_latency::total 16321.915006 # average overall miss latency
964system.cpu.dcache.blocked_cycles::no_mshrs 154484 # number of cycles access was blocked
965system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
966system.cpu.dcache.blocked::no_mshrs 23933 # number of cycles access was blocked
967system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
968system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.454853 # average number of cycles each access was blocked
969system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
970system.cpu.dcache.fast_writes 0 # number of fast writes performed
971system.cpu.dcache.cache_copies 0 # number of cache copies performed
972system.cpu.dcache.writebacks::writebacks 942932 # number of writebacks
973system.cpu.dcache.writebacks::total 942932 # number of writebacks
974system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269988 # number of ReadReq MSHR hits
975system.cpu.dcache.ReadReq_mshr_hits::total 269988 # number of ReadReq MSHR hits
976system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158763 # number of WriteReq MSHR hits
977system.cpu.dcache.WriteReq_mshr_hits::total 158763 # number of WriteReq MSHR hits
978system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
979system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
980system.cpu.dcache.demand_mshr_hits::cpu.data 428751 # number of demand (read+write) MSHR hits
981system.cpu.dcache.demand_mshr_hits::total 428751 # number of demand (read+write) MSHR hits
982system.cpu.dcache.overall_mshr_hits::cpu.data 428751 # number of overall MSHR hits
983system.cpu.dcache.overall_mshr_hits::total 428751 # number of overall MSHR hits
984system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903940 # number of ReadReq MSHR misses
985system.cpu.dcache.ReadReq_mshr_misses::total 903940 # number of ReadReq MSHR misses
986system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43699 # number of WriteReq MSHR misses
987system.cpu.dcache.WriteReq_mshr_misses::total 43699 # number of WriteReq MSHR misses
988system.cpu.dcache.demand_mshr_misses::cpu.data 947639 # number of demand (read+write) MSHR misses
989system.cpu.dcache.demand_mshr_misses::total 947639 # number of demand (read+write) MSHR misses
990system.cpu.dcache.overall_mshr_misses::cpu.data 947639 # number of overall MSHR misses
991system.cpu.dcache.overall_mshr_misses::total 947639 # number of overall MSHR misses
992system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994791010 # number of ReadReq MSHR miss cycles
993system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994791010 # number of ReadReq MSHR miss cycles
994system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1332397702 # number of WriteReq MSHR miss cycles
995system.cpu.dcache.WriteReq_mshr_miss_latency::total 1332397702 # number of WriteReq MSHR miss cycles
996system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11327188712 # number of demand (read+write) MSHR miss cycles
997system.cpu.dcache.demand_mshr_miss_latency::total 11327188712 # number of demand (read+write) MSHR miss cycles
998system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11327188712 # number of overall MSHR miss cycles
999system.cpu.dcache.overall_mshr_miss_latency::total 11327188712 # number of overall MSHR miss cycles
1000system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036482 # mshr miss rate for ReadReq accesses
1001system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036482 # mshr miss rate for ReadReq accesses
1002system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009229 # mshr miss rate for WriteReq accesses
1003system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009229 # mshr miss rate for WriteReq accesses
1004system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032110 # mshr miss rate for demand accesses
1005system.cpu.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses
1006system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032110 # mshr miss rate for overall accesses
1007system.cpu.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses
1008system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.918612 # average ReadReq mshr miss latency
1009system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.918612 # average ReadReq mshr miss latency
1010system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30490.347651 # average WriteReq mshr miss latency
1011system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30490.347651 # average WriteReq mshr miss latency
1012system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11953.063046 # average overall mshr miss latency
1013system.cpu.dcache.demand_avg_mshr_miss_latency::total 11953.063046 # average overall mshr miss latency
1014system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11953.063046 # average overall mshr miss latency
1015system.cpu.dcache.overall_avg_mshr_miss_latency::total 11953.063046 # average overall mshr miss latency
1016system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1017
1018---------- End Simulation Statistics ----------