1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.026786 # Number of seconds simulated
4sim_ticks 26785824500 # Number of ticks simulated
5final_tick 26785824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 121944 # Simulator instruction rate (inst/s)
8host_op_rate 122819 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 36056613 # Simulator tick rate (ticks/s)
10host_mem_usage 374016 # Number of bytes of host memory used
11host_seconds 742.88 # Real time elapsed on the host
12sim_insts 90589798 # Number of instructions simulated
13sim_ops 91240351 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory
16system.physmem.bytes_read::total 992832 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 15513 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1679694 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 35385881 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 37065575 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1679694 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1679694 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1679694 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 35385881 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 37065575 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 15513 # Total number of read requests seen
31system.physmem.writeReqs 0 # Total number of write requests seen
32system.physmem.cpureqs 15516 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 992832 # Total number of bytes read from memory
34system.physmem.bytesWritten 0 # Total number of bytes written to memory
35system.physmem.bytesConsumedRd 992832 # bytesRead derated as per pkt->getSize()
36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 996 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 997 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis
44system.physmem.perBankRdReqs::5 1013 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::6 925 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::10 992 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::15 1001 # Track reads on a per bank basis
55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
73system.physmem.totGap 26785652500 # Total gap between requests
74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes
80system.physmem.readPktSize::6 15513 # Categorize read packet sizes
81system.physmem.writePktSize::0 0 # Categorize write packet sizes
82system.physmem.writePktSize::1 0 # Categorize write packet sizes
83system.physmem.writePktSize::2 0 # Categorize write packet sizes
84system.physmem.writePktSize::3 0 # Categorize write packet sizes
85system.physmem.writePktSize::4 0 # Categorize write packet sizes
86system.physmem.writePktSize::5 0 # Categorize write packet sizes
87system.physmem.writePktSize::6 0 # Categorize write packet sizes
88system.physmem.rdQLenPdf::0 10163 # What read queue length does an incoming req see
89system.physmem.rdQLenPdf::1 5065 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::2 255 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see

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112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see

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144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
152system.physmem.totQLat 55611750 # Total cycles spent in queuing delays
153system.physmem.totMemAccLat 315006750 # Sum of mem lat for all requests
154system.physmem.totBusLat 77565000 # Total cycles spent in databus access
155system.physmem.totBankLat 181830000 # Total cycles spent in bank access
156system.physmem.avgQLat 3584.85 # Average queueing delay per request
157system.physmem.avgBankLat 11721.14 # Average bank access latency per request
158system.physmem.avgBusLat 5000.00 # Average bus latency per request
159system.physmem.avgMemAccLat 20305.99 # Average memory access latency
160system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s
161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
162system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s
163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
165system.physmem.busUtil 0.29 # Data bus utilization in percentage
166system.physmem.avgRdQLen 0.01 # Average read queue length over time
167system.physmem.avgWrQLen 0.00 # Average write queue length over time
168system.physmem.readRowHits 14781 # Number of row buffer hits during reads
169system.physmem.writeRowHits 0 # Number of row buffer hits during writes
170system.physmem.readRowHitRate 95.28 # Row buffer hit rate for reads
171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
172system.physmem.avgGap 1726658.45 # Average gap between requests
173system.cpu.branchPred.lookups 26682480 # Number of BP lookups
174system.cpu.branchPred.condPredicted 22002618 # Number of conditional branches predicted
175system.cpu.branchPred.condIncorrect 841998 # Number of conditional branches incorrect
176system.cpu.branchPred.BTBLookups 11368270 # Number of BTB lookups
177system.cpu.branchPred.BTBHits 11282813 # Number of BTB hits
178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
179system.cpu.branchPred.BTBHitPct 99.248285 # BTB Hit Percentage
180system.cpu.branchPred.usedRAS 69658 # Number of times the RAS was used to get a target.
181system.cpu.branchPred.RASInCorrect 194 # Number of incorrect RAS predictions.
182system.cpu.dtb.inst_hits 0 # ITB inst hits
183system.cpu.dtb.inst_misses 0 # ITB inst misses
184system.cpu.dtb.read_hits 0 # DTB read hits
185system.cpu.dtb.read_misses 0 # DTB read misses
186system.cpu.dtb.write_hits 0 # DTB write hits
187system.cpu.dtb.write_misses 0 # DTB write misses
188system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
189system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 27 unchanged lines hidden (view full) ---

217system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
218system.cpu.itb.read_accesses 0 # DTB read accesses
219system.cpu.itb.write_accesses 0 # DTB write accesses
220system.cpu.itb.inst_accesses 0 # ITB inst accesses
221system.cpu.itb.hits 0 # DTB hits
222system.cpu.itb.misses 0 # DTB misses
223system.cpu.itb.accesses 0 # DTB accesses
224system.cpu.workload.num_syscalls 442 # Number of system calls
225system.cpu.numCycles 53571650 # number of cpu cycles simulated
226system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
227system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
228system.cpu.fetch.icacheStallCycles 14170612 # Number of cycles fetch is stalled on an Icache miss
229system.cpu.fetch.Insts 127882618 # Number of instructions fetch has processed
230system.cpu.fetch.Branches 26682480 # Number of branches that fetch encountered
231system.cpu.fetch.predictedBranches 11352471 # Number of branches that fetch has predicted taken
232system.cpu.fetch.Cycles 24034762 # Number of cycles fetch has run and was not squashing or blocked
233system.cpu.fetch.SquashCycles 4762849 # Number of cycles fetch has spent squashing
234system.cpu.fetch.BlockedCycles 11235788 # Number of cycles fetch has spent blocked
235system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
236system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
237system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
238system.cpu.fetch.CacheLines 13843090 # Number of cache lines fetched
239system.cpu.fetch.IcacheSquashes 329835 # Number of outstanding Icache misses that were squashed
240system.cpu.fetch.rateDist::samples 53345786 # Number of instructions fetched each cycle (Total)
241system.cpu.fetch.rateDist::mean 2.413719 # Number of instructions fetched each cycle (Total)
242system.cpu.fetch.rateDist::stdev 3.215837 # Number of instructions fetched each cycle (Total)
243system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
244system.cpu.fetch.rateDist::0 29349323 55.02% 55.02% # Number of instructions fetched each cycle (Total)
245system.cpu.fetch.rateDist::1 3389433 6.35% 61.37% # Number of instructions fetched each cycle (Total)
246system.cpu.fetch.rateDist::2 2028287 3.80% 65.17% # Number of instructions fetched each cycle (Total)
247system.cpu.fetch.rateDist::3 1555177 2.92% 68.09% # Number of instructions fetched each cycle (Total)
248system.cpu.fetch.rateDist::4 1667492 3.13% 71.21% # Number of instructions fetched each cycle (Total)
249system.cpu.fetch.rateDist::5 2918592 5.47% 76.69% # Number of instructions fetched each cycle (Total)
250system.cpu.fetch.rateDist::6 1510888 2.83% 79.52% # Number of instructions fetched each cycle (Total)
251system.cpu.fetch.rateDist::7 1090794 2.04% 81.56% # Number of instructions fetched each cycle (Total)
252system.cpu.fetch.rateDist::8 9835800 18.44% 100.00% # Number of instructions fetched each cycle (Total)
253system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
254system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
255system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
256system.cpu.fetch.rateDist::total 53345786 # Number of instructions fetched each cycle (Total)
257system.cpu.fetch.branchRate 0.498071 # Number of branch fetches per cycle
258system.cpu.fetch.rate 2.387132 # Number of inst fetches per cycle
259system.cpu.decode.IdleCycles 16933018 # Number of cycles decode is idle
260system.cpu.decode.BlockedCycles 9083258 # Number of cycles decode is blocked
261system.cpu.decode.RunCycles 22434897 # Number of cycles decode is running
262system.cpu.decode.UnblockCycles 998703 # Number of cycles decode is unblocking
263system.cpu.decode.SquashCycles 3895910 # Number of cycles decode is squashing
264system.cpu.decode.BranchResolved 4442085 # Number of times decode resolved a branch
265system.cpu.decode.BranchMispred 8696 # Number of times decode detected a branch misprediction
266system.cpu.decode.DecodedInsts 126062223 # Number of instructions handled by decode
267system.cpu.decode.SquashedInsts 42630 # Number of squashed instructions handled by decode
268system.cpu.rename.SquashCycles 3895910 # Number of cycles rename is squashing
269system.cpu.rename.IdleCycles 18712984 # Number of cycles rename is idle
270system.cpu.rename.BlockCycles 3548131 # Number of cycles rename is blocking
271system.cpu.rename.serializeStallCycles 156179 # count of cycles rename stalled for serializing inst
272system.cpu.rename.RunCycles 21551652 # Number of cycles rename is running
273system.cpu.rename.UnblockCycles 5480930 # Number of cycles rename is unblocking
274system.cpu.rename.RenamedInsts 123149853 # Number of instructions processed by rename
275system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full
276system.cpu.rename.IQFullEvents 423091 # Number of times rename has blocked due to IQ full
277system.cpu.rename.LSQFullEvents 4597179 # Number of times rename has blocked due to LSQ full
278system.cpu.rename.FullRegisterEvents 1286 # Number of times there has been no free registers
279system.cpu.rename.RenamedOperands 143608098 # Number of destination operands rename has renamed
280system.cpu.rename.RenameLookups 536423645 # Number of register rename lookups that rename has made
281system.cpu.rename.int_rename_lookups 536418417 # Number of integer rename lookups
282system.cpu.rename.fp_rename_lookups 5228 # Number of floating rename lookups
283system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
284system.cpu.rename.UndoneMaps 36193912 # Number of HB maps that are undone due to squashing
285system.cpu.rename.serializingInsts 4607 # count of serializing insts renamed
286system.cpu.rename.tempSerializingInsts 4605 # count of temporary serializing insts renamed
287system.cpu.rename.skidInsts 12518412 # count of insts added to the skid buffer
288system.cpu.memDep0.insertedLoads 29475899 # Number of loads inserted to the mem dependence unit.
289system.cpu.memDep0.insertedStores 5522776 # Number of stores inserted to the mem dependence unit.
290system.cpu.memDep0.conflictingLoads 2125822 # Number of conflicting loads.
291system.cpu.memDep0.conflictingStores 1253238 # Number of conflicting stores.
292system.cpu.iq.iqInstsAdded 118167784 # Number of instructions added to the IQ (excludes non-spec)
293system.cpu.iq.iqNonSpecInstsAdded 8472 # Number of non-speculative instructions added to the IQ
294system.cpu.iq.iqInstsIssued 105151160 # Number of instructions issued
295system.cpu.iq.iqSquashedInstsIssued 77497 # Number of squashed instructions issued
296system.cpu.iq.iqSquashedInstsExamined 26739027 # Number of squashed instructions iterated over during squash; mainly for profiling
297system.cpu.iq.iqSquashedOperandsExamined 65605268 # Number of squashed operands that are examined and possibly removed from graph
298system.cpu.iq.iqSquashedNonSpecRemoved 254 # Number of squashed non-spec instructions that were removed
299system.cpu.iq.issued_per_cycle::samples 53345786 # Number of insts issued each cycle
300system.cpu.iq.issued_per_cycle::mean 1.971124 # Number of insts issued each cycle
301system.cpu.iq.issued_per_cycle::stdev 1.910487 # Number of insts issued each cycle
302system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
303system.cpu.iq.issued_per_cycle::0 15316861 28.71% 28.71% # Number of insts issued each cycle
304system.cpu.iq.issued_per_cycle::1 11639595 21.82% 50.53% # Number of insts issued each cycle
305system.cpu.iq.issued_per_cycle::2 8263506 15.49% 66.02% # Number of insts issued each cycle
306system.cpu.iq.issued_per_cycle::3 6760248 12.67% 78.69% # Number of insts issued each cycle
307system.cpu.iq.issued_per_cycle::4 4974624 9.33% 88.02% # Number of insts issued each cycle
308system.cpu.iq.issued_per_cycle::5 2955128 5.54% 93.56% # Number of insts issued each cycle
309system.cpu.iq.issued_per_cycle::6 2464546 4.62% 98.18% # Number of insts issued each cycle
310system.cpu.iq.issued_per_cycle::7 527827 0.99% 99.17% # Number of insts issued each cycle
311system.cpu.iq.issued_per_cycle::8 443451 0.83% 100.00% # Number of insts issued each cycle
312system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
313system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
314system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
315system.cpu.iq.issued_per_cycle::total 53345786 # Number of insts issued each cycle
316system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
317system.cpu.iq.fu_full::IntAlu 44563 6.73% 6.73% # attempts to use FU when none available
318system.cpu.iq.fu_full::IntMult 27 0.00% 6.74% # attempts to use FU when none available
319system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available
320system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available
321system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available
322system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available
323system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available
324system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available
325system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available
326system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available
327system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available
328system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available
329system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available
330system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available
331system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available
332system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available
333system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available
334system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available
335system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available
336system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available
337system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available
338system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available
339system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available
340system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available
341system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available
342system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available
343system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available
344system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available
345system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available
346system.cpu.iq.fu_full::MemRead 340033 51.38% 58.11% # attempts to use FU when none available
347system.cpu.iq.fu_full::MemWrite 277229 41.89% 100.00% # attempts to use FU when none available
348system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
349system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
350system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
351system.cpu.iq.FU_type_0::IntAlu 74420309 70.77% 70.77% # Type of FU issued
352system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.79% # Type of FU issued
353system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
354system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
355system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
356system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
357system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
358system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
359system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
360system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
361system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
362system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
363system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
364system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
365system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
366system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
367system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
368system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
369system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
370system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
371system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
372system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
373system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.79% # Type of FU issued
374system.cpu.iq.FU_type_0::SimdFloatCvt 155 0.00% 70.79% # Type of FU issued
375system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
376system.cpu.iq.FU_type_0::SimdFloatMisc 201 0.00% 70.79% # Type of FU issued
377system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
378system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.79% # Type of FU issued
379system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
380system.cpu.iq.FU_type_0::MemRead 25602989 24.35% 95.13% # Type of FU issued
381system.cpu.iq.FU_type_0::MemWrite 5116524 4.87% 100.00% # Type of FU issued
382system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
383system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
384system.cpu.iq.FU_type_0::total 105151160 # Type of FU issued
385system.cpu.iq.rate 1.962814 # Inst issue rate
386system.cpu.iq.fu_busy_cnt 661852 # FU busy when requested
387system.cpu.iq.fu_busy_rate 0.006294 # FU busy rate (busy events/executed inst)
388system.cpu.iq.int_inst_queue_reads 264386671 # Number of integer instruction queue reads
389system.cpu.iq.int_inst_queue_writes 144919691 # Number of integer instruction queue writes
390system.cpu.iq.int_inst_queue_wakeup_accesses 102682625 # Number of integer instruction queue wakeup accesses
391system.cpu.iq.fp_inst_queue_reads 784 # Number of floating instruction queue reads
392system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes
393system.cpu.iq.fp_inst_queue_wakeup_accesses 339 # Number of floating instruction queue wakeup accesses
394system.cpu.iq.int_alu_accesses 105812622 # Number of integer alu accesses
395system.cpu.iq.fp_alu_accesses 390 # Number of floating point alu accesses
396system.cpu.iew.lsq.thread0.forwLoads 443741 # Number of loads that had data forwarded from stores
397system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
398system.cpu.iew.lsq.thread0.squashedLoads 6901933 # Number of loads squashed
399system.cpu.iew.lsq.thread0.ignoredResponses 6293 # Number of memory responses ignored because the instruction is squashed
400system.cpu.iew.lsq.thread0.memOrderViolation 6180 # Number of memory ordering violations
401system.cpu.iew.lsq.thread0.squashedStores 777932 # Number of stores squashed
402system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
403system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
404system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
405system.cpu.iew.lsq.thread0.cacheBlocked 31373 # Number of times an access to memory failed due to the cache being blocked
406system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
407system.cpu.iew.iewSquashCycles 3895910 # Number of cycles IEW is squashing
408system.cpu.iew.iewBlockCycles 928973 # Number of cycles IEW is blocking
409system.cpu.iew.iewUnblockCycles 127070 # Number of cycles IEW is unblocking
410system.cpu.iew.iewDispatchedInsts 118188976 # Number of instructions dispatched to IQ
411system.cpu.iew.iewDispSquashedInsts 309212 # Number of squashed instructions skipped by dispatch
412system.cpu.iew.iewDispLoadInsts 29475899 # Number of dispatched load instructions
413system.cpu.iew.iewDispStoreInsts 5522776 # Number of dispatched store instructions
414system.cpu.iew.iewDispNonSpecInsts 4584 # Number of dispatched non-speculative instructions
415system.cpu.iew.iewIQFullEvents 66075 # Number of times the IQ has become full, causing a stall
416system.cpu.iew.iewLSQFullEvents 6911 # Number of times the LSQ has become full, causing a stall
417system.cpu.iew.memOrderViolationEvents 6180 # Number of memory order violations
418system.cpu.iew.predictedTakenIncorrect 446439 # Number of branches that were predicted taken incorrectly
419system.cpu.iew.predictedNotTakenIncorrect 445443 # Number of branches that were predicted not taken incorrectly
420system.cpu.iew.branchMispredicts 891882 # Number of branch mispredicts detected at execute
421system.cpu.iew.iewExecutedInsts 104175676 # Number of executed instructions
422system.cpu.iew.iewExecLoadInsts 25284542 # Number of load instructions executed
423system.cpu.iew.iewExecSquashedInsts 975484 # Number of squashed instructions skipped in execute
424system.cpu.iew.exec_swp 0 # number of swp insts executed
425system.cpu.iew.exec_nop 12720 # number of nop insts executed
426system.cpu.iew.exec_refs 30343976 # number of memory reference insts executed
427system.cpu.iew.exec_branches 21325145 # Number of branches executed
428system.cpu.iew.exec_stores 5059434 # Number of stores executed
429system.cpu.iew.exec_rate 1.944605 # Inst execution rate
430system.cpu.iew.wb_sent 102960011 # cumulative count of insts sent to commit
431system.cpu.iew.wb_count 102682964 # cumulative count of insts written-back
432system.cpu.iew.wb_producers 62233069 # num instructions producing a value
433system.cpu.iew.wb_consumers 104282875 # num instructions consuming a value
434system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
435system.cpu.iew.wb_rate 1.916741 # insts written-back per cycle
436system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back
437system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
438system.cpu.commit.commitSquashedInsts 26939053 # The number of squashed insts skipped by commit
439system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
440system.cpu.commit.branchMispredicts 833398 # The number of times a branch was mispredicted
441system.cpu.commit.committed_per_cycle::samples 49449876 # Number of insts commited each cycle
442system.cpu.commit.committed_per_cycle::mean 1.845363 # Number of insts commited each cycle
443system.cpu.commit.committed_per_cycle::stdev 2.541608 # Number of insts commited each cycle
444system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
445system.cpu.commit.committed_per_cycle::0 19967148 40.38% 40.38% # Number of insts commited each cycle
446system.cpu.commit.committed_per_cycle::1 13135707 26.56% 66.94% # Number of insts commited each cycle
447system.cpu.commit.committed_per_cycle::2 4163389 8.42% 75.36% # Number of insts commited each cycle
448system.cpu.commit.committed_per_cycle::3 3434332 6.95% 82.31% # Number of insts commited each cycle
449system.cpu.commit.committed_per_cycle::4 1535763 3.11% 85.41% # Number of insts commited each cycle
450system.cpu.commit.committed_per_cycle::5 744463 1.51% 86.92% # Number of insts commited each cycle
451system.cpu.commit.committed_per_cycle::6 942034 1.91% 88.82% # Number of insts commited each cycle
452system.cpu.commit.committed_per_cycle::7 246412 0.50% 89.32% # Number of insts commited each cycle
453system.cpu.commit.committed_per_cycle::8 5280628 10.68% 100.00% # Number of insts commited each cycle
454system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
455system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
456system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
457system.cpu.commit.committed_per_cycle::total 49449876 # Number of insts commited each cycle
458system.cpu.commit.committedInsts 90602407 # Number of instructions committed
459system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
460system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
461system.cpu.commit.refs 27318810 # Number of memory references committed
462system.cpu.commit.loads 22573966 # Number of loads committed
463system.cpu.commit.membars 3888 # Number of memory barriers committed
464system.cpu.commit.branches 18732304 # Number of branches committed
465system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
466system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
467system.cpu.commit.function_calls 56148 # Number of function calls committed.
468system.cpu.commit.bw_lim_events 5280628 # number cycles where commit BW limit reached
469system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
470system.cpu.rob.rob_reads 162355527 # The number of ROB reads
471system.cpu.rob.rob_writes 240299704 # The number of ROB writes
472system.cpu.timesIdled 43654 # Number of times that the entire CPU went into an idle state and unscheduled itself
473system.cpu.idleCycles 225864 # Total number of cycles that the CPU has spent unscheduled due to idling
474system.cpu.committedInsts 90589798 # Number of Instructions Simulated
475system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
476system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
477system.cpu.cpi 0.591365 # CPI: Cycles Per Instruction
478system.cpu.cpi_total 0.591365 # CPI: Total CPI of All Threads
479system.cpu.ipc 1.691003 # IPC: Instructions Per Cycle
480system.cpu.ipc_total 1.691003 # IPC: Total IPC of All Threads
481system.cpu.int_regfile_reads 495535708 # number of integer regfile reads
482system.cpu.int_regfile_writes 120542575 # number of integer regfile writes
483system.cpu.fp_regfile_reads 173 # number of floating regfile reads
484system.cpu.fp_regfile_writes 431 # number of floating regfile writes
485system.cpu.misc_regfile_reads 29089632 # number of misc regfile reads
486system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
487system.cpu.icache.replacements 3 # number of replacements
488system.cpu.icache.tagsinuse 630.397373 # Cycle average of tags in use
489system.cpu.icache.total_refs 13842106 # Total number of references to valid blocks.
490system.cpu.icache.sampled_refs 728 # Sample count of references to valid blocks.
491system.cpu.icache.avg_refs 19013.881868 # Average number of references to valid blocks.
492system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
493system.cpu.icache.occ_blocks::cpu.inst 630.397373 # Average occupied blocks per requestor
494system.cpu.icache.occ_percent::cpu.inst 0.307811 # Average percentage of cache occupancy
495system.cpu.icache.occ_percent::total 0.307811 # Average percentage of cache occupancy
496system.cpu.icache.ReadReq_hits::cpu.inst 13842106 # number of ReadReq hits
497system.cpu.icache.ReadReq_hits::total 13842106 # number of ReadReq hits
498system.cpu.icache.demand_hits::cpu.inst 13842106 # number of demand (read+write) hits
499system.cpu.icache.demand_hits::total 13842106 # number of demand (read+write) hits
500system.cpu.icache.overall_hits::cpu.inst 13842106 # number of overall hits
501system.cpu.icache.overall_hits::total 13842106 # number of overall hits
502system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses
503system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses
504system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses
505system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses
506system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses
507system.cpu.icache.overall_misses::total 983 # number of overall misses
508system.cpu.icache.ReadReq_miss_latency::cpu.inst 49432499 # number of ReadReq miss cycles
509system.cpu.icache.ReadReq_miss_latency::total 49432499 # number of ReadReq miss cycles
510system.cpu.icache.demand_miss_latency::cpu.inst 49432499 # number of demand (read+write) miss cycles
511system.cpu.icache.demand_miss_latency::total 49432499 # number of demand (read+write) miss cycles
512system.cpu.icache.overall_miss_latency::cpu.inst 49432499 # number of overall miss cycles
513system.cpu.icache.overall_miss_latency::total 49432499 # number of overall miss cycles
514system.cpu.icache.ReadReq_accesses::cpu.inst 13843089 # number of ReadReq accesses(hits+misses)
515system.cpu.icache.ReadReq_accesses::total 13843089 # number of ReadReq accesses(hits+misses)
516system.cpu.icache.demand_accesses::cpu.inst 13843089 # number of demand (read+write) accesses
517system.cpu.icache.demand_accesses::total 13843089 # number of demand (read+write) accesses
518system.cpu.icache.overall_accesses::cpu.inst 13843089 # number of overall (read+write) accesses
519system.cpu.icache.overall_accesses::total 13843089 # number of overall (read+write) accesses
520system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
521system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
522system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
523system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
524system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
525system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
526system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50287.384537 # average ReadReq miss latency
527system.cpu.icache.ReadReq_avg_miss_latency::total 50287.384537 # average ReadReq miss latency
528system.cpu.icache.demand_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency
529system.cpu.icache.demand_avg_miss_latency::total 50287.384537 # average overall miss latency
530system.cpu.icache.overall_avg_miss_latency::cpu.inst 50287.384537 # average overall miss latency
531system.cpu.icache.overall_avg_miss_latency::total 50287.384537 # average overall miss latency
532system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked
533system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
534system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
535system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
536system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked
537system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
538system.cpu.icache.fast_writes 0 # number of fast writes performed
539system.cpu.icache.cache_copies 0 # number of cache copies performed
540system.cpu.icache.ReadReq_mshr_hits::cpu.inst 250 # number of ReadReq MSHR hits
541system.cpu.icache.ReadReq_mshr_hits::total 250 # number of ReadReq MSHR hits
542system.cpu.icache.demand_mshr_hits::cpu.inst 250 # number of demand (read+write) MSHR hits
543system.cpu.icache.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits
544system.cpu.icache.overall_mshr_hits::cpu.inst 250 # number of overall MSHR hits
545system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits
546system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses
547system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses
548system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses
549system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses
550system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses
551system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses
552system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37907999 # number of ReadReq MSHR miss cycles
553system.cpu.icache.ReadReq_mshr_miss_latency::total 37907999 # number of ReadReq MSHR miss cycles
554system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37907999 # number of demand (read+write) MSHR miss cycles
555system.cpu.icache.demand_mshr_miss_latency::total 37907999 # number of demand (read+write) MSHR miss cycles
556system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37907999 # number of overall MSHR miss cycles
557system.cpu.icache.overall_mshr_miss_latency::total 37907999 # number of overall MSHR miss cycles
558system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
559system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
560system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
561system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
562system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
563system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
564system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51716.233288 # average ReadReq mshr miss latency
565system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51716.233288 # average ReadReq mshr miss latency
566system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51716.233288 # average overall mshr miss latency
567system.cpu.icache.demand_avg_mshr_miss_latency::total 51716.233288 # average overall mshr miss latency
568system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51716.233288 # average overall mshr miss latency
569system.cpu.icache.overall_avg_mshr_miss_latency::total 51716.233288 # average overall mshr miss latency
570system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
571system.cpu.l2cache.replacements 0 # number of replacements
572system.cpu.l2cache.tagsinuse 10760.479556 # Cycle average of tags in use
573system.cpu.l2cache.total_refs 1831525 # Total number of references to valid blocks.
574system.cpu.l2cache.sampled_refs 15496 # Sample count of references to valid blocks.
575system.cpu.l2cache.avg_refs 118.193405 # Average number of references to valid blocks.
576system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
577system.cpu.l2cache.occ_blocks::writebacks 9911.805562 # Average occupied blocks per requestor
578system.cpu.l2cache.occ_blocks::cpu.inst 616.761334 # Average occupied blocks per requestor
579system.cpu.l2cache.occ_blocks::cpu.data 231.912660 # Average occupied blocks per requestor
580system.cpu.l2cache.occ_percent::writebacks 0.302484 # Average percentage of cache occupancy
581system.cpu.l2cache.occ_percent::cpu.inst 0.018822 # Average percentage of cache occupancy
582system.cpu.l2cache.occ_percent::cpu.data 0.007077 # Average percentage of cache occupancy
583system.cpu.l2cache.occ_percent::total 0.328384 # Average percentage of cache occupancy
584system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
585system.cpu.l2cache.ReadReq_hits::cpu.data 903743 # number of ReadReq hits
586system.cpu.l2cache.ReadReq_hits::total 903767 # number of ReadReq hits
587system.cpu.l2cache.Writeback_hits::writebacks 942900 # number of Writeback hits
588system.cpu.l2cache.Writeback_hits::total 942900 # number of Writeback hits
589system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits
590system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
591system.cpu.l2cache.ReadExReq_hits::cpu.data 29045 # number of ReadExReq hits
592system.cpu.l2cache.ReadExReq_hits::total 29045 # number of ReadExReq hits
593system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits
594system.cpu.l2cache.demand_hits::cpu.data 932788 # number of demand (read+write) hits
595system.cpu.l2cache.demand_hits::total 932812 # number of demand (read+write) hits
596system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits
597system.cpu.l2cache.overall_hits::cpu.data 932788 # number of overall hits
598system.cpu.l2cache.overall_hits::total 932812 # number of overall hits
599system.cpu.l2cache.ReadReq_misses::cpu.inst 704 # number of ReadReq misses
600system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses
601system.cpu.l2cache.ReadReq_misses::total 985 # number of ReadReq misses
602system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
603system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
604system.cpu.l2cache.ReadExReq_misses::cpu.data 14539 # number of ReadExReq misses
605system.cpu.l2cache.ReadExReq_misses::total 14539 # number of ReadExReq misses
606system.cpu.l2cache.demand_misses::cpu.inst 704 # number of demand (read+write) misses
607system.cpu.l2cache.demand_misses::cpu.data 14820 # number of demand (read+write) misses
608system.cpu.l2cache.demand_misses::total 15524 # number of demand (read+write) misses
609system.cpu.l2cache.overall_misses::cpu.inst 704 # number of overall misses
610system.cpu.l2cache.overall_misses::cpu.data 14820 # number of overall misses
611system.cpu.l2cache.overall_misses::total 15524 # number of overall misses
612system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 36918500 # number of ReadReq miss cycles
613system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15609500 # number of ReadReq miss cycles
614system.cpu.l2cache.ReadReq_miss_latency::total 52528000 # number of ReadReq miss cycles
615system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 628655000 # number of ReadExReq miss cycles
616system.cpu.l2cache.ReadExReq_miss_latency::total 628655000 # number of ReadExReq miss cycles
617system.cpu.l2cache.demand_miss_latency::cpu.inst 36918500 # number of demand (read+write) miss cycles
618system.cpu.l2cache.demand_miss_latency::cpu.data 644264500 # number of demand (read+write) miss cycles
619system.cpu.l2cache.demand_miss_latency::total 681183000 # number of demand (read+write) miss cycles
620system.cpu.l2cache.overall_miss_latency::cpu.inst 36918500 # number of overall miss cycles
621system.cpu.l2cache.overall_miss_latency::cpu.data 644264500 # number of overall miss cycles
622system.cpu.l2cache.overall_miss_latency::total 681183000 # number of overall miss cycles
623system.cpu.l2cache.ReadReq_accesses::cpu.inst 728 # number of ReadReq accesses(hits+misses)
624system.cpu.l2cache.ReadReq_accesses::cpu.data 904024 # number of ReadReq accesses(hits+misses)
625system.cpu.l2cache.ReadReq_accesses::total 904752 # number of ReadReq accesses(hits+misses)
626system.cpu.l2cache.Writeback_accesses::writebacks 942900 # number of Writeback accesses(hits+misses)
627system.cpu.l2cache.Writeback_accesses::total 942900 # number of Writeback accesses(hits+misses)
628system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses)
629system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses)
630system.cpu.l2cache.ReadExReq_accesses::cpu.data 43584 # number of ReadExReq accesses(hits+misses)
631system.cpu.l2cache.ReadExReq_accesses::total 43584 # number of ReadExReq accesses(hits+misses)
632system.cpu.l2cache.demand_accesses::cpu.inst 728 # number of demand (read+write) accesses
633system.cpu.l2cache.demand_accesses::cpu.data 947608 # number of demand (read+write) accesses
634system.cpu.l2cache.demand_accesses::total 948336 # number of demand (read+write) accesses
635system.cpu.l2cache.overall_accesses::cpu.inst 728 # number of overall (read+write) accesses
636system.cpu.l2cache.overall_accesses::cpu.data 947608 # number of overall (read+write) accesses
637system.cpu.l2cache.overall_accesses::total 948336 # number of overall (read+write) accesses
638system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967033 # miss rate for ReadReq accesses
639system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000311 # miss rate for ReadReq accesses
640system.cpu.l2cache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses
641system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses
642system.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses
643system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.333586 # miss rate for ReadExReq accesses
644system.cpu.l2cache.ReadExReq_miss_rate::total 0.333586 # miss rate for ReadExReq accesses
645system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967033 # miss rate for demand accesses
646system.cpu.l2cache.demand_miss_rate::cpu.data 0.015639 # miss rate for demand accesses
647system.cpu.l2cache.demand_miss_rate::total 0.016370 # miss rate for demand accesses
648system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967033 # miss rate for overall accesses
649system.cpu.l2cache.overall_miss_rate::cpu.data 0.015639 # miss rate for overall accesses
650system.cpu.l2cache.overall_miss_rate::total 0.016370 # miss rate for overall accesses
651system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52441.051136 # average ReadReq miss latency
652system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55549.822064 # average ReadReq miss latency
653system.cpu.l2cache.ReadReq_avg_miss_latency::total 53327.918782 # average ReadReq miss latency
654system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43239.218653 # average ReadExReq miss latency
655system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43239.218653 # average ReadExReq miss latency
656system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52441.051136 # average overall miss latency
657system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43472.638327 # average overall miss latency
658system.cpu.l2cache.demand_avg_miss_latency::total 43879.348106 # average overall miss latency
659system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52441.051136 # average overall miss latency
660system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43472.638327 # average overall miss latency
661system.cpu.l2cache.overall_avg_miss_latency::total 43879.348106 # average overall miss latency
662system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
663system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
664system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
665system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
666system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
667system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
668system.cpu.l2cache.fast_writes 0 # number of fast writes performed
669system.cpu.l2cache.cache_copies 0 # number of cache copies performed
670system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
671system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
672system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
673system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
674system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
675system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
676system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
677system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
678system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
679system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 703 # number of ReadReq MSHR misses
680system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses
681system.cpu.l2cache.ReadReq_mshr_misses::total 974 # number of ReadReq MSHR misses
682system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
683system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
684system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14539 # number of ReadExReq MSHR misses
685system.cpu.l2cache.ReadExReq_mshr_misses::total 14539 # number of ReadExReq MSHR misses
686system.cpu.l2cache.demand_mshr_misses::cpu.inst 703 # number of demand (read+write) MSHR misses
687system.cpu.l2cache.demand_mshr_misses::cpu.data 14810 # number of demand (read+write) MSHR misses
688system.cpu.l2cache.demand_mshr_misses::total 15513 # number of demand (read+write) MSHR misses
689system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses
690system.cpu.l2cache.overall_mshr_misses::cpu.data 14810 # number of overall MSHR misses
691system.cpu.l2cache.overall_mshr_misses::total 15513 # number of overall MSHR misses
692system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27943554 # number of ReadReq MSHR miss cycles
693system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11832709 # number of ReadReq MSHR miss cycles
694system.cpu.l2cache.ReadReq_mshr_miss_latency::total 39776263 # number of ReadReq MSHR miss cycles
695system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles
696system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles
697system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 448424221 # number of ReadExReq MSHR miss cycles
698system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 448424221 # number of ReadExReq MSHR miss cycles
699system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27943554 # number of demand (read+write) MSHR miss cycles
700system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 460256930 # number of demand (read+write) MSHR miss cycles
701system.cpu.l2cache.demand_mshr_miss_latency::total 488200484 # number of demand (read+write) MSHR miss cycles
702system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27943554 # number of overall MSHR miss cycles
703system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 460256930 # number of overall MSHR miss cycles
704system.cpu.l2cache.overall_mshr_miss_latency::total 488200484 # number of overall MSHR miss cycles
705system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for ReadReq accesses
706system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses
707system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001077 # mshr miss rate for ReadReq accesses
708system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses
709system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses
710system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333586 # mshr miss rate for ReadExReq accesses
711system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333586 # mshr miss rate for ReadExReq accesses
712system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for demand accesses
713system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015629 # mshr miss rate for demand accesses
714system.cpu.l2cache.demand_mshr_miss_rate::total 0.016358 # mshr miss rate for demand accesses
715system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965659 # mshr miss rate for overall accesses
716system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015629 # mshr miss rate for overall accesses
717system.cpu.l2cache.overall_mshr_miss_rate::total 0.016358 # mshr miss rate for overall accesses
718system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39749.009957 # average ReadReq mshr miss latency
719system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43663.132841 # average ReadReq mshr miss latency
720system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40838.052361 # average ReadReq mshr miss latency
721system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
722system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
723system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30842.851709 # average ReadExReq mshr miss latency
724system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30842.851709 # average ReadExReq mshr miss latency
725system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39749.009957 # average overall mshr miss latency
726system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31077.442944 # average overall mshr miss latency
727system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31470.410881 # average overall mshr miss latency
728system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39749.009957 # average overall mshr miss latency
729system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31077.442944 # average overall mshr miss latency
730system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31470.410881 # average overall mshr miss latency
731system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
732system.cpu.dcache.replacements 943512 # number of replacements
733system.cpu.dcache.tagsinuse 3674.906425 # Cycle average of tags in use
734system.cpu.dcache.total_refs 28139228 # Total number of references to valid blocks.
735system.cpu.dcache.sampled_refs 947608 # Sample count of references to valid blocks.
736system.cpu.dcache.avg_refs 29.695009 # Average number of references to valid blocks.
737system.cpu.dcache.warmup_cycle 7938358000 # Cycle when the warmup percentage was hit.
738system.cpu.dcache.occ_blocks::cpu.data 3674.906425 # Average occupied blocks per requestor
739system.cpu.dcache.occ_percent::cpu.data 0.897194 # Average percentage of cache occupancy
740system.cpu.dcache.occ_percent::total 0.897194 # Average percentage of cache occupancy
741system.cpu.dcache.ReadReq_hits::cpu.data 23594668 # number of ReadReq hits
742system.cpu.dcache.ReadReq_hits::total 23594668 # number of ReadReq hits
743system.cpu.dcache.WriteReq_hits::cpu.data 4536751 # number of WriteReq hits
744system.cpu.dcache.WriteReq_hits::total 4536751 # number of WriteReq hits
745system.cpu.dcache.LoadLockedReq_hits::cpu.data 3908 # number of LoadLockedReq hits
746system.cpu.dcache.LoadLockedReq_hits::total 3908 # number of LoadLockedReq hits
747system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
748system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
749system.cpu.dcache.demand_hits::cpu.data 28131419 # number of demand (read+write) hits
750system.cpu.dcache.demand_hits::total 28131419 # number of demand (read+write) hits
751system.cpu.dcache.overall_hits::cpu.data 28131419 # number of overall hits
752system.cpu.dcache.overall_hits::total 28131419 # number of overall hits
753system.cpu.dcache.ReadReq_misses::cpu.data 1172935 # number of ReadReq misses
754system.cpu.dcache.ReadReq_misses::total 1172935 # number of ReadReq misses
755system.cpu.dcache.WriteReq_misses::cpu.data 198230 # number of WriteReq misses
756system.cpu.dcache.WriteReq_misses::total 198230 # number of WriteReq misses
757system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
758system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
759system.cpu.dcache.demand_misses::cpu.data 1371165 # number of demand (read+write) misses
760system.cpu.dcache.demand_misses::total 1371165 # number of demand (read+write) misses
761system.cpu.dcache.overall_misses::cpu.data 1371165 # number of overall misses
762system.cpu.dcache.overall_misses::total 1371165 # number of overall misses
763system.cpu.dcache.ReadReq_miss_latency::cpu.data 13884681000 # number of ReadReq miss cycles
764system.cpu.dcache.ReadReq_miss_latency::total 13884681000 # number of ReadReq miss cycles
765system.cpu.dcache.WriteReq_miss_latency::cpu.data 5602018407 # number of WriteReq miss cycles
766system.cpu.dcache.WriteReq_miss_latency::total 5602018407 # number of WriteReq miss cycles
767system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247000 # number of LoadLockedReq miss cycles
768system.cpu.dcache.LoadLockedReq_miss_latency::total 247000 # number of LoadLockedReq miss cycles
769system.cpu.dcache.demand_miss_latency::cpu.data 19486699407 # number of demand (read+write) miss cycles
770system.cpu.dcache.demand_miss_latency::total 19486699407 # number of demand (read+write) miss cycles
771system.cpu.dcache.overall_miss_latency::cpu.data 19486699407 # number of overall miss cycles
772system.cpu.dcache.overall_miss_latency::total 19486699407 # number of overall miss cycles
773system.cpu.dcache.ReadReq_accesses::cpu.data 24767603 # number of ReadReq accesses(hits+misses)
774system.cpu.dcache.ReadReq_accesses::total 24767603 # number of ReadReq accesses(hits+misses)
775system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
776system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
777system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3914 # number of LoadLockedReq accesses(hits+misses)
778system.cpu.dcache.LoadLockedReq_accesses::total 3914 # number of LoadLockedReq accesses(hits+misses)
779system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
780system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
781system.cpu.dcache.demand_accesses::cpu.data 29502584 # number of demand (read+write) accesses
782system.cpu.dcache.demand_accesses::total 29502584 # number of demand (read+write) accesses
783system.cpu.dcache.overall_accesses::cpu.data 29502584 # number of overall (read+write) accesses
784system.cpu.dcache.overall_accesses::total 29502584 # number of overall (read+write) accesses
785system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047358 # miss rate for ReadReq accesses
786system.cpu.dcache.ReadReq_miss_rate::total 0.047358 # miss rate for ReadReq accesses
787system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041865 # miss rate for WriteReq accesses
788system.cpu.dcache.WriteReq_miss_rate::total 0.041865 # miss rate for WriteReq accesses
789system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001533 # miss rate for LoadLockedReq accesses
790system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001533 # miss rate for LoadLockedReq accesses
791system.cpu.dcache.demand_miss_rate::cpu.data 0.046476 # miss rate for demand accesses
792system.cpu.dcache.demand_miss_rate::total 0.046476 # miss rate for demand accesses
793system.cpu.dcache.overall_miss_rate::cpu.data 0.046476 # miss rate for overall accesses
794system.cpu.dcache.overall_miss_rate::total 0.046476 # miss rate for overall accesses
795system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.553658 # average ReadReq miss latency
796system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.553658 # average ReadReq miss latency
797system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28260.194759 # average WriteReq miss latency
798system.cpu.dcache.WriteReq_avg_miss_latency::total 28260.194759 # average WriteReq miss latency
799system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41166.666667 # average LoadLockedReq miss latency
800system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41166.666667 # average LoadLockedReq miss latency
801system.cpu.dcache.demand_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency
802system.cpu.dcache.demand_avg_miss_latency::total 14211.782978 # average overall miss latency
803system.cpu.dcache.overall_avg_miss_latency::cpu.data 14211.782978 # average overall miss latency
804system.cpu.dcache.overall_avg_miss_latency::total 14211.782978 # average overall miss latency
805system.cpu.dcache.blocked_cycles::no_mshrs 152466 # number of cycles access was blocked
806system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
807system.cpu.dcache.blocked::no_mshrs 23833 # number of cycles access was blocked
808system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
809system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.397264 # average number of cycles each access was blocked
810system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
811system.cpu.dcache.fast_writes 0 # number of fast writes performed
812system.cpu.dcache.cache_copies 0 # number of cache copies performed
813system.cpu.dcache.writebacks::writebacks 942900 # number of writebacks
814system.cpu.dcache.writebacks::total 942900 # number of writebacks
815system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268897 # number of ReadReq MSHR hits
816system.cpu.dcache.ReadReq_mshr_hits::total 268897 # number of ReadReq MSHR hits
817system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154655 # number of WriteReq MSHR hits
818system.cpu.dcache.WriteReq_mshr_hits::total 154655 # number of WriteReq MSHR hits
819system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
820system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
821system.cpu.dcache.demand_mshr_hits::cpu.data 423552 # number of demand (read+write) MSHR hits
822system.cpu.dcache.demand_mshr_hits::total 423552 # number of demand (read+write) MSHR hits
823system.cpu.dcache.overall_mshr_hits::cpu.data 423552 # number of overall MSHR hits
824system.cpu.dcache.overall_mshr_hits::total 423552 # number of overall MSHR hits
825system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904038 # number of ReadReq MSHR misses
826system.cpu.dcache.ReadReq_mshr_misses::total 904038 # number of ReadReq MSHR misses
827system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43575 # number of WriteReq MSHR misses
828system.cpu.dcache.WriteReq_mshr_misses::total 43575 # number of WriteReq MSHR misses
829system.cpu.dcache.demand_mshr_misses::cpu.data 947613 # number of demand (read+write) MSHR misses
830system.cpu.dcache.demand_mshr_misses::total 947613 # number of demand (read+write) MSHR misses
831system.cpu.dcache.overall_mshr_misses::cpu.data 947613 # number of overall MSHR misses
832system.cpu.dcache.overall_mshr_misses::total 947613 # number of overall MSHR misses
833system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990153500 # number of ReadReq MSHR miss cycles
834system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990153500 # number of ReadReq MSHR miss cycles
835system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 984037459 # number of WriteReq MSHR miss cycles
836system.cpu.dcache.WriteReq_mshr_miss_latency::total 984037459 # number of WriteReq MSHR miss cycles
837system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10974190959 # number of demand (read+write) MSHR miss cycles
838system.cpu.dcache.demand_mshr_miss_latency::total 10974190959 # number of demand (read+write) MSHR miss cycles
839system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10974190959 # number of overall MSHR miss cycles
840system.cpu.dcache.overall_mshr_miss_latency::total 10974190959 # number of overall MSHR miss cycles
841system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036501 # mshr miss rate for ReadReq accesses
842system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036501 # mshr miss rate for ReadReq accesses
843system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009203 # mshr miss rate for WriteReq accesses
844system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009203 # mshr miss rate for WriteReq accesses
845system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for demand accesses
846system.cpu.dcache.demand_mshr_miss_rate::total 0.032120 # mshr miss rate for demand accesses
847system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032120 # mshr miss rate for overall accesses
848system.cpu.dcache.overall_mshr_miss_rate::total 0.032120 # mshr miss rate for overall accesses
849system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.590241 # average ReadReq mshr miss latency
850system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.590241 # average ReadReq mshr miss latency
851system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22582.615238 # average WriteReq mshr miss latency
852system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22582.615238 # average WriteReq mshr miss latency
853system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency
854system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency
855system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.878438 # average overall mshr miss latency
856system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.878438 # average overall mshr miss latency
857system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
858
859---------- End Simulation Statistics ----------