1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.057713 # Number of seconds simulated
4sim_ticks 57712782000 # Number of ticks simulated
5final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 133015 # Simulator instruction rate (inst/s)
8host_op_rate 133677 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 84740771 # Simulator tick rate (ticks/s)
10host_mem_usage 440040 # Number of bytes of host memory used
11host_seconds 681.05 # Real time elapsed on the host
12sim_insts 90589798 # Number of instructions simulated
13sim_ops 91041029 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 8896 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 68416 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 1042048 # Number of bytes read from this memory
19system.physmem.bytes_read::total 1119360 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 8896 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 8896 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 73600 # Number of bytes written to this memory
23system.physmem.bytes_written::total 73600 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 139 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 1069 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.l2cache.prefetcher 16282 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 17490 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 1150 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 1150 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 154143 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 1185457 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.l2cache.prefetcher 18055758 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 19395357 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 154143 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 154143 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 1275281 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 1275281 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 1275281 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 154143 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 1185457 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.l2cache.prefetcher 18055758 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 20670638 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 17490 # Number of read requests accepted
44system.physmem.writeReqs 1150 # Number of write requests accepted
45system.physmem.readBursts 17490 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 1150 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 1100032 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue
49system.physmem.bytesWritten 71488 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 1119360 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 73600 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 1094 # Per bank write bursts
56system.physmem.perBankRdBursts::1 953 # Per bank write bursts
57system.physmem.perBankRdBursts::2 1083 # Per bank write bursts
58system.physmem.perBankRdBursts::3 1113 # Per bank write bursts
59system.physmem.perBankRdBursts::4 1125 # Per bank write bursts
60system.physmem.perBankRdBursts::5 1235 # Per bank write bursts
61system.physmem.perBankRdBursts::6 1314 # Per bank write bursts
62system.physmem.perBankRdBursts::7 1243 # Per bank write bursts
63system.physmem.perBankRdBursts::8 1060 # Per bank write bursts
64system.physmem.perBankRdBursts::9 962 # Per bank write bursts
65system.physmem.perBankRdBursts::10 1021 # Per bank write bursts
66system.physmem.perBankRdBursts::11 923 # Per bank write bursts
67system.physmem.perBankRdBursts::12 921 # Per bank write bursts
68system.physmem.perBankRdBursts::13 987 # Per bank write bursts
69system.physmem.perBankRdBursts::14 1105 # Per bank write bursts
70system.physmem.perBankRdBursts::15 1049 # Per bank write bursts
71system.physmem.perBankWrBursts::0 72 # Per bank write bursts
72system.physmem.perBankWrBursts::1 0 # Per bank write bursts
73system.physmem.perBankWrBursts::2 62 # Per bank write bursts
74system.physmem.perBankWrBursts::3 19 # Per bank write bursts
75system.physmem.perBankWrBursts::4 14 # Per bank write bursts
76system.physmem.perBankWrBursts::5 111 # Per bank write bursts
77system.physmem.perBankWrBursts::6 193 # Per bank write bursts
78system.physmem.perBankWrBursts::7 122 # Per bank write bursts
79system.physmem.perBankWrBursts::8 49 # Per bank write bursts
80system.physmem.perBankWrBursts::9 0 # Per bank write bursts
81system.physmem.perBankWrBursts::10 68 # Per bank write bursts
82system.physmem.perBankWrBursts::11 20 # Per bank write bursts
83system.physmem.perBankWrBursts::12 15 # Per bank write bursts
84system.physmem.perBankWrBursts::13 94 # Per bank write bursts
85system.physmem.perBankWrBursts::14 168 # Per bank write bursts
86system.physmem.perBankWrBursts::15 110 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89system.physmem.totGap 57712604500 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 17490 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 1150 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 11254 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 2508 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 618 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 551 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 423 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 408 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 392 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 391 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 120 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 50 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 51 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 59 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 61 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 62 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 63 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 63 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 66 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 66 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 66 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 68 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 70 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 68 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 63 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 63 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 63 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 63 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see

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192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 2975 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 393.336471 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 197.951950 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 413.488148 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 1360 45.71% 45.71% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 404 13.58% 59.29% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 131 4.40% 63.70% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 68 2.29% 65.98% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 81 2.72% 68.71% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 67 2.25% 70.96% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 54 1.82% 72.77% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 34 1.14% 73.92% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 776 26.08% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 2975 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 63 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 272.444444 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::gmean 27.585882 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::stdev 1910.173610 # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::0-511 62 98.41% 98.41% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::14848-15359 1 1.59% 100.00% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::total 63 # Reads before turning the bus around for writes
221system.physmem.wrPerTurnAround::samples 63 # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::mean 17.730159 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::gmean 17.698769 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::stdev 1.080716 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::16 12 19.05% 19.05% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::17 1 1.59% 20.63% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::18 46 73.02% 93.65% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::19 3 4.76% 98.41% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::23 1 1.59% 100.00% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::total 63 # Writes before turning the bus around for reads
231system.physmem.totQLat 228948216 # Total ticks spent queuing
232system.physmem.totMemAccLat 551223216 # Total ticks spent from burst creation until serviced by the DRAM
233system.physmem.totBusLat 85940000 # Total ticks spent in databus transfers
234system.physmem.avgQLat 13320.24 # Average queueing delay per DRAM burst
235system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
236system.physmem.avgMemAccLat 32070.24 # Average memory access latency per DRAM burst
237system.physmem.avgRdBW 19.06 # Average DRAM read bandwidth in MiByte/s
238system.physmem.avgWrBW 1.24 # Average achieved write bandwidth in MiByte/s
239system.physmem.avgRdBWSys 19.40 # Average system read bandwidth in MiByte/s
240system.physmem.avgWrBWSys 1.28 # Average system write bandwidth in MiByte/s
241system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
242system.physmem.busUtil 0.16 # Data bus utilization in percentage
243system.physmem.busUtilRead 0.15 # Data bus utilization in percentage for reads
244system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
245system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
246system.physmem.avgWrQLen 14.66 # Average write queue length when enqueuing
247system.physmem.readRowHits 14950 # Number of row buffer hits during reads
248system.physmem.writeRowHits 375 # Number of row buffer hits during writes
249system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads
250system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes
251system.physmem.avgGap 3096169.77 # Average gap between requests
252system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined
253system.physmem.memoryStateTime::IDLE 51355249007 # Time in different power states
254system.physmem.memoryStateTime::REF 1927120000 # Time in different power states
255system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
256system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states
257system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
258system.membus.trans_dist::ReadReq 17158 # Transaction distribution
259system.membus.trans_dist::ReadResp 17158 # Transaction distribution
260system.membus.trans_dist::Writeback 1150 # Transaction distribution
261system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
262system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
263system.membus.trans_dist::ReadExReq 332 # Transaction distribution
264system.membus.trans_dist::ReadExResp 332 # Transaction distribution
265system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 36134 # Packet count per connected master and slave (bytes)
266system.membus.pkt_count::total 36134 # Packet count per connected master and slave (bytes)
267system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192960 # Cumulative packet size per connected master and slave (bytes)
268system.membus.pkt_size::total 1192960 # Cumulative packet size per connected master and slave (bytes)
269system.membus.snoops 0 # Total snoops (count)
270system.membus.snoop_fanout::samples 18642 # Request fanout histogram
271system.membus.snoop_fanout::mean 0 # Request fanout histogram
272system.membus.snoop_fanout::stdev 0 # Request fanout histogram
273system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
274system.membus.snoop_fanout::0 18642 100.00% 100.00% # Request fanout histogram
275system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
276system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
277system.membus.snoop_fanout::min_value 0 # Request fanout histogram
278system.membus.snoop_fanout::max_value 0 # Request fanout histogram
279system.membus.snoop_fanout::total 18642 # Request fanout histogram
280system.membus.reqLayer0.occupancy 32019899 # Layer occupancy (ticks)
281system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
282system.membus.respLayer1.occupancy 163550691 # Layer occupancy (ticks)
283system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
284system.cpu_clk_domain.clock 500 # Clock period in ticks
285system.cpu.branchPred.lookups 28272297 # Number of BP lookups
286system.cpu.branchPred.condPredicted 23289786 # Number of conditional branches predicted
287system.cpu.branchPred.condIncorrect 837936 # Number of conditional branches incorrect
288system.cpu.branchPred.BTBLookups 11858499 # Number of BTB lookups
289system.cpu.branchPred.BTBHits 11790100 # Number of BTB hits
290system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
291system.cpu.branchPred.BTBHitPct 99.423207 # BTB Hit Percentage
292system.cpu.branchPred.usedRAS 75765 # Number of times the RAS was used to get a target.
293system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions.
294system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
295system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
296system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
297system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
298system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
299system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
300system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
301system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

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371system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
372system.cpu.itb.read_accesses 0 # DTB read accesses
373system.cpu.itb.write_accesses 0 # DTB write accesses
374system.cpu.itb.inst_accesses 0 # ITB inst accesses
375system.cpu.itb.hits 0 # DTB hits
376system.cpu.itb.misses 0 # DTB misses
377system.cpu.itb.accesses 0 # DTB accesses
378system.cpu.workload.num_syscalls 442 # Number of system calls
379system.cpu.numCycles 115425565 # number of cpu cycles simulated
380system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
381system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
382system.cpu.fetch.icacheStallCycles 745807 # Number of cycles fetch is stalled on an Icache miss
383system.cpu.fetch.Insts 135034231 # Number of instructions fetch has processed
384system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered
385system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken
386system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked
387system.cpu.fetch.SquashCycles 1679444 # Number of cycles fetch has spent squashing
388system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
389system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR
390system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched
391system.cpu.fetch.IcacheSquashes 456 # Number of outstanding Icache misses that were squashed
392system.cpu.fetch.rateDist::samples 115408607 # Number of instructions fetched each cycle (Total)
393system.cpu.fetch.rateDist::mean 1.175345 # Number of instructions fetched each cycle (Total)
394system.cpu.fetch.rateDist::stdev 1.320714 # Number of instructions fetched each cycle (Total)
395system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
396system.cpu.fetch.rateDist::0 57851940 50.13% 50.13% # Number of instructions fetched each cycle (Total)
397system.cpu.fetch.rateDist::1 13925142 12.07% 62.19% # Number of instructions fetched each cycle (Total)
398system.cpu.fetch.rateDist::2 9174755 7.95% 70.14% # Number of instructions fetched each cycle (Total)
399system.cpu.fetch.rateDist::3 34456770 29.86% 100.00% # Number of instructions fetched each cycle (Total)
400system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
401system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
402system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
403system.cpu.fetch.rateDist::total 115408607 # Number of instructions fetched each cycle (Total)
404system.cpu.fetch.branchRate 0.244940 # Number of branch fetches per cycle
405system.cpu.fetch.rate 1.169881 # Number of inst fetches per cycle
406system.cpu.decode.IdleCycles 8865132 # Number of cycles decode is idle
407system.cpu.decode.BlockedCycles 63135589 # Number of cycles decode is blocked
408system.cpu.decode.RunCycles 33034927 # Number of cycles decode is running
409system.cpu.decode.UnblockCycles 9545475 # Number of cycles decode is unblocking
410system.cpu.decode.SquashCycles 827484 # Number of cycles decode is squashing
411system.cpu.decode.BranchResolved 4101291 # Number of times decode resolved a branch
412system.cpu.decode.BranchMispred 12346 # Number of times decode detected a branch misprediction
413system.cpu.decode.DecodedInsts 114392929 # Number of instructions handled by decode
414system.cpu.decode.SquashedInsts 1987160 # Number of squashed instructions handled by decode
415system.cpu.rename.SquashCycles 827484 # Number of cycles rename is squashing
416system.cpu.rename.IdleCycles 15218972 # Number of cycles rename is idle
417system.cpu.rename.BlockCycles 49233807 # Number of cycles rename is blocking
418system.cpu.rename.serializeStallCycles 108012 # count of cycles rename stalled for serializing inst
419system.cpu.rename.RunCycles 35472939 # Number of cycles rename is running
420system.cpu.rename.UnblockCycles 14547393 # Number of cycles rename is unblocking
421system.cpu.rename.RenamedInsts 110855235 # Number of instructions processed by rename
422system.cpu.rename.SquashedInsts 1413432 # Number of squashed instructions processed by rename
423system.cpu.rename.ROBFullEvents 11041669 # Number of times rename has blocked due to ROB full
424system.cpu.rename.IQFullEvents 1056479 # Number of times rename has blocked due to IQ full
425system.cpu.rename.LQFullEvents 1457795 # Number of times rename has blocked due to LQ full
426system.cpu.rename.SQFullEvents 455993 # Number of times rename has blocked due to SQ full
427system.cpu.rename.RenamedOperands 129914313 # Number of destination operands rename has renamed
428system.cpu.rename.RenameLookups 483072528 # Number of register rename lookups that rename has made
429system.cpu.rename.int_rename_lookups 119436601 # Number of integer rename lookups
430system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups
431system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
432system.cpu.rename.UndoneMaps 22601394 # Number of HB maps that are undone due to squashing
433system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed
434system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed
435system.cpu.rename.skidInsts 21215231 # count of insts added to the skid buffer
436system.cpu.memDep0.insertedLoads 26814209 # Number of loads inserted to the mem dependence unit.
437system.cpu.memDep0.insertedStores 5348913 # Number of stores inserted to the mem dependence unit.
438system.cpu.memDep0.conflictingLoads 553765 # Number of conflicting loads.
439system.cpu.memDep0.conflictingStores 291016 # Number of conflicting stores.
440system.cpu.iq.iqInstsAdded 109685133 # Number of instructions added to the IQ (excludes non-spec)
441system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ
442system.cpu.iq.iqInstsIssued 101428277 # Number of instructions issued
443system.cpu.iq.iqSquashedInstsIssued 1059458 # Number of squashed instructions issued
444system.cpu.iq.iqSquashedInstsExamined 18454529 # Number of squashed instructions iterated over during squash; mainly for profiling
445system.cpu.iq.iqSquashedOperandsExamined 41507183 # Number of squashed operands that are examined and possibly removed from graph
446system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed
447system.cpu.iq.issued_per_cycle::samples 115408607 # Number of insts issued each cycle
448system.cpu.iq.issued_per_cycle::mean 0.878862 # Number of insts issued each cycle
449system.cpu.iq.issued_per_cycle::stdev 1.000028 # Number of insts issued each cycle
450system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
451system.cpu.iq.issued_per_cycle::0 54542432 47.26% 47.26% # Number of insts issued each cycle
452system.cpu.iq.issued_per_cycle::1 30109521 26.09% 73.35% # Number of insts issued each cycle
453system.cpu.iq.issued_per_cycle::2 22147517 19.19% 92.54% # Number of insts issued each cycle
454system.cpu.iq.issued_per_cycle::3 7413143 6.42% 98.96% # Number of insts issued each cycle
455system.cpu.iq.issued_per_cycle::4 1195677 1.04% 100.00% # Number of insts issued each cycle
456system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle
457system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
458system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
459system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
460system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
461system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
462system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
463system.cpu.iq.issued_per_cycle::total 115408607 # Number of insts issued each cycle
464system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
465system.cpu.iq.fu_full::IntAlu 9750275 48.86% 48.86% # attempts to use FU when none available
466system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available
467system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available
468system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available
469system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available
470system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available
471system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available
472system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available
473system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
474system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available
475system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available
476system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available
477system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available
478system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available
479system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available
480system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available
481system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available
482system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available
483system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available
484system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available
485system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available
486system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available
487system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available
488system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available
489system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available
490system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
494system.cpu.iq.fu_full::MemRead 9493870 47.57% 96.43% # attempts to use FU when none available
495system.cpu.iq.fu_full::MemWrite 712253 3.57% 100.00% # attempts to use FU when none available
496system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
497system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
498system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
499system.cpu.iq.FU_type_0::IntAlu 71987588 70.97% 70.97% # Type of FU issued
500system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued
501system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued
502system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued
503system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued
504system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued
505system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued
506system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued
507system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued
508system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued
509system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued
510system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued
511system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued
512system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued
513system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued
514system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued
515system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued
516system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued
517system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued
518system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued
519system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued
520system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued
521system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued
522system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 70.98% # Type of FU issued
523system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued
524system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued
525system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued
526system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued
527system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued
528system.cpu.iq.FU_type_0::MemRead 24380841 24.04% 95.02% # Type of FU issued
529system.cpu.iq.FU_type_0::MemWrite 5048955 4.98% 100.00% # Type of FU issued
530system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
531system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
532system.cpu.iq.FU_type_0::total 101428277 # Type of FU issued
533system.cpu.iq.rate 0.878733 # Inst issue rate
534system.cpu.iq.fu_busy_cnt 19956461 # FU busy when requested
535system.cpu.iq.fu_busy_rate 0.196754 # FU busy rate (busy events/executed inst)
536system.cpu.iq.int_inst_queue_reads 339280619 # Number of integer instruction queue reads
537system.cpu.iq.int_inst_queue_writes 128148692 # Number of integer instruction queue writes
538system.cpu.iq.int_inst_queue_wakeup_accesses 99657487 # Number of integer instruction queue wakeup accesses
539system.cpu.iq.fp_inst_queue_reads 461 # Number of floating instruction queue reads
540system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes
541system.cpu.iq.fp_inst_queue_wakeup_accesses 120 # Number of floating instruction queue wakeup accesses
542system.cpu.iq.int_alu_accesses 121384498 # Number of integer alu accesses
543system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses
544system.cpu.iew.lsq.thread0.forwLoads 285190 # Number of loads that had data forwarded from stores
545system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
546system.cpu.iew.lsq.thread0.squashedLoads 4338298 # Number of loads squashed
547system.cpu.iew.lsq.thread0.ignoredResponses 1479 # Number of memory responses ignored because the instruction is squashed
548system.cpu.iew.lsq.thread0.memOrderViolation 1420 # Number of memory ordering violations
549system.cpu.iew.lsq.thread0.squashedStores 604069 # Number of stores squashed
550system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
551system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
552system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled
553system.cpu.iew.lsq.thread0.cacheBlocked 130354 # Number of times an access to memory failed due to the cache being blocked
554system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
555system.cpu.iew.iewSquashCycles 827484 # Number of cycles IEW is squashing
556system.cpu.iew.iewBlockCycles 8008710 # Number of cycles IEW is blocking
557system.cpu.iew.iewUnblockCycles 730406 # Number of cycles IEW is unblocking
558system.cpu.iew.iewDispatchedInsts 109706046 # Number of instructions dispatched to IQ
559system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
560system.cpu.iew.iewDispLoadInsts 26814209 # Number of dispatched load instructions
561system.cpu.iew.iewDispStoreInsts 5348913 # Number of dispatched store instructions
562system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions
563system.cpu.iew.iewIQFullEvents 187279 # Number of times the IQ has become full, causing a stall
564system.cpu.iew.iewLSQFullEvents 360662 # Number of times the LSQ has become full, causing a stall
565system.cpu.iew.memOrderViolationEvents 1420 # Number of memory order violations
566system.cpu.iew.predictedTakenIncorrect 436360 # Number of branches that were predicted taken incorrectly
567system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly
568system.cpu.iew.branchMispredicts 849241 # Number of branch mispredicts detected at execute
569system.cpu.iew.iewExecutedInsts 100145631 # Number of executed instructions
570system.cpu.iew.iewExecLoadInsts 23824107 # Number of load instructions executed
571system.cpu.iew.iewExecSquashedInsts 1282646 # Number of squashed instructions skipped in execute
572system.cpu.iew.exec_swp 0 # number of swp insts executed
573system.cpu.iew.exec_nop 12666 # number of nop insts executed
574system.cpu.iew.exec_refs 28742996 # number of memory reference insts executed
575system.cpu.iew.exec_branches 20629033 # Number of branches executed
576system.cpu.iew.exec_stores 4918889 # Number of stores executed
577system.cpu.iew.exec_rate 0.867621 # Inst execution rate
578system.cpu.iew.wb_sent 99755826 # cumulative count of insts sent to commit
579system.cpu.iew.wb_count 99657607 # cumulative count of insts written-back
580system.cpu.iew.wb_producers 59710820 # num instructions producing a value
581system.cpu.iew.wb_consumers 95563157 # num instructions consuming a value
582system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
583system.cpu.iew.wb_rate 0.863393 # insts written-back per cycle
584system.cpu.iew.wb_fanout 0.624831 # average fanout of values written-back
585system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
586system.cpu.commit.commitSquashedInsts 17390640 # The number of squashed insts skipped by commit
587system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
588system.cpu.commit.branchMispredicts 825698 # The number of times a branch was mispredicted
589system.cpu.commit.committed_per_cycle::samples 112714742 # Number of insts commited each cycle
590system.cpu.commit.committed_per_cycle::mean 0.807824 # Number of insts commited each cycle
591system.cpu.commit.committed_per_cycle::stdev 1.745908 # Number of insts commited each cycle
592system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
593system.cpu.commit.committed_per_cycle::0 76462569 67.84% 67.84% # Number of insts commited each cycle
594system.cpu.commit.committed_per_cycle::1 18443635 16.36% 84.20% # Number of insts commited each cycle
595system.cpu.commit.committed_per_cycle::2 7118441 6.32% 90.52% # Number of insts commited each cycle
596system.cpu.commit.committed_per_cycle::3 3374531 2.99% 93.51% # Number of insts commited each cycle
597system.cpu.commit.committed_per_cycle::4 1758227 1.56% 95.07% # Number of insts commited each cycle
598system.cpu.commit.committed_per_cycle::5 536893 0.48% 95.55% # Number of insts commited each cycle
599system.cpu.commit.committed_per_cycle::6 726177 0.64% 96.19% # Number of insts commited each cycle
600system.cpu.commit.committed_per_cycle::7 179059 0.16% 96.35% # Number of insts commited each cycle
601system.cpu.commit.committed_per_cycle::8 4115210 3.65% 100.00% # Number of insts commited each cycle
602system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
603system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
604system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
605system.cpu.commit.committed_per_cycle::total 112714742 # Number of insts commited each cycle
606system.cpu.commit.committedInsts 90602407 # Number of instructions committed
607system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed
608system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
609system.cpu.commit.refs 27220755 # Number of memory references committed
610system.cpu.commit.loads 22475911 # Number of loads committed
611system.cpu.commit.membars 3888 # Number of memory barriers committed
612system.cpu.commit.branches 18732304 # Number of branches committed
613system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.

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643system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
644system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
645system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
646system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
647system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
648system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
649system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
650system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction
651system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached
652system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
653system.cpu.rob.rob_reads 217038076 # The number of ROB reads
654system.cpu.rob.rob_writes 219583064 # The number of ROB writes
655system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself
656system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling
657system.cpu.committedInsts 90589798 # Number of Instructions Simulated
658system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated
659system.cpu.cpi 1.274156 # CPI: Cycles Per Instruction
660system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads
661system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle
662system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads
663system.cpu.int_regfile_reads 108123919 # number of integer regfile reads
664system.cpu.int_regfile_writes 58738896 # number of integer regfile writes
665system.cpu.fp_regfile_reads 58 # number of floating regfile reads
666system.cpu.fp_regfile_writes 100 # number of floating regfile writes
667system.cpu.cc_regfile_reads 369252810 # number of cc regfile reads
668system.cpu.cc_regfile_writes 58698459 # number of cc regfile writes
669system.cpu.misc_regfile_reads 28460470 # number of misc regfile reads
670system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
671system.cpu.toL2Bus.trans_dist::ReadReq 5262392 # Transaction distribution
672system.cpu.toL2Bus.trans_dist::ReadResp 5262392 # Transaction distribution
673system.cpu.toL2Bus.trans_dist::Writeback 5407164 # Transaction distribution
674system.cpu.toL2Bus.trans_dist::HardPFReq 28368 # Transaction distribution
675system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
676system.cpu.toL2Bus.trans_dist::ReadExReq 225287 # Transaction distribution
677system.cpu.toL2Bus.trans_dist::ReadExResp 225287 # Transaction distribution
678system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1832 # Packet count per connected master and slave (bytes)
679system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16380692 # Packet count per connected master and slave (bytes)
680system.cpu.toL2Bus.pkt_count::total 16382524 # Packet count per connected master and slave (bytes)
681system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58624 # Cumulative packet size per connected master and slave (bytes)
682system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697211456 # Cumulative packet size per connected master and slave (bytes)
683system.cpu.toL2Bus.pkt_size::total 697270080 # Cumulative packet size per connected master and slave (bytes)
684system.cpu.toL2Bus.snoops 28370 # Total snoops (count)
685system.cpu.toL2Bus.snoop_fanout::samples 10923218 # Request fanout histogram
686system.cpu.toL2Bus.snoop_fanout::mean 5.002597 # Request fanout histogram
687system.cpu.toL2Bus.snoop_fanout::stdev 0.050895 # Request fanout histogram
688system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
689system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
690system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
691system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
692system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
693system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
694system.cpu.toL2Bus.snoop_fanout::5 10894850 99.74% 99.74% # Request fanout histogram
695system.cpu.toL2Bus.snoop_fanout::6 28368 0.26% 100.00% # Request fanout histogram
696system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
697system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
698system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
699system.cpu.toL2Bus.snoop_fanout::total 10923218 # Request fanout histogram
700system.cpu.toL2Bus.reqLayer0.occupancy 10854591744 # Layer occupancy (ticks)
701system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%)
702system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks)
703system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
704system.cpu.toL2Bus.respLayer0.occupancy 1387749 # Layer occupancy (ticks)
705system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
706system.cpu.toL2Bus.respLayer1.occupancy 8230203749 # Layer occupancy (ticks)
707system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%)
708system.cpu.icache.tags.replacements 456 # number of replacements
709system.cpu.icache.tags.tagsinuse 432.039034 # Cycle average of tags in use
710system.cpu.icache.tags.total_refs 32315555 # Total number of references to valid blocks.
711system.cpu.icache.tags.sampled_refs 916 # Sample count of references to valid blocks.
712system.cpu.icache.tags.avg_refs 35278.990175 # Average number of references to valid blocks.
713system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
714system.cpu.icache.tags.occ_blocks::cpu.inst 432.039034 # Average occupied blocks per requestor
715system.cpu.icache.tags.occ_percent::cpu.inst 0.843826 # Average percentage of cache occupancy
716system.cpu.icache.tags.occ_percent::total 0.843826 # Average percentage of cache occupancy
717system.cpu.icache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
718system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
719system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
720system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
721system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id
722system.cpu.icache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id
723system.cpu.icache.tags.tag_accesses 64634074 # Number of tag accesses
724system.cpu.icache.tags.data_accesses 64634074 # Number of data accesses
725system.cpu.icache.ReadReq_hits::cpu.inst 32315555 # number of ReadReq hits
726system.cpu.icache.ReadReq_hits::total 32315555 # number of ReadReq hits
727system.cpu.icache.demand_hits::cpu.inst 32315555 # number of demand (read+write) hits
728system.cpu.icache.demand_hits::total 32315555 # number of demand (read+write) hits
729system.cpu.icache.overall_hits::cpu.inst 32315555 # number of overall hits
730system.cpu.icache.overall_hits::total 32315555 # number of overall hits
731system.cpu.icache.ReadReq_misses::cpu.inst 1024 # number of ReadReq misses
732system.cpu.icache.ReadReq_misses::total 1024 # number of ReadReq misses
733system.cpu.icache.demand_misses::cpu.inst 1024 # number of demand (read+write) misses
734system.cpu.icache.demand_misses::total 1024 # number of demand (read+write) misses
735system.cpu.icache.overall_misses::cpu.inst 1024 # number of overall misses
736system.cpu.icache.overall_misses::total 1024 # number of overall misses
737system.cpu.icache.ReadReq_miss_latency::cpu.inst 21430236 # number of ReadReq miss cycles
738system.cpu.icache.ReadReq_miss_latency::total 21430236 # number of ReadReq miss cycles
739system.cpu.icache.demand_miss_latency::cpu.inst 21430236 # number of demand (read+write) miss cycles
740system.cpu.icache.demand_miss_latency::total 21430236 # number of demand (read+write) miss cycles
741system.cpu.icache.overall_miss_latency::cpu.inst 21430236 # number of overall miss cycles
742system.cpu.icache.overall_miss_latency::total 21430236 # number of overall miss cycles
743system.cpu.icache.ReadReq_accesses::cpu.inst 32316579 # number of ReadReq accesses(hits+misses)
744system.cpu.icache.ReadReq_accesses::total 32316579 # number of ReadReq accesses(hits+misses)
745system.cpu.icache.demand_accesses::cpu.inst 32316579 # number of demand (read+write) accesses
746system.cpu.icache.demand_accesses::total 32316579 # number of demand (read+write) accesses
747system.cpu.icache.overall_accesses::cpu.inst 32316579 # number of overall (read+write) accesses
748system.cpu.icache.overall_accesses::total 32316579 # number of overall (read+write) accesses
749system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses
750system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses
751system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses
752system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses
753system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses
754system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses
755system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.964844 # average ReadReq miss latency
756system.cpu.icache.ReadReq_avg_miss_latency::total 20927.964844 # average ReadReq miss latency
757system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency
758system.cpu.icache.demand_avg_miss_latency::total 20927.964844 # average overall miss latency
759system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency
760system.cpu.icache.overall_avg_miss_latency::total 20927.964844 # average overall miss latency
761system.cpu.icache.blocked_cycles::no_mshrs 3188 # number of cycles access was blocked
762system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
763system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked
764system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
765system.cpu.icache.avg_blocked_cycles::no_mshrs 18.752941 # average number of cycles each access was blocked
766system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
767system.cpu.icache.fast_writes 0 # number of fast writes performed
768system.cpu.icache.cache_copies 0 # number of cache copies performed
769system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits
770system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits
771system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits
772system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
773system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits
774system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits
775system.cpu.icache.ReadReq_mshr_misses::cpu.inst 916 # number of ReadReq MSHR misses
776system.cpu.icache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses
777system.cpu.icache.demand_mshr_misses::cpu.inst 916 # number of demand (read+write) MSHR misses
778system.cpu.icache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses
779system.cpu.icache.overall_mshr_misses::cpu.inst 916 # number of overall MSHR misses
780system.cpu.icache.overall_mshr_misses::total 916 # number of overall MSHR misses
781system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17850739 # number of ReadReq MSHR miss cycles
782system.cpu.icache.ReadReq_mshr_miss_latency::total 17850739 # number of ReadReq MSHR miss cycles
783system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17850739 # number of demand (read+write) MSHR miss cycles
784system.cpu.icache.demand_mshr_miss_latency::total 17850739 # number of demand (read+write) MSHR miss cycles
785system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17850739 # number of overall MSHR miss cycles
786system.cpu.icache.overall_mshr_miss_latency::total 17850739 # number of overall MSHR miss cycles
787system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
788system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
789system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
790system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
791system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
792system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
793system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19487.706332 # average ReadReq mshr miss latency
794system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19487.706332 # average ReadReq mshr miss latency
795system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency
796system.cpu.icache.demand_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency
797system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency
798system.cpu.icache.overall_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency
799system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
800system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 8891809 # number of hwpf identified
801system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 13933 # number of hwpf that were already in mshr
802system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7995771 # number of hwpf that were already in the cache
803system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 738007 # number of hwpf that were already in the prefetch queue
804system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
805system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 118754 # number of hwpf removed because MSHR allocated
806system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 25344 # number of hwpf issued
807system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 15103327 # number of hwpf spanning a virtual page
808system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
809system.cpu.l2cache.tags.replacements 1672 # number of replacements
810system.cpu.l2cache.tags.tagsinuse 12558.688532 # Cycle average of tags in use
811system.cpu.l2cache.tags.total_refs 10641390 # Total number of references to valid blocks.
812system.cpu.l2cache.tags.sampled_refs 17530 # Sample count of references to valid blocks.
813system.cpu.l2cache.tags.avg_refs 607.038791 # Average number of references to valid blocks.
814system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
815system.cpu.l2cache.tags.occ_blocks::writebacks 10807.797190 # Average occupied blocks per requestor
816system.cpu.l2cache.tags.occ_blocks::cpu.inst 104.008842 # Average occupied blocks per requestor
817system.cpu.l2cache.tags.occ_blocks::cpu.data 299.224972 # Average occupied blocks per requestor
818system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1347.657528 # Average occupied blocks per requestor
819system.cpu.l2cache.tags.occ_percent::writebacks 0.659656 # Average percentage of cache occupancy
820system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006348 # Average percentage of cache occupancy
821system.cpu.l2cache.tags.occ_percent::cpu.data 0.018263 # Average percentage of cache occupancy
822system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082254 # Average percentage of cache occupancy
823system.cpu.l2cache.tags.occ_percent::total 0.766522 # Average percentage of cache occupancy
824system.cpu.l2cache.tags.occ_task_id_blocks::1022 1557 # Occupied blocks per task id
825system.cpu.l2cache.tags.occ_task_id_blocks::1024 14301 # Occupied blocks per task id
826system.cpu.l2cache.tags.age_task_id_blocks_1022::0 48 # Occupied blocks per task id
827system.cpu.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id
828system.cpu.l2cache.tags.age_task_id_blocks_1022::2 89 # Occupied blocks per task id
829system.cpu.l2cache.tags.age_task_id_blocks_1022::3 39 # Occupied blocks per task id
830system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1370 # Occupied blocks per task id
831system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
832system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
833system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id
834system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id
835system.cpu.l2cache.tags.age_task_id_blocks_1024::4 12200 # Occupied blocks per task id
836system.cpu.l2cache.tags.occ_task_id_percent::1022 0.095032 # Percentage of cache occupancy per task id
837system.cpu.l2cache.tags.occ_task_id_percent::1024 0.872864 # Percentage of cache occupancy per task id
838system.cpu.l2cache.tags.tag_accesses 174560305 # Number of tag accesses
839system.cpu.l2cache.tags.data_accesses 174560305 # Number of data accesses
840system.cpu.l2cache.ReadReq_hits::cpu.inst 753 # number of ReadReq hits
841system.cpu.l2cache.ReadReq_hits::cpu.data 5260483 # number of ReadReq hits
842system.cpu.l2cache.ReadReq_hits::total 5261236 # number of ReadReq hits
843system.cpu.l2cache.Writeback_hits::writebacks 5407164 # number of Writeback hits
844system.cpu.l2cache.Writeback_hits::total 5407164 # number of Writeback hits
845system.cpu.l2cache.ReadExReq_hits::cpu.data 224791 # number of ReadExReq hits
846system.cpu.l2cache.ReadExReq_hits::total 224791 # number of ReadExReq hits
847system.cpu.l2cache.demand_hits::cpu.inst 753 # number of demand (read+write) hits
848system.cpu.l2cache.demand_hits::cpu.data 5485274 # number of demand (read+write) hits
849system.cpu.l2cache.demand_hits::total 5486027 # number of demand (read+write) hits
850system.cpu.l2cache.overall_hits::cpu.inst 753 # number of overall hits
851system.cpu.l2cache.overall_hits::cpu.data 5485274 # number of overall hits
852system.cpu.l2cache.overall_hits::total 5486027 # number of overall hits
853system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
854system.cpu.l2cache.ReadReq_misses::cpu.data 993 # number of ReadReq misses
855system.cpu.l2cache.ReadReq_misses::total 1156 # number of ReadReq misses
856system.cpu.l2cache.ReadExReq_misses::cpu.data 496 # number of ReadExReq misses
857system.cpu.l2cache.ReadExReq_misses::total 496 # number of ReadExReq misses
858system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
859system.cpu.l2cache.demand_misses::cpu.data 1489 # number of demand (read+write) misses
860system.cpu.l2cache.demand_misses::total 1652 # number of demand (read+write) misses
861system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
862system.cpu.l2cache.overall_misses::cpu.data 1489 # number of overall misses
863system.cpu.l2cache.overall_misses::total 1652 # number of overall misses
864system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12439500 # number of ReadReq miss cycles
865system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59393247 # number of ReadReq miss cycles
866system.cpu.l2cache.ReadReq_miss_latency::total 71832747 # number of ReadReq miss cycles
867system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31513998 # number of ReadExReq miss cycles
868system.cpu.l2cache.ReadExReq_miss_latency::total 31513998 # number of ReadExReq miss cycles
869system.cpu.l2cache.demand_miss_latency::cpu.inst 12439500 # number of demand (read+write) miss cycles
870system.cpu.l2cache.demand_miss_latency::cpu.data 90907245 # number of demand (read+write) miss cycles
871system.cpu.l2cache.demand_miss_latency::total 103346745 # number of demand (read+write) miss cycles
872system.cpu.l2cache.overall_miss_latency::cpu.inst 12439500 # number of overall miss cycles
873system.cpu.l2cache.overall_miss_latency::cpu.data 90907245 # number of overall miss cycles
874system.cpu.l2cache.overall_miss_latency::total 103346745 # number of overall miss cycles
875system.cpu.l2cache.ReadReq_accesses::cpu.inst 916 # number of ReadReq accesses(hits+misses)
876system.cpu.l2cache.ReadReq_accesses::cpu.data 5261476 # number of ReadReq accesses(hits+misses)
877system.cpu.l2cache.ReadReq_accesses::total 5262392 # number of ReadReq accesses(hits+misses)
878system.cpu.l2cache.Writeback_accesses::writebacks 5407164 # number of Writeback accesses(hits+misses)
879system.cpu.l2cache.Writeback_accesses::total 5407164 # number of Writeback accesses(hits+misses)
880system.cpu.l2cache.ReadExReq_accesses::cpu.data 225287 # number of ReadExReq accesses(hits+misses)
881system.cpu.l2cache.ReadExReq_accesses::total 225287 # number of ReadExReq accesses(hits+misses)
882system.cpu.l2cache.demand_accesses::cpu.inst 916 # number of demand (read+write) accesses
883system.cpu.l2cache.demand_accesses::cpu.data 5486763 # number of demand (read+write) accesses
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885system.cpu.l2cache.overall_accesses::cpu.inst 916 # number of overall (read+write) accesses
886system.cpu.l2cache.overall_accesses::cpu.data 5486763 # number of overall (read+write) accesses
887system.cpu.l2cache.overall_accesses::total 5487679 # number of overall (read+write) accesses
888system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177948 # miss rate for ReadReq accesses
889system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000189 # miss rate for ReadReq accesses
890system.cpu.l2cache.ReadReq_miss_rate::total 0.000220 # miss rate for ReadReq accesses
891system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002202 # miss rate for ReadExReq accesses
892system.cpu.l2cache.ReadExReq_miss_rate::total 0.002202 # miss rate for ReadExReq accesses
893system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177948 # miss rate for demand accesses
894system.cpu.l2cache.demand_miss_rate::cpu.data 0.000271 # miss rate for demand accesses
895system.cpu.l2cache.demand_miss_rate::total 0.000301 # miss rate for demand accesses
896system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177948 # miss rate for overall accesses
897system.cpu.l2cache.overall_miss_rate::cpu.data 0.000271 # miss rate for overall accesses
898system.cpu.l2cache.overall_miss_rate::total 0.000301 # miss rate for overall accesses
899system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76315.950920 # average ReadReq miss latency
900system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59811.930514 # average ReadReq miss latency
901system.cpu.l2cache.ReadReq_avg_miss_latency::total 62139.054498 # average ReadReq miss latency
902system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63536.286290 # average ReadExReq miss latency
903system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63536.286290 # average ReadExReq miss latency
904system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency
905system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency
906system.cpu.l2cache.demand_avg_miss_latency::total 62558.562349 # average overall miss latency
907system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency
908system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency
909system.cpu.l2cache.overall_avg_miss_latency::total 62558.562349 # average overall miss latency
910system.cpu.l2cache.blocked_cycles::no_mshrs 820 # number of cycles access was blocked
911system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
912system.cpu.l2cache.blocked::no_mshrs 50 # number of cycles access was blocked
913system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
914system.cpu.l2cache.avg_blocked_cycles::no_mshrs 16.400000 # average number of cycles each access was blocked
915system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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917system.cpu.l2cache.cache_copies 0 # number of cache copies performed
918system.cpu.l2cache.writebacks::writebacks 1150 # number of writebacks
919system.cpu.l2cache.writebacks::total 1150 # number of writebacks
920system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits
921system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 256 # number of ReadReq MSHR hits
922system.cpu.l2cache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits
923system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits
924system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits
925system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits
926system.cpu.l2cache.demand_mshr_hits::cpu.data 418 # number of demand (read+write) MSHR hits
927system.cpu.l2cache.demand_mshr_hits::total 442 # number of demand (read+write) MSHR hits
928system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits
929system.cpu.l2cache.overall_mshr_hits::cpu.data 418 # number of overall MSHR hits
930system.cpu.l2cache.overall_mshr_hits::total 442 # number of overall MSHR hits
931system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 139 # number of ReadReq MSHR misses
932system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 737 # number of ReadReq MSHR misses
933system.cpu.l2cache.ReadReq_mshr_misses::total 876 # number of ReadReq MSHR misses
934system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 25344 # number of HardPFReq MSHR misses
935system.cpu.l2cache.HardPFReq_mshr_misses::total 25344 # number of HardPFReq MSHR misses
936system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 334 # number of ReadExReq MSHR misses
937system.cpu.l2cache.ReadExReq_mshr_misses::total 334 # number of ReadExReq MSHR misses
938system.cpu.l2cache.demand_mshr_misses::cpu.inst 139 # number of demand (read+write) MSHR misses
939system.cpu.l2cache.demand_mshr_misses::cpu.data 1071 # number of demand (read+write) MSHR misses
940system.cpu.l2cache.demand_mshr_misses::total 1210 # number of demand (read+write) MSHR misses
941system.cpu.l2cache.overall_mshr_misses::cpu.inst 139 # number of overall MSHR misses
942system.cpu.l2cache.overall_mshr_misses::cpu.data 1071 # number of overall MSHR misses
943system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 25344 # number of overall MSHR misses
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946system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41114499 # number of ReadReq MSHR miss cycles
947system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51400499 # number of ReadReq MSHR miss cycles
948system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of HardPFReq MSHR miss cycles
949system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 910618800 # number of HardPFReq MSHR miss cycles
950system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 20873252 # number of ReadExReq MSHR miss cycles
951system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 20873252 # number of ReadExReq MSHR miss cycles
952system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10286000 # number of demand (read+write) MSHR miss cycles
953system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61987751 # number of demand (read+write) MSHR miss cycles
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955system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10286000 # number of overall MSHR miss cycles
956system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61987751 # number of overall MSHR miss cycles
957system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of overall MSHR miss cycles
958system.cpu.l2cache.overall_mshr_miss_latency::total 982892551 # number of overall MSHR miss cycles
959system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for ReadReq accesses
960system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000140 # mshr miss rate for ReadReq accesses
961system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000166 # mshr miss rate for ReadReq accesses
962system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
963system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
964system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001483 # mshr miss rate for ReadExReq accesses
965system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001483 # mshr miss rate for ReadExReq accesses
966system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for demand accesses
967system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for demand accesses
968system.cpu.l2cache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses
969system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for overall accesses
970system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for overall accesses
971system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
972system.cpu.l2cache.overall_mshr_miss_rate::total 0.004839 # mshr miss rate for overall accesses
973system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74000 # average ReadReq mshr miss latency
974system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55786.294437 # average ReadReq mshr miss latency
975system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58676.368721 # average ReadReq mshr miss latency
976system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average HardPFReq mshr miss latency
977system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35930.350379 # average HardPFReq mshr miss latency
978system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62494.766467 # average ReadExReq mshr miss latency
979system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62494.766467 # average ReadExReq mshr miss latency
980system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency
981system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency
982system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59730.372727 # average overall mshr miss latency
983system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency
984system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency
985system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average overall mshr miss latency
986system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37014.858439 # average overall mshr miss latency
987system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
988system.cpu.dcache.tags.replacements 5486251 # number of replacements
989system.cpu.dcache.tags.tagsinuse 511.841559 # Cycle average of tags in use
990system.cpu.dcache.tags.total_refs 18271309 # Total number of references to valid blocks.
991system.cpu.dcache.tags.sampled_refs 5486763 # Sample count of references to valid blocks.
992system.cpu.dcache.tags.avg_refs 3.330071 # Average number of references to valid blocks.
993system.cpu.dcache.tags.warmup_cycle 27123000 # Cycle when the warmup percentage was hit.
994system.cpu.dcache.tags.occ_blocks::cpu.data 511.841559 # Average occupied blocks per requestor
995system.cpu.dcache.tags.occ_percent::cpu.data 0.999691 # Average percentage of cache occupancy
996system.cpu.dcache.tags.occ_percent::total 0.999691 # Average percentage of cache occupancy
997system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
998system.cpu.dcache.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id
999system.cpu.dcache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id
1000system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1001system.cpu.dcache.tags.tag_accesses 61969579 # Number of tag accesses
1002system.cpu.dcache.tags.data_accesses 61969579 # Number of data accesses
1003system.cpu.dcache.ReadReq_hits::cpu.data 13905693 # number of ReadReq hits
1004system.cpu.dcache.ReadReq_hits::total 13905693 # number of ReadReq hits
1005system.cpu.dcache.WriteReq_hits::cpu.data 4357334 # number of WriteReq hits
1006system.cpu.dcache.WriteReq_hits::total 4357334 # number of WriteReq hits
1007system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
1008system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
1009system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits
1010system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits
1011system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
1012system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
1013system.cpu.dcache.demand_hits::cpu.data 18263027 # number of demand (read+write) hits
1014system.cpu.dcache.demand_hits::total 18263027 # number of demand (read+write) hits
1015system.cpu.dcache.overall_hits::cpu.data 18263549 # number of overall hits
1016system.cpu.dcache.overall_hits::total 18263549 # number of overall hits
1017system.cpu.dcache.ReadReq_misses::cpu.data 9592430 # number of ReadReq misses
1018system.cpu.dcache.ReadReq_misses::total 9592430 # number of ReadReq misses
1019system.cpu.dcache.WriteReq_misses::cpu.data 377647 # number of WriteReq misses
1020system.cpu.dcache.WriteReq_misses::total 377647 # number of WriteReq misses
1021system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses
1022system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses
1023system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses
1024system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses
1025system.cpu.dcache.demand_misses::cpu.data 9970077 # number of demand (read+write) misses
1026system.cpu.dcache.demand_misses::total 9970077 # number of demand (read+write) misses
1027system.cpu.dcache.overall_misses::cpu.data 9970085 # number of overall misses
1028system.cpu.dcache.overall_misses::total 9970085 # number of overall misses
1029system.cpu.dcache.ReadReq_miss_latency::cpu.data 87035855746 # number of ReadReq miss cycles
1030system.cpu.dcache.ReadReq_miss_latency::total 87035855746 # number of ReadReq miss cycles
1031system.cpu.dcache.WriteReq_miss_latency::cpu.data 3957576177 # number of WriteReq miss cycles
1032system.cpu.dcache.WriteReq_miss_latency::total 3957576177 # number of WriteReq miss cycles
1033system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 283250 # number of LoadLockedReq miss cycles
1034system.cpu.dcache.LoadLockedReq_miss_latency::total 283250 # number of LoadLockedReq miss cycles
1035system.cpu.dcache.demand_miss_latency::cpu.data 90993431923 # number of demand (read+write) miss cycles
1036system.cpu.dcache.demand_miss_latency::total 90993431923 # number of demand (read+write) miss cycles
1037system.cpu.dcache.overall_miss_latency::cpu.data 90993431923 # number of overall miss cycles
1038system.cpu.dcache.overall_miss_latency::total 90993431923 # number of overall miss cycles
1039system.cpu.dcache.ReadReq_accesses::cpu.data 23498123 # number of ReadReq accesses(hits+misses)
1040system.cpu.dcache.ReadReq_accesses::total 23498123 # number of ReadReq accesses(hits+misses)
1041system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
1042system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
1043system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses)
1044system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses)
1045system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
1046system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
1047system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
1048system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
1049system.cpu.dcache.demand_accesses::cpu.data 28233104 # number of demand (read+write) accesses
1050system.cpu.dcache.demand_accesses::total 28233104 # number of demand (read+write) accesses
1051system.cpu.dcache.overall_accesses::cpu.data 28233634 # number of overall (read+write) accesses
1052system.cpu.dcache.overall_accesses::total 28233634 # number of overall (read+write) accesses
1053system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408221 # miss rate for ReadReq accesses
1054system.cpu.dcache.ReadReq_miss_rate::total 0.408221 # miss rate for ReadReq accesses
1055system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079757 # miss rate for WriteReq accesses
1056system.cpu.dcache.WriteReq_miss_rate::total 0.079757 # miss rate for WriteReq accesses
1057system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses
1058system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses
1059system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses
1060system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses
1061system.cpu.dcache.demand_miss_rate::cpu.data 0.353134 # miss rate for demand accesses
1062system.cpu.dcache.demand_miss_rate::total 0.353134 # miss rate for demand accesses
1063system.cpu.dcache.overall_miss_rate::cpu.data 0.353128 # miss rate for overall accesses
1064system.cpu.dcache.overall_miss_rate::total 0.353128 # miss rate for overall accesses
1065system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9073.389719 # average ReadReq miss latency
1066system.cpu.dcache.ReadReq_avg_miss_latency::total 9073.389719 # average ReadReq miss latency
1067system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10479.564718 # average WriteReq miss latency
1068system.cpu.dcache.WriteReq_avg_miss_latency::total 10479.564718 # average WriteReq miss latency
1069system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20232.142857 # average LoadLockedReq miss latency
1070system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20232.142857 # average LoadLockedReq miss latency
1071system.cpu.dcache.demand_avg_miss_latency::cpu.data 9126.652876 # average overall miss latency
1072system.cpu.dcache.demand_avg_miss_latency::total 9126.652876 # average overall miss latency
1073system.cpu.dcache.overall_avg_miss_latency::cpu.data 9126.645552 # average overall miss latency
1074system.cpu.dcache.overall_avg_miss_latency::total 9126.645552 # average overall miss latency
1075system.cpu.dcache.blocked_cycles::no_mshrs 301384 # number of cycles access was blocked
1076system.cpu.dcache.blocked_cycles::no_targets 67125 # number of cycles access was blocked
1077system.cpu.dcache.blocked::no_mshrs 120500 # number of cycles access was blocked
1078system.cpu.dcache.blocked::no_targets 12183 # number of cycles access was blocked
1079system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.501112 # average number of cycles each access was blocked
1080system.cpu.dcache.avg_blocked_cycles::no_targets 5.509727 # average number of cycles each access was blocked
1081system.cpu.dcache.fast_writes 0 # number of fast writes performed
1082system.cpu.dcache.cache_copies 0 # number of cache copies performed
1083system.cpu.dcache.writebacks::writebacks 5407164 # number of writebacks
1084system.cpu.dcache.writebacks::total 5407164 # number of writebacks
1085system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328464 # number of ReadReq MSHR hits
1086system.cpu.dcache.ReadReq_mshr_hits::total 4328464 # number of ReadReq MSHR hits
1087system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154855 # number of WriteReq MSHR hits
1088system.cpu.dcache.WriteReq_mshr_hits::total 154855 # number of WriteReq MSHR hits
1089system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits
1090system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits
1091system.cpu.dcache.demand_mshr_hits::cpu.data 4483319 # number of demand (read+write) MSHR hits
1092system.cpu.dcache.demand_mshr_hits::total 4483319 # number of demand (read+write) MSHR hits
1093system.cpu.dcache.overall_mshr_hits::cpu.data 4483319 # number of overall MSHR hits
1094system.cpu.dcache.overall_mshr_hits::total 4483319 # number of overall MSHR hits
1095system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263966 # number of ReadReq MSHR misses
1096system.cpu.dcache.ReadReq_mshr_misses::total 5263966 # number of ReadReq MSHR misses
1097system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222792 # number of WriteReq MSHR misses
1098system.cpu.dcache.WriteReq_mshr_misses::total 222792 # number of WriteReq MSHR misses
1099system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses
1100system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses
1101system.cpu.dcache.demand_mshr_misses::cpu.data 5486758 # number of demand (read+write) MSHR misses
1102system.cpu.dcache.demand_mshr_misses::total 5486758 # number of demand (read+write) MSHR misses
1103system.cpu.dcache.overall_mshr_misses::cpu.data 5486763 # number of overall MSHR misses
1104system.cpu.dcache.overall_mshr_misses::total 5486763 # number of overall MSHR misses
1105system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38232328002 # number of ReadReq MSHR miss cycles
1106system.cpu.dcache.ReadReq_mshr_miss_latency::total 38232328002 # number of ReadReq MSHR miss cycles
1107system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2158774283 # number of WriteReq MSHR miss cycles
1108system.cpu.dcache.WriteReq_mshr_miss_latency::total 2158774283 # number of WriteReq MSHR miss cycles
1109system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 284500 # number of SoftPFReq MSHR miss cycles
1110system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 284500 # number of SoftPFReq MSHR miss cycles
1111system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40391102285 # number of demand (read+write) MSHR miss cycles
1112system.cpu.dcache.demand_mshr_miss_latency::total 40391102285 # number of demand (read+write) MSHR miss cycles
1113system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40391386785 # number of overall MSHR miss cycles
1114system.cpu.dcache.overall_mshr_miss_latency::total 40391386785 # number of overall MSHR miss cycles
1115system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224016 # mshr miss rate for ReadReq accesses
1116system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224016 # mshr miss rate for ReadReq accesses
1117system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses
1118system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses
1119system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses
1120system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses
1121system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194338 # mshr miss rate for demand accesses
1122system.cpu.dcache.demand_mshr_miss_rate::total 0.194338 # mshr miss rate for demand accesses
1123system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194334 # mshr miss rate for overall accesses
1124system.cpu.dcache.overall_mshr_miss_rate::total 0.194334 # mshr miss rate for overall accesses
1125system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7263.027155 # average ReadReq mshr miss latency
1126system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7263.027155 # average ReadReq mshr miss latency
1127system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9689.640036 # average WriteReq mshr miss latency
1128system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9689.640036 # average WriteReq mshr miss latency
1129system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56900 # average SoftPFReq mshr miss latency
1130system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56900 # average SoftPFReq mshr miss latency
1131system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7361.560740 # average overall mshr miss latency
1132system.cpu.dcache.demand_avg_mshr_miss_latency::total 7361.560740 # average overall mshr miss latency
1133system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7361.605884 # average overall mshr miss latency
1134system.cpu.dcache.overall_avg_mshr_miss_latency::total 7361.605884 # average overall mshr miss latency
1135system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1136
1137---------- End Simulation Statistics ----------