Cross Reference: /gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini

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config.ini (9885:afd9ea6101d9)	config.ini (9924:31ef410b6843)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu.branchPred 50cachePorts=200 51checker=Null 52clk_domain=system.cpu_clk_domain 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu.dtb 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78interrupts=system.cpu.interrupts 79isa=system.cpu.isa 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83max_insts_all_threads=0 84max_insts_any_thread=0 85max_loads_all_threads=0 86max_loads_any_thread=0 87needsTSO=false 88numIQEntries=64	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu.branchPred 50cachePorts=200 51checker=Null 52clk_domain=system.cpu_clk_domain 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu.dtb 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78interrupts=system.cpu.interrupts 79isa=system.cpu.isa 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83max_insts_all_threads=0 84max_insts_any_thread=0 85max_loads_all_threads=0 86max_loads_any_thread=0 87needsTSO=false 88numIQEntries=64
	89numPhysCCRegs=0
89numPhysFloatRegs=256 90numPhysIntRegs=256 91numROBEntries=192 92numRobs=1 93numThreads=1 94profile=0 95progress_interval=0 96renameToDecodeDelay=1 97renameToFetchDelay=1 98renameToIEWDelay=2 99renameToROBDelay=1 100renameWidth=8 101simpoint_start_insts= 102smtCommitPolicy=RoundRobin 103smtFetchPolicy=SingleThread 104smtIQPolicy=Partitioned 105smtIQThreshold=100 106smtLSQPolicy=Partitioned 107smtLSQThreshold=100 108smtNumFetchingThreads=1 109smtROBPolicy=Partitioned 110smtROBThreshold=100 111squashWidth=8 112store_set_clear_period=250000 113switched_out=false 114system=system 115tracer=system.cpu.tracer 116trapLatency=13 117wbDepth=1 118wbWidth=8 119workload=system.cpu.workload 120dcache_port=system.cpu.dcache.cpu_side 121icache_port=system.cpu.icache.cpu_side 122 123[system.cpu.branchPred] 124type=BranchPredictor 125BTBEntries=4096 126BTBTagSize=16 127RASSize=16 128choiceCtrBits=2 129choicePredictorSize=8192 130globalCtrBits=2 131globalPredictorSize=8192 132instShiftAmt=2 133localCtrBits=2 134localHistoryTableSize=2048 135localPredictorSize=2048 136numThreads=1 137predType=tournament 138 139[system.cpu.dcache] 140type=BaseCache 141children=tags 142addr_ranges=0:18446744073709551615 143assoc=2 144clk_domain=system.cpu_clk_domain 145forward_snoops=true 146hit_latency=2 147is_top_level=true 148max_miss_count=0 149mshrs=4 150prefetch_on_access=false 151prefetcher=Null 152response_latency=2 153size=262144 154system=system 155tags=system.cpu.dcache.tags 156tgts_per_mshr=20 157two_queue=false 158write_buffers=8 159cpu_side=system.cpu.dcache_port 160mem_side=system.cpu.toL2Bus.slave[1] 161 162[system.cpu.dcache.tags] 163type=LRU 164assoc=2 165block_size=64 166clk_domain=system.cpu_clk_domain 167hit_latency=2 168size=262144 169 170[system.cpu.dtb] 171type=ArmTLB 172children=walker 173size=64 174walker=system.cpu.dtb.walker 175 176[system.cpu.dtb.walker] 177type=ArmTableWalker 178clk_domain=system.cpu_clk_domain 179num_squash_per_cycle=2 180sys=system 181port=system.cpu.toL2Bus.slave[3] 182 183[system.cpu.fuPool] 184type=FUPool 185children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 186FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 187 188[system.cpu.fuPool.FUList0] 189type=FUDesc 190children=opList 191count=6 192opList=system.cpu.fuPool.FUList0.opList 193 194[system.cpu.fuPool.FUList0.opList] 195type=OpDesc 196issueLat=1 197opClass=IntAlu 198opLat=1 199 200[system.cpu.fuPool.FUList1] 201type=FUDesc 202children=opList0 opList1 203count=2 204opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 205 206[system.cpu.fuPool.FUList1.opList0] 207type=OpDesc 208issueLat=1 209opClass=IntMult 210opLat=3 211 212[system.cpu.fuPool.FUList1.opList1] 213type=OpDesc 214issueLat=19 215opClass=IntDiv 216opLat=20 217 218[system.cpu.fuPool.FUList2] 219type=FUDesc 220children=opList0 opList1 opList2 221count=4 222opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 223 224[system.cpu.fuPool.FUList2.opList0] 225type=OpDesc 226issueLat=1 227opClass=FloatAdd 228opLat=2 229 230[system.cpu.fuPool.FUList2.opList1] 231type=OpDesc 232issueLat=1 233opClass=FloatCmp 234opLat=2 235 236[system.cpu.fuPool.FUList2.opList2] 237type=OpDesc 238issueLat=1 239opClass=FloatCvt 240opLat=2 241 242[system.cpu.fuPool.FUList3] 243type=FUDesc 244children=opList0 opList1 opList2 245count=2 246opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 247 248[system.cpu.fuPool.FUList3.opList0] 249type=OpDesc 250issueLat=1 251opClass=FloatMult 252opLat=4 253 254[system.cpu.fuPool.FUList3.opList1] 255type=OpDesc 256issueLat=12 257opClass=FloatDiv 258opLat=12 259 260[system.cpu.fuPool.FUList3.opList2] 261type=OpDesc 262issueLat=24 263opClass=FloatSqrt 264opLat=24 265 266[system.cpu.fuPool.FUList4] 267type=FUDesc 268children=opList 269count=0 270opList=system.cpu.fuPool.FUList4.opList 271 272[system.cpu.fuPool.FUList4.opList] 273type=OpDesc 274issueLat=1 275opClass=MemRead 276opLat=1 277 278[system.cpu.fuPool.FUList5] 279type=FUDesc 280children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 281count=4 282opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 283 284[system.cpu.fuPool.FUList5.opList00] 285type=OpDesc 286issueLat=1 287opClass=SimdAdd 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList01] 291type=OpDesc 292issueLat=1 293opClass=SimdAddAcc 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList02] 297type=OpDesc 298issueLat=1 299opClass=SimdAlu 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList03] 303type=OpDesc 304issueLat=1 305opClass=SimdCmp 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList04] 309type=OpDesc 310issueLat=1 311opClass=SimdCvt 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList05] 315type=OpDesc 316issueLat=1 317opClass=SimdMisc 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList06] 321type=OpDesc 322issueLat=1 323opClass=SimdMult 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList07] 327type=OpDesc 328issueLat=1 329opClass=SimdMultAcc 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList08] 333type=OpDesc 334issueLat=1 335opClass=SimdShift 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList09] 339type=OpDesc 340issueLat=1 341opClass=SimdShiftAcc 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList10] 345type=OpDesc 346issueLat=1 347opClass=SimdSqrt 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList11] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatAdd 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList12] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatAlu 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList13] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatCmp 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList14] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatCvt 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList15] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatDiv 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList16] 381type=OpDesc 382issueLat=1 383opClass=SimdFloatMisc 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList17] 387type=OpDesc 388issueLat=1 389opClass=SimdFloatMult 390opLat=1 391 392[system.cpu.fuPool.FUList5.opList18] 393type=OpDesc 394issueLat=1 395opClass=SimdFloatMultAcc 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList19] 399type=OpDesc 400issueLat=1 401opClass=SimdFloatSqrt 402opLat=1 403 404[system.cpu.fuPool.FUList6] 405type=FUDesc 406children=opList 407count=0 408opList=system.cpu.fuPool.FUList6.opList 409 410[system.cpu.fuPool.FUList6.opList] 411type=OpDesc 412issueLat=1 413opClass=MemWrite 414opLat=1 415 416[system.cpu.fuPool.FUList7] 417type=FUDesc 418children=opList0 opList1 419count=4 420opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 421 422[system.cpu.fuPool.FUList7.opList0] 423type=OpDesc 424issueLat=1 425opClass=MemRead 426opLat=1 427 428[system.cpu.fuPool.FUList7.opList1] 429type=OpDesc 430issueLat=1 431opClass=MemWrite 432opLat=1 433 434[system.cpu.fuPool.FUList8] 435type=FUDesc 436children=opList 437count=1 438opList=system.cpu.fuPool.FUList8.opList 439 440[system.cpu.fuPool.FUList8.opList] 441type=OpDesc 442issueLat=3 443opClass=IprAccess 444opLat=3 445 446[system.cpu.icache] 447type=BaseCache 448children=tags 449addr_ranges=0:18446744073709551615 450assoc=2 451clk_domain=system.cpu_clk_domain 452forward_snoops=true 453hit_latency=2 454is_top_level=true 455max_miss_count=0 456mshrs=4 457prefetch_on_access=false 458prefetcher=Null 459response_latency=2 460size=131072 461system=system 462tags=system.cpu.icache.tags 463tgts_per_mshr=20 464two_queue=false 465write_buffers=8 466cpu_side=system.cpu.icache_port 467mem_side=system.cpu.toL2Bus.slave[0] 468 469[system.cpu.icache.tags] 470type=LRU 471assoc=2 472block_size=64 473clk_domain=system.cpu_clk_domain 474hit_latency=2 475size=131072 476 477[system.cpu.interrupts] 478type=ArmInterrupts 479 480[system.cpu.isa] 481type=ArmISA 482fpsid=1090793632 483id_isar0=34607377 484id_isar1=34677009 485id_isar2=555950401 486id_isar3=17899825 487id_isar4=268501314 488id_isar5=0 489id_mmfr0=3 490id_mmfr1=0 491id_mmfr2=19070976 492id_mmfr3=4027589137 493id_pfr0=49 494id_pfr1=1 495midr=890224640 496 497[system.cpu.itb] 498type=ArmTLB 499children=walker 500size=64 501walker=system.cpu.itb.walker 502 503[system.cpu.itb.walker] 504type=ArmTableWalker 505clk_domain=system.cpu_clk_domain 506num_squash_per_cycle=2 507sys=system 508port=system.cpu.toL2Bus.slave[2] 509 510[system.cpu.l2cache] 511type=BaseCache 512children=tags 513addr_ranges=0:18446744073709551615 514assoc=8 515clk_domain=system.cpu_clk_domain 516forward_snoops=true 517hit_latency=20 518is_top_level=false 519max_miss_count=0 520mshrs=20 521prefetch_on_access=false 522prefetcher=Null 523response_latency=20 524size=2097152 525system=system 526tags=system.cpu.l2cache.tags 527tgts_per_mshr=12 528two_queue=false 529write_buffers=8 530cpu_side=system.cpu.toL2Bus.master[0] 531mem_side=system.membus.slave[1] 532 533[system.cpu.l2cache.tags] 534type=LRU 535assoc=8 536block_size=64 537clk_domain=system.cpu_clk_domain 538hit_latency=20 539size=2097152 540 541[system.cpu.toL2Bus] 542type=CoherentBus 543clk_domain=system.cpu_clk_domain 544header_cycles=1 545system=system 546use_default_range=false 547width=32 548master=system.cpu.l2cache.cpu_side 549slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 550 551[system.cpu.tracer] 552type=ExeTracer 553 554[system.cpu.workload] 555type=LiveProcess 556cmd=mcf mcf.in 557cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing 558egid=100 559env= 560errout=cerr 561euid=100 562executable=/dist/m5/cpu2000/binaries/arm/linux/mcf 563gid=100 564input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in 565max_stack_size=67108864 566output=cout 567pid=100 568ppid=99 569simpoint=55300000000 570system=system 571uid=100 572 573[system.cpu_clk_domain] 574type=SrcClockDomain 575clock=500 576voltage_domain=system.voltage_domain 577 578[system.membus] 579type=CoherentBus 580clk_domain=system.clk_domain 581header_cycles=1 582system=system 583use_default_range=false 584width=8 585master=system.physmem.port 586slave=system.system_port system.cpu.l2cache.mem_side 587 588[system.physmem] 589type=SimpleDRAM 590activation_limit=4 591addr_mapping=RaBaChCo 592banks_per_rank=8 593burst_length=8 594channels=1 595clk_domain=system.clk_domain 596conf_table_reported=true 597device_bus_width=8 598device_rowbuffer_size=1024 599devices_per_rank=8 600in_addr_map=true 601mem_sched_policy=frfcfs 602null=false 603page_policy=open 604range=0:268435455 605ranks_per_channel=2 606read_buffer_size=32 607static_backend_latency=10000 608static_frontend_latency=10000 609tBURST=5000 610tCL=13750 611tRCD=13750 612tREFI=7800000 613tRFC=300000 614tRP=13750 615tWTR=7500 616tXAW=40000 617write_buffer_size=32 618write_thresh_perc=70 619port=system.membus.master[0] 620 621[system.voltage_domain] 622type=VoltageDomain 623voltage=1.000000 624	90numPhysFloatRegs=256 91numPhysIntRegs=256 92numROBEntries=192 93numRobs=1 94numThreads=1 95profile=0 96progress_interval=0 97renameToDecodeDelay=1 98renameToFetchDelay=1 99renameToIEWDelay=2 100renameToROBDelay=1 101renameWidth=8 102simpoint_start_insts= 103smtCommitPolicy=RoundRobin 104smtFetchPolicy=SingleThread 105smtIQPolicy=Partitioned 106smtIQThreshold=100 107smtLSQPolicy=Partitioned 108smtLSQThreshold=100 109smtNumFetchingThreads=1 110smtROBPolicy=Partitioned 111smtROBThreshold=100 112squashWidth=8 113store_set_clear_period=250000 114switched_out=false 115system=system 116tracer=system.cpu.tracer 117trapLatency=13 118wbDepth=1 119wbWidth=8 120workload=system.cpu.workload 121dcache_port=system.cpu.dcache.cpu_side 122icache_port=system.cpu.icache.cpu_side 123 124[system.cpu.branchPred] 125type=BranchPredictor 126BTBEntries=4096 127BTBTagSize=16 128RASSize=16 129choiceCtrBits=2 130choicePredictorSize=8192 131globalCtrBits=2 132globalPredictorSize=8192 133instShiftAmt=2 134localCtrBits=2 135localHistoryTableSize=2048 136localPredictorSize=2048 137numThreads=1 138predType=tournament 139 140[system.cpu.dcache] 141type=BaseCache 142children=tags 143addr_ranges=0:18446744073709551615 144assoc=2 145clk_domain=system.cpu_clk_domain 146forward_snoops=true 147hit_latency=2 148is_top_level=true 149max_miss_count=0 150mshrs=4 151prefetch_on_access=false 152prefetcher=Null 153response_latency=2 154size=262144 155system=system 156tags=system.cpu.dcache.tags 157tgts_per_mshr=20 158two_queue=false 159write_buffers=8 160cpu_side=system.cpu.dcache_port 161mem_side=system.cpu.toL2Bus.slave[1] 162 163[system.cpu.dcache.tags] 164type=LRU 165assoc=2 166block_size=64 167clk_domain=system.cpu_clk_domain 168hit_latency=2 169size=262144 170 171[system.cpu.dtb] 172type=ArmTLB 173children=walker 174size=64 175walker=system.cpu.dtb.walker 176 177[system.cpu.dtb.walker] 178type=ArmTableWalker 179clk_domain=system.cpu_clk_domain 180num_squash_per_cycle=2 181sys=system 182port=system.cpu.toL2Bus.slave[3] 183 184[system.cpu.fuPool] 185type=FUPool 186children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 187FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 188 189[system.cpu.fuPool.FUList0] 190type=FUDesc 191children=opList 192count=6 193opList=system.cpu.fuPool.FUList0.opList 194 195[system.cpu.fuPool.FUList0.opList] 196type=OpDesc 197issueLat=1 198opClass=IntAlu 199opLat=1 200 201[system.cpu.fuPool.FUList1] 202type=FUDesc 203children=opList0 opList1 204count=2 205opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 206 207[system.cpu.fuPool.FUList1.opList0] 208type=OpDesc 209issueLat=1 210opClass=IntMult 211opLat=3 212 213[system.cpu.fuPool.FUList1.opList1] 214type=OpDesc 215issueLat=19 216opClass=IntDiv 217opLat=20 218 219[system.cpu.fuPool.FUList2] 220type=FUDesc 221children=opList0 opList1 opList2 222count=4 223opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 224 225[system.cpu.fuPool.FUList2.opList0] 226type=OpDesc 227issueLat=1 228opClass=FloatAdd 229opLat=2 230 231[system.cpu.fuPool.FUList2.opList1] 232type=OpDesc 233issueLat=1 234opClass=FloatCmp 235opLat=2 236 237[system.cpu.fuPool.FUList2.opList2] 238type=OpDesc 239issueLat=1 240opClass=FloatCvt 241opLat=2 242 243[system.cpu.fuPool.FUList3] 244type=FUDesc 245children=opList0 opList1 opList2 246count=2 247opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 248 249[system.cpu.fuPool.FUList3.opList0] 250type=OpDesc 251issueLat=1 252opClass=FloatMult 253opLat=4 254 255[system.cpu.fuPool.FUList3.opList1] 256type=OpDesc 257issueLat=12 258opClass=FloatDiv 259opLat=12 260 261[system.cpu.fuPool.FUList3.opList2] 262type=OpDesc 263issueLat=24 264opClass=FloatSqrt 265opLat=24 266 267[system.cpu.fuPool.FUList4] 268type=FUDesc 269children=opList 270count=0 271opList=system.cpu.fuPool.FUList4.opList 272 273[system.cpu.fuPool.FUList4.opList] 274type=OpDesc 275issueLat=1 276opClass=MemRead 277opLat=1 278 279[system.cpu.fuPool.FUList5] 280type=FUDesc 281children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 282count=4 283opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 284 285[system.cpu.fuPool.FUList5.opList00] 286type=OpDesc 287issueLat=1 288opClass=SimdAdd 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList01] 292type=OpDesc 293issueLat=1 294opClass=SimdAddAcc 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList02] 298type=OpDesc 299issueLat=1 300opClass=SimdAlu 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList03] 304type=OpDesc 305issueLat=1 306opClass=SimdCmp 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList04] 310type=OpDesc 311issueLat=1 312opClass=SimdCvt 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList05] 316type=OpDesc 317issueLat=1 318opClass=SimdMisc 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList06] 322type=OpDesc 323issueLat=1 324opClass=SimdMult 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList07] 328type=OpDesc 329issueLat=1 330opClass=SimdMultAcc 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList08] 334type=OpDesc 335issueLat=1 336opClass=SimdShift 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList09] 340type=OpDesc 341issueLat=1 342opClass=SimdShiftAcc 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList10] 346type=OpDesc 347issueLat=1 348opClass=SimdSqrt 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList11] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatAdd 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList12] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatAlu 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList13] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatCmp 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList14] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatCvt 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList15] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatDiv 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList16] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatMisc 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList17] 388type=OpDesc 389issueLat=1 390opClass=SimdFloatMult 391opLat=1 392 393[system.cpu.fuPool.FUList5.opList18] 394type=OpDesc 395issueLat=1 396opClass=SimdFloatMultAcc 397opLat=1 398 399[system.cpu.fuPool.FUList5.opList19] 400type=OpDesc 401issueLat=1 402opClass=SimdFloatSqrt 403opLat=1 404 405[system.cpu.fuPool.FUList6] 406type=FUDesc 407children=opList 408count=0 409opList=system.cpu.fuPool.FUList6.opList 410 411[system.cpu.fuPool.FUList6.opList] 412type=OpDesc 413issueLat=1 414opClass=MemWrite 415opLat=1 416 417[system.cpu.fuPool.FUList7] 418type=FUDesc 419children=opList0 opList1 420count=4 421opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 422 423[system.cpu.fuPool.FUList7.opList0] 424type=OpDesc 425issueLat=1 426opClass=MemRead 427opLat=1 428 429[system.cpu.fuPool.FUList7.opList1] 430type=OpDesc 431issueLat=1 432opClass=MemWrite 433opLat=1 434 435[system.cpu.fuPool.FUList8] 436type=FUDesc 437children=opList 438count=1 439opList=system.cpu.fuPool.FUList8.opList 440 441[system.cpu.fuPool.FUList8.opList] 442type=OpDesc 443issueLat=3 444opClass=IprAccess 445opLat=3 446 447[system.cpu.icache] 448type=BaseCache 449children=tags 450addr_ranges=0:18446744073709551615 451assoc=2 452clk_domain=system.cpu_clk_domain 453forward_snoops=true 454hit_latency=2 455is_top_level=true 456max_miss_count=0 457mshrs=4 458prefetch_on_access=false 459prefetcher=Null 460response_latency=2 461size=131072 462system=system 463tags=system.cpu.icache.tags 464tgts_per_mshr=20 465two_queue=false 466write_buffers=8 467cpu_side=system.cpu.icache_port 468mem_side=system.cpu.toL2Bus.slave[0] 469 470[system.cpu.icache.tags] 471type=LRU 472assoc=2 473block_size=64 474clk_domain=system.cpu_clk_domain 475hit_latency=2 476size=131072 477 478[system.cpu.interrupts] 479type=ArmInterrupts 480 481[system.cpu.isa] 482type=ArmISA 483fpsid=1090793632 484id_isar0=34607377 485id_isar1=34677009 486id_isar2=555950401 487id_isar3=17899825 488id_isar4=268501314 489id_isar5=0 490id_mmfr0=3 491id_mmfr1=0 492id_mmfr2=19070976 493id_mmfr3=4027589137 494id_pfr0=49 495id_pfr1=1 496midr=890224640 497 498[system.cpu.itb] 499type=ArmTLB 500children=walker 501size=64 502walker=system.cpu.itb.walker 503 504[system.cpu.itb.walker] 505type=ArmTableWalker 506clk_domain=system.cpu_clk_domain 507num_squash_per_cycle=2 508sys=system 509port=system.cpu.toL2Bus.slave[2] 510 511[system.cpu.l2cache] 512type=BaseCache 513children=tags 514addr_ranges=0:18446744073709551615 515assoc=8 516clk_domain=system.cpu_clk_domain 517forward_snoops=true 518hit_latency=20 519is_top_level=false 520max_miss_count=0 521mshrs=20 522prefetch_on_access=false 523prefetcher=Null 524response_latency=20 525size=2097152 526system=system 527tags=system.cpu.l2cache.tags 528tgts_per_mshr=12 529two_queue=false 530write_buffers=8 531cpu_side=system.cpu.toL2Bus.master[0] 532mem_side=system.membus.slave[1] 533 534[system.cpu.l2cache.tags] 535type=LRU 536assoc=8 537block_size=64 538clk_domain=system.cpu_clk_domain 539hit_latency=20 540size=2097152 541 542[system.cpu.toL2Bus] 543type=CoherentBus 544clk_domain=system.cpu_clk_domain 545header_cycles=1 546system=system 547use_default_range=false 548width=32 549master=system.cpu.l2cache.cpu_side 550slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 551 552[system.cpu.tracer] 553type=ExeTracer 554 555[system.cpu.workload] 556type=LiveProcess 557cmd=mcf mcf.in 558cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing 559egid=100 560env= 561errout=cerr 562euid=100 563executable=/dist/m5/cpu2000/binaries/arm/linux/mcf 564gid=100 565input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in 566max_stack_size=67108864 567output=cout 568pid=100 569ppid=99 570simpoint=55300000000 571system=system 572uid=100 573 574[system.cpu_clk_domain] 575type=SrcClockDomain 576clock=500 577voltage_domain=system.voltage_domain 578 579[system.membus] 580type=CoherentBus 581clk_domain=system.clk_domain 582header_cycles=1 583system=system 584use_default_range=false 585width=8 586master=system.physmem.port 587slave=system.system_port system.cpu.l2cache.mem_side 588 589[system.physmem] 590type=SimpleDRAM 591activation_limit=4 592addr_mapping=RaBaChCo 593banks_per_rank=8 594burst_length=8 595channels=1 596clk_domain=system.clk_domain 597conf_table_reported=true 598device_bus_width=8 599device_rowbuffer_size=1024 600devices_per_rank=8 601in_addr_map=true 602mem_sched_policy=frfcfs 603null=false 604page_policy=open 605range=0:268435455 606ranks_per_channel=2 607read_buffer_size=32 608static_backend_latency=10000 609static_frontend_latency=10000 610tBURST=5000 611tCL=13750 612tRCD=13750 613tREFI=7800000 614tRFC=300000 615tRP=13750 616tWTR=7500 617tXAW=40000 618write_buffer_size=32 619write_thresh_perc=70 620port=system.membus.master[0] 621 622[system.voltage_domain] 623type=VoltageDomain 624voltage=1.000000 625