Cross Reference: /gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini

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config.ini (11103:38f6188421e0)	config.ini (11384:e3cbd2823210)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0
	18exit_on_work_items=false
18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false	19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false
	28multi_thread=false
27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=16 52LSQCheckLoads=true 53LSQDepCheckShift=0 54SQEntries=16 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=2 70decodeWidth=3 71dispatchWidth=6 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dstage2_mmu=system.cpu.dstage2_mmu 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=16 79fetchQueueSize=32 80fetchToDecodeDelay=3 81fetchTrapLatency=1 82fetchWidth=3 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95istage2_mmu=system.cpu.istage2_mmu 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=32 103numPhysCCRegs=640 104numPhysFloatRegs=192 105numPhysIntRegs=128 106numROBEntries=40 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=1 114renameToROBDelay=1 115renameWidth=3 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.branchPred] 139type=BiModeBP 140BTBEntries=2048 141BTBTagSize=18 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149numThreads=1 150 151[system.cpu.dcache] 152type=Cache 153children=tags 154addr_ranges=0:18446744073709551615 155assoc=2 156clk_domain=system.cpu_clk_domain	29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=DerivO3CPU 51children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 52LFSTSize=1024 53LQEntries=16 54LSQCheckLoads=true 55LSQDepCheckShift=0 56SQEntries=16 57SSITSize=1024 58activity=0 59backComSize=5 60branchPred=system.cpu.branchPred 61cachePorts=200 62checker=Null 63clk_domain=system.cpu_clk_domain 64commitToDecodeDelay=1 65commitToFetchDelay=1 66commitToIEWDelay=1 67commitToRenameDelay=1 68commitWidth=8 69cpu_id=0 70decodeToFetchDelay=1 71decodeToRenameDelay=2 72decodeWidth=3 73dispatchWidth=6 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dstage2_mmu=system.cpu.dstage2_mmu 78dtb=system.cpu.dtb 79eventq_index=0 80fetchBufferSize=16 81fetchQueueSize=32 82fetchToDecodeDelay=3 83fetchTrapLatency=1 84fetchWidth=3 85forwardComSize=5 86fuPool=system.cpu.fuPool 87function_trace=false 88function_trace_start=0 89iewToCommitDelay=1 90iewToDecodeDelay=1 91iewToFetchDelay=1 92iewToRenameDelay=1 93interrupts=system.cpu.interrupts 94isa=system.cpu.isa 95issueToExecuteDelay=1 96issueWidth=8 97istage2_mmu=system.cpu.istage2_mmu 98itb=system.cpu.itb 99max_insts_all_threads=0 100max_insts_any_thread=0 101max_loads_all_threads=0 102max_loads_any_thread=0 103needsTSO=false 104numIQEntries=32 105numPhysCCRegs=640 106numPhysFloatRegs=192 107numPhysIntRegs=128 108numROBEntries=40 109numRobs=1 110numThreads=1 111profile=0 112progress_interval=0 113renameToDecodeDelay=1 114renameToFetchDelay=1 115renameToIEWDelay=1 116renameToROBDelay=1 117renameWidth=3 118simpoint_start_insts= 119smtCommitPolicy=RoundRobin 120smtFetchPolicy=SingleThread 121smtIQPolicy=Partitioned 122smtIQThreshold=100 123smtLSQPolicy=Partitioned 124smtLSQThreshold=100 125smtNumFetchingThreads=1 126smtROBPolicy=Partitioned 127smtROBThreshold=100 128socket_id=0 129squashWidth=8 130store_set_clear_period=250000 131switched_out=false 132system=system 133tracer=system.cpu.tracer 134trapLatency=13 135wbWidth=8 136workload=system.cpu.workload 137dcache_port=system.cpu.dcache.cpu_side 138icache_port=system.cpu.icache.cpu_side 139 140[system.cpu.branchPred] 141type=BiModeBP 142BTBEntries=2048 143BTBTagSize=18 144RASSize=16 145choiceCtrBits=2 146choicePredictorSize=8192 147eventq_index=0 148globalCtrBits=2 149globalPredictorSize=8192 150instShiftAmt=2 151numThreads=1 152 153[system.cpu.dcache] 154type=Cache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain
	159clusivity=mostly_incl
157demand_mshr_reserve=1 158eventq_index=0	160demand_mshr_reserve=1 161eventq_index=0
159forward_snoops=true
160hit_latency=2 161is_read_only=false 162max_miss_count=0 163mshrs=6 164prefetch_on_access=false 165prefetcher=Null 166response_latency=2 167sequential_access=false 168size=32768 169system=system 170tags=system.cpu.dcache.tags 171tgts_per_mshr=8 172write_buffers=16	162hit_latency=2 163is_read_only=false 164max_miss_count=0 165mshrs=6 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 169sequential_access=false 170size=32768 171system=system 172tags=system.cpu.dcache.tags 173tgts_per_mshr=8 174write_buffers=16
	175writeback_clean=true
173cpu_side=system.cpu.dcache_port 174mem_side=system.cpu.toL2Bus.slave[1] 175 176[system.cpu.dcache.tags] 177type=LRU 178assoc=2 179block_size=64 180clk_domain=system.cpu_clk_domain 181eventq_index=0 182hit_latency=2 183sequential_access=false 184size=32768 185 186[system.cpu.dstage2_mmu] 187type=ArmStage2MMU 188children=stage2_tlb 189eventq_index=0 190stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 191sys=system 192tlb=system.cpu.dtb 193 194[system.cpu.dstage2_mmu.stage2_tlb] 195type=ArmTLB 196children=walker 197eventq_index=0 198is_stage2=true 199size=32 200walker=system.cpu.dstage2_mmu.stage2_tlb.walker 201 202[system.cpu.dstage2_mmu.stage2_tlb.walker] 203type=ArmTableWalker 204clk_domain=system.cpu_clk_domain 205eventq_index=0 206is_stage2=true 207num_squash_per_cycle=2 208sys=system 209 210[system.cpu.dtb] 211type=ArmTLB 212children=walker 213eventq_index=0 214is_stage2=false 215size=64 216walker=system.cpu.dtb.walker 217 218[system.cpu.dtb.walker] 219type=ArmTableWalker 220clk_domain=system.cpu_clk_domain 221eventq_index=0 222is_stage2=false 223num_squash_per_cycle=2 224sys=system 225port=system.cpu.toL2Bus.slave[3] 226 227[system.cpu.fuPool] 228type=FUPool 229children=FUList0 FUList1 FUList2 FUList3 FUList4 230FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 231eventq_index=0 232 233[system.cpu.fuPool.FUList0] 234type=FUDesc 235children=opList 236count=2 237eventq_index=0 238opList=system.cpu.fuPool.FUList0.opList 239 240[system.cpu.fuPool.FUList0.opList] 241type=OpDesc 242eventq_index=0 243opClass=IntAlu 244opLat=1 245pipelined=true 246 247[system.cpu.fuPool.FUList1] 248type=FUDesc 249children=opList0 opList1 opList2 250count=1 251eventq_index=0 252opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 253 254[system.cpu.fuPool.FUList1.opList0] 255type=OpDesc 256eventq_index=0 257opClass=IntMult 258opLat=3 259pipelined=true 260 261[system.cpu.fuPool.FUList1.opList1] 262type=OpDesc 263eventq_index=0 264opClass=IntDiv 265opLat=12 266pipelined=false 267 268[system.cpu.fuPool.FUList1.opList2] 269type=OpDesc 270eventq_index=0 271opClass=IprAccess 272opLat=3 273pipelined=true 274 275[system.cpu.fuPool.FUList2] 276type=FUDesc 277children=opList 278count=1 279eventq_index=0 280opList=system.cpu.fuPool.FUList2.opList 281 282[system.cpu.fuPool.FUList2.opList] 283type=OpDesc 284eventq_index=0 285opClass=MemRead 286opLat=2 287pipelined=true 288 289[system.cpu.fuPool.FUList3] 290type=FUDesc 291children=opList 292count=1 293eventq_index=0 294opList=system.cpu.fuPool.FUList3.opList 295 296[system.cpu.fuPool.FUList3.opList] 297type=OpDesc 298eventq_index=0 299opClass=MemWrite 300opLat=2 301pipelined=true 302 303[system.cpu.fuPool.FUList4] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 306count=2 307eventq_index=0 308opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 309 310[system.cpu.fuPool.FUList4.opList00] 311type=OpDesc 312eventq_index=0 313opClass=SimdAdd 314opLat=4 315pipelined=true 316 317[system.cpu.fuPool.FUList4.opList01] 318type=OpDesc 319eventq_index=0 320opClass=SimdAddAcc 321opLat=4 322pipelined=true 323 324[system.cpu.fuPool.FUList4.opList02] 325type=OpDesc 326eventq_index=0 327opClass=SimdAlu 328opLat=4 329pipelined=true 330 331[system.cpu.fuPool.FUList4.opList03] 332type=OpDesc 333eventq_index=0 334opClass=SimdCmp 335opLat=4 336pipelined=true 337 338[system.cpu.fuPool.FUList4.opList04] 339type=OpDesc 340eventq_index=0 341opClass=SimdCvt 342opLat=3 343pipelined=true 344 345[system.cpu.fuPool.FUList4.opList05] 346type=OpDesc 347eventq_index=0 348opClass=SimdMisc 349opLat=3 350pipelined=true 351 352[system.cpu.fuPool.FUList4.opList06] 353type=OpDesc 354eventq_index=0 355opClass=SimdMult 356opLat=5 357pipelined=true 358 359[system.cpu.fuPool.FUList4.opList07] 360type=OpDesc 361eventq_index=0 362opClass=SimdMultAcc 363opLat=5 364pipelined=true 365 366[system.cpu.fuPool.FUList4.opList08] 367type=OpDesc 368eventq_index=0 369opClass=SimdShift 370opLat=3 371pipelined=true 372 373[system.cpu.fuPool.FUList4.opList09] 374type=OpDesc 375eventq_index=0 376opClass=SimdShiftAcc 377opLat=3 378pipelined=true 379 380[system.cpu.fuPool.FUList4.opList10] 381type=OpDesc 382eventq_index=0 383opClass=SimdSqrt 384opLat=9 385pipelined=true 386 387[system.cpu.fuPool.FUList4.opList11] 388type=OpDesc 389eventq_index=0 390opClass=SimdFloatAdd 391opLat=5 392pipelined=true 393 394[system.cpu.fuPool.FUList4.opList12] 395type=OpDesc 396eventq_index=0 397opClass=SimdFloatAlu 398opLat=5 399pipelined=true 400 401[system.cpu.fuPool.FUList4.opList13] 402type=OpDesc 403eventq_index=0 404opClass=SimdFloatCmp 405opLat=3 406pipelined=true 407 408[system.cpu.fuPool.FUList4.opList14] 409type=OpDesc 410eventq_index=0 411opClass=SimdFloatCvt 412opLat=3 413pipelined=true 414 415[system.cpu.fuPool.FUList4.opList15] 416type=OpDesc 417eventq_index=0 418opClass=SimdFloatDiv 419opLat=3 420pipelined=true 421 422[system.cpu.fuPool.FUList4.opList16] 423type=OpDesc 424eventq_index=0 425opClass=SimdFloatMisc 426opLat=3 427pipelined=true 428 429[system.cpu.fuPool.FUList4.opList17] 430type=OpDesc 431eventq_index=0 432opClass=SimdFloatMult 433opLat=3 434pipelined=true 435 436[system.cpu.fuPool.FUList4.opList18] 437type=OpDesc 438eventq_index=0 439opClass=SimdFloatMultAcc 440opLat=1 441pipelined=true 442 443[system.cpu.fuPool.FUList4.opList19] 444type=OpDesc 445eventq_index=0 446opClass=SimdFloatSqrt 447opLat=9 448pipelined=true 449 450[system.cpu.fuPool.FUList4.opList20] 451type=OpDesc 452eventq_index=0 453opClass=FloatAdd 454opLat=5 455pipelined=true 456 457[system.cpu.fuPool.FUList4.opList21] 458type=OpDesc 459eventq_index=0 460opClass=FloatCmp 461opLat=5 462pipelined=true 463 464[system.cpu.fuPool.FUList4.opList22] 465type=OpDesc 466eventq_index=0 467opClass=FloatCvt 468opLat=5 469pipelined=true 470 471[system.cpu.fuPool.FUList4.opList23] 472type=OpDesc 473eventq_index=0 474opClass=FloatDiv 475opLat=9 476pipelined=false 477 478[system.cpu.fuPool.FUList4.opList24] 479type=OpDesc 480eventq_index=0 481opClass=FloatSqrt 482opLat=33 483pipelined=false 484 485[system.cpu.fuPool.FUList4.opList25] 486type=OpDesc 487eventq_index=0 488opClass=FloatMult 489opLat=4 490pipelined=true 491 492[system.cpu.icache] 493type=Cache 494children=tags 495addr_ranges=0:18446744073709551615 496assoc=2 497clk_domain=system.cpu_clk_domain	176cpu_side=system.cpu.dcache_port 177mem_side=system.cpu.toL2Bus.slave[1] 178 179[system.cpu.dcache.tags] 180type=LRU 181assoc=2 182block_size=64 183clk_domain=system.cpu_clk_domain 184eventq_index=0 185hit_latency=2 186sequential_access=false 187size=32768 188 189[system.cpu.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 194sys=system 195tlb=system.cpu.dtb 196 197[system.cpu.dstage2_mmu.stage2_tlb] 198type=ArmTLB 199children=walker 200eventq_index=0 201is_stage2=true 202size=32 203walker=system.cpu.dstage2_mmu.stage2_tlb.walker 204 205[system.cpu.dstage2_mmu.stage2_tlb.walker] 206type=ArmTableWalker 207clk_domain=system.cpu_clk_domain 208eventq_index=0 209is_stage2=true 210num_squash_per_cycle=2 211sys=system 212 213[system.cpu.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.dtb.walker 220 221[system.cpu.dtb.walker] 222type=ArmTableWalker 223clk_domain=system.cpu_clk_domain 224eventq_index=0 225is_stage2=false 226num_squash_per_cycle=2 227sys=system 228port=system.cpu.toL2Bus.slave[3] 229 230[system.cpu.fuPool] 231type=FUPool 232children=FUList0 FUList1 FUList2 FUList3 FUList4 233FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 234eventq_index=0 235 236[system.cpu.fuPool.FUList0] 237type=FUDesc 238children=opList 239count=2 240eventq_index=0 241opList=system.cpu.fuPool.FUList0.opList 242 243[system.cpu.fuPool.FUList0.opList] 244type=OpDesc 245eventq_index=0 246opClass=IntAlu 247opLat=1 248pipelined=true 249 250[system.cpu.fuPool.FUList1] 251type=FUDesc 252children=opList0 opList1 opList2 253count=1 254eventq_index=0 255opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 256 257[system.cpu.fuPool.FUList1.opList0] 258type=OpDesc 259eventq_index=0 260opClass=IntMult 261opLat=3 262pipelined=true 263 264[system.cpu.fuPool.FUList1.opList1] 265type=OpDesc 266eventq_index=0 267opClass=IntDiv 268opLat=12 269pipelined=false 270 271[system.cpu.fuPool.FUList1.opList2] 272type=OpDesc 273eventq_index=0 274opClass=IprAccess 275opLat=3 276pipelined=true 277 278[system.cpu.fuPool.FUList2] 279type=FUDesc 280children=opList 281count=1 282eventq_index=0 283opList=system.cpu.fuPool.FUList2.opList 284 285[system.cpu.fuPool.FUList2.opList] 286type=OpDesc 287eventq_index=0 288opClass=MemRead 289opLat=2 290pipelined=true 291 292[system.cpu.fuPool.FUList3] 293type=FUDesc 294children=opList 295count=1 296eventq_index=0 297opList=system.cpu.fuPool.FUList3.opList 298 299[system.cpu.fuPool.FUList3.opList] 300type=OpDesc 301eventq_index=0 302opClass=MemWrite 303opLat=2 304pipelined=true 305 306[system.cpu.fuPool.FUList4] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 309count=2 310eventq_index=0 311opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 312 313[system.cpu.fuPool.FUList4.opList00] 314type=OpDesc 315eventq_index=0 316opClass=SimdAdd 317opLat=4 318pipelined=true 319 320[system.cpu.fuPool.FUList4.opList01] 321type=OpDesc 322eventq_index=0 323opClass=SimdAddAcc 324opLat=4 325pipelined=true 326 327[system.cpu.fuPool.FUList4.opList02] 328type=OpDesc 329eventq_index=0 330opClass=SimdAlu 331opLat=4 332pipelined=true 333 334[system.cpu.fuPool.FUList4.opList03] 335type=OpDesc 336eventq_index=0 337opClass=SimdCmp 338opLat=4 339pipelined=true 340 341[system.cpu.fuPool.FUList4.opList04] 342type=OpDesc 343eventq_index=0 344opClass=SimdCvt 345opLat=3 346pipelined=true 347 348[system.cpu.fuPool.FUList4.opList05] 349type=OpDesc 350eventq_index=0 351opClass=SimdMisc 352opLat=3 353pipelined=true 354 355[system.cpu.fuPool.FUList4.opList06] 356type=OpDesc 357eventq_index=0 358opClass=SimdMult 359opLat=5 360pipelined=true 361 362[system.cpu.fuPool.FUList4.opList07] 363type=OpDesc 364eventq_index=0 365opClass=SimdMultAcc 366opLat=5 367pipelined=true 368 369[system.cpu.fuPool.FUList4.opList08] 370type=OpDesc 371eventq_index=0 372opClass=SimdShift 373opLat=3 374pipelined=true 375 376[system.cpu.fuPool.FUList4.opList09] 377type=OpDesc 378eventq_index=0 379opClass=SimdShiftAcc 380opLat=3 381pipelined=true 382 383[system.cpu.fuPool.FUList4.opList10] 384type=OpDesc 385eventq_index=0 386opClass=SimdSqrt 387opLat=9 388pipelined=true 389 390[system.cpu.fuPool.FUList4.opList11] 391type=OpDesc 392eventq_index=0 393opClass=SimdFloatAdd 394opLat=5 395pipelined=true 396 397[system.cpu.fuPool.FUList4.opList12] 398type=OpDesc 399eventq_index=0 400opClass=SimdFloatAlu 401opLat=5 402pipelined=true 403 404[system.cpu.fuPool.FUList4.opList13] 405type=OpDesc 406eventq_index=0 407opClass=SimdFloatCmp 408opLat=3 409pipelined=true 410 411[system.cpu.fuPool.FUList4.opList14] 412type=OpDesc 413eventq_index=0 414opClass=SimdFloatCvt 415opLat=3 416pipelined=true 417 418[system.cpu.fuPool.FUList4.opList15] 419type=OpDesc 420eventq_index=0 421opClass=SimdFloatDiv 422opLat=3 423pipelined=true 424 425[system.cpu.fuPool.FUList4.opList16] 426type=OpDesc 427eventq_index=0 428opClass=SimdFloatMisc 429opLat=3 430pipelined=true 431 432[system.cpu.fuPool.FUList4.opList17] 433type=OpDesc 434eventq_index=0 435opClass=SimdFloatMult 436opLat=3 437pipelined=true 438 439[system.cpu.fuPool.FUList4.opList18] 440type=OpDesc 441eventq_index=0 442opClass=SimdFloatMultAcc 443opLat=1 444pipelined=true 445 446[system.cpu.fuPool.FUList4.opList19] 447type=OpDesc 448eventq_index=0 449opClass=SimdFloatSqrt 450opLat=9 451pipelined=true 452 453[system.cpu.fuPool.FUList4.opList20] 454type=OpDesc 455eventq_index=0 456opClass=FloatAdd 457opLat=5 458pipelined=true 459 460[system.cpu.fuPool.FUList4.opList21] 461type=OpDesc 462eventq_index=0 463opClass=FloatCmp 464opLat=5 465pipelined=true 466 467[system.cpu.fuPool.FUList4.opList22] 468type=OpDesc 469eventq_index=0 470opClass=FloatCvt 471opLat=5 472pipelined=true 473 474[system.cpu.fuPool.FUList4.opList23] 475type=OpDesc 476eventq_index=0 477opClass=FloatDiv 478opLat=9 479pipelined=false 480 481[system.cpu.fuPool.FUList4.opList24] 482type=OpDesc 483eventq_index=0 484opClass=FloatSqrt 485opLat=33 486pipelined=false 487 488[system.cpu.fuPool.FUList4.opList25] 489type=OpDesc 490eventq_index=0 491opClass=FloatMult 492opLat=4 493pipelined=true 494 495[system.cpu.icache] 496type=Cache 497children=tags 498addr_ranges=0:18446744073709551615 499assoc=2 500clk_domain=system.cpu_clk_domain
	501clusivity=mostly_incl
498demand_mshr_reserve=1 499eventq_index=0	502demand_mshr_reserve=1 503eventq_index=0
500forward_snoops=false
501hit_latency=1 502is_read_only=true 503max_miss_count=0 504mshrs=2 505prefetch_on_access=false 506prefetcher=Null 507response_latency=1 508sequential_access=false 509size=32768 510system=system 511tags=system.cpu.icache.tags 512tgts_per_mshr=8 513write_buffers=8	504hit_latency=1 505is_read_only=true 506max_miss_count=0 507mshrs=2 508prefetch_on_access=false 509prefetcher=Null 510response_latency=1 511sequential_access=false 512size=32768 513system=system 514tags=system.cpu.icache.tags 515tgts_per_mshr=8 516write_buffers=8
	517writeback_clean=true
514cpu_side=system.cpu.icache_port 515mem_side=system.cpu.toL2Bus.slave[0] 516 517[system.cpu.icache.tags] 518type=LRU 519assoc=2 520block_size=64 521clk_domain=system.cpu_clk_domain 522eventq_index=0 523hit_latency=1 524sequential_access=false 525size=32768 526 527[system.cpu.interrupts] 528type=ArmInterrupts 529eventq_index=0 530 531[system.cpu.isa] 532type=ArmISA	518cpu_side=system.cpu.icache_port 519mem_side=system.cpu.toL2Bus.slave[0] 520 521[system.cpu.icache.tags] 522type=LRU 523assoc=2 524block_size=64 525clk_domain=system.cpu_clk_domain 526eventq_index=0 527hit_latency=1 528sequential_access=false 529size=32768 530 531[system.cpu.interrupts] 532type=ArmInterrupts 533eventq_index=0 534 535[system.cpu.isa] 536type=ArmISA
	537decoderFlavour=Generic
533eventq_index=0 534fpsid=1090793632 535id_aa64afr0_el1=0 536id_aa64afr1_el1=0 537id_aa64dfr0_el1=1052678 538id_aa64dfr1_el1=0 539id_aa64isar0_el1=0 540id_aa64isar1_el1=0 541id_aa64mmfr0_el1=15728642 542id_aa64mmfr1_el1=0 543id_aa64pfr0_el1=17 544id_aa64pfr1_el1=0 545id_isar0=34607377 546id_isar1=34677009 547id_isar2=555950401 548id_isar3=17899825 549id_isar4=268501314 550id_isar5=0 551id_mmfr0=270536963 552id_mmfr1=0 553id_mmfr2=19070976 554id_mmfr3=34611729 555id_pfr0=49 556id_pfr1=4113 557midr=1091551472 558pmu=Null 559system=system 560 561[system.cpu.istage2_mmu] 562type=ArmStage2MMU 563children=stage2_tlb 564eventq_index=0 565stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 566sys=system 567tlb=system.cpu.itb 568 569[system.cpu.istage2_mmu.stage2_tlb] 570type=ArmTLB 571children=walker 572eventq_index=0 573is_stage2=true 574size=32 575walker=system.cpu.istage2_mmu.stage2_tlb.walker 576 577[system.cpu.istage2_mmu.stage2_tlb.walker] 578type=ArmTableWalker 579clk_domain=system.cpu_clk_domain 580eventq_index=0 581is_stage2=true 582num_squash_per_cycle=2 583sys=system 584 585[system.cpu.itb] 586type=ArmTLB 587children=walker 588eventq_index=0 589is_stage2=false 590size=64 591walker=system.cpu.itb.walker 592 593[system.cpu.itb.walker] 594type=ArmTableWalker 595clk_domain=system.cpu_clk_domain 596eventq_index=0 597is_stage2=false 598num_squash_per_cycle=2 599sys=system 600port=system.cpu.toL2Bus.slave[2] 601 602[system.cpu.l2cache] 603type=Cache 604children=prefetcher tags 605addr_ranges=0:18446744073709551615 606assoc=16 607clk_domain=system.cpu_clk_domain	538eventq_index=0 539fpsid=1090793632 540id_aa64afr0_el1=0 541id_aa64afr1_el1=0 542id_aa64dfr0_el1=1052678 543id_aa64dfr1_el1=0 544id_aa64isar0_el1=0 545id_aa64isar1_el1=0 546id_aa64mmfr0_el1=15728642 547id_aa64mmfr1_el1=0 548id_aa64pfr0_el1=17 549id_aa64pfr1_el1=0 550id_isar0=34607377 551id_isar1=34677009 552id_isar2=555950401 553id_isar3=17899825 554id_isar4=268501314 555id_isar5=0 556id_mmfr0=270536963 557id_mmfr1=0 558id_mmfr2=19070976 559id_mmfr3=34611729 560id_pfr0=49 561id_pfr1=4113 562midr=1091551472 563pmu=Null 564system=system 565 566[system.cpu.istage2_mmu] 567type=ArmStage2MMU 568children=stage2_tlb 569eventq_index=0 570stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 571sys=system 572tlb=system.cpu.itb 573 574[system.cpu.istage2_mmu.stage2_tlb] 575type=ArmTLB 576children=walker 577eventq_index=0 578is_stage2=true 579size=32 580walker=system.cpu.istage2_mmu.stage2_tlb.walker 581 582[system.cpu.istage2_mmu.stage2_tlb.walker] 583type=ArmTableWalker 584clk_domain=system.cpu_clk_domain 585eventq_index=0 586is_stage2=true 587num_squash_per_cycle=2 588sys=system 589 590[system.cpu.itb] 591type=ArmTLB 592children=walker 593eventq_index=0 594is_stage2=false 595size=64 596walker=system.cpu.itb.walker 597 598[system.cpu.itb.walker] 599type=ArmTableWalker 600clk_domain=system.cpu_clk_domain 601eventq_index=0 602is_stage2=false 603num_squash_per_cycle=2 604sys=system 605port=system.cpu.toL2Bus.slave[2] 606 607[system.cpu.l2cache] 608type=Cache 609children=prefetcher tags 610addr_ranges=0:18446744073709551615 611assoc=16 612clk_domain=system.cpu_clk_domain
	613clusivity=mostly_excl
608demand_mshr_reserve=1 609eventq_index=0	614demand_mshr_reserve=1 615eventq_index=0
610forward_snoops=true
611hit_latency=12 612is_read_only=false 613max_miss_count=0 614mshrs=16 615prefetch_on_access=true 616prefetcher=system.cpu.l2cache.prefetcher 617response_latency=12 618sequential_access=false 619size=1048576 620system=system 621tags=system.cpu.l2cache.tags 622tgts_per_mshr=8 623write_buffers=8	616hit_latency=12 617is_read_only=false 618max_miss_count=0 619mshrs=16 620prefetch_on_access=true 621prefetcher=system.cpu.l2cache.prefetcher 622response_latency=12 623sequential_access=false 624size=1048576 625system=system 626tags=system.cpu.l2cache.tags 627tgts_per_mshr=8 628write_buffers=8
	629writeback_clean=false
624cpu_side=system.cpu.toL2Bus.master[0] 625mem_side=system.membus.slave[1] 626 627[system.cpu.l2cache.prefetcher] 628type=StridePrefetcher 629cache_snoop=false 630clk_domain=system.cpu_clk_domain 631degree=8 632eventq_index=0 633latency=1 634max_conf=7 635min_conf=0 636on_data=true 637on_inst=true 638on_miss=false 639on_read=true 640on_write=true 641queue_filter=true 642queue_size=32 643queue_squash=true 644start_conf=4 645sys=system 646table_assoc=4 647table_sets=16 648tag_prefetch=true 649thresh_conf=4 650use_master_id=true 651 652[system.cpu.l2cache.tags] 653type=RandomRepl 654assoc=16 655block_size=64 656clk_domain=system.cpu_clk_domain 657eventq_index=0 658hit_latency=12 659sequential_access=false 660size=1048576 661 662[system.cpu.toL2Bus] 663type=CoherentXBar	630cpu_side=system.cpu.toL2Bus.master[0] 631mem_side=system.membus.slave[1] 632 633[system.cpu.l2cache.prefetcher] 634type=StridePrefetcher 635cache_snoop=false 636clk_domain=system.cpu_clk_domain 637degree=8 638eventq_index=0 639latency=1 640max_conf=7 641min_conf=0 642on_data=true 643on_inst=true 644on_miss=false 645on_read=true 646on_write=true 647queue_filter=true 648queue_size=32 649queue_squash=true 650start_conf=4 651sys=system 652table_assoc=4 653table_sets=16 654tag_prefetch=true 655thresh_conf=4 656use_master_id=true 657 658[system.cpu.l2cache.tags] 659type=RandomRepl 660assoc=16 661block_size=64 662clk_domain=system.cpu_clk_domain 663eventq_index=0 664hit_latency=12 665sequential_access=false 666size=1048576 667 668[system.cpu.toL2Bus] 669type=CoherentXBar
	670children=snoop_filter
664clk_domain=system.cpu_clk_domain 665eventq_index=0 666forward_latency=0 667frontend_latency=1	671clk_domain=system.cpu_clk_domain 672eventq_index=0 673forward_latency=0 674frontend_latency=1
	675point_of_coherency=false
668response_latency=1	676response_latency=1
669snoop_filter=Null	677snoop_filter=system.cpu.toL2Bus.snoop_filter
670snoop_response_latency=1 671system=system 672use_default_range=false 673width=32 674master=system.cpu.l2cache.cpu_side 675slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 676	678snoop_response_latency=1 679system=system 680use_default_range=false 681width=32 682master=system.cpu.l2cache.cpu_side 683slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 684
	685[system.cpu.toL2Bus.snoop_filter] 686type=SnoopFilter 687eventq_index=0 688lookup_latency=0 689max_capacity=8388608 690system=system 691
677[system.cpu.tracer] 678type=ExeTracer 679eventq_index=0 680 681[system.cpu.workload] 682type=LiveProcess 683cmd=mcf mcf.in 684cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing 685drivers= 686egid=100 687env= 688errout=cerr 689euid=100 690eventq_index=0	692[system.cpu.tracer] 693type=ExeTracer 694eventq_index=0 695 696[system.cpu.workload] 697type=LiveProcess 698cmd=mcf mcf.in 699cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing 700drivers= 701egid=100 702env= 703errout=cerr 704euid=100 705eventq_index=0
691executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf	706executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
692gid=100	707gid=100
693input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in	708input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
694kvmInSE=false 695max_stack_size=67108864 696output=cout 697pid=100 698ppid=99 699simpoint=55300000000 700system=system 701uid=100 702useArchPT=false 703 704[system.cpu_clk_domain] 705type=SrcClockDomain 706clock=500 707domain_id=-1 708eventq_index=0 709init_perf_level=0 710voltage_domain=system.voltage_domain 711 712[system.dvfs_handler] 713type=DVFSHandler 714domains= 715enable=false 716eventq_index=0 717sys_clk_domain=system.clk_domain 718transition_latency=100000000 719 720[system.membus] 721type=CoherentXBar 722clk_domain=system.clk_domain 723eventq_index=0 724forward_latency=4 725frontend_latency=3	709kvmInSE=false 710max_stack_size=67108864 711output=cout 712pid=100 713ppid=99 714simpoint=55300000000 715system=system 716uid=100 717useArchPT=false 718 719[system.cpu_clk_domain] 720type=SrcClockDomain 721clock=500 722domain_id=-1 723eventq_index=0 724init_perf_level=0 725voltage_domain=system.voltage_domain 726 727[system.dvfs_handler] 728type=DVFSHandler 729domains= 730enable=false 731eventq_index=0 732sys_clk_domain=system.clk_domain 733transition_latency=100000000 734 735[system.membus] 736type=CoherentXBar 737clk_domain=system.clk_domain 738eventq_index=0 739forward_latency=4 740frontend_latency=3
	741point_of_coherency=true
726response_latency=2 727snoop_filter=Null 728snoop_response_latency=4 729system=system 730use_default_range=false 731width=16 732master=system.physmem.port 733slave=system.system_port system.cpu.l2cache.mem_side 734 735[system.physmem] 736type=DRAMCtrl 737IDD0=0.075000 738IDD02=0.000000 739IDD2N=0.050000 740IDD2N2=0.000000 741IDD2P0=0.000000 742IDD2P02=0.000000 743IDD2P1=0.000000 744IDD2P12=0.000000 745IDD3N=0.057000 746IDD3N2=0.000000 747IDD3P0=0.000000 748IDD3P02=0.000000 749IDD3P1=0.000000 750IDD3P12=0.000000 751IDD4R=0.187000 752IDD4R2=0.000000 753IDD4W=0.165000 754IDD4W2=0.000000 755IDD5=0.220000 756IDD52=0.000000 757IDD6=0.000000 758IDD62=0.000000 759VDD=1.500000 760VDD2=0.000000 761activation_limit=4 762addr_mapping=RoRaBaCoCh 763bank_groups_per_rank=0 764banks_per_rank=8 765burst_length=8 766channels=1 767clk_domain=system.clk_domain 768conf_table_reported=true 769device_bus_width=8 770device_rowbuffer_size=1024 771device_size=536870912 772devices_per_rank=8 773dll=true 774eventq_index=0 775in_addr_map=true 776max_accesses_per_row=16 777mem_sched_policy=frfcfs 778min_writes_per_switch=16 779null=false 780page_policy=open_adaptive 781range=0:268435455 782ranks_per_channel=2 783read_buffer_size=32 784static_backend_latency=10000 785static_frontend_latency=10000 786tBURST=5000 787tCCD_L=0 788tCK=1250 789tCL=13750 790tCS=2500 791tRAS=35000 792tRCD=13750 793tREFI=7800000 794tRFC=260000 795tRP=13750 796tRRD=6000 797tRRD_L=0 798tRTP=7500 799tRTW=2500 800tWR=15000 801tWTR=7500 802tXAW=30000 803tXP=0 804tXPDLL=0 805tXS=0 806tXSDLL=0 807write_buffer_size=64 808write_high_thresh_perc=85 809write_low_thresh_perc=50 810port=system.membus.master[0] 811 812[system.voltage_domain] 813type=VoltageDomain 814eventq_index=0 815voltage=1.000000 816	742response_latency=2 743snoop_filter=Null 744snoop_response_latency=4 745system=system 746use_default_range=false 747width=16 748master=system.physmem.port 749slave=system.system_port system.cpu.l2cache.mem_side 750 751[system.physmem] 752type=DRAMCtrl 753IDD0=0.075000 754IDD02=0.000000 755IDD2N=0.050000 756IDD2N2=0.000000 757IDD2P0=0.000000 758IDD2P02=0.000000 759IDD2P1=0.000000 760IDD2P12=0.000000 761IDD3N=0.057000 762IDD3N2=0.000000 763IDD3P0=0.000000 764IDD3P02=0.000000 765IDD3P1=0.000000 766IDD3P12=0.000000 767IDD4R=0.187000 768IDD4R2=0.000000 769IDD4W=0.165000 770IDD4W2=0.000000 771IDD5=0.220000 772IDD52=0.000000 773IDD6=0.000000 774IDD62=0.000000 775VDD=1.500000 776VDD2=0.000000 777activation_limit=4 778addr_mapping=RoRaBaCoCh 779bank_groups_per_rank=0 780banks_per_rank=8 781burst_length=8 782channels=1 783clk_domain=system.clk_domain 784conf_table_reported=true 785device_bus_width=8 786device_rowbuffer_size=1024 787device_size=536870912 788devices_per_rank=8 789dll=true 790eventq_index=0 791in_addr_map=true 792max_accesses_per_row=16 793mem_sched_policy=frfcfs 794min_writes_per_switch=16 795null=false 796page_policy=open_adaptive 797range=0:268435455 798ranks_per_channel=2 799read_buffer_size=32 800static_backend_latency=10000 801static_frontend_latency=10000 802tBURST=5000 803tCCD_L=0 804tCK=1250 805tCL=13750 806tCS=2500 807tRAS=35000 808tRCD=13750 809tREFI=7800000 810tRFC=260000 811tRP=13750 812tRRD=6000 813tRRD_L=0 814tRTP=7500 815tRTW=2500 816tWR=15000 817tWTR=7500 818tXAW=30000 819tXP=0 820tXPDLL=0 821tXS=0 822tXSDLL=0 823write_buffer_size=64 824write_high_thresh_perc=85 825write_low_thresh_perc=50 826port=system.membus.master[0] 827 828[system.voltage_domain] 829type=VoltageDomain 830eventq_index=0 831voltage=1.000000 832