| stats.txt (11687:b3d5f0e9e258) | stats.txt (11754:c209cb86278a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.062553 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.062553 # Number of seconds simulated |
| 4sim_ticks 62552970500 # Number of ticks simulated 5final_tick 62552970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 62553193500 # Number of ticks simulated 5final_tick 62553193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 423901 # Simulator instruction rate (inst/s) 8host_op_rate 426012 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 292664487 # Simulator tick rate (ticks/s) 10host_mem_usage 404124 # Number of bytes of host memory used 11host_seconds 213.74 # Real time elapsed on the host | 7host_inst_rate 434587 # Simulator instruction rate (inst/s) 8host_op_rate 436752 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 300043763 # Simulator tick rate (ticks/s) 10host_mem_usage 405580 # Number of bytes of host memory used 11host_seconds 208.48 # Real time elapsed on the host |
| 12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory 19system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory 19system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 790882 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 15143390 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 15934271 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 790882 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 790882 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 790882 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 15143390 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 15934271 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 790879 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 15143336 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 15934214 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 790879 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 790879 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 790879 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 15143336 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 15934214 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 15574 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 15574 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 62552869500 # Total gap between requests | 79system.physmem.totGap 62553092500 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 15574 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 79 5.13% 33.51% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 15574 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 79 5.13% 33.51% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation |
| 204system.physmem.totQLat 211081250 # Total ticks spent queuing 205system.physmem.totMemAccLat 503093750 # Total ticks spent from burst creation until serviced by the DRAM | 204system.physmem.totQLat 211075250 # Total ticks spent queuing 205system.physmem.totMemAccLat 503087750 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 13553.44 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 13553.05 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 32303.44 # Average memory access latency per DRAM burst | 209system.physmem.avgMemAccLat 32303.05 # Average memory access latency per DRAM burst |
| 210system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.12 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 14027 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 210system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.12 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 14027 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 4016493.48 # Average gap between requests | 224system.physmem.avgGap 4016507.80 # Average gap between requests |
| 225system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ) | 225system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 136599930 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 8776800 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 736788270 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 212075520 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 14428808400 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 15801654720 # Total energy per rank (pJ) 237system.physmem_0.averagePower 252.612376 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 62230500750 # Total Idle time Per DRAM Rank | 231system.physmem_0.actBackEnergy 136590810 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 8775360 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 736795110 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 212078880 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 14428861800 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 15801707760 # Total energy per rank (pJ) 237system.physmem_0.averagePower 252.612326 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 62230723750 # Total Idle time Per DRAM Rank |
| 239system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states 240system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states | 239system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states 240system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states |
| 241system.physmem_0.memoryStateTime::SREF 60062510500 # Time in different power states | 241system.physmem_0.memoryStateTime::SREF 60062733500 # Time in different power states |
| 242system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states 245system.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ) | 242system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states 245system.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 136420380 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 13274400 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 827381220 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 248160000 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 14377425165 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 15919954335 # Total energy per rank (pJ) 256system.physmem_1.averagePower 254.503567 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 62217855000 # Total Idle time Per DRAM Rank | 250system.physmem_1.actBackEnergy 136418100 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 13273920 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 827375520 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 248165280 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 14377479765 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 15920005755 # Total energy per rank (pJ) 256system.physmem_1.averagePower 254.503484 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 62218080000 # Total Idle time Per DRAM Rank |
| 258system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states | 258system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states |
| 260system.physmem_1.memoryStateTime::SREF 59758396500 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 646214750 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 203977250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 1814551000 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 260system.physmem_1.memoryStateTime::SREF 59758619500 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 646225750 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 203975250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 1814542000 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 265system.cpu.branchPred.lookups 20808248 # Number of BP lookups 266system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 8965663 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 8840828 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 98.607632 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks | 265system.cpu.branchPred.lookups 20808248 # Number of BP lookups 266system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 8965663 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 8840828 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 98.607632 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 279system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 279system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 280system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 282system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 283system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 284system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 301system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 304system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 305system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 306system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 307system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 308system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 280system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 282system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 283system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 284system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 301system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 304system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 305system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 306system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 307system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 308system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 309system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 309system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 310system.cpu.dtb.walker.walks 0 # Table walker walks requested 311system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 331system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.dtb.read_accesses 0 # DTB read accesses 334system.cpu.dtb.write_accesses 0 # DTB write accesses 335system.cpu.dtb.inst_accesses 0 # ITB inst accesses 336system.cpu.dtb.hits 0 # DTB hits 337system.cpu.dtb.misses 0 # DTB misses 338system.cpu.dtb.accesses 0 # DTB accesses | 310system.cpu.dtb.walker.walks 0 # Table walker walks requested 311system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 331system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.dtb.read_accesses 0 # DTB read accesses 334system.cpu.dtb.write_accesses 0 # DTB write accesses 335system.cpu.dtb.inst_accesses 0 # ITB inst accesses 336system.cpu.dtb.hits 0 # DTB hits 337system.cpu.dtb.misses 0 # DTB misses 338system.cpu.dtb.accesses 0 # DTB accesses |
| 339system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 339system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 340system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 361system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 340system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 361system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 369system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 369system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 370system.cpu.itb.walker.walks 0 # Table walker walks requested 371system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 392system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.itb.read_accesses 0 # DTB read accesses 394system.cpu.itb.write_accesses 0 # DTB write accesses 395system.cpu.itb.inst_accesses 0 # ITB inst accesses 396system.cpu.itb.hits 0 # DTB hits 397system.cpu.itb.misses 0 # DTB misses 398system.cpu.itb.accesses 0 # DTB accesses 399system.cpu.workload.num_syscalls 442 # Number of system calls | 370system.cpu.itb.walker.walks 0 # Table walker walks requested 371system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 392system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.itb.read_accesses 0 # DTB read accesses 394system.cpu.itb.write_accesses 0 # DTB write accesses 395system.cpu.itb.inst_accesses 0 # ITB inst accesses 396system.cpu.itb.hits 0 # DTB hits 397system.cpu.itb.misses 0 # DTB misses 398system.cpu.itb.accesses 0 # DTB accesses 399system.cpu.workload.num_syscalls 442 # Number of system calls |
| 400system.cpu.pwrStateResidencyTicks::ON 62552970500 # Cumulative time (in ticks) in various power states 401system.cpu.numCycles 125105941 # number of cpu cycles simulated | 400system.cpu.pwrStateResidencyTicks::ON 62553193500 # Cumulative time (in ticks) in various power states 401system.cpu.numCycles 125106387 # number of cpu cycles simulated |
| 402system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 403system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 404system.cpu.committedInsts 90602850 # Number of instructions committed 405system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed 406system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit 407system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 402system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 403system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 404system.cpu.committedInsts 90602850 # Number of instructions committed 405system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed 406system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit 407system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 408system.cpu.cpi 1.380817 # CPI: cycles per instruction 409system.cpu.ipc 0.724209 # IPC: instructions per cycle | 408system.cpu.cpi 1.380822 # CPI: cycles per instruction 409system.cpu.ipc 0.724206 # IPC: instructions per cycle |
| 410system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 411system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction 412system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 413system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 414system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 415system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 416system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 417system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 441system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 442system.cpu.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction 443system.cpu.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction 444system.cpu.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction 445system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction 446system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 447system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 448system.cpu.op_class_0::total 91054081 # Class of committed instruction | 410system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 411system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction 412system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 413system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 414system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 415system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 416system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 417system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 441system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 442system.cpu.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction 443system.cpu.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction 444system.cpu.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction 445system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction 446system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 447system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 448system.cpu.op_class_0::total 91054081 # Class of committed instruction |
| 449system.cpu.tickCycles 110521627 # Number of cycles that the object actually ticked 450system.cpu.idleCycles 14584314 # Total number of cycles that the object has spent stopped 451system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 449system.cpu.tickCycles 110521789 # Number of cycles that the object actually ticked 450system.cpu.idleCycles 14584598 # Total number of cycles that the object has spent stopped 451system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 452system.cpu.dcache.tags.replacements 946101 # number of replacements | 452system.cpu.dcache.tags.replacements 946101 # number of replacements |
| 453system.cpu.dcache.tags.tagsinuse 3621.108293 # Cycle average of tags in use 454system.cpu.dcache.tags.total_refs 26274912 # Total number of references to valid blocks. | 453system.cpu.dcache.tags.tagsinuse 3621.109986 # Cycle average of tags in use 454system.cpu.dcache.tags.total_refs 26274729 # Total number of references to valid blocks. |
| 455system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. | 455system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. |
| 456system.cpu.dcache.tags.avg_refs 27.652068 # Average number of references to valid blocks. | 456system.cpu.dcache.tags.avg_refs 27.651875 # Average number of references to valid blocks. |
| 457system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit. | 457system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit. |
| 458system.cpu.dcache.tags.occ_blocks::cpu.data 3621.108293 # Average occupied blocks per requestor | 458system.cpu.dcache.tags.occ_blocks::cpu.data 3621.109986 # Average occupied blocks per requestor |
| 459system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy 460system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy 461system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 462system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id 463system.cpu.dcache.tags.age_task_id_blocks_1024::1 2202 # Occupied blocks per task id 464system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 # Occupied blocks per task id 465system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 466system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses 467system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses | 459system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy 460system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy 461system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 462system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id 463system.cpu.dcache.tags.age_task_id_blocks_1024::1 2202 # Occupied blocks per task id 464system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 # Occupied blocks per task id 465system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 466system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses 467system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses |
| 468system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states 469system.cpu.dcache.ReadReq_hits::cpu.data 21605963 # number of ReadReq hits 470system.cpu.dcache.ReadReq_hits::total 21605963 # number of ReadReq hits | 468system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states 469system.cpu.dcache.ReadReq_hits::cpu.data 21605780 # number of ReadReq hits 470system.cpu.dcache.ReadReq_hits::total 21605780 # number of ReadReq hits |
| 471system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits 472system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits 473system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 474system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 475system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 476system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 477system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 478system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits | 471system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits 472system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits 473system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 474system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 475system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 476system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 477system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 478system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits |
| 479system.cpu.dcache.demand_hits::cpu.data 26266630 # number of demand (read+write) hits 480system.cpu.dcache.demand_hits::total 26266630 # number of demand (read+write) hits 481system.cpu.dcache.overall_hits::cpu.data 26267138 # number of overall hits 482system.cpu.dcache.overall_hits::total 26267138 # number of overall hits 483system.cpu.dcache.ReadReq_misses::cpu.data 906313 # number of ReadReq misses 484system.cpu.dcache.ReadReq_misses::total 906313 # number of ReadReq misses | 479system.cpu.dcache.demand_hits::cpu.data 26266447 # number of demand (read+write) hits 480system.cpu.dcache.demand_hits::total 26266447 # number of demand (read+write) hits 481system.cpu.dcache.overall_hits::cpu.data 26266955 # number of overall hits 482system.cpu.dcache.overall_hits::total 26266955 # number of overall hits 483system.cpu.dcache.ReadReq_misses::cpu.data 906496 # number of ReadReq misses 484system.cpu.dcache.ReadReq_misses::total 906496 # number of ReadReq misses |
| 485system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses 486system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses 487system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 488system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses | 485system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses 486system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses 487system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 488system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses |
| 489system.cpu.dcache.demand_misses::cpu.data 980627 # number of demand (read+write) misses 490system.cpu.dcache.demand_misses::total 980627 # number of demand (read+write) misses 491system.cpu.dcache.overall_misses::cpu.data 980631 # number of overall misses 492system.cpu.dcache.overall_misses::total 980631 # number of overall misses 493system.cpu.dcache.ReadReq_miss_latency::cpu.data 11831745500 # number of ReadReq miss cycles 494system.cpu.dcache.ReadReq_miss_latency::total 11831745500 # number of ReadReq miss cycles 495system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760211000 # number of WriteReq miss cycles 496system.cpu.dcache.WriteReq_miss_latency::total 2760211000 # number of WriteReq miss cycles 497system.cpu.dcache.demand_miss_latency::cpu.data 14591956500 # number of demand (read+write) miss cycles 498system.cpu.dcache.demand_miss_latency::total 14591956500 # number of demand (read+write) miss cycles 499system.cpu.dcache.overall_miss_latency::cpu.data 14591956500 # number of overall miss cycles 500system.cpu.dcache.overall_miss_latency::total 14591956500 # number of overall miss cycles | 489system.cpu.dcache.demand_misses::cpu.data 980810 # number of demand (read+write) misses 490system.cpu.dcache.demand_misses::total 980810 # number of demand (read+write) misses 491system.cpu.dcache.overall_misses::cpu.data 980814 # number of overall misses 492system.cpu.dcache.overall_misses::total 980814 # number of overall misses 493system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832179000 # number of ReadReq miss cycles 494system.cpu.dcache.ReadReq_miss_latency::total 11832179000 # number of ReadReq miss cycles 495system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760205500 # number of WriteReq miss cycles 496system.cpu.dcache.WriteReq_miss_latency::total 2760205500 # number of WriteReq miss cycles 497system.cpu.dcache.demand_miss_latency::cpu.data 14592384500 # number of demand (read+write) miss cycles 498system.cpu.dcache.demand_miss_latency::total 14592384500 # number of demand (read+write) miss cycles 499system.cpu.dcache.overall_miss_latency::cpu.data 14592384500 # number of overall miss cycles 500system.cpu.dcache.overall_miss_latency::total 14592384500 # number of overall miss cycles |
| 501system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses) 502system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses) 503system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 504system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 505system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 506system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 507system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 508system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 509system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 510system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 511system.cpu.dcache.demand_accesses::cpu.data 27247257 # number of demand (read+write) accesses 512system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses 513system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses 514system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses | 501system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses) 502system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses) 503system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 504system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 505system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 506system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 507system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 508system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 509system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 510system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 511system.cpu.dcache.demand_accesses::cpu.data 27247257 # number of demand (read+write) accesses 512system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses 513system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses 514system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses |
| 515system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses 516system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses | 515system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses 516system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses |
| 517system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses 518system.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses 519system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 520system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses | 517system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses 518system.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses 519system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 520system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses |
| 521system.cpu.dcache.demand_miss_rate::cpu.data 0.035990 # miss rate for demand accesses 522system.cpu.dcache.demand_miss_rate::total 0.035990 # miss rate for demand accesses 523system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses 524system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses 525system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13054.811638 # average ReadReq miss latency 526system.cpu.dcache.ReadReq_avg_miss_latency::total 13054.811638 # average ReadReq miss latency 527system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.543801 # average WriteReq miss latency 528system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.543801 # average WriteReq miss latency 529system.cpu.dcache.demand_avg_miss_latency::cpu.data 14880.231219 # average overall miss latency 530system.cpu.dcache.demand_avg_miss_latency::total 14880.231219 # average overall miss latency 531system.cpu.dcache.overall_avg_miss_latency::cpu.data 14880.170523 # average overall miss latency 532system.cpu.dcache.overall_avg_miss_latency::total 14880.170523 # average overall miss latency | 521system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 # miss rate for demand accesses 522system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses 523system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses 524system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses 525system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397 # average ReadReq miss latency 526system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397 # average ReadReq miss latency 527system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790 # average WriteReq miss latency 528system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790 # average WriteReq miss latency 529system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233 # average overall miss latency 530system.cpu.dcache.demand_avg_miss_latency::total 14877.891233 # average overall miss latency 531system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557 # average overall miss latency 532system.cpu.dcache.overall_avg_miss_latency::total 14877.830557 # average overall miss latency |
| 533system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 534system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 535system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 536system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 537system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 538system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 539system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks 540system.cpu.dcache.writebacks::total 943282 # number of writebacks | 533system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 534system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 535system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 536system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 537system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 538system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 539system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks 540system.cpu.dcache.writebacks::total 943282 # number of writebacks |
| 541system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2883 # number of ReadReq MSHR hits 542system.cpu.dcache.ReadReq_mshr_hits::total 2883 # number of ReadReq MSHR hits | 541system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3066 # number of ReadReq MSHR hits 542system.cpu.dcache.ReadReq_mshr_hits::total 3066 # number of ReadReq MSHR hits |
| 543system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits 544system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits | 543system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits 544system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits |
| 545system.cpu.dcache.demand_mshr_hits::cpu.data 30433 # number of demand (read+write) MSHR hits 546system.cpu.dcache.demand_mshr_hits::total 30433 # number of demand (read+write) MSHR hits 547system.cpu.dcache.overall_mshr_hits::cpu.data 30433 # number of overall MSHR hits 548system.cpu.dcache.overall_mshr_hits::total 30433 # number of overall MSHR hits | 545system.cpu.dcache.demand_mshr_hits::cpu.data 30616 # number of demand (read+write) MSHR hits 546system.cpu.dcache.demand_mshr_hits::total 30616 # number of demand (read+write) MSHR hits 547system.cpu.dcache.overall_mshr_hits::cpu.data 30616 # number of overall MSHR hits 548system.cpu.dcache.overall_mshr_hits::total 30616 # number of overall MSHR hits |
| 549system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses 550system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses 551system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses 552system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses 553system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 554system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 555system.cpu.dcache.demand_mshr_misses::cpu.data 950194 # number of demand (read+write) MSHR misses 556system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses 557system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses 558system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses | 549system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses 550system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses 551system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses 552system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses 553system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 554system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 555system.cpu.dcache.demand_mshr_misses::cpu.data 950194 # number of demand (read+write) MSHR misses 556system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses 557system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses 558system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses |
| 559system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889954000 # number of ReadReq MSHR miss cycles 560system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889954000 # number of ReadReq MSHR miss cycles 561system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596188500 # number of WriteReq MSHR miss cycles 562system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596188500 # number of WriteReq MSHR miss cycles | 559system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889871500 # number of ReadReq MSHR miss cycles 560system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889871500 # number of ReadReq MSHR miss cycles 561system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596189500 # number of WriteReq MSHR miss cycles 562system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596189500 # number of WriteReq MSHR miss cycles |
| 563system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles 564system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles | 563system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles 564system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles |
| 565system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486142500 # number of demand (read+write) MSHR miss cycles 566system.cpu.dcache.demand_mshr_miss_latency::total 12486142500 # number of demand (read+write) MSHR miss cycles 567system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486312500 # number of overall MSHR miss cycles 568system.cpu.dcache.overall_mshr_miss_latency::total 12486312500 # number of overall MSHR miss cycles | 565system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486061000 # number of demand (read+write) MSHR miss cycles 566system.cpu.dcache.demand_mshr_miss_latency::total 12486061000 # number of demand (read+write) MSHR miss cycles 567system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486231000 # number of overall MSHR miss cycles 568system.cpu.dcache.overall_mshr_miss_latency::total 12486231000 # number of overall MSHR miss cycles |
| 569system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses 570system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses 571system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 572system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 573system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 574system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 575system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses 576system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses 577system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses 578system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses | 569system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses 570system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses 571system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 572system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 573system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 574system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 575system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses 576system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses 577system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses 578system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses |
| 579system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12054.009719 # average ReadReq mshr miss latency 580system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12054.009719 # average ReadReq mshr miss latency 581system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.847917 # average WriteReq mshr miss latency 582system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.847917 # average WriteReq mshr miss latency | 579system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400 # average ReadReq mshr miss latency 580system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400 # average ReadReq mshr miss latency 581system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301 # average WriteReq mshr miss latency 582system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301 # average WriteReq mshr miss latency |
| 583system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency 584system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency | 583system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency 584system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency |
| 585system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.624441 # average overall mshr miss latency 586system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.624441 # average overall mshr miss latency 587system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.761863 # average overall mshr miss latency 588system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.761863 # average overall mshr miss latency 589system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 585system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669 # average overall mshr miss latency 586system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669 # average overall mshr miss latency 587system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091 # average overall mshr miss latency 588system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091 # average overall mshr miss latency 589system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 590system.cpu.icache.tags.replacements 5 # number of replacements | 590system.cpu.icache.tags.replacements 5 # number of replacements |
| 591system.cpu.icache.tags.tagsinuse 689.568004 # Cycle average of tags in use | 591system.cpu.icache.tags.tagsinuse 689.568187 # Cycle average of tags in use |
| 592system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks. 593system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. 594system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks. 595system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 592system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks. 593system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. 594system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks. 595system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 596system.cpu.icache.tags.occ_blocks::cpu.inst 689.568004 # Average occupied blocks per requestor | 596system.cpu.icache.tags.occ_blocks::cpu.inst 689.568187 # Average occupied blocks per requestor |
| 597system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy 598system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy 599system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id 600system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 601system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 602system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 603system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 604system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id 605system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses 606system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses | 597system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy 598system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy 599system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id 600system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 601system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 602system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 603system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 604system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id 605system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses 606system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses |
| 607system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 607system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 608system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits 609system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits 610system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits 611system.cpu.icache.demand_hits::total 27835083 # number of demand (read+write) hits 612system.cpu.icache.overall_hits::cpu.inst 27835083 # number of overall hits 613system.cpu.icache.overall_hits::total 27835083 # number of overall hits 614system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses 615system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses 616system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses 617system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses 618system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses 619system.cpu.icache.overall_misses::total 801 # number of overall misses | 608system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits 609system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits 610system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits 611system.cpu.icache.demand_hits::total 27835083 # number of demand (read+write) hits 612system.cpu.icache.overall_hits::cpu.inst 27835083 # number of overall hits 613system.cpu.icache.overall_hits::total 27835083 # number of overall hits 614system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses 615system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses 616system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses 617system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses 618system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses 619system.cpu.icache.overall_misses::total 801 # number of overall misses |
| 620system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410000 # number of ReadReq miss cycles 621system.cpu.icache.ReadReq_miss_latency::total 71410000 # number of ReadReq miss cycles 622system.cpu.icache.demand_miss_latency::cpu.inst 71410000 # number of demand (read+write) miss cycles 623system.cpu.icache.demand_miss_latency::total 71410000 # number of demand (read+write) miss cycles 624system.cpu.icache.overall_miss_latency::cpu.inst 71410000 # number of overall miss cycles 625system.cpu.icache.overall_miss_latency::total 71410000 # number of overall miss cycles | 620system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410500 # number of ReadReq miss cycles 621system.cpu.icache.ReadReq_miss_latency::total 71410500 # number of ReadReq miss cycles 622system.cpu.icache.demand_miss_latency::cpu.inst 71410500 # number of demand (read+write) miss cycles 623system.cpu.icache.demand_miss_latency::total 71410500 # number of demand (read+write) miss cycles 624system.cpu.icache.overall_miss_latency::cpu.inst 71410500 # number of overall miss cycles 625system.cpu.icache.overall_miss_latency::total 71410500 # number of overall miss cycles |
| 626system.cpu.icache.ReadReq_accesses::cpu.inst 27835884 # number of ReadReq accesses(hits+misses) 627system.cpu.icache.ReadReq_accesses::total 27835884 # number of ReadReq accesses(hits+misses) 628system.cpu.icache.demand_accesses::cpu.inst 27835884 # number of demand (read+write) accesses 629system.cpu.icache.demand_accesses::total 27835884 # number of demand (read+write) accesses 630system.cpu.icache.overall_accesses::cpu.inst 27835884 # number of overall (read+write) accesses 631system.cpu.icache.overall_accesses::total 27835884 # number of overall (read+write) accesses 632system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 633system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 634system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 635system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 636system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 637system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses | 626system.cpu.icache.ReadReq_accesses::cpu.inst 27835884 # number of ReadReq accesses(hits+misses) 627system.cpu.icache.ReadReq_accesses::total 27835884 # number of ReadReq accesses(hits+misses) 628system.cpu.icache.demand_accesses::cpu.inst 27835884 # number of demand (read+write) accesses 629system.cpu.icache.demand_accesses::total 27835884 # number of demand (read+write) accesses 630system.cpu.icache.overall_accesses::cpu.inst 27835884 # number of overall (read+write) accesses 631system.cpu.icache.overall_accesses::total 27835884 # number of overall (read+write) accesses 632system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 633system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 634system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 635system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 636system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 637system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses |
| 638system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.061174 # average ReadReq miss latency 639system.cpu.icache.ReadReq_avg_miss_latency::total 89151.061174 # average ReadReq miss latency 640system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency 641system.cpu.icache.demand_avg_miss_latency::total 89151.061174 # average overall miss latency 642system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency 643system.cpu.icache.overall_avg_miss_latency::total 89151.061174 # average overall miss latency | 638system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.685393 # average ReadReq miss latency 639system.cpu.icache.ReadReq_avg_miss_latency::total 89151.685393 # average ReadReq miss latency 640system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency 641system.cpu.icache.demand_avg_miss_latency::total 89151.685393 # average overall miss latency 642system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency 643system.cpu.icache.overall_avg_miss_latency::total 89151.685393 # average overall miss latency |
| 644system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 645system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 647system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 648system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 649system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu.icache.writebacks::writebacks 5 # number of writebacks 651system.cpu.icache.writebacks::total 5 # number of writebacks 652system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses 653system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses 654system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses 655system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses 656system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses 657system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses | 644system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 645system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 647system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 648system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 649system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu.icache.writebacks::writebacks 5 # number of writebacks 651system.cpu.icache.writebacks::total 5 # number of writebacks 652system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses 653system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses 654system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses 655system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses 656system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses 657system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses |
| 658system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609000 # number of ReadReq MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_latency::total 70609000 # number of ReadReq MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609000 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.demand_mshr_miss_latency::total 70609000 # number of demand (read+write) MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609000 # number of overall MSHR miss cycles 663system.cpu.icache.overall_mshr_miss_latency::total 70609000 # number of overall MSHR miss cycles | 658system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609500 # number of ReadReq MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_latency::total 70609500 # number of ReadReq MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609500 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.demand_mshr_miss_latency::total 70609500 # number of demand (read+write) MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609500 # number of overall MSHR miss cycles 663system.cpu.icache.overall_mshr_miss_latency::total 70609500 # number of overall MSHR miss cycles |
| 664system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 665system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 666system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 667system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 668system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 669system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses | 664system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 665system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 666system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 667system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 668system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 669system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses |
| 670system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.061174 # average ReadReq mshr miss latency 671system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.061174 # average ReadReq mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency 673system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency 674system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency 675system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency 676system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 670system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.685393 # average ReadReq mshr miss latency 671system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.685393 # average ReadReq mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency 673system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency 674system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency 675system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency 676system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 677system.cpu.l2cache.tags.replacements 0 # number of replacements | 677system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 678system.cpu.l2cache.tags.tagsinuse 11307.978899 # Cycle average of tags in use | 678system.cpu.l2cache.tags.tagsinuse 11307.993669 # Cycle average of tags in use |
| 679system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. 680system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. 681system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. 682system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 679system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. 680system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. 681system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. 682system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 683system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.572897 # Average occupied blocks per requestor 684system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.406002 # Average occupied blocks per requestor | 683system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.573080 # Average occupied blocks per requestor 684system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.420588 # Average occupied blocks per requestor |
| 685system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020586 # Average percentage of cache occupancy 686system.cpu.l2cache.tags.occ_percent::cpu.data 0.324506 # Average percentage of cache occupancy | 685system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020586 # Average percentage of cache occupancy 686system.cpu.l2cache.tags.occ_percent::cpu.data 0.324506 # Average percentage of cache occupancy |
| 687system.cpu.l2cache.tags.occ_percent::total 0.345092 # Average percentage of cache occupancy | 687system.cpu.l2cache.tags.occ_percent::total 0.345093 # Average percentage of cache occupancy |
| 688system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id 689system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 690system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id 691system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id 692system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 693system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id 694system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id 695system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses 696system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses | 688system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id 689system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 690system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id 691system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id 692system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 693system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id 694system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id 695system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses 696system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses |
| 697system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 697system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 698system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits 699system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits 700system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 701system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits 702system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 703system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 704system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 27 # number of ReadCleanReq hits 705system.cpu.l2cache.ReadCleanReq_hits::total 27 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 718system.cpu.l2cache.ReadSharedReq_misses::cpu.data 263 # number of ReadSharedReq misses 719system.cpu.l2cache.ReadSharedReq_misses::total 263 # number of ReadSharedReq misses 720system.cpu.l2cache.demand_misses::cpu.inst 774 # number of demand (read+write) misses 721system.cpu.l2cache.demand_misses::cpu.data 14807 # number of demand (read+write) misses 722system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses 723system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses 724system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses 725system.cpu.l2cache.overall_misses::total 15581 # number of overall misses | 698system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits 699system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits 700system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 701system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits 702system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 703system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 704system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 27 # number of ReadCleanReq hits 705system.cpu.l2cache.ReadCleanReq_hits::total 27 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 718system.cpu.l2cache.ReadSharedReq_misses::cpu.data 263 # number of ReadSharedReq misses 719system.cpu.l2cache.ReadSharedReq_misses::total 263 # number of ReadSharedReq misses 720system.cpu.l2cache.demand_misses::cpu.inst 774 # number of demand (read+write) misses 721system.cpu.l2cache.demand_misses::cpu.data 14807 # number of demand (read+write) misses 722system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses 723system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses 724system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses 725system.cpu.l2cache.overall_misses::total 15581 # number of overall misses |
| 726system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182252000 # number of ReadExReq miss cycles 727system.cpu.l2cache.ReadExReq_miss_latency::total 1182252000 # number of ReadExReq miss cycles 728system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69100500 # number of ReadCleanReq miss cycles 729system.cpu.l2cache.ReadCleanReq_miss_latency::total 69100500 # number of ReadCleanReq miss cycles | 726system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182247000 # number of ReadExReq miss cycles 727system.cpu.l2cache.ReadExReq_miss_latency::total 1182247000 # number of ReadExReq miss cycles 728system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69101000 # number of ReadCleanReq miss cycles 729system.cpu.l2cache.ReadCleanReq_miss_latency::total 69101000 # number of ReadCleanReq miss cycles |
| 730system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49237000 # number of ReadSharedReq miss cycles 731system.cpu.l2cache.ReadSharedReq_miss_latency::total 49237000 # number of ReadSharedReq miss cycles | 730system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49237000 # number of ReadSharedReq miss cycles 731system.cpu.l2cache.ReadSharedReq_miss_latency::total 49237000 # number of ReadSharedReq miss cycles |
| 732system.cpu.l2cache.demand_miss_latency::cpu.inst 69100500 # number of demand (read+write) miss cycles 733system.cpu.l2cache.demand_miss_latency::cpu.data 1231489000 # number of demand (read+write) miss cycles 734system.cpu.l2cache.demand_miss_latency::total 1300589500 # number of demand (read+write) miss cycles 735system.cpu.l2cache.overall_miss_latency::cpu.inst 69100500 # number of overall miss cycles 736system.cpu.l2cache.overall_miss_latency::cpu.data 1231489000 # number of overall miss cycles 737system.cpu.l2cache.overall_miss_latency::total 1300589500 # number of overall miss cycles | 732system.cpu.l2cache.demand_miss_latency::cpu.inst 69101000 # number of demand (read+write) miss cycles 733system.cpu.l2cache.demand_miss_latency::cpu.data 1231484000 # number of demand (read+write) miss cycles 734system.cpu.l2cache.demand_miss_latency::total 1300585000 # number of demand (read+write) miss cycles 735system.cpu.l2cache.overall_miss_latency::cpu.inst 69101000 # number of overall miss cycles 736system.cpu.l2cache.overall_miss_latency::cpu.data 1231484000 # number of overall miss cycles 737system.cpu.l2cache.overall_miss_latency::total 1300585000 # number of overall miss cycles |
| 738system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) 739system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) 740system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) 741system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) 742system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) 743system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) 744system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) 745system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 758system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses 759system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses 760system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966292 # miss rate for demand accesses 761system.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses 762system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses 763system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses 764system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses 765system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses | 738system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) 739system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) 740system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) 741system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) 742system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) 743system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) 744system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) 745system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 758system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses 759system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses 760system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966292 # miss rate for demand accesses 761system.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses 762system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses 763system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses 764system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses 765system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses |
| 766system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.953795 # average ReadExReq miss latency 767system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.953795 # average ReadExReq miss latency 768system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.131783 # average ReadCleanReq miss latency 769system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.131783 # average ReadCleanReq miss latency | 766system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011 # average ReadExReq miss latency 767system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011 # average ReadExReq miss latency 768system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778 # average ReadCleanReq miss latency 769system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778 # average ReadCleanReq miss latency |
| 770system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency 771system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency | 770system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency 771system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency |
| 772system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency 773system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency 774system.cpu.l2cache.demand_avg_miss_latency::total 83472.787369 # average overall miss latency 775system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency 776system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency 777system.cpu.l2cache.overall_avg_miss_latency::total 83472.787369 # average overall miss latency | 772system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency 773system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency 774system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556 # average overall miss latency 775system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency 776system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency 777system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556 # average overall miss latency |
| 778system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 779system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 780system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 781system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 782system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 783system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 784system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 785system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits --- 12 unchanged lines hidden (view full) --- 798system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses 799system.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses 800system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses 801system.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses 802system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 803system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses 804system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses 805system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses | 778system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 779system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 780system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 781system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 782system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 783system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 784system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 785system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits --- 12 unchanged lines hidden (view full) --- 798system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses 799system.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses 800system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses 801system.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses 802system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 803system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses 804system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses 805system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses |
| 806system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036812000 # number of ReadExReq MSHR miss cycles 807system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036812000 # number of ReadExReq MSHR miss cycles 808system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297000 # number of ReadCleanReq MSHR miss cycles 809system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297000 # number of ReadCleanReq MSHR miss cycles | 806system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036807000 # number of ReadExReq MSHR miss cycles 807system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036807000 # number of ReadExReq MSHR miss cycles 808system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297500 # number of ReadCleanReq MSHR miss cycles 809system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297500 # number of ReadCleanReq MSHR miss cycles |
| 810system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles 811system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles | 810system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles 811system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles |
| 812system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297000 # number of demand (read+write) MSHR miss cycles 813system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083046000 # number of demand (read+write) MSHR miss cycles 814system.cpu.l2cache.demand_mshr_miss_latency::total 1144343000 # number of demand (read+write) MSHR miss cycles 815system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297000 # number of overall MSHR miss cycles 816system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083046000 # number of overall MSHR miss cycles 817system.cpu.l2cache.overall_mshr_miss_latency::total 1144343000 # number of overall MSHR miss cycles | 812system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297500 # number of demand (read+write) MSHR miss cycles 813system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083041000 # number of demand (read+write) MSHR miss cycles 814system.cpu.l2cache.demand_mshr_miss_latency::total 1144338500 # number of demand (read+write) MSHR miss cycles 815system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297500 # number of overall MSHR miss cycles 816system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083041000 # number of overall MSHR miss cycles 817system.cpu.l2cache.overall_mshr_miss_latency::total 1144338500 # number of overall MSHR miss cycles |
| 818system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses 819system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses 820system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses 821system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses 822system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses 823system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses 824system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses 825system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses 826system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses 827system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses 828system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses 829system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses | 818system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses 819system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses 820system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses 821system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses 822system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses 823system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses 824system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses 825system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses 826system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses 827system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses 828system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses 829system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses |
| 830system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.953795 # average ReadExReq mshr miss latency 831system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.953795 # average ReadExReq mshr miss latency 832system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79297.542044 # average ReadCleanReq mshr miss latency 833system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79297.542044 # average ReadCleanReq mshr miss latency | 830system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011 # average ReadExReq mshr miss latency 831system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011 # average ReadExReq mshr miss latency 832system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875 # average ReadCleanReq mshr miss latency 833system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875 # average ReadCleanReq mshr miss latency |
| 834system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency 835system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency | 834system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency 835system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency |
| 836system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency 837system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency 838system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency 839system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency 840system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency 841system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency | 836system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency 837system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency 838system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency 839system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency 840system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency 841system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency |
| 842system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. 843system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. 844system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 845system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 846system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 847system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 842system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. 843system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. 844system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 845system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 846system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 847system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 848system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 848system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 849system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution 850system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution 851system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution 852system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution 853system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 854system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 855system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution 856system.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution --- 23 unchanged lines hidden (view full) --- 880system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) 881system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 882system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter. 883system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 884system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 885system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 886system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 887system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 849system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution 850system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution 851system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution 852system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution 853system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 854system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 855system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution 856system.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution --- 23 unchanged lines hidden (view full) --- 880system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) 881system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 882system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter. 883system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 884system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 885system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 886system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 887system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 888system.membus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states | 888system.membus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states |
| 889system.membus.trans_dist::ReadResp 1030 # Transaction distribution 890system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 891system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 892system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution 893system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) 894system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) 895system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) 896system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 901system.membus.snoop_fanout::stdev 0 # Request fanout histogram 902system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 903system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 904system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 905system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 906system.membus.snoop_fanout::min_value 0 # Request fanout histogram 907system.membus.snoop_fanout::max_value 0 # Request fanout histogram 908system.membus.snoop_fanout::total 15574 # Request fanout histogram | 889system.membus.trans_dist::ReadResp 1030 # Transaction distribution 890system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 891system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 892system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution 893system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) 894system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) 895system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) 896system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 901system.membus.snoop_fanout::stdev 0 # Request fanout histogram 902system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 903system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 904system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 905system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 906system.membus.snoop_fanout::min_value 0 # Request fanout histogram 907system.membus.snoop_fanout::max_value 0 # Request fanout histogram 908system.membus.snoop_fanout::total 15574 # Request fanout histogram |
| 909system.membus.reqLayer0.occupancy 21777000 # Layer occupancy (ticks) | 909system.membus.reqLayer0.occupancy 21778500 # Layer occupancy (ticks) |
| 910system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 911system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks) 912system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 913 914---------- End Simulation Statistics ---------- | 910system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 911system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks) 912system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 913 914---------- End Simulation Statistics ---------- |