stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
---|---|
1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 0.062409 # Number of seconds simulated 4sim_ticks 62408957500 # Number of ticks simulated 5final_tick 62408957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.062421 # Number of seconds simulated 4sim_ticks 62420912500 # Number of ticks simulated 5final_tick 62420912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 176281 # Simulator instruction rate (inst/s) 8host_op_rate 177159 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 121425676 # Simulator tick rate (ticks/s) 10host_mem_usage 399932 # Number of bytes of host memory used 11host_seconds 513.97 # Real time elapsed on the host | 7host_inst_rate 255603 # Simulator instruction rate (inst/s) 8host_op_rate 256876 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 176097831 # Simulator tick rate (ticks/s) 10host_mem_usage 405340 # Number of bytes of host memory used 11host_seconds 354.47 # Real time elapsed on the host |
12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
16system.physmem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
17system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory 19system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory 19system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory |
25system.physmem.bw_read::cpu.inst 792707 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 15178334 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 15971041 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 792707 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 792707 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 792707 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 15178334 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 15971041 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 792555 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 15175427 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 15967982 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 792555 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 792555 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 792555 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 15175427 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 15967982 # Total bandwidth to/from this memory (bytes/s) |
33system.physmem.readReqs 15574 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 15574 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
79system.physmem.totGap 62408863500 # Total gap between requests | 79system.physmem.totGap 62420817500 # Total gap between requests |
80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 15574 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 15574 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
94system.physmem.rdQLenPdf::0 15459 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 15458 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see |
96system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 96system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
190system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 642.437702 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 437.017774 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 401.182344 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 251 16.20% 16.20% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 185 11.94% 28.15% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 90 5.81% 33.96% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 67 4.33% 38.28% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 77 4.97% 43.25% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 93 6.00% 49.26% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 42 2.71% 51.97% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 43 2.78% 54.74% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 701 45.26% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation 204system.physmem.totQLat 75120250 # Total ticks spent queuing 205system.physmem.totMemAccLat 367132750 # Total ticks spent from burst creation until serviced by the DRAM | 190system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 645.984416 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 440.038624 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 401.127365 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 251 16.30% 16.30% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 179 11.62% 27.92% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 84 5.45% 33.38% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 75 4.87% 38.25% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 76 4.94% 43.18% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 73 4.74% 47.92% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 57 3.70% 51.62% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 48 3.12% 54.74% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 697 45.26% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation 204system.physmem.totQLat 72080000 # Total ticks spent queuing 205system.physmem.totMemAccLat 364092500 # Total ticks spent from burst creation until serviced by the DRAM |
206system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers |
207system.physmem.avgQLat 4823.44 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 4628.23 # Average queueing delay per DRAM burst |
208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
209system.physmem.avgMemAccLat 23573.44 # Average memory access latency per DRAM burst | 209system.physmem.avgMemAccLat 23378.23 # Average memory access latency per DRAM burst |
210system.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.12 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 210system.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.12 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
220system.physmem.readRowHits 14020 # Number of row buffer hits during reads | 220system.physmem.readRowHits 14024 # Number of row buffer hits during reads |
221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
222system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads |
223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
224system.physmem.avgGap 4007246.92 # Average gap between requests 225system.physmem.pageHitRate 90.02 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 6395760 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 3489750 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) | 224system.physmem.avgGap 4008014.48 # Average gap between requests 225system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 6335280 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 3456750 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 63648000 # Energy for read commands per rank (pJ) |
229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
230system.physmem_0.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 2565881505 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 35193459000 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 41909107215 # Total energy per rank (pJ) 234system.physmem_0.averagePower 671.544396 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 58537353750 # Time in different power states 236system.physmem_0.memoryStateTime::REF 2083900000 # Time in different power states | 230system.physmem_0.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 2557911195 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 35205114000 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 41913082185 # Total energy per rank (pJ) 234system.physmem_0.averagePower 671.524455 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 58558754750 # Time in different power states 236system.physmem_0.memoryStateTime::REF 2084160000 # Time in different power states |
237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
238system.physmem_0.memoryStateTime::ACT 1785901250 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT 1773814250 # Time in different power states |
239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
240system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) | 240system.physmem_1.actEnergy 5292000 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 2887500 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) |
243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
244system.physmem_1.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) 245system.physmem_1.actBackEnergy 2571480045 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 35188548000 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 41901860400 # Total energy per rank (pJ) 248system.physmem_1.averagePower 671.428274 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 58529558500 # Time in different power states 250system.physmem_1.memoryStateTime::REF 2083900000 # Time in different power states | 244system.physmem_1.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) 245system.physmem_1.actBackEnergy 2600892900 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 35167410750 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 41910562710 # Total energy per rank (pJ) 248system.physmem_1.averagePower 671.484088 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 58497118250 # Time in different power states 250system.physmem_1.memoryStateTime::REF 2084160000 # Time in different power states |
251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
252system.physmem_1.memoryStateTime::ACT 1793609000 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT 1836331750 # Time in different power states |
253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
254system.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 255system.cpu.branchPred.lookups 20808236 # Number of BP lookups 256system.cpu.branchPred.condPredicted 17115622 # Number of conditional branches predicted | 254system.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states 255system.cpu.branchPred.lookups 20808241 # Number of BP lookups 256system.cpu.branchPred.condPredicted 17115627 # Number of conditional branches predicted |
257system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect | 257system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect |
258system.cpu.branchPred.BTBLookups 8965652 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 8840815 # Number of BTB hits | 258system.cpu.branchPred.BTBLookups 8965661 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 8840824 # Number of BTB hits |
260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
261system.cpu.branchPred.BTBHitPct 98.607608 # BTB Hit Percentage | 261system.cpu.branchPred.BTBHitPct 98.607610 # BTB Hit Percentage |
262system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks | 262system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks |
269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses | 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses |
329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
360system.cpu.itb.walker.walks 0 # Table walker walks requested 361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.itb.read_accesses 0 # DTB read accesses 384system.cpu.itb.write_accesses 0 # DTB write accesses 385system.cpu.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.itb.hits 0 # DTB hits 387system.cpu.itb.misses 0 # DTB misses 388system.cpu.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 442 # Number of system calls | 360system.cpu.itb.walker.walks 0 # Table walker walks requested 361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.itb.read_accesses 0 # DTB read accesses 384system.cpu.itb.write_accesses 0 # DTB write accesses 385system.cpu.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.itb.hits 0 # DTB hits 387system.cpu.itb.misses 0 # DTB misses 388system.cpu.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 442 # Number of system calls |
390system.cpu.pwrStateResidencyTicks::ON 62408957500 # Cumulative time (in ticks) in various power states 391system.cpu.numCycles 124817915 # number of cpu cycles simulated | 390system.cpu.pwrStateResidencyTicks::ON 62420912500 # Cumulative time (in ticks) in various power states 391system.cpu.numCycles 124841825 # number of cpu cycles simulated |
392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.committedInsts 90602850 # Number of instructions committed 395system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed | 392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.committedInsts 90602850 # Number of instructions committed 395system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed |
396system.cpu.discardedOps 2182474 # Number of ops (including micro ops) which were discarded before commit | 396system.cpu.discardedOps 2182225 # Number of ops (including micro ops) which were discarded before commit |
397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
398system.cpu.cpi 1.377638 # CPI: cycles per instruction 399system.cpu.ipc 0.725880 # IPC: instructions per cycle | 398system.cpu.cpi 1.377902 # CPI: cycles per instruction 399system.cpu.ipc 0.725741 # IPC: instructions per cycle |
400system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 401system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction 402system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 403system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 404system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 405system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 406system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 407system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 427system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 428system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 429system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 430system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 431system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 434system.cpu.op_class_0::total 91054081 # Class of committed instruction | 400system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 401system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction 402system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 403system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 404system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 405system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 406system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 407system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 427system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 428system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 429system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 430system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 431system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 434system.cpu.op_class_0::total 91054081 # Class of committed instruction |
435system.cpu.tickCycles 110516717 # Number of cycles that the object actually ticked 436system.cpu.idleCycles 14301198 # Total number of cycles that the object has spent stopped 437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 435system.cpu.tickCycles 110516273 # Number of cycles that the object actually ticked 436system.cpu.idleCycles 14325552 # Total number of cycles that the object has spent stopped 437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
438system.cpu.dcache.tags.replacements 946101 # number of replacements | 438system.cpu.dcache.tags.replacements 946101 # number of replacements |
439system.cpu.dcache.tags.tagsinuse 3621.431844 # Cycle average of tags in use 440system.cpu.dcache.tags.total_refs 26274920 # Total number of references to valid blocks. | 439system.cpu.dcache.tags.tagsinuse 3621.404220 # Cycle average of tags in use 440system.cpu.dcache.tags.total_refs 26274921 # Total number of references to valid blocks. |
441system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. | 441system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. |
442system.cpu.dcache.tags.avg_refs 27.652076 # Average number of references to valid blocks. 443system.cpu.dcache.tags.warmup_cycle 20702462500 # Cycle when the warmup percentage was hit. 444system.cpu.dcache.tags.occ_blocks::cpu.data 3621.431844 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.data 0.884139 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.884139 # Average percentage of cache occupancy | 442system.cpu.dcache.tags.avg_refs 27.652077 # Average number of references to valid blocks. 443system.cpu.dcache.tags.warmup_cycle 20706654500 # Cycle when the warmup percentage was hit. 444system.cpu.dcache.tags.occ_blocks::cpu.data 3621.404220 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.data 0.884132 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.884132 # Average percentage of cache occupancy |
447system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id | 447system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id |
449system.cpu.dcache.tags.age_task_id_blocks_1024::1 2203 # Occupied blocks per task id 450system.cpu.dcache.tags.age_task_id_blocks_1024::2 1651 # Occupied blocks per task id | 449system.cpu.dcache.tags.age_task_id_blocks_1024::1 2205 # Occupied blocks per task id 450system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id |
451system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 451system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
452system.cpu.dcache.tags.tag_accesses 55461267 # Number of tag accesses 453system.cpu.dcache.tags.data_accesses 55461267 # Number of data accesses 454system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 455system.cpu.dcache.ReadReq_hits::cpu.data 21605941 # number of ReadReq hits 456system.cpu.dcache.ReadReq_hits::total 21605941 # number of ReadReq hits 457system.cpu.dcache.WriteReq_hits::cpu.data 4660697 # number of WriteReq hits 458system.cpu.dcache.WriteReq_hits::total 4660697 # number of WriteReq hits | 452system.cpu.dcache.tags.tag_accesses 55461265 # Number of tag accesses 453system.cpu.dcache.tags.data_accesses 55461265 # Number of data accesses 454system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states 455system.cpu.dcache.ReadReq_hits::cpu.data 21605938 # number of ReadReq hits 456system.cpu.dcache.ReadReq_hits::total 21605938 # number of ReadReq hits 457system.cpu.dcache.WriteReq_hits::cpu.data 4660701 # number of WriteReq hits 458system.cpu.dcache.WriteReq_hits::total 4660701 # number of WriteReq hits |
459system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 460system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 461system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 462system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 463system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 464system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits | 459system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 460system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 461system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 462system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 463system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 464system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits |
465system.cpu.dcache.demand_hits::cpu.data 26266638 # number of demand (read+write) hits 466system.cpu.dcache.demand_hits::total 26266638 # number of demand (read+write) hits 467system.cpu.dcache.overall_hits::cpu.data 26267146 # number of overall hits 468system.cpu.dcache.overall_hits::total 26267146 # number of overall hits 469system.cpu.dcache.ReadReq_misses::cpu.data 906327 # number of ReadReq misses 470system.cpu.dcache.ReadReq_misses::total 906327 # number of ReadReq misses 471system.cpu.dcache.WriteReq_misses::cpu.data 74284 # number of WriteReq misses 472system.cpu.dcache.WriteReq_misses::total 74284 # number of WriteReq misses | 465system.cpu.dcache.demand_hits::cpu.data 26266639 # number of demand (read+write) hits 466system.cpu.dcache.demand_hits::total 26266639 # number of demand (read+write) hits 467system.cpu.dcache.overall_hits::cpu.data 26267147 # number of overall hits 468system.cpu.dcache.overall_hits::total 26267147 # number of overall hits 469system.cpu.dcache.ReadReq_misses::cpu.data 906329 # number of ReadReq misses 470system.cpu.dcache.ReadReq_misses::total 906329 # number of ReadReq misses 471system.cpu.dcache.WriteReq_misses::cpu.data 74280 # number of WriteReq misses 472system.cpu.dcache.WriteReq_misses::total 74280 # number of WriteReq misses |
473system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 474system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses | 473system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 474system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses |
475system.cpu.dcache.demand_misses::cpu.data 980611 # number of demand (read+write) misses 476system.cpu.dcache.demand_misses::total 980611 # number of demand (read+write) misses 477system.cpu.dcache.overall_misses::cpu.data 980615 # number of overall misses 478system.cpu.dcache.overall_misses::total 980615 # number of overall misses 479system.cpu.dcache.ReadReq_miss_latency::cpu.data 11805097500 # number of ReadReq miss cycles 480system.cpu.dcache.ReadReq_miss_latency::total 11805097500 # number of ReadReq miss cycles 481system.cpu.dcache.WriteReq_miss_latency::cpu.data 2540928500 # number of WriteReq miss cycles 482system.cpu.dcache.WriteReq_miss_latency::total 2540928500 # number of WriteReq miss cycles 483system.cpu.dcache.demand_miss_latency::cpu.data 14346026000 # number of demand (read+write) miss cycles 484system.cpu.dcache.demand_miss_latency::total 14346026000 # number of demand (read+write) miss cycles 485system.cpu.dcache.overall_miss_latency::cpu.data 14346026000 # number of overall miss cycles 486system.cpu.dcache.overall_miss_latency::total 14346026000 # number of overall miss cycles 487system.cpu.dcache.ReadReq_accesses::cpu.data 22512268 # number of ReadReq accesses(hits+misses) 488system.cpu.dcache.ReadReq_accesses::total 22512268 # number of ReadReq accesses(hits+misses) | 475system.cpu.dcache.demand_misses::cpu.data 980609 # number of demand (read+write) misses 476system.cpu.dcache.demand_misses::total 980609 # number of demand (read+write) misses 477system.cpu.dcache.overall_misses::cpu.data 980613 # number of overall misses 478system.cpu.dcache.overall_misses::total 980613 # number of overall misses 479system.cpu.dcache.ReadReq_miss_latency::cpu.data 11804222500 # number of ReadReq miss cycles 480system.cpu.dcache.ReadReq_miss_latency::total 11804222500 # number of ReadReq miss cycles 481system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566012000 # number of WriteReq miss cycles 482system.cpu.dcache.WriteReq_miss_latency::total 2566012000 # number of WriteReq miss cycles 483system.cpu.dcache.demand_miss_latency::cpu.data 14370234500 # number of demand (read+write) miss cycles 484system.cpu.dcache.demand_miss_latency::total 14370234500 # number of demand (read+write) miss cycles 485system.cpu.dcache.overall_miss_latency::cpu.data 14370234500 # number of overall miss cycles 486system.cpu.dcache.overall_miss_latency::total 14370234500 # number of overall miss cycles 487system.cpu.dcache.ReadReq_accesses::cpu.data 22512267 # number of ReadReq accesses(hits+misses) 488system.cpu.dcache.ReadReq_accesses::total 22512267 # number of ReadReq accesses(hits+misses) |
489system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 490system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 491system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 492system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 493system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 494system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 495system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 496system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) | 489system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 490system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 491system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 492system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 493system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 494system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 495system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 496system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) |
497system.cpu.dcache.demand_accesses::cpu.data 27247249 # number of demand (read+write) accesses 498system.cpu.dcache.demand_accesses::total 27247249 # number of demand (read+write) accesses 499system.cpu.dcache.overall_accesses::cpu.data 27247761 # number of overall (read+write) accesses 500system.cpu.dcache.overall_accesses::total 27247761 # number of overall (read+write) accesses | 497system.cpu.dcache.demand_accesses::cpu.data 27247248 # number of demand (read+write) accesses 498system.cpu.dcache.demand_accesses::total 27247248 # number of demand (read+write) accesses 499system.cpu.dcache.overall_accesses::cpu.data 27247760 # number of overall (read+write) accesses 500system.cpu.dcache.overall_accesses::total 27247760 # number of overall (read+write) accesses |
501system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses 502system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses | 501system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses 502system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses |
503system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses 504system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses | 503system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015687 # miss rate for WriteReq accesses 504system.cpu.dcache.WriteReq_miss_rate::total 0.015687 # miss rate for WriteReq accesses |
505system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 506system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses 507system.cpu.dcache.demand_miss_rate::cpu.data 0.035989 # miss rate for demand accesses 508system.cpu.dcache.demand_miss_rate::total 0.035989 # miss rate for demand accesses 509system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses 510system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses | 505system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 506system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses 507system.cpu.dcache.demand_miss_rate::cpu.data 0.035989 # miss rate for demand accesses 508system.cpu.dcache.demand_miss_rate::total 0.035989 # miss rate for demand accesses 509system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses 510system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses |
511system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.207789 # average ReadReq miss latency 512system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.207789 # average ReadReq miss latency 513system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34205.596091 # average WriteReq miss latency 514system.cpu.dcache.WriteReq_avg_miss_latency::total 34205.596091 # average WriteReq miss latency 515system.cpu.dcache.demand_avg_miss_latency::cpu.data 14629.680883 # average overall miss latency 516system.cpu.dcache.demand_avg_miss_latency::total 14629.680883 # average overall miss latency 517system.cpu.dcache.overall_avg_miss_latency::cpu.data 14629.621207 # average overall miss latency 518system.cpu.dcache.overall_avg_miss_latency::total 14629.621207 # average overall miss latency | 511system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13024.213613 # average ReadReq miss latency 512system.cpu.dcache.ReadReq_avg_miss_latency::total 13024.213613 # average ReadReq miss latency 513system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34545.126548 # average WriteReq miss latency 514system.cpu.dcache.WriteReq_avg_miss_latency::total 34545.126548 # average WriteReq miss latency 515system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.397930 # average overall miss latency 516system.cpu.dcache.demand_avg_miss_latency::total 14654.397930 # average overall miss latency 517system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.338154 # average overall miss latency 518system.cpu.dcache.overall_avg_miss_latency::total 14654.338154 # average overall miss latency |
519system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 520system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 521system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 522system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 523system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 524system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 525system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks 526system.cpu.dcache.writebacks::total 943282 # number of writebacks | 519system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 520system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 521system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 522system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 523system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 524system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 525system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks 526system.cpu.dcache.writebacks::total 943282 # number of writebacks |
527system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2897 # number of ReadReq MSHR hits 528system.cpu.dcache.ReadReq_mshr_hits::total 2897 # number of ReadReq MSHR hits 529system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27520 # number of WriteReq MSHR hits 530system.cpu.dcache.WriteReq_mshr_hits::total 27520 # number of WriteReq MSHR hits 531system.cpu.dcache.demand_mshr_hits::cpu.data 30417 # number of demand (read+write) MSHR hits 532system.cpu.dcache.demand_mshr_hits::total 30417 # number of demand (read+write) MSHR hits 533system.cpu.dcache.overall_mshr_hits::cpu.data 30417 # number of overall MSHR hits 534system.cpu.dcache.overall_mshr_hits::total 30417 # number of overall MSHR hits | 527system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2899 # number of ReadReq MSHR hits 528system.cpu.dcache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits 529system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits 530system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits 531system.cpu.dcache.demand_mshr_hits::cpu.data 30415 # number of demand (read+write) MSHR hits 532system.cpu.dcache.demand_mshr_hits::total 30415 # number of demand (read+write) MSHR hits 533system.cpu.dcache.overall_mshr_hits::cpu.data 30415 # number of overall MSHR hits 534system.cpu.dcache.overall_mshr_hits::total 30415 # number of overall MSHR hits |
535system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses 536system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses 537system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses 538system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses 539system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 540system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 541system.cpu.dcache.demand_mshr_misses::cpu.data 950194 # number of demand (read+write) MSHR misses 542system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses 543system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses 544system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses | 535system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses 536system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses 537system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses 538system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses 539system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 540system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 541system.cpu.dcache.demand_mshr_misses::cpu.data 950194 # number of demand (read+write) MSHR misses 542system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses 543system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses 544system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses |
545system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10863020500 # number of ReadReq MSHR miss cycles 546system.cpu.dcache.ReadReq_mshr_miss_latency::total 10863020500 # number of ReadReq MSHR miss cycles 547system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1482579500 # number of WriteReq MSHR miss cycles 548system.cpu.dcache.WriteReq_mshr_miss_latency::total 1482579500 # number of WriteReq MSHR miss cycles 549system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156000 # number of SoftPFReq MSHR miss cycles 550system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156000 # number of SoftPFReq MSHR miss cycles 551system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345600000 # number of demand (read+write) MSHR miss cycles 552system.cpu.dcache.demand_mshr_miss_latency::total 12345600000 # number of demand (read+write) MSHR miss cycles 553system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345756000 # number of overall MSHR miss cycles 554system.cpu.dcache.overall_mshr_miss_latency::total 12345756000 # number of overall MSHR miss cycles | 545system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862380000 # number of ReadReq MSHR miss cycles 546system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862380000 # number of ReadReq MSHR miss cycles 547system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1495373500 # number of WriteReq MSHR miss cycles 548system.cpu.dcache.WriteReq_mshr_miss_latency::total 1495373500 # number of WriteReq MSHR miss cycles 549system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 158000 # number of SoftPFReq MSHR miss cycles 550system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 158000 # number of SoftPFReq MSHR miss cycles 551system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12357753500 # number of demand (read+write) MSHR miss cycles 552system.cpu.dcache.demand_mshr_miss_latency::total 12357753500 # number of demand (read+write) MSHR miss cycles 553system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12357911500 # number of overall MSHR miss cycles 554system.cpu.dcache.overall_mshr_miss_latency::total 12357911500 # number of overall MSHR miss cycles |
555system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses 556system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses 557system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 558system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 559system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 560system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 561system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses 562system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses 563system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses 564system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses | 555system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses 556system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses 557system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 558system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 559system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 560system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 561system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses 562system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses 563system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses 564system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses |
565system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12024.197226 # average ReadReq mshr miss latency 566system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12024.197226 # average ReadReq mshr miss latency 567system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31703.436404 # average WriteReq mshr miss latency 568system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31703.436404 # average WriteReq mshr miss latency 569system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52000 # average SoftPFReq mshr miss latency 570system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52000 # average SoftPFReq mshr miss latency 571system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.715172 # average overall mshr miss latency 572system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.715172 # average overall mshr miss latency 573system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.838327 # average overall mshr miss latency 574system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.838327 # average overall mshr miss latency 575system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 565system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.488261 # average ReadReq mshr miss latency 566system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.488261 # average ReadReq mshr miss latency 567system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31977.022924 # average WriteReq mshr miss latency 568system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31977.022924 # average WriteReq mshr miss latency 569system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52666.666667 # average SoftPFReq mshr miss latency 570system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52666.666667 # average SoftPFReq mshr miss latency 571system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13005.505718 # average overall mshr miss latency 572system.cpu.dcache.demand_avg_mshr_miss_latency::total 13005.505718 # average overall mshr miss latency 573system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13005.630938 # average overall mshr miss latency 574system.cpu.dcache.overall_avg_mshr_miss_latency::total 13005.630938 # average overall mshr miss latency 575system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
576system.cpu.icache.tags.replacements 5 # number of replacements | 576system.cpu.icache.tags.replacements 5 # number of replacements |
577system.cpu.icache.tags.tagsinuse 689.591924 # Cycle average of tags in use 578system.cpu.icache.tags.total_refs 27835291 # Total number of references to valid blocks. | 577system.cpu.icache.tags.tagsinuse 689.589449 # Cycle average of tags in use 578system.cpu.icache.tags.total_refs 27835051 # Total number of references to valid blocks. |
579system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. | 579system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. |
580system.cpu.icache.tags.avg_refs 34750.675406 # Average number of references to valid blocks. | 580system.cpu.icache.tags.avg_refs 34750.375780 # Average number of references to valid blocks. |
581system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 581system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
582system.cpu.icache.tags.occ_blocks::cpu.inst 689.591924 # Average occupied blocks per requestor 583system.cpu.icache.tags.occ_percent::cpu.inst 0.336715 # Average percentage of cache occupancy 584system.cpu.icache.tags.occ_percent::total 0.336715 # Average percentage of cache occupancy | 582system.cpu.icache.tags.occ_blocks::cpu.inst 689.589449 # Average occupied blocks per requestor 583system.cpu.icache.tags.occ_percent::cpu.inst 0.336714 # Average percentage of cache occupancy 584system.cpu.icache.tags.occ_percent::total 0.336714 # Average percentage of cache occupancy |
585system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id 586system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 587system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 588system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 590system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id | 585system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id 586system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 587system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 588system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 590system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id |
591system.cpu.icache.tags.tag_accesses 55672985 # Number of tag accesses 592system.cpu.icache.tags.data_accesses 55672985 # Number of data accesses 593system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 594system.cpu.icache.ReadReq_hits::cpu.inst 27835291 # number of ReadReq hits 595system.cpu.icache.ReadReq_hits::total 27835291 # number of ReadReq hits 596system.cpu.icache.demand_hits::cpu.inst 27835291 # number of demand (read+write) hits 597system.cpu.icache.demand_hits::total 27835291 # number of demand (read+write) hits 598system.cpu.icache.overall_hits::cpu.inst 27835291 # number of overall hits 599system.cpu.icache.overall_hits::total 27835291 # number of overall hits | 591system.cpu.icache.tags.tag_accesses 55672505 # Number of tag accesses 592system.cpu.icache.tags.data_accesses 55672505 # Number of data accesses 593system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states 594system.cpu.icache.ReadReq_hits::cpu.inst 27835051 # number of ReadReq hits 595system.cpu.icache.ReadReq_hits::total 27835051 # number of ReadReq hits 596system.cpu.icache.demand_hits::cpu.inst 27835051 # number of demand (read+write) hits 597system.cpu.icache.demand_hits::total 27835051 # number of demand (read+write) hits 598system.cpu.icache.overall_hits::cpu.inst 27835051 # number of overall hits 599system.cpu.icache.overall_hits::total 27835051 # number of overall hits |
600system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses 601system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses 602system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses 603system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses 604system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses 605system.cpu.icache.overall_misses::total 801 # number of overall misses | 600system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses 601system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses 602system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses 603system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses 604system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses 605system.cpu.icache.overall_misses::total 801 # number of overall misses |
606system.cpu.icache.ReadReq_miss_latency::cpu.inst 60446000 # number of ReadReq miss cycles 607system.cpu.icache.ReadReq_miss_latency::total 60446000 # number of ReadReq miss cycles 608system.cpu.icache.demand_miss_latency::cpu.inst 60446000 # number of demand (read+write) miss cycles 609system.cpu.icache.demand_miss_latency::total 60446000 # number of demand (read+write) miss cycles 610system.cpu.icache.overall_miss_latency::cpu.inst 60446000 # number of overall miss cycles 611system.cpu.icache.overall_miss_latency::total 60446000 # number of overall miss cycles 612system.cpu.icache.ReadReq_accesses::cpu.inst 27836092 # number of ReadReq accesses(hits+misses) 613system.cpu.icache.ReadReq_accesses::total 27836092 # number of ReadReq accesses(hits+misses) 614system.cpu.icache.demand_accesses::cpu.inst 27836092 # number of demand (read+write) accesses 615system.cpu.icache.demand_accesses::total 27836092 # number of demand (read+write) accesses 616system.cpu.icache.overall_accesses::cpu.inst 27836092 # number of overall (read+write) accesses 617system.cpu.icache.overall_accesses::total 27836092 # number of overall (read+write) accesses | 606system.cpu.icache.ReadReq_miss_latency::cpu.inst 60780500 # number of ReadReq miss cycles 607system.cpu.icache.ReadReq_miss_latency::total 60780500 # number of ReadReq miss cycles 608system.cpu.icache.demand_miss_latency::cpu.inst 60780500 # number of demand (read+write) miss cycles 609system.cpu.icache.demand_miss_latency::total 60780500 # number of demand (read+write) miss cycles 610system.cpu.icache.overall_miss_latency::cpu.inst 60780500 # number of overall miss cycles 611system.cpu.icache.overall_miss_latency::total 60780500 # number of overall miss cycles 612system.cpu.icache.ReadReq_accesses::cpu.inst 27835852 # number of ReadReq accesses(hits+misses) 613system.cpu.icache.ReadReq_accesses::total 27835852 # number of ReadReq accesses(hits+misses) 614system.cpu.icache.demand_accesses::cpu.inst 27835852 # number of demand (read+write) accesses 615system.cpu.icache.demand_accesses::total 27835852 # number of demand (read+write) accesses 616system.cpu.icache.overall_accesses::cpu.inst 27835852 # number of overall (read+write) accesses 617system.cpu.icache.overall_accesses::total 27835852 # number of overall (read+write) accesses |
618system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 619system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 620system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 621system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 622system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 623system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses | 618system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 619system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 620system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 621system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 622system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 623system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses |
624system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75463.171036 # average ReadReq miss latency 625system.cpu.icache.ReadReq_avg_miss_latency::total 75463.171036 # average ReadReq miss latency 626system.cpu.icache.demand_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency 627system.cpu.icache.demand_avg_miss_latency::total 75463.171036 # average overall miss latency 628system.cpu.icache.overall_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency 629system.cpu.icache.overall_avg_miss_latency::total 75463.171036 # average overall miss latency | 624system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75880.774032 # average ReadReq miss latency 625system.cpu.icache.ReadReq_avg_miss_latency::total 75880.774032 # average ReadReq miss latency 626system.cpu.icache.demand_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency 627system.cpu.icache.demand_avg_miss_latency::total 75880.774032 # average overall miss latency 628system.cpu.icache.overall_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency 629system.cpu.icache.overall_avg_miss_latency::total 75880.774032 # average overall miss latency |
630system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 631system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 633system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 634system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 635system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.icache.writebacks::writebacks 5 # number of writebacks 637system.cpu.icache.writebacks::total 5 # number of writebacks 638system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses 639system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses 640system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses 641system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses 642system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses 643system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses | 630system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 631system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 633system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 634system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 635system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.icache.writebacks::writebacks 5 # number of writebacks 637system.cpu.icache.writebacks::total 5 # number of writebacks 638system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses 639system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses 640system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses 641system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses 642system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses 643system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses |
644system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59645000 # number of ReadReq MSHR miss cycles 645system.cpu.icache.ReadReq_mshr_miss_latency::total 59645000 # number of ReadReq MSHR miss cycles 646system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59645000 # number of demand (read+write) MSHR miss cycles 647system.cpu.icache.demand_mshr_miss_latency::total 59645000 # number of demand (read+write) MSHR miss cycles 648system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59645000 # number of overall MSHR miss cycles 649system.cpu.icache.overall_mshr_miss_latency::total 59645000 # number of overall MSHR miss cycles | 644system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59979500 # number of ReadReq MSHR miss cycles 645system.cpu.icache.ReadReq_mshr_miss_latency::total 59979500 # number of ReadReq MSHR miss cycles 646system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59979500 # number of demand (read+write) MSHR miss cycles 647system.cpu.icache.demand_mshr_miss_latency::total 59979500 # number of demand (read+write) MSHR miss cycles 648system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59979500 # number of overall MSHR miss cycles 649system.cpu.icache.overall_mshr_miss_latency::total 59979500 # number of overall MSHR miss cycles |
650system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 651system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 652system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 653system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 654system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 655system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses | 650system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 651system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 652system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 653system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 654system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 655system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses |
656system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74463.171036 # average ReadReq mshr miss latency 657system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74463.171036 # average ReadReq mshr miss latency 658system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency 659system.cpu.icache.demand_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency 660system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency 661system.cpu.icache.overall_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency 662system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 656system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74880.774032 # average ReadReq mshr miss latency 657system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74880.774032 # average ReadReq mshr miss latency 658system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency 659system.cpu.icache.demand_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency 660system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency 661system.cpu.icache.overall_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency 662system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
663system.cpu.l2cache.tags.replacements 0 # number of replacements | 663system.cpu.l2cache.tags.replacements 0 # number of replacements |
664system.cpu.l2cache.tags.tagsinuse 10294.680667 # Cycle average of tags in use 665system.cpu.l2cache.tags.total_refs 1834001 # Total number of references to valid blocks. 666system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. 667system.cpu.l2cache.tags.avg_refs 117.889117 # Average number of references to valid blocks. | 664system.cpu.l2cache.tags.tagsinuse 11312.672856 # Cycle average of tags in use 665system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. 666system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. 667system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. |
668system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 668system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
669system.cpu.l2cache.tags.occ_blocks::writebacks 9404.439964 # Average occupied blocks per requestor 670system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.596313 # Average occupied blocks per requestor 671system.cpu.l2cache.tags.occ_blocks::cpu.data 215.644390 # Average occupied blocks per requestor 672system.cpu.l2cache.tags.occ_percent::writebacks 0.287001 # Average percentage of cache occupancy | 669system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.593915 # Average occupied blocks per requestor 670system.cpu.l2cache.tags.occ_blocks::cpu.data 10638.078941 # Average occupied blocks per requestor |
673system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy | 671system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy |
674system.cpu.l2cache.tags.occ_percent::cpu.data 0.006581 # Average percentage of cache occupancy 675system.cpu.l2cache.tags.occ_percent::total 0.314169 # Average percentage of cache occupancy 676system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id | 672system.cpu.l2cache.tags.occ_percent::cpu.data 0.324648 # Average percentage of cache occupancy 673system.cpu.l2cache.tags.occ_percent::total 0.345235 # Average percentage of cache occupancy 674system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id |
677system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id | 675system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id |
678system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 679system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id 680system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id 681system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id 682system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id 683system.cpu.l2cache.tags.tag_accesses 15237953 # Number of tag accesses 684system.cpu.l2cache.tags.data_accesses 15237953 # Number of data accesses 685system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 676system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id 677system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id 678system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 679system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id 680system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id 681system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses 682system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses 683system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
686system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits 687system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits 688system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 689system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits 690system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 691system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 692system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 27 # number of ReadCleanReq hits 693system.cpu.l2cache.ReadCleanReq_hits::total 27 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 706system.cpu.l2cache.ReadSharedReq_misses::cpu.data 263 # number of ReadSharedReq misses 707system.cpu.l2cache.ReadSharedReq_misses::total 263 # number of ReadSharedReq misses 708system.cpu.l2cache.demand_misses::cpu.inst 774 # number of demand (read+write) misses 709system.cpu.l2cache.demand_misses::cpu.data 14807 # number of demand (read+write) misses 710system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses 711system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses 712system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses 713system.cpu.l2cache.overall_misses::total 15581 # number of overall misses | 684system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits 685system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits 686system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 687system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits 688system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 689system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 690system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 27 # number of ReadCleanReq hits 691system.cpu.l2cache.ReadCleanReq_hits::total 27 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 704system.cpu.l2cache.ReadSharedReq_misses::cpu.data 263 # number of ReadSharedReq misses 705system.cpu.l2cache.ReadSharedReq_misses::total 263 # number of ReadSharedReq misses 706system.cpu.l2cache.demand_misses::cpu.inst 774 # number of demand (read+write) misses 707system.cpu.l2cache.demand_misses::cpu.data 14807 # number of demand (read+write) misses 708system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses 709system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses 710system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses 711system.cpu.l2cache.overall_misses::total 15581 # number of overall misses |
714system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1068633000 # number of ReadExReq miss cycles 715system.cpu.l2cache.ReadExReq_miss_latency::total 1068633000 # number of ReadExReq miss cycles 716system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58136500 # number of ReadCleanReq miss cycles 717system.cpu.l2cache.ReadCleanReq_miss_latency::total 58136500 # number of ReadCleanReq miss cycles 718system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22289000 # number of ReadSharedReq miss cycles 719system.cpu.l2cache.ReadSharedReq_miss_latency::total 22289000 # number of ReadSharedReq miss cycles 720system.cpu.l2cache.demand_miss_latency::cpu.inst 58136500 # number of demand (read+write) miss cycles 721system.cpu.l2cache.demand_miss_latency::cpu.data 1090922000 # number of demand (read+write) miss cycles 722system.cpu.l2cache.demand_miss_latency::total 1149058500 # number of demand (read+write) miss cycles 723system.cpu.l2cache.overall_miss_latency::cpu.inst 58136500 # number of overall miss cycles 724system.cpu.l2cache.overall_miss_latency::cpu.data 1090922000 # number of overall miss cycles 725system.cpu.l2cache.overall_miss_latency::total 1149058500 # number of overall miss cycles | 712system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1081439500 # number of ReadExReq miss cycles 713system.cpu.l2cache.ReadExReq_miss_latency::total 1081439500 # number of ReadExReq miss cycles 714system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58471000 # number of ReadCleanReq miss cycles 715system.cpu.l2cache.ReadCleanReq_miss_latency::total 58471000 # number of ReadCleanReq miss cycles 716system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21652500 # number of ReadSharedReq miss cycles 717system.cpu.l2cache.ReadSharedReq_miss_latency::total 21652500 # number of ReadSharedReq miss cycles 718system.cpu.l2cache.demand_miss_latency::cpu.inst 58471000 # number of demand (read+write) miss cycles 719system.cpu.l2cache.demand_miss_latency::cpu.data 1103092000 # number of demand (read+write) miss cycles 720system.cpu.l2cache.demand_miss_latency::total 1161563000 # number of demand (read+write) miss cycles 721system.cpu.l2cache.overall_miss_latency::cpu.inst 58471000 # number of overall miss cycles 722system.cpu.l2cache.overall_miss_latency::cpu.data 1103092000 # number of overall miss cycles 723system.cpu.l2cache.overall_miss_latency::total 1161563000 # number of overall miss cycles |
726system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) 727system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) 728system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) 729system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) 730system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) 731system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) 732system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) 733system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 746system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses 747system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses 748system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966292 # miss rate for demand accesses 749system.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses 750system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses 751system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses 752system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses 753system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses | 724system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) 725system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) 726system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) 727system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) 728system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) 729system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) 730system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) 731system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 744system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses 745system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses 746system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966292 # miss rate for demand accesses 747system.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses 748system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses 749system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses 750system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses 751system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses |
754system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73475.866337 # average ReadExReq miss latency 755system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73475.866337 # average ReadExReq miss latency 756system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75111.757106 # average ReadCleanReq miss latency 757system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75111.757106 # average ReadCleanReq miss latency 758system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84749.049430 # average ReadSharedReq miss latency 759system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84749.049430 # average ReadSharedReq miss latency 760system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency 761system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency 762system.cpu.l2cache.demand_avg_miss_latency::total 73747.416725 # average overall miss latency 763system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency 764system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency 765system.cpu.l2cache.overall_avg_miss_latency::total 73747.416725 # average overall miss latency | 752system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74356.401265 # average ReadExReq miss latency 753system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74356.401265 # average ReadExReq miss latency 754system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75543.927649 # average ReadCleanReq miss latency 755system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75543.927649 # average ReadCleanReq miss latency 756system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82328.897338 # average ReadSharedReq miss latency 757system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82328.897338 # average ReadSharedReq miss latency 758system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency 759system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency 760system.cpu.l2cache.demand_avg_miss_latency::total 74549.964701 # average overall miss latency 761system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency 762system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency 763system.cpu.l2cache.overall_avg_miss_latency::total 74549.964701 # average overall miss latency |
766system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 767system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 768system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 769system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 770system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 771system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 772system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 773system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits --- 12 unchanged lines hidden (view full) --- 786system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses 787system.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses 788system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses 789system.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses 790system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 791system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses 792system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses 793system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses | 764system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 765system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 766system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 767system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 768system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 769system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 770system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 771system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits --- 12 unchanged lines hidden (view full) --- 784system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses 785system.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses 786system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses 787system.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses 788system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 789system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses 790system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses 791system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses |
794system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 923193000 # number of ReadExReq MSHR miss cycles 795system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 923193000 # number of ReadExReq MSHR miss cycles 796system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50340000 # number of ReadCleanReq MSHR miss cycles 797system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50340000 # number of ReadCleanReq MSHR miss cycles 798system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19328000 # number of ReadSharedReq MSHR miss cycles 799system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19328000 # number of ReadSharedReq MSHR miss cycles 800system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50340000 # number of demand (read+write) MSHR miss cycles 801system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 942521000 # number of demand (read+write) MSHR miss cycles 802system.cpu.l2cache.demand_mshr_miss_latency::total 992861000 # number of demand (read+write) MSHR miss cycles 803system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50340000 # number of overall MSHR miss cycles 804system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 942521000 # number of overall MSHR miss cycles 805system.cpu.l2cache.overall_mshr_miss_latency::total 992861000 # number of overall MSHR miss cycles | 792system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 935999500 # number of ReadExReq MSHR miss cycles 793system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 935999500 # number of ReadExReq MSHR miss cycles 794system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50673500 # number of ReadCleanReq MSHR miss cycles 795system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50673500 # number of ReadCleanReq MSHR miss cycles 796system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18685500 # number of ReadSharedReq MSHR miss cycles 797system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18685500 # number of ReadSharedReq MSHR miss cycles 798system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50673500 # number of demand (read+write) MSHR miss cycles 799system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 954685000 # number of demand (read+write) MSHR miss cycles 800system.cpu.l2cache.demand_mshr_miss_latency::total 1005358500 # number of demand (read+write) MSHR miss cycles 801system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50673500 # number of overall MSHR miss cycles 802system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 954685000 # number of overall MSHR miss cycles 803system.cpu.l2cache.overall_mshr_miss_latency::total 1005358500 # number of overall MSHR miss cycles |
806system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses 807system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses 808system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses 809system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses 810system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses 811system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses 812system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses 813system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses 814system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses 815system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses 816system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses 817system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses | 804system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses 805system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses 806system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses 807system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses 808system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses 809system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses 810system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses 811system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses 812system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses 813system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses 814system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses 815system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses |
818system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63475.866337 # average ReadExReq mshr miss latency 819system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63475.866337 # average ReadExReq mshr miss latency 820system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65122.897801 # average ReadCleanReq mshr miss latency 821system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65122.897801 # average ReadCleanReq mshr miss latency 822system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75206.225681 # average ReadSharedReq mshr miss latency 823system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75206.225681 # average ReadSharedReq mshr miss latency 824system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency 825system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency 826system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency 827system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency 828system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency 829system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency | 816system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64356.401265 # average ReadExReq mshr miss latency 817system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64356.401265 # average ReadExReq mshr miss latency 818system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65554.333765 # average ReadCleanReq mshr miss latency 819system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65554.333765 # average ReadCleanReq mshr miss latency 820system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72706.225681 # average ReadSharedReq mshr miss latency 821system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72706.225681 # average ReadSharedReq mshr miss latency 822system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency 823system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency 824system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency 825system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency 826system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency 827system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency |
830system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. 831system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. 832system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 833system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 834system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 835system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 828system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. 829system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. 830system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 831system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 832system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 833system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
836system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 834system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
837system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution 838system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution 839system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution 840system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution 841system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 842system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 843system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution 844system.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution --- 17 unchanged lines hidden (view full) --- 862system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 863system.cpu.toL2Bus.snoop_fanout::total 950998 # Request fanout histogram 864system.cpu.toL2Bus.reqLayer0.occupancy 1891839000 # Layer occupancy (ticks) 865system.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%) 866system.cpu.toL2Bus.respLayer0.occupancy 1201999 # Layer occupancy (ticks) 867system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 868system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) 869system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) | 835system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution 836system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution 837system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution 838system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution 839system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 840system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 841system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution 842system.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution --- 17 unchanged lines hidden (view full) --- 860system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 861system.cpu.toL2Bus.snoop_fanout::total 950998 # Request fanout histogram 862system.cpu.toL2Bus.reqLayer0.occupancy 1891839000 # Layer occupancy (ticks) 863system.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%) 864system.cpu.toL2Bus.respLayer0.occupancy 1201999 # Layer occupancy (ticks) 865system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 866system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) 867system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) |
870system.membus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states | 868system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter. 869system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 870system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 871system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 872system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 873system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 874system.membus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states |
871system.membus.trans_dist::ReadResp 1030 # Transaction distribution 872system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 873system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 874system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution 875system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) 876system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) 877system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) 878system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 883system.membus.snoop_fanout::stdev 0 # Request fanout histogram 884system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 885system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 886system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 887system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 888system.membus.snoop_fanout::min_value 0 # Request fanout histogram 889system.membus.snoop_fanout::max_value 0 # Request fanout histogram 890system.membus.snoop_fanout::total 15574 # Request fanout histogram | 875system.membus.trans_dist::ReadResp 1030 # Transaction distribution 876system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 877system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 878system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution 879system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) 880system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) 881system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) 882system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 887system.membus.snoop_fanout::stdev 0 # Request fanout histogram 888system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 889system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 890system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 891system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 892system.membus.snoop_fanout::min_value 0 # Request fanout histogram 893system.membus.snoop_fanout::max_value 0 # Request fanout histogram 894system.membus.snoop_fanout::total 15574 # Request fanout histogram |
891system.membus.reqLayer0.occupancy 21833000 # Layer occupancy (ticks) | 895system.membus.reqLayer0.occupancy 21795000 # Layer occupancy (ticks) |
892system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 896system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
893system.membus.respLayer1.occupancy 82137750 # Layer occupancy (ticks) | 897system.membus.respLayer1.occupancy 82138750 # Layer occupancy (ticks) |
894system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 895 896---------- End Simulation Statistics ---------- | 898system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 899 900---------- End Simulation Statistics ---------- |