Cross Reference: /gem5/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt

stats.txt (11507:be6065c1d8d2)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061235 # Number of seconds simulated 4sim_ticks 61234797500 # Number of ticks simulated 5final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061235 # Number of seconds simulated 4sim_ticks 61234797500 # Number of ticks simulated 5final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 196562 # Simulator instruction rate (inst/s) 8host_op_rate 197541 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 132848546 # Simulator tick rate (ticks/s) 10host_mem_usage 399976 # Number of bytes of host memory used 11host_seconds 460.94 # Real time elapsed on the host	7host_inst_rate 433531 # Simulator instruction rate (inst/s) 8host_op_rate 435690 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 293005809 # Simulator tick rate (ticks/s) 10host_mem_usage 447448 # Number of bytes of host memory used 11host_seconds 208.99 # Real time elapsed on the host
12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory 18system.physmem.bytes_read::total 996672 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ) 247system.physmem_1.averagePower 671.499745 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states	17system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory 19system.physmem.bytes_read::total 996672 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 246system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ) 248system.physmem_1.averagePower 671.499745 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states 250system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
	254system.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
253system.cpu.branchPred.lookups 20750031 # Number of BP lookups 254system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks	255system.cpu.branchPred.lookups 20750031 # Number of BP lookups 256system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks
	269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
296system.cpu.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses	300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses
	329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
354system.cpu.itb.walker.walks 0 # Table walker walks requested 355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 442 # Number of system calls	360system.cpu.itb.walker.walks 0 # Table walker walks requested 361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.itb.read_accesses 0 # DTB read accesses 384system.cpu.itb.write_accesses 0 # DTB write accesses 385system.cpu.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.itb.hits 0 # DTB hits 387system.cpu.itb.misses 0 # DTB misses 388system.cpu.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 442 # Number of system calls
	390system.cpu.pwrStateResidencyTicks::ON 61234797500 # Cumulative time (in ticks) in various power states
384system.cpu.numCycles 122469595 # number of cpu cycles simulated 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 387system.cpu.committedInsts 90602850 # Number of instructions committed 388system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed 389system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit 390system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 391system.cpu.cpi 1.351719 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 422system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 423system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 424system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 425system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 426system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 427system.cpu.op_class_0::total 91054081 # Class of committed instruction 428system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked 429system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped	391system.cpu.numCycles 122469595 # number of cpu cycles simulated 392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.committedInsts 90602850 # Number of instructions committed 395system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed 396system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit 397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 398system.cpu.cpi 1.351719 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 429system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 430system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 431system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 434system.cpu.op_class_0::total 91054081 # Class of committed instruction 435system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked 436system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped
	437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
430system.cpu.dcache.tags.replacements 946097 # number of replacements 431system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use 432system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks. 433system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. 434system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks. 435system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit. 436system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor 437system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy 438system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy 439system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 440system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id 441system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id 442system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id 443system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 444system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses 445system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses	438system.cpu.dcache.tags.replacements 946097 # number of replacements 439system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use 440system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks. 441system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. 442system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks. 443system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit. 444system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy 447system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id 449system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id 450system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id 451system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 452system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses 453system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses
	454system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
446system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits 447system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits 448system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits 449system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits 450system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 451system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 452system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 453system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 558system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency 559system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency 560system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency 561system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency 562system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency 563system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency 564system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency 565system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency	455system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits 456system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits 457system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits 458system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits 459system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 460system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 461system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 462system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 567system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency 568system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency 569system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency 570system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency 571system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency 572system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency 573system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency 574system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency
	575system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
566system.cpu.icache.tags.replacements 5 # number of replacements 567system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use 568system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks. 569system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. 570system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks. 571system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 572system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor 573system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy 574system.cpu.icache.tags.occ_percent::total 0.336476 # Average percentage of cache occupancy 575system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id 576system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 577system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 578system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 579system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 580system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id 581system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses 582system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses	576system.cpu.icache.tags.replacements 5 # number of replacements 577system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use 578system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks. 579system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. 580system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks. 581system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 582system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor 583system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy 584system.cpu.icache.tags.occ_percent::total 0.336476 # Average percentage of cache occupancy 585system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id 586system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 587system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 588system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 590system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id 591system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses 592system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses
	593system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
583system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits 584system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits 585system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits 586system.cpu.icache.demand_hits::total 27766889 # number of demand (read+write) hits 587system.cpu.icache.overall_hits::cpu.inst 27766889 # number of overall hits 588system.cpu.icache.overall_hits::total 27766889 # number of overall hits 589system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses 590system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 643system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 644system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency 646system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency 648system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency 650system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency	594system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits 595system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits 596system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits 597system.cpu.icache.demand_hits::total 27766889 # number of demand (read+write) hits 598system.cpu.icache.overall_hits::cpu.inst 27766889 # number of overall hits 599system.cpu.icache.overall_hits::total 27766889 # number of overall hits 600system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses 601system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 654system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 655system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses 656system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency 657system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency 658system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency 659system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency 660system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency 661system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
	662system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
651system.cpu.l2cache.tags.replacements 0 # number of replacements 652system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use 653system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks. 654system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks. 655system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks. 656system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 657system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor 658system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 665system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 666system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 667system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id 668system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1096 # Occupied blocks per task id 669system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id 670system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id 671system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses 672system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses	663system.cpu.l2cache.tags.replacements 0 # number of replacements 664system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use 665system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks. 666system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks. 667system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks. 668system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 669system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor 670system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 677system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 678system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 679system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id 680system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1096 # Occupied blocks per task id 681system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id 682system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id 683system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses 684system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses
	685system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
673system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits 674system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits 675system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 676system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits 677system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 678system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 679system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits 680system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits --- 134 unchanged lines hidden (view full) --- 815system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency 816system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency 817system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter. 818system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. 819system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 820system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 821system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 822system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	686system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits 687system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits 688system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 689system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits 690system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 691system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 692system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits 693system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits --- 134 unchanged lines hidden (view full) --- 828system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency 829system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency 830system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter. 831system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. 832system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 833system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 834system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 835system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	836system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
823system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution 824system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution 825system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution 826system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution 827system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 828system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 829system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution 830system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 847system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 848system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram 849system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks) 850system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) 851system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks) 852system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 853system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) 854system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)	837system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution 838system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution 839system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution 840system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution 841system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 842system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 843system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution 844system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 861system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 862system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram 863system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks) 864system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) 865system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks) 866system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 867system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) 868system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
	869system.membus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
855system.membus.trans_dist::ReadResp 1029 # Transaction distribution 856system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 857system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 858system.membus.trans_dist::ReadSharedReq 1029 # Transaction distribution 859system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31146 # Packet count per connected master and slave (bytes) 860system.membus.pkt_count::total 31146 # Packet count per connected master and slave (bytes) 861system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996672 # Cumulative packet size per connected master and slave (bytes) 862system.membus.pkt_size::total 996672 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden ---	870system.membus.trans_dist::ReadResp 1029 # Transaction distribution 871system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 872system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 873system.membus.trans_dist::ReadSharedReq 1029 # Transaction distribution 874system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31146 # Packet count per connected master and slave (bytes) 875system.membus.pkt_count::total 31146 # Packet count per connected master and slave (bytes) 876system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996672 # Cumulative packet size per connected master and slave (bytes) 877system.membus.pkt_size::total 996672 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.061235 # Number of seconds simulated
4sim_ticks 61234797500 # Number of ticks simulated
5final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 196562 # Simulator instruction rate (inst/s)
8host_op_rate 197541 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 132848546 # Simulator tick rate (ticks/s)
10host_mem_usage 399976 # Number of bytes of host memory used
11host_seconds 460.94 # Real time elapsed on the host

7host_inst_rate 433531 # Simulator instruction rate (inst/s)
8host_op_rate 435690 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 293005809 # Simulator tick rate (ticks/s)
10host_mem_usage 447448 # Number of bytes of host memory used
11host_seconds 208.99 # Real time elapsed on the host

12sim_insts 90602850 # Number of instructions simulated
13sim_ops 91054081 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
18system.physmem.bytes_read::total 996672 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory

--- 221 unchanged lines hidden (view full) ---

245system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ)
247system.physmem_1.averagePower 671.499745 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states
249system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

17system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
19system.physmem.bytes_read::total 996672 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory

--- 221 unchanged lines hidden (view full) ---

246system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ)
247system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ)
248system.physmem_1.averagePower 671.499745 # Core power per rank (mW)
249system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states
250system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states
251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
252system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states
253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

254system.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

253system.cpu.branchPred.lookups 20750031 # Number of BP lookups
254system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
262system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups.
263system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits.
264system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses.
265system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches.
266system.cpu_clk_domain.clock 500 # Clock period in ticks

255system.cpu.branchPred.lookups 20750031 # Number of BP lookups
256system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted
257system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect
258system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups
259system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits
260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
261system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage
262system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target.
263system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
264system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups.
265system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits.
266system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses.
267system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches.
268system.cpu_clk_domain.clock 500 # Clock period in ticks

269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

296system.cpu.dtb.walker.walks 0 # Table walker walks requested
297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
319system.cpu.dtb.read_accesses 0 # DTB read accesses
320system.cpu.dtb.write_accesses 0 # DTB write accesses
321system.cpu.dtb.inst_accesses 0 # ITB inst accesses
322system.cpu.dtb.hits 0 # DTB hits
323system.cpu.dtb.misses 0 # DTB misses
324system.cpu.dtb.accesses 0 # DTB accesses

300system.cpu.dtb.walker.walks 0 # Table walker walks requested
301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
323system.cpu.dtb.read_accesses 0 # DTB read accesses
324system.cpu.dtb.write_accesses 0 # DTB write accesses
325system.cpu.dtb.inst_accesses 0 # ITB inst accesses
326system.cpu.dtb.hits 0 # DTB hits
327system.cpu.dtb.misses 0 # DTB misses
328system.cpu.dtb.accesses 0 # DTB accesses

329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

354system.cpu.itb.walker.walks 0 # Table walker walks requested
355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
377system.cpu.itb.read_accesses 0 # DTB read accesses
378system.cpu.itb.write_accesses 0 # DTB write accesses
379system.cpu.itb.inst_accesses 0 # ITB inst accesses
380system.cpu.itb.hits 0 # DTB hits
381system.cpu.itb.misses 0 # DTB misses
382system.cpu.itb.accesses 0 # DTB accesses
383system.cpu.workload.num_syscalls 442 # Number of system calls

360system.cpu.itb.walker.walks 0 # Table walker walks requested
361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
383system.cpu.itb.read_accesses 0 # DTB read accesses
384system.cpu.itb.write_accesses 0 # DTB write accesses
385system.cpu.itb.inst_accesses 0 # ITB inst accesses
386system.cpu.itb.hits 0 # DTB hits
387system.cpu.itb.misses 0 # DTB misses
388system.cpu.itb.accesses 0 # DTB accesses
389system.cpu.workload.num_syscalls 442 # Number of system calls

390system.cpu.pwrStateResidencyTicks::ON 61234797500 # Cumulative time (in ticks) in various power states

384system.cpu.numCycles 122469595 # number of cpu cycles simulated
385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
387system.cpu.committedInsts 90602850 # Number of instructions committed
388system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
389system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit
390system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
391system.cpu.cpi 1.351719 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

422system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
423system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
424system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
425system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
426system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
427system.cpu.op_class_0::total 91054081 # Class of committed instruction
428system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked
429system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped

391system.cpu.numCycles 122469595 # number of cpu cycles simulated
392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
394system.cpu.committedInsts 90602850 # Number of instructions committed
395system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
396system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit
397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
398system.cpu.cpi 1.351719 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

429system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
430system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
431system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
434system.cpu.op_class_0::total 91054081 # Class of committed instruction
435system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked
436system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped

437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

430system.cpu.dcache.tags.replacements 946097 # number of replacements
431system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use
432system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks.
433system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks.
434system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks.
435system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit.
436system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor
437system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy
438system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy
439system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
440system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
441system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id
442system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id
443system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
444system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses
445system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses

438system.cpu.dcache.tags.replacements 946097 # number of replacements
439system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use
440system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks.
441system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks.
442system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks.
443system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit.
444system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor
445system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy
446system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy
447system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
448system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
449system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id
450system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id
451system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
452system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses
453system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses

454system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

446system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits
447system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits
448system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits
449system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits
450system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
451system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
452system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
453system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

558system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency
559system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency
560system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency
561system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency
562system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency
563system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency
564system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency
565system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency

455system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits
456system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits
457system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits
458system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits
459system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
460system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
461system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
462system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

567system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency
568system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency
569system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency
570system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency
571system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency
572system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency
573system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency
574system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency

575system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

566system.cpu.icache.tags.replacements 5 # number of replacements
567system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use
568system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks.
569system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks.
570system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks.
571system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
572system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor
573system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy
574system.cpu.icache.tags.occ_percent::total 0.336476 # Average percentage of cache occupancy
575system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id
576system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
577system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
578system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
579system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id
580system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id
581system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses
582system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses

576system.cpu.icache.tags.replacements 5 # number of replacements
577system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use
578system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks.
579system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks.
580system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks.
581system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
582system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor
583system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy
584system.cpu.icache.tags.occ_percent::total 0.336476 # Average percentage of cache occupancy
585system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id
586system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
587system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
588system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
589system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id
590system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id
591system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses
592system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses

593system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

583system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits
584system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits
585system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits
586system.cpu.icache.demand_hits::total 27766889 # number of demand (read+write) hits
587system.cpu.icache.overall_hits::cpu.inst 27766889 # number of overall hits
588system.cpu.icache.overall_hits::total 27766889 # number of overall hits
589system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses
590system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

643system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
644system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
645system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency
646system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency
647system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
648system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
649system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
650system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency

594system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits
595system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits
596system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits
597system.cpu.icache.demand_hits::total 27766889 # number of demand (read+write) hits
598system.cpu.icache.overall_hits::cpu.inst 27766889 # number of overall hits
599system.cpu.icache.overall_hits::total 27766889 # number of overall hits
600system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses
601system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

654system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
655system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
656system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency
657system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency
658system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
659system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
660system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
661system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency

662system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

651system.cpu.l2cache.tags.replacements 0 # number of replacements
652system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use
653system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks.
654system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks.
655system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks.
656system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
657system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor
658system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

665system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
666system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
667system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
668system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1096 # Occupied blocks per task id
669system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id
670system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id
671system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses
672system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses

663system.cpu.l2cache.tags.replacements 0 # number of replacements
664system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use
665system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks.
666system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks.
667system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks.
668system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
669system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor
670system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

677system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
678system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
679system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
680system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1096 # Occupied blocks per task id
681system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id
682system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id
683system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses
684system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses

685system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

673system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits
674system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits
675system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits
676system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits
677system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits
678system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits
679system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits
680system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits

--- 134 unchanged lines hidden (view full) ---

815system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
816system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
817system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter.
818system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
819system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
820system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
821system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
822system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

686system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits
687system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits
688system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits
689system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits
690system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits
691system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits
692system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits
693system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits

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828system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
829system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
830system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter.
831system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
832system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
833system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
834system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
835system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

836system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states

823system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
824system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution
825system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
826system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution
827system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
828system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
829system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution
830system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution

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847system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
848system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram
849system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks)
850system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
851system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks)
852system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
853system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks)
854system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)

837system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
838system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution
839system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
840system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution
841system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
842system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
843system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution
844system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution

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861system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
862system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram
863system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks)
864system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
865system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks)
866system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
867system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks)
868system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)

869system.membus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states