stats.txt (11441:0edcf757b6a2) stats.txt (11456:c0fb4435b80f)
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.061235 # Number of seconds simulated
4sim_ticks 61234797500 # Number of ticks simulated
5final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.061235 # Number of seconds simulated
4sim_ticks 61234797500 # Number of ticks simulated
5final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 274685 # Simulator instruction rate (inst/s)
8host_op_rate 276053 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 185648704 # Simulator tick rate (ticks/s)
10host_mem_usage 404860 # Number of bytes of host memory used
11host_seconds 329.84 # Real time elapsed on the host
7host_inst_rate 283902 # Simulator instruction rate (inst/s)
8host_op_rate 285316 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 191877896 # Simulator tick rate (ticks/s)
10host_mem_usage 404856 # Number of bytes of host memory used
11host_seconds 319.13 # Real time elapsed on the host
12sim_insts 90602850 # Number of instructions simulated
13sim_ops 91054081 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
18system.physmem.bytes_read::total 996672 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory

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508system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294 # average overall miss latency
509system.cpu.dcache.overall_avg_miss_latency::total 14616.621294 # average overall miss latency
510system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
511system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
512system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
513system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
514system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
515system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
12sim_insts 90602850 # Number of instructions simulated
13sim_ops 91054081 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
18system.physmem.bytes_read::total 996672 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory

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508system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294 # average overall miss latency
509system.cpu.dcache.overall_avg_miss_latency::total 14616.621294 # average overall miss latency
510system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
511system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
512system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
513system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
514system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
515system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
516system.cpu.dcache.fast_writes 0 # number of fast writes performed
517system.cpu.dcache.cache_copies 0 # number of cache copies performed
518system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks
519system.cpu.dcache.writebacks::total 943278 # number of writebacks
520system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11500 # number of ReadReq MSHR hits
521system.cpu.dcache.ReadReq_mshr_hits::total 11500 # number of ReadReq MSHR hits
522system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27525 # number of WriteReq MSHR hits
523system.cpu.dcache.WriteReq_mshr_hits::total 27525 # number of WriteReq MSHR hits
524system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits
525system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits

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560system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency
561system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency
562system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency
563system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency
564system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency
565system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency
566system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency
567system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency
516system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks
517system.cpu.dcache.writebacks::total 943278 # number of writebacks
518system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11500 # number of ReadReq MSHR hits
519system.cpu.dcache.ReadReq_mshr_hits::total 11500 # number of ReadReq MSHR hits
520system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27525 # number of WriteReq MSHR hits
521system.cpu.dcache.WriteReq_mshr_hits::total 27525 # number of WriteReq MSHR hits
522system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits
523system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits

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558system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency
559system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency
560system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency
561system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency
562system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency
563system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency
564system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency
565system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency
568system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
569system.cpu.icache.tags.replacements 5 # number of replacements
570system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use
571system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks.
572system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks.
573system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks.
574system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
575system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor
576system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy

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620system.cpu.icache.overall_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency
621system.cpu.icache.overall_avg_miss_latency::total 75191.011236 # average overall miss latency
622system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
623system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
624system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
625system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
626system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
627system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
566system.cpu.icache.tags.replacements 5 # number of replacements
567system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use
568system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks.
569system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks.
570system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks.
571system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
572system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor
573system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy

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617system.cpu.icache.overall_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency
618system.cpu.icache.overall_avg_miss_latency::total 75191.011236 # average overall miss latency
619system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
620system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
621system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
622system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
623system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
624system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
628system.cpu.icache.fast_writes 0 # number of fast writes performed
629system.cpu.icache.cache_copies 0 # number of cache copies performed
630system.cpu.icache.writebacks::writebacks 5 # number of writebacks
631system.cpu.icache.writebacks::total 5 # number of writebacks
632system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
633system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
634system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses
635system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
636system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
637system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses

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648system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
649system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
650system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency
651system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency
652system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
653system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
654system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
655system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
625system.cpu.icache.writebacks::writebacks 5 # number of writebacks
626system.cpu.icache.writebacks::total 5 # number of writebacks
627system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
628system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
629system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses
630system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
631system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
632system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses

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643system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
644system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
645system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency
646system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency
647system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
648system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
649system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
650system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
656system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
657system.cpu.l2cache.tags.replacements 0 # number of replacements
658system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use
659system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks.
660system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks.
661system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks.
662system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
663system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor
664system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor

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757system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency
758system.cpu.l2cache.overall_avg_miss_latency::total 73580.225916 # average overall miss latency
759system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
760system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
761system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
762system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
763system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
764system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
651system.cpu.l2cache.tags.replacements 0 # number of replacements
652system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use
653system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks.
654system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks.
655system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks.
656system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
657system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor
658system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor

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751system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency
752system.cpu.l2cache.overall_avg_miss_latency::total 73580.225916 # average overall miss latency
753system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
754system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
755system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
756system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
757system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
758system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
765system.cpu.l2cache.fast_writes 0 # number of fast writes performed
766system.cpu.l2cache.cache_copies 0 # number of cache copies performed
767system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
768system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
769system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
770system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
771system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
772system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
773system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
774system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits

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817system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125 # average ReadSharedReq mshr miss latency
818system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125 # average ReadSharedReq mshr miss latency
819system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
820system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
821system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
822system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
823system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
824system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
759system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
760system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
761system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
762system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
763system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
764system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
765system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
766system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits

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809system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125 # average ReadSharedReq mshr miss latency
810system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125 # average ReadSharedReq mshr miss latency
811system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
812system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
813system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
814system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
815system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
816system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
825system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
826system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter.
827system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
828system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
829system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
830system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
831system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
832system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
833system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution

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817system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter.
818system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
819system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
820system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
821system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
822system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
823system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
824system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution

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