| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061241 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061241 # Number of seconds simulated |
| 4sim_ticks 61240850500 # Number of ticks simulated 5final_tick 61240850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 61241011500 # Number of ticks simulated 5final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 182783 # Simulator instruction rate (inst/s) 8host_op_rate 183693 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 123547949 # Simulator tick rate (ticks/s) 10host_mem_usage 442472 # Number of bytes of host memory used 11host_seconds 495.69 # Real time elapsed on the host | 7host_inst_rate 252391 # Simulator instruction rate (inst/s) 8host_op_rate 253648 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 170598134 # Simulator tick rate (ticks/s) 10host_mem_usage 450980 # Number of bytes of host memory used 11host_seconds 358.98 # Real time elapsed on the host |
| 12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory 18system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory | 12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory 18system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 808872 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 15466800 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 16275672 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 808872 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 808872 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 808872 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 15466800 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 16275672 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 808870 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 15466760 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 16275629 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 808870 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 808870 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 808870 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 15466760 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 16275629 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 15574 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 15574 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 61240757000 # Total gap between requests | 78system.physmem.totGap 61240917000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 15574 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 15574 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 644.601036 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 438.502120 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 402.393837 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 247 16.00% 16.00% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 189 12.24% 28.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 92 5.96% 34.20% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 68 4.40% 38.60% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 69 4.47% 43.07% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 87 5.63% 48.70% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 40 2.59% 51.30% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 47 3.04% 54.34% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 705 45.66% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation 203system.physmem.totQLat 73458500 # Total ticks spent queuing 204system.physmem.totMemAccLat 365471000 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 1543 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 644.935839 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 438.870546 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 402.302511 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 247 16.01% 16.01% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 187 12.12% 28.13% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 93 6.03% 34.15% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 68 4.41% 38.56% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 69 4.47% 43.03% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 87 5.64% 48.67% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation 203system.physmem.totQLat 73241750 # Total ticks spent queuing 204system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 4716.74 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 23466.74 # Average memory access latency per DRAM burst | 208system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst |
| 209system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.13 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 14026 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 90.06 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 209system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.13 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 14026 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 90.06 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 3932243.29 # Average gap between requests | 223system.physmem.avgGap 3932253.56 # Average gap between requests |
| 224system.physmem.pageHitRate 90.06 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 6305040 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 3440250 # Energy for precharge commands per rank (pJ) | 224system.physmem.pageHitRate 90.06 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 6305040 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 3440250 # Energy for precharge commands per rank (pJ) |
| 227system.physmem_0.readEnergy 63780600 # Energy for read commands per rank (pJ) | 227system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) |
| 230system.physmem_0.actBackEnergy 2494978920 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 34554891750 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 41123220960 # Total energy per rank (pJ) 233system.physmem_0.averagePower 671.518851 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 57475186750 # Time in different power states | 230system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ) 233system.physmem_0.averagePower 671.511702 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states |
| 235system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 235system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 1719043250 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 239system.physmem_1.actEnergy 5367600 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2928750 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ) | 239system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) |
| 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) | 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) |
| 244system.physmem_1.actBackEnergy 2555622360 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 34501695750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 41122956060 # Total energy per rank (pJ) 247system.physmem_1.averagePower 671.514525 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 57387265750 # Time in different power states | 244system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ) 247system.physmem_1.averagePower 671.513254 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states |
| 249system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 249system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 1807269750 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 20752188 # Number of BP lookups 254system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 757746 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 8939036 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 8856390 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 99.075448 # BTB Hit Percentage --- 112 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 442 # Number of system calls | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 20752188 # Number of BP lookups 254system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 757746 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 8939036 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 8856390 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 99.075448 # BTB Hit Percentage --- 112 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 442 # Number of system calls |
| 380system.cpu.numCycles 122481701 # number of cpu cycles simulated | 380system.cpu.numCycles 122482023 # number of cpu cycles simulated |
| 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 90602850 # Number of instructions committed 384system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed | 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 90602850 # Number of instructions committed 384system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed |
| 385system.cpu.discardedOps 2176622 # Number of ops (including micro ops) which were discarded before commit | 385system.cpu.discardedOps 2176623 # Number of ops (including micro ops) which were discarded before commit |
| 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 387system.cpu.cpi 1.351853 # CPI: cycles per instruction 388system.cpu.ipc 0.739726 # IPC: instructions per cycle 389system.cpu.tickCycles 109255125 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 13226576 # Total number of cycles that the object has spent stopped | 387system.cpu.cpi 1.351856 # CPI: cycles per instruction 388system.cpu.ipc 0.739724 # IPC: instructions per cycle 389system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped |
| 391system.cpu.dcache.tags.replacements 946097 # number of replacements | 391system.cpu.dcache.tags.replacements 946097 # number of replacements |
| 392system.cpu.dcache.tags.tagsinuse 3616.871508 # Cycle average of tags in use | 392system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use |
| 393system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. 394system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. 395system.cpu.dcache.tags.avg_refs 27.639841 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 20511562500 # Cycle when the warmup percentage was hit. | 393system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. 394system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. 395system.cpu.dcache.tags.avg_refs 27.639841 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 20511562500 # Cycle when the warmup percentage was hit. |
| 397system.cpu.dcache.tags.occ_blocks::cpu.data 3616.871508 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.883025 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.883025 # Average percentage of cache occupancy | 397system.cpu.dcache.tags.occ_blocks::cpu.data 3616.872758 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.883026 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.883026 # Average percentage of cache occupancy |
| 400system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 400system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 2246 # Occupied blocks per task id | 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id |
| 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id 404system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 405system.cpu.dcache.tags.tag_accesses 55455001 # Number of tag accesses 406system.cpu.dcache.tags.data_accesses 55455001 # Number of data accesses 407system.cpu.dcache.ReadReq_hits::cpu.data 21594211 # number of ReadReq hits 408system.cpu.dcache.ReadReq_hits::total 21594211 # number of ReadReq hits 409system.cpu.dcache.WriteReq_hits::cpu.data 4660690 # number of WriteReq hits 410system.cpu.dcache.WriteReq_hits::total 4660690 # number of WriteReq hits --- 12 unchanged lines hidden (view full) --- 423system.cpu.dcache.WriteReq_misses::cpu.data 74291 # number of WriteReq misses 424system.cpu.dcache.WriteReq_misses::total 74291 # number of WriteReq misses 425system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 426system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses 427system.cpu.dcache.demand_misses::cpu.data 989217 # number of demand (read+write) misses 428system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses 429system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses 430system.cpu.dcache.overall_misses::total 989221 # number of overall misses | 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id 404system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 405system.cpu.dcache.tags.tag_accesses 55455001 # Number of tag accesses 406system.cpu.dcache.tags.data_accesses 55455001 # Number of data accesses 407system.cpu.dcache.ReadReq_hits::cpu.data 21594211 # number of ReadReq hits 408system.cpu.dcache.ReadReq_hits::total 21594211 # number of ReadReq hits 409system.cpu.dcache.WriteReq_hits::cpu.data 4660690 # number of WriteReq hits 410system.cpu.dcache.WriteReq_hits::total 4660690 # number of WriteReq hits --- 12 unchanged lines hidden (view full) --- 423system.cpu.dcache.WriteReq_misses::cpu.data 74291 # number of WriteReq misses 424system.cpu.dcache.WriteReq_misses::total 74291 # number of WriteReq misses 425system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 426system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses 427system.cpu.dcache.demand_misses::cpu.data 989217 # number of demand (read+write) misses 428system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses 429system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses 430system.cpu.dcache.overall_misses::total 989221 # number of overall misses |
| 431system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918942500 # number of ReadReq miss cycles 432system.cpu.dcache.ReadReq_miss_latency::total 11918942500 # number of ReadReq miss cycles 433system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542548000 # number of WriteReq miss cycles 434system.cpu.dcache.WriteReq_miss_latency::total 2542548000 # number of WriteReq miss cycles 435system.cpu.dcache.demand_miss_latency::cpu.data 14461490500 # number of demand (read+write) miss cycles 436system.cpu.dcache.demand_miss_latency::total 14461490500 # number of demand (read+write) miss cycles 437system.cpu.dcache.overall_miss_latency::cpu.data 14461490500 # number of overall miss cycles 438system.cpu.dcache.overall_miss_latency::total 14461490500 # number of overall miss cycles | 431system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles 432system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles 433system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles 434system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles 435system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles 436system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles 437system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles 438system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles |
| 439system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) 440system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) 441system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 442system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 443system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 444system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 445system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 446system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 455system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015690 # miss rate for WriteReq accesses 456system.cpu.dcache.WriteReq_miss_rate::total 0.015690 # miss rate for WriteReq accesses 457system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 458system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses 459system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 # miss rate for demand accesses 460system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses 461system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses 462system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses | 439system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) 440system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) 441system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 442system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 443system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 444system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 445system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 446system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 455system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015690 # miss rate for WriteReq accesses 456system.cpu.dcache.WriteReq_miss_rate::total 0.015690 # miss rate for WriteReq accesses 457system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 458system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses 459system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 # miss rate for demand accesses 460system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses 461system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses 462system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses |
| 463system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.220234 # average ReadReq miss latency 464system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.220234 # average ReadReq miss latency 465system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34224.172511 # average WriteReq miss latency 466system.cpu.dcache.WriteReq_avg_miss_latency::total 34224.172511 # average WriteReq miss latency 467system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.128563 # average overall miss latency 468system.cpu.dcache.demand_avg_miss_latency::total 14619.128563 # average overall miss latency 469system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.069450 # average overall miss latency 470system.cpu.dcache.overall_avg_miss_latency::total 14619.069450 # average overall miss latency | 463system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency 464system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency 465system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency 466system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency 467system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency 468system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency 469system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency 470system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency |
| 471system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 472system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 473system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 476system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 477system.cpu.dcache.fast_writes 0 # number of fast writes performed 478system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 491system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46765 # number of WriteReq MSHR misses 492system.cpu.dcache.WriteReq_mshr_misses::total 46765 # number of WriteReq MSHR misses 493system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 494system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 495system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses 496system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses 497system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses 498system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses | 471system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 472system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 473system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 476system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 477system.cpu.dcache.fast_writes 0 # number of fast writes performed 478system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 491system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46765 # number of WriteReq MSHR misses 492system.cpu.dcache.WriteReq_mshr_misses::total 46765 # number of WriteReq MSHR misses 493system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 494system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 495system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses 496system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses 497system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses 498system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses |
| 499system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865257500 # number of ReadReq MSHR miss cycles 500system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865257500 # number of ReadReq MSHR miss cycles 501system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481584500 # number of WriteReq MSHR miss cycles 502system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481584500 # number of WriteReq MSHR miss cycles | 499system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles 500system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles 501system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles 502system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles |
| 503system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles 504system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles | 503system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles 504system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles |
| 505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346842000 # number of demand (read+write) MSHR miss cycles 506system.cpu.dcache.demand_mshr_miss_latency::total 12346842000 # number of demand (read+write) MSHR miss cycles 507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346998500 # number of overall MSHR miss cycles 508system.cpu.dcache.overall_mshr_miss_latency::total 12346998500 # number of overall MSHR miss cycles | 505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles 506system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles 507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles 508system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles |
| 509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses 510system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses 511system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 512system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 513system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 514system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 515system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for demand accesses 516system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses 517system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses 518system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses | 509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses 510system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses 511system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 512system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 513system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 514system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 515system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for demand accesses 516system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses 517system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses 518system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses |
| 519system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.739906 # average ReadReq mshr miss latency 520system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.739906 # average ReadReq mshr miss latency 521system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31681.481877 # average WriteReq mshr miss latency 522system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31681.481877 # average WriteReq mshr miss latency | 519system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency 520system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency 521system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency 522system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency |
| 523system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency 524system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency | 523system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency 524system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency |
| 525system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.076974 # average overall mshr miss latency 526system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.076974 # average overall mshr miss latency 527system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.200652 # average overall mshr miss latency 528system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.200652 # average overall mshr miss latency | 525system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency 526system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency 527system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency 528system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency |
| 529system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 530system.cpu.icache.tags.replacements 5 # number of replacements | 529system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 530system.cpu.icache.tags.replacements 5 # number of replacements |
| 531system.cpu.icache.tags.tagsinuse 689.439690 # Cycle average of tags in use 532system.cpu.icache.tags.total_refs 27770466 # Total number of references to valid blocks. | 531system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use 532system.cpu.icache.tags.total_refs 27770468 # Total number of references to valid blocks. |
| 533system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. | 533system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. |
| 534system.cpu.icache.tags.avg_refs 34626.516209 # Average number of references to valid blocks. | 534system.cpu.icache.tags.avg_refs 34626.518703 # Average number of references to valid blocks. |
| 535system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 535system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 536system.cpu.icache.tags.occ_blocks::cpu.inst 689.439690 # Average occupied blocks per requestor 537system.cpu.icache.tags.occ_percent::cpu.inst 0.336640 # Average percentage of cache occupancy 538system.cpu.icache.tags.occ_percent::total 0.336640 # Average percentage of cache occupancy | 536system.cpu.icache.tags.occ_blocks::cpu.inst 689.439811 # Average occupied blocks per requestor 537system.cpu.icache.tags.occ_percent::cpu.inst 0.336641 # Average percentage of cache occupancy 538system.cpu.icache.tags.occ_percent::total 0.336641 # Average percentage of cache occupancy |
| 539system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id 540system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 541system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 543system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id | 539system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id 540system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 541system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 543system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id |
| 544system.cpu.icache.tags.tag_accesses 55543338 # Number of tag accesses 545system.cpu.icache.tags.data_accesses 55543338 # Number of data accesses 546system.cpu.icache.ReadReq_hits::cpu.inst 27770466 # number of ReadReq hits 547system.cpu.icache.ReadReq_hits::total 27770466 # number of ReadReq hits 548system.cpu.icache.demand_hits::cpu.inst 27770466 # number of demand (read+write) hits 549system.cpu.icache.demand_hits::total 27770466 # number of demand (read+write) hits 550system.cpu.icache.overall_hits::cpu.inst 27770466 # number of overall hits 551system.cpu.icache.overall_hits::total 27770466 # number of overall hits | 544system.cpu.icache.tags.tag_accesses 55543342 # Number of tag accesses 545system.cpu.icache.tags.data_accesses 55543342 # Number of data accesses 546system.cpu.icache.ReadReq_hits::cpu.inst 27770468 # number of ReadReq hits 547system.cpu.icache.ReadReq_hits::total 27770468 # number of ReadReq hits 548system.cpu.icache.demand_hits::cpu.inst 27770468 # number of demand (read+write) hits 549system.cpu.icache.demand_hits::total 27770468 # number of demand (read+write) hits 550system.cpu.icache.overall_hits::cpu.inst 27770468 # number of overall hits 551system.cpu.icache.overall_hits::total 27770468 # number of overall hits |
| 552system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses 553system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses 554system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses 555system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses 556system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses 557system.cpu.icache.overall_misses::total 802 # number of overall misses | 552system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses 553system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses 554system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses 555system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses 556system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses 557system.cpu.icache.overall_misses::total 802 # number of overall misses |
| 558system.cpu.icache.ReadReq_miss_latency::cpu.inst 60107000 # number of ReadReq miss cycles 559system.cpu.icache.ReadReq_miss_latency::total 60107000 # number of ReadReq miss cycles 560system.cpu.icache.demand_miss_latency::cpu.inst 60107000 # number of demand (read+write) miss cycles 561system.cpu.icache.demand_miss_latency::total 60107000 # number of demand (read+write) miss cycles 562system.cpu.icache.overall_miss_latency::cpu.inst 60107000 # number of overall miss cycles 563system.cpu.icache.overall_miss_latency::total 60107000 # number of overall miss cycles 564system.cpu.icache.ReadReq_accesses::cpu.inst 27771268 # number of ReadReq accesses(hits+misses) 565system.cpu.icache.ReadReq_accesses::total 27771268 # number of ReadReq accesses(hits+misses) 566system.cpu.icache.demand_accesses::cpu.inst 27771268 # number of demand (read+write) accesses 567system.cpu.icache.demand_accesses::total 27771268 # number of demand (read+write) accesses 568system.cpu.icache.overall_accesses::cpu.inst 27771268 # number of overall (read+write) accesses 569system.cpu.icache.overall_accesses::total 27771268 # number of overall (read+write) accesses | 558system.cpu.icache.ReadReq_miss_latency::cpu.inst 59898000 # number of ReadReq miss cycles 559system.cpu.icache.ReadReq_miss_latency::total 59898000 # number of ReadReq miss cycles 560system.cpu.icache.demand_miss_latency::cpu.inst 59898000 # number of demand (read+write) miss cycles 561system.cpu.icache.demand_miss_latency::total 59898000 # number of demand (read+write) miss cycles 562system.cpu.icache.overall_miss_latency::cpu.inst 59898000 # number of overall miss cycles 563system.cpu.icache.overall_miss_latency::total 59898000 # number of overall miss cycles 564system.cpu.icache.ReadReq_accesses::cpu.inst 27771270 # number of ReadReq accesses(hits+misses) 565system.cpu.icache.ReadReq_accesses::total 27771270 # number of ReadReq accesses(hits+misses) 566system.cpu.icache.demand_accesses::cpu.inst 27771270 # number of demand (read+write) accesses 567system.cpu.icache.demand_accesses::total 27771270 # number of demand (read+write) accesses 568system.cpu.icache.overall_accesses::cpu.inst 27771270 # number of overall (read+write) accesses 569system.cpu.icache.overall_accesses::total 27771270 # number of overall (read+write) accesses |
| 570system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 571system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 572system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 573system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 574system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 575system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses | 570system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 571system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 572system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 573system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 574system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 575system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses |
| 576system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74946.384040 # average ReadReq miss latency 577system.cpu.icache.ReadReq_avg_miss_latency::total 74946.384040 # average ReadReq miss latency 578system.cpu.icache.demand_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency 579system.cpu.icache.demand_avg_miss_latency::total 74946.384040 # average overall miss latency 580system.cpu.icache.overall_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency 581system.cpu.icache.overall_avg_miss_latency::total 74946.384040 # average overall miss latency | 576system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74685.785536 # average ReadReq miss latency 577system.cpu.icache.ReadReq_avg_miss_latency::total 74685.785536 # average ReadReq miss latency 578system.cpu.icache.demand_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency 579system.cpu.icache.demand_avg_miss_latency::total 74685.785536 # average overall miss latency 580system.cpu.icache.overall_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency 581system.cpu.icache.overall_avg_miss_latency::total 74685.785536 # average overall miss latency |
| 582system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 583system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 584system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 585system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 586system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 587system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 588system.cpu.icache.fast_writes 0 # number of fast writes performed 589system.cpu.icache.cache_copies 0 # number of cache copies performed 590system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses 591system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses 592system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses 593system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses 594system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses 595system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses | 582system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 583system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 584system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 585system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 586system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 587system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 588system.cpu.icache.fast_writes 0 # number of fast writes performed 589system.cpu.icache.cache_copies 0 # number of cache copies performed 590system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses 591system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses 592system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses 593system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses 594system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses 595system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses |
| 596system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59305000 # number of ReadReq MSHR miss cycles 597system.cpu.icache.ReadReq_mshr_miss_latency::total 59305000 # number of ReadReq MSHR miss cycles 598system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59305000 # number of demand (read+write) MSHR miss cycles 599system.cpu.icache.demand_mshr_miss_latency::total 59305000 # number of demand (read+write) MSHR miss cycles 600system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59305000 # number of overall MSHR miss cycles 601system.cpu.icache.overall_mshr_miss_latency::total 59305000 # number of overall MSHR miss cycles | 596system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59096000 # number of ReadReq MSHR miss cycles 597system.cpu.icache.ReadReq_mshr_miss_latency::total 59096000 # number of ReadReq MSHR miss cycles 598system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59096000 # number of demand (read+write) MSHR miss cycles 599system.cpu.icache.demand_mshr_miss_latency::total 59096000 # number of demand (read+write) MSHR miss cycles 600system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59096000 # number of overall MSHR miss cycles 601system.cpu.icache.overall_mshr_miss_latency::total 59096000 # number of overall MSHR miss cycles |
| 602system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 603system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 604system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 605system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 606system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 607system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses | 602system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 603system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 604system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 605system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 606system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 607system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses |
| 608system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73946.384040 # average ReadReq mshr miss latency 609system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73946.384040 # average ReadReq mshr miss latency 610system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency 611system.cpu.icache.demand_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency 612system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency 613system.cpu.icache.overall_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency | 608system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73685.785536 # average ReadReq mshr miss latency 609system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73685.785536 # average ReadReq mshr miss latency 610system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency 611system.cpu.icache.demand_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency 612system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency 613system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency |
| 614system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 615system.cpu.l2cache.tags.replacements 0 # number of replacements | 614system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 615system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 616system.cpu.l2cache.tags.tagsinuse 10245.543243 # Cycle average of tags in use | 616system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use |
| 617system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. 618system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. 619system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. 620system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 617system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. 618system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. 619system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. 620system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 621system.cpu.l2cache.tags.occ_blocks::writebacks 9355.642515 # Average occupied blocks per requestor 622system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444420 # Average occupied blocks per requestor 623system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456307 # Average occupied blocks per requestor | 621system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor 622system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor 623system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor |
| 624system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy 625system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020582 # Average percentage of cache occupancy 626system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy | 624system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy 625system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020582 # Average percentage of cache occupancy 626system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy |
| 627system.cpu.l2cache.tags.occ_percent::total 0.312669 # Average percentage of cache occupancy | 627system.cpu.l2cache.tags.occ_percent::total 0.312670 # Average percentage of cache occupancy |
| 628system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id 629system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 630system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 631system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 632system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id 633system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id 634system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id 635system.cpu.l2cache.tags.tag_accesses 15237898 # Number of tag accesses --- 19 unchanged lines hidden (view full) --- 655system.cpu.l2cache.ReadSharedReq_misses::cpu.data 262 # number of ReadSharedReq misses 656system.cpu.l2cache.ReadSharedReq_misses::total 262 # number of ReadSharedReq misses 657system.cpu.l2cache.demand_misses::cpu.inst 776 # number of demand (read+write) misses 658system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses 659system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses 660system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses 661system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses 662system.cpu.l2cache.overall_misses::total 15582 # number of overall misses | 628system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id 629system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 630system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 631system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 632system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id 633system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id 634system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id 635system.cpu.l2cache.tags.tag_accesses 15237898 # Number of tag accesses --- 19 unchanged lines hidden (view full) --- 655system.cpu.l2cache.ReadSharedReq_misses::cpu.data 262 # number of ReadSharedReq misses 656system.cpu.l2cache.ReadSharedReq_misses::total 262 # number of ReadSharedReq misses 657system.cpu.l2cache.demand_misses::cpu.inst 776 # number of demand (read+write) misses 658system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses 659system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses 660system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses 661system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses 662system.cpu.l2cache.overall_misses::total 15582 # number of overall misses |
| 663system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067640500 # number of ReadExReq miss cycles 664system.cpu.l2cache.ReadExReq_miss_latency::total 1067640500 # number of ReadExReq miss cycles 665system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57828000 # number of ReadCleanReq miss cycles 666system.cpu.l2cache.ReadCleanReq_miss_latency::total 57828000 # number of ReadCleanReq miss cycles 667system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21914500 # number of ReadSharedReq miss cycles 668system.cpu.l2cache.ReadSharedReq_miss_latency::total 21914500 # number of ReadSharedReq miss cycles 669system.cpu.l2cache.demand_miss_latency::cpu.inst 57828000 # number of demand (read+write) miss cycles 670system.cpu.l2cache.demand_miss_latency::cpu.data 1089555000 # number of demand (read+write) miss cycles 671system.cpu.l2cache.demand_miss_latency::total 1147383000 # number of demand (read+write) miss cycles 672system.cpu.l2cache.overall_miss_latency::cpu.inst 57828000 # number of overall miss cycles 673system.cpu.l2cache.overall_miss_latency::cpu.data 1089555000 # number of overall miss cycles 674system.cpu.l2cache.overall_miss_latency::total 1147383000 # number of overall miss cycles | 663system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles 664system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles 665system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles 666system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles 667system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles 668system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles 669system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles 670system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles 671system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles 672system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles 673system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles 674system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles |
| 675system.cpu.l2cache.Writeback_accesses::writebacks 943278 # number of Writeback accesses(hits+misses) 676system.cpu.l2cache.Writeback_accesses::total 943278 # number of Writeback accesses(hits+misses) 677system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses) 678system.cpu.l2cache.ReadExReq_accesses::total 46765 # number of ReadExReq accesses(hits+misses) 679system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) 680system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) 681system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903428 # number of ReadSharedReq accesses(hits+misses) 682system.cpu.l2cache.ReadSharedReq_accesses::total 903428 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 693system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses 694system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses 695system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967581 # miss rate for demand accesses 696system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses 697system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses 698system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses 699system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses 700system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses | 675system.cpu.l2cache.Writeback_accesses::writebacks 943278 # number of Writeback accesses(hits+misses) 676system.cpu.l2cache.Writeback_accesses::total 943278 # number of Writeback accesses(hits+misses) 677system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses) 678system.cpu.l2cache.ReadExReq_accesses::total 46765 # number of ReadExReq accesses(hits+misses) 679system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) 680system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) 681system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903428 # number of ReadSharedReq accesses(hits+misses) 682system.cpu.l2cache.ReadSharedReq_accesses::total 903428 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 693system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses 694system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses 695system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967581 # miss rate for demand accesses 696system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses 697system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses 698system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses 699system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses 700system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses |
| 701system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.625138 # average ReadExReq miss latency 702system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.625138 # average ReadExReq miss latency 703system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74520.618557 # average ReadCleanReq miss latency 704system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74520.618557 # average ReadCleanReq miss latency 705system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83643.129771 # average ReadSharedReq miss latency 706system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83643.129771 # average ReadSharedReq miss latency 707system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency 708system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency 709system.cpu.l2cache.demand_avg_miss_latency::total 73635.155949 # average overall miss latency 710system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency 711system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency 712system.cpu.l2cache.overall_avg_miss_latency::total 73635.155949 # average overall miss latency | 701system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency 702system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency 703system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency 704system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency 705system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency 706system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency 707system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency 708system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency 709system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency 710system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency 711system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency 712system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency |
| 713system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 714system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 715system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 716system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 717system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 718system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 719system.cpu.l2cache.fast_writes 0 # number of fast writes performed 720system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 14 unchanged lines hidden (view full) --- 735system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256 # number of ReadSharedReq MSHR misses 736system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256 # number of ReadSharedReq MSHR misses 737system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses 738system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses 739system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 740system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses 741system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses 742system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses | 713system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 714system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 715system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 716system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 717system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 718system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 719system.cpu.l2cache.fast_writes 0 # number of fast writes performed 720system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 14 unchanged lines hidden (view full) --- 735system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256 # number of ReadSharedReq MSHR misses 736system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256 # number of ReadSharedReq MSHR misses 737system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses 738system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses 739system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 740system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses 741system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses 742system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses |
| 743system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922200500 # number of ReadExReq MSHR miss cycles 744system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922200500 # number of ReadExReq MSHR miss cycles 745system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49941000 # number of ReadCleanReq MSHR miss cycles 746system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49941000 # number of ReadCleanReq MSHR miss cycles 747system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18963500 # number of ReadSharedReq MSHR miss cycles 748system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18963500 # number of ReadSharedReq MSHR miss cycles 749system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49941000 # number of demand (read+write) MSHR miss cycles 750system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941164000 # number of demand (read+write) MSHR miss cycles 751system.cpu.l2cache.demand_mshr_miss_latency::total 991105000 # number of demand (read+write) MSHR miss cycles 752system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49941000 # number of overall MSHR miss cycles 753system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941164000 # number of overall MSHR miss cycles 754system.cpu.l2cache.overall_mshr_miss_latency::total 991105000 # number of overall MSHR miss cycles | 743system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles 744system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles 745system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles 746system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles 747system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles 748system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles 749system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles 750system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles 751system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles 752system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles 753system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles 754system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles |
| 755system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses 756system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses 757system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses 758system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses 759system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses 760system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses 761system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses 762system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses 763system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 764system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses 765system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses 766system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses | 755system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses 756system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses 757system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses 758system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses 759system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses 760system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses 761system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses 762system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses 763system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 764system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses 765system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses 766system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses |
| 767system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63407.625138 # average ReadExReq mshr miss latency 768system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63407.625138 # average ReadExReq mshr miss latency 769system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64523.255814 # average ReadCleanReq mshr miss latency 770system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64523.255814 # average ReadCleanReq mshr miss latency 771system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74076.171875 # average ReadSharedReq mshr miss latency 772system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74076.171875 # average ReadSharedReq mshr miss latency 773system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency 774system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency 775system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency 776system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency 777system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency 778system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency | 767system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency 768system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency 769system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency 770system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency 771system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency 772system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency 773system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency 774system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency 775system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency 776system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency 777system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency 778system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency |
| 779system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 779system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 780system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter. 781system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. 782system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 783system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 784system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 785system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 780system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution 781system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution 782system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution 783system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution 784system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution 785system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution 786system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 # Transaction distribution 787system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes) 788system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes) 789system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes) 790system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) 791system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) 792system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes) 793system.cpu.toL2Bus.snoops 0 # Total snoops (count) 794system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram | 786system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution 787system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution 788system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution 789system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution 790system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution 791system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution 792system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 # Transaction distribution 793system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes) 794system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes) 795system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes) 796system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) 797system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) 798system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes) 799system.cpu.toL2Bus.snoops 0 # Total snoops (count) 800system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram |
| 795system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 796system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 801system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram 802system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram |
| 797system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 803system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 798system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 799system.cpu.toL2Bus.snoop_fanout::1 1897097 100.00% 100.00% # Request fanout histogram | 804system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram 805system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram |
| 800system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 801system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 806system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 807system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 802system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 808system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 803system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 804system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram 805system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks) 806system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) 807system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks) 808system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 809system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) 810system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) --- 11 unchanged lines hidden (view full) --- 822system.membus.snoop_fanout::stdev 0 # Request fanout histogram 823system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 824system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 825system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 826system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 827system.membus.snoop_fanout::min_value 0 # Request fanout histogram 828system.membus.snoop_fanout::max_value 0 # Request fanout histogram 829system.membus.snoop_fanout::total 15574 # Request fanout histogram | 809system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 810system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram 811system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks) 812system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) 813system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks) 814system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 815system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) 816system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) --- 11 unchanged lines hidden (view full) --- 828system.membus.snoop_fanout::stdev 0 # Request fanout histogram 829system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 830system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 831system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 832system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 833system.membus.snoop_fanout::min_value 0 # Request fanout histogram 834system.membus.snoop_fanout::max_value 0 # Request fanout histogram 835system.membus.snoop_fanout::total 15574 # Request fanout histogram |
| 830system.membus.reqLayer0.occupancy 21739500 # Layer occupancy (ticks) | 836system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks) |
| 831system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 837system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 832system.membus.respLayer1.occupancy 82130500 # Layer occupancy (ticks) | 838system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks) |
| 833system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 834 835---------- End Simulation Statistics ---------- | 839system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 840 841---------- End Simulation Statistics ---------- |