| stats.txt (10636:9ac724889705) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.061494 # Number of seconds simulated 4sim_ticks 61493732000 # Number of ticks simulated 5final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.061593 # Number of seconds simulated 4sim_ticks 61592600500 # Number of ticks simulated 5final_tick 61592600500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 144123 # Simulator instruction rate (inst/s) 8host_op_rate 144840 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 97818525 # Simulator tick rate (ticks/s) 10host_mem_usage 433504 # Number of bytes of host memory used 11host_seconds 628.65 # Real time elapsed on the host | 7host_inst_rate 271325 # Simulator instruction rate (inst/s) 8host_op_rate 272676 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 184448880 # Simulator tick rate (ticks/s) 10host_mem_usage 445184 # Number of bytes of host memory used 11host_seconds 333.93 # Real time elapsed on the host |
| 12sim_insts 90602849 # Number of instructions simulated 13sim_ops 91054080 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 49600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory 18system.physmem.bytes_read::total 996800 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory | 12sim_insts 90602849 # Number of instructions simulated 13sim_ops 91054080 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 49600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory 18system.physmem.bytes_read::total 996800 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 806586 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 15403196 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 806586 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 15403196 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 805292 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 15378471 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 16183762 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 805292 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 805292 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 805292 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 15378471 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 16183762 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 15575 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 15575 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 61493643500 # Total gap between requests | 78system.physmem.totGap 61592506000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 15575 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 15575 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 112 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 95system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 1534 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 648.594524 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 444.741065 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 399.329877 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 241 15.71% 15.71% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 178 11.60% 27.31% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation 203system.physmem.totQLat 73247750 # Total ticks spent queuing 204system.physmem.totMemAccLat 365279000 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 642.644287 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 437.986910 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 400.933627 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 248 16.01% 16.01% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 186 12.01% 28.02% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 90 5.81% 33.83% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 71 4.58% 38.41% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 77 4.97% 43.38% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 93 6.00% 49.39% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 43 2.78% 52.16% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 36 2.32% 54.49% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 705 45.51% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation 203system.physmem.totQLat 77242000 # Total ticks spent queuing 204system.physmem.totMemAccLat 369273250 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 4702.91 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 4959.36 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 23452.91 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 23709.36 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.13 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.13 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 14031 # Number of row buffer hits during reads | 219system.physmem.readRowHits 14018 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 3948227.51 # Average gap between requests 224system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 6320160 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 3448500 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 3954575.02 # Average gap between requests 224system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 6373080 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 3477375 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 63718200 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 229system.physmem_0.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 2490640650 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 34708185000 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 41288356230 # Total energy per rank (pJ) 233system.physmem_0.averagePower 671.483541 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 57732029500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 2053220000 # Time in different power states | 229system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 2539008855 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 34726497750 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 41361784860 # Total energy per rank (pJ) 233system.physmem_0.averagePower 671.572046 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 57760380750 # Time in different power states 235system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states |
| 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 1704707500 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 1772530500 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 239system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) | 239system.physmem_1.actEnergy 5329800 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2908125 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 57478200 # Energy for read commands per rank (pJ) |
| 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 243system.physmem_1.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 2514095865 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 34687610250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 41283399795 # Total energy per rank (pJ) 247system.physmem_1.averagePower 671.402933 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 57698939250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 2053220000 # Time in different power states | 243system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 2571546735 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 34697955750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 41357928210 # Total energy per rank (pJ) 247system.physmem_1.averagePower 671.509428 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 57713961000 # Time in different power states 249system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states |
| 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 1738589750 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 1819631500 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.cpu.branchPred.lookups 20789429 # Number of BP lookups 254system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted | 253system.cpu.branchPred.lookups 20789446 # Number of BP lookups 254system.cpu.branchPred.condPredicted 17091418 # Number of conditional branches predicted |
| 255system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect | 255system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect |
| 256system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits | 256system.cpu.branchPred.BTBLookups 8973614 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 8867024 # Number of BTB hits |
| 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 259system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target. | 259system.cpu.branchPred.BTBHitPct 98.812184 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target. |
| 261system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 442 # Number of system calls | 261system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 442 # Number of system calls |
| 380system.cpu.numCycles 122987464 # number of cpu cycles simulated | 380system.cpu.numCycles 123185201 # number of cpu cycles simulated |
| 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 90602849 # Number of instructions committed 384system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed | 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 90602849 # Number of instructions committed 384system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed |
| 385system.cpu.discardedOps 2068195 # Number of ops (including micro ops) which were discarded before commit | 385system.cpu.discardedOps 2068247 # Number of ops (including micro ops) which were discarded before commit |
| 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 387system.cpu.cpi 1.357435 # CPI: cycles per instruction 388system.cpu.ipc 0.736684 # IPC: instructions per cycle 389system.cpu.tickCycles 109826570 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 13160894 # Total number of cycles that the object has spent stopped | 387system.cpu.cpi 1.359617 # CPI: cycles per instruction 388system.cpu.ipc 0.735501 # IPC: instructions per cycle 389system.cpu.tickCycles 109827605 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 13357596 # Total number of cycles that the object has spent stopped |
| 391system.cpu.dcache.tags.replacements 946107 # number of replacements | 391system.cpu.dcache.tags.replacements 946107 # number of replacements |
| 392system.cpu.dcache.tags.tagsinuse 3616.604238 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 26267660 # Total number of references to valid blocks. | 392system.cpu.dcache.tags.tagsinuse 3616.143974 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 26267423 # Total number of references to valid blocks. |
| 394system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. | 394system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. |
| 395system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit. 397system.cpu.dcache.tags.occ_blocks::cpu.data 3616.604238 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.882960 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy | 395system.cpu.dcache.tags.avg_refs 27.644012 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit. 397system.cpu.dcache.tags.occ_blocks::cpu.data 3616.143974 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.882848 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.882848 # Average percentage of cache occupancy |
| 400system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 400system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 2249 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id | 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id |
| 404system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 404system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 405system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses 406system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses 407system.cpu.dcache.ReadReq_hits::cpu.data 21598813 # number of ReadReq hits 408system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits 409system.cpu.dcache.WriteReq_hits::cpu.data 4661073 # number of WriteReq hits 410system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits | 405system.cpu.dcache.tags.tag_accesses 55463259 # Number of tag accesses 406system.cpu.dcache.tags.data_accesses 55463259 # Number of data accesses 407system.cpu.dcache.ReadReq_hits::cpu.data 21598839 # number of ReadReq hits 408system.cpu.dcache.ReadReq_hits::total 21598839 # number of ReadReq hits 409system.cpu.dcache.WriteReq_hits::cpu.data 4660810 # number of WriteReq hits 410system.cpu.dcache.WriteReq_hits::total 4660810 # number of WriteReq hits |
| 411system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 412system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 413system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 414system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits | 411system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 412system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 413system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 414system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits |
| 415system.cpu.dcache.demand_hits::cpu.data 26259886 # number of demand (read+write) hits 416system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits 417system.cpu.dcache.overall_hits::cpu.data 26259886 # number of overall hits 418system.cpu.dcache.overall_hits::total 26259886 # number of overall hits 419system.cpu.dcache.ReadReq_misses::cpu.data 914958 # number of ReadReq misses 420system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses 421system.cpu.dcache.WriteReq_misses::cpu.data 73908 # number of WriteReq misses 422system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses 423system.cpu.dcache.demand_misses::cpu.data 988866 # number of demand (read+write) misses 424system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses 425system.cpu.dcache.overall_misses::cpu.data 988866 # number of overall misses 426system.cpu.dcache.overall_misses::total 988866 # number of overall misses 427system.cpu.dcache.ReadReq_miss_latency::cpu.data 11910296994 # number of ReadReq miss cycles 428system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles 429system.cpu.dcache.WriteReq_miss_latency::cpu.data 2345727500 # number of WriteReq miss cycles 430system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles 431system.cpu.dcache.demand_miss_latency::cpu.data 14256024494 # number of demand (read+write) miss cycles 432system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles 433system.cpu.dcache.overall_miss_latency::cpu.data 14256024494 # number of overall miss cycles 434system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles 435system.cpu.dcache.ReadReq_accesses::cpu.data 22513771 # number of ReadReq accesses(hits+misses) 436system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) | 415system.cpu.dcache.demand_hits::cpu.data 26259649 # number of demand (read+write) hits 416system.cpu.dcache.demand_hits::total 26259649 # number of demand (read+write) hits 417system.cpu.dcache.overall_hits::cpu.data 26259649 # number of overall hits 418system.cpu.dcache.overall_hits::total 26259649 # number of overall hits 419system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses 420system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses 421system.cpu.dcache.WriteReq_misses::cpu.data 74171 # number of WriteReq misses 422system.cpu.dcache.WriteReq_misses::total 74171 # number of WriteReq misses 423system.cpu.dcache.demand_misses::cpu.data 989105 # number of demand (read+write) misses 424system.cpu.dcache.demand_misses::total 989105 # number of demand (read+write) misses 425system.cpu.dcache.overall_misses::cpu.data 989105 # number of overall misses 426system.cpu.dcache.overall_misses::total 989105 # number of overall misses 427system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918412494 # number of ReadReq miss cycles 428system.cpu.dcache.ReadReq_miss_latency::total 11918412494 # number of ReadReq miss cycles 429system.cpu.dcache.WriteReq_miss_latency::cpu.data 2568231500 # number of WriteReq miss cycles 430system.cpu.dcache.WriteReq_miss_latency::total 2568231500 # number of WriteReq miss cycles 431system.cpu.dcache.demand_miss_latency::cpu.data 14486643994 # number of demand (read+write) miss cycles 432system.cpu.dcache.demand_miss_latency::total 14486643994 # number of demand (read+write) miss cycles 433system.cpu.dcache.overall_miss_latency::cpu.data 14486643994 # number of overall miss cycles 434system.cpu.dcache.overall_miss_latency::total 14486643994 # number of overall miss cycles 435system.cpu.dcache.ReadReq_accesses::cpu.data 22513773 # number of ReadReq accesses(hits+misses) 436system.cpu.dcache.ReadReq_accesses::total 22513773 # number of ReadReq accesses(hits+misses) |
| 437system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 438system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 439system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 440system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 441system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 442system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) | 437system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 438system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 439system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 440system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 441system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 442system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) |
| 443system.cpu.dcache.demand_accesses::cpu.data 27248752 # number of demand (read+write) accesses 444system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses 445system.cpu.dcache.overall_accesses::cpu.data 27248752 # number of overall (read+write) accesses 446system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses 447system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses 448system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses 449system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015609 # miss rate for WriteReq accesses 450system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses 451system.cpu.dcache.demand_miss_rate::cpu.data 0.036290 # miss rate for demand accesses 452system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses 453system.cpu.dcache.overall_miss_rate::cpu.data 0.036290 # miss rate for overall accesses 454system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses 455system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13017.315542 # average ReadReq miss latency 456system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency 457system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31738.478920 # average WriteReq miss latency 458system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency 459system.cpu.dcache.demand_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency 460system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency 461system.cpu.dcache.overall_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency 462system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency | 443system.cpu.dcache.demand_accesses::cpu.data 27248754 # number of demand (read+write) accesses 444system.cpu.dcache.demand_accesses::total 27248754 # number of demand (read+write) accesses 445system.cpu.dcache.overall_accesses::cpu.data 27248754 # number of overall (read+write) accesses 446system.cpu.dcache.overall_accesses::total 27248754 # number of overall (read+write) accesses 447system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses 448system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses 449system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses 450system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses 451system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses 452system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses 453system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses 454system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses 455system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.527043 # average ReadReq miss latency 456system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.527043 # average ReadReq miss latency 457system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34625.817368 # average WriteReq miss latency 458system.cpu.dcache.WriteReq_avg_miss_latency::total 34625.817368 # average WriteReq miss latency 459system.cpu.dcache.demand_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency 460system.cpu.dcache.demand_avg_miss_latency::total 14646.214501 # average overall miss latency 461system.cpu.dcache.overall_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency 462system.cpu.dcache.overall_avg_miss_latency::total 14646.214501 # average overall miss latency |
| 463system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 464system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 465system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 466system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 467system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 468system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 469system.cpu.dcache.fast_writes 0 # number of fast writes performed 470system.cpu.dcache.cache_copies 0 # number of cache copies performed 471system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks 472system.cpu.dcache.writebacks::total 943286 # number of writebacks | 463system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 464system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 465system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 466system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 467system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 468system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 469system.cpu.dcache.fast_writes 0 # number of fast writes performed 470system.cpu.dcache.cache_copies 0 # number of cache copies performed 471system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks 472system.cpu.dcache.writebacks::total 943286 # number of writebacks |
| 473system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11523 # number of ReadReq MSHR hits 474system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits 475system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27140 # number of WriteReq MSHR hits 476system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits 477system.cpu.dcache.demand_mshr_hits::cpu.data 38663 # number of demand (read+write) MSHR hits 478system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits 479system.cpu.dcache.overall_mshr_hits::cpu.data 38663 # number of overall MSHR hits 480system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits | 473system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11499 # number of ReadReq MSHR hits 474system.cpu.dcache.ReadReq_mshr_hits::total 11499 # number of ReadReq MSHR hits 475system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27403 # number of WriteReq MSHR hits 476system.cpu.dcache.WriteReq_mshr_hits::total 27403 # number of WriteReq MSHR hits 477system.cpu.dcache.demand_mshr_hits::cpu.data 38902 # number of demand (read+write) MSHR hits 478system.cpu.dcache.demand_mshr_hits::total 38902 # number of demand (read+write) MSHR hits 479system.cpu.dcache.overall_mshr_hits::cpu.data 38902 # number of overall MSHR hits 480system.cpu.dcache.overall_mshr_hits::total 38902 # number of overall MSHR hits |
| 481system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses 482system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses 483system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses 484system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses 485system.cpu.dcache.demand_mshr_misses::cpu.data 950203 # number of demand (read+write) MSHR misses 486system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses 487system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses 488system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses | 481system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses 482system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses 483system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses 484system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses 485system.cpu.dcache.demand_mshr_misses::cpu.data 950203 # number of demand (read+write) MSHR misses 486system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses 487system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses 488system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses |
| 489system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9958855506 # number of ReadReq MSHR miss cycles 490system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles 491system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1333449750 # number of WriteReq MSHR miss cycles 492system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles 493system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11292305256 # number of demand (read+write) MSHR miss cycles 494system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles 495system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11292305256 # number of overall MSHR miss cycles 496system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles | 489system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413322256 # number of ReadReq MSHR miss cycles 490system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413322256 # number of ReadReq MSHR miss cycles 491system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464464500 # number of WriteReq MSHR miss cycles 492system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464464500 # number of WriteReq MSHR miss cycles 493system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877786756 # number of demand (read+write) MSHR miss cycles 494system.cpu.dcache.demand_mshr_miss_latency::total 11877786756 # number of demand (read+write) MSHR miss cycles 495system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877786756 # number of overall MSHR miss cycles 496system.cpu.dcache.overall_mshr_miss_latency::total 11877786756 # number of overall MSHR miss cycles |
| 497system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses 498system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses 499system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses 500system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses 501system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses 502system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses 503system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses 504system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses | 497system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses 498system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses 499system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses 500system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses 501system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses 502system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses 503system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses 504system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses |
| 505system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.322659 # average ReadReq mshr miss latency 506system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency 507system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28512.011418 # average WriteReq mshr miss latency 508system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency 509system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency 510system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency 511system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency 512system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency | 505system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.365766 # average ReadReq mshr miss latency 506system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.365766 # average ReadReq mshr miss latency 507system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31313.387359 # average WriteReq mshr miss latency 508system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31313.387359 # average WriteReq mshr miss latency 509system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency 510system.cpu.dcache.demand_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency 511system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency 512system.cpu.dcache.overall_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency |
| 513system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 514system.cpu.icache.tags.replacements 5 # number of replacements | 513system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 514system.cpu.icache.tags.replacements 5 # number of replacements |
| 515system.cpu.icache.tags.tagsinuse 690.411182 # Cycle average of tags in use 516system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks. | 515system.cpu.icache.tags.tagsinuse 690.370829 # Cycle average of tags in use 516system.cpu.icache.tags.total_refs 27857028 # Total number of references to valid blocks. |
| 517system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. | 517system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. |
| 518system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks. | 518system.cpu.icache.tags.avg_refs 34691.193026 # Average number of references to valid blocks. |
| 519system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 519system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 520system.cpu.icache.tags.occ_blocks::cpu.inst 690.411182 # Average occupied blocks per requestor 521system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy 522system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy | 520system.cpu.icache.tags.occ_blocks::cpu.inst 690.370829 # Average occupied blocks per requestor 521system.cpu.icache.tags.occ_percent::cpu.inst 0.337095 # Average percentage of cache occupancy 522system.cpu.icache.tags.occ_percent::total 0.337095 # Average percentage of cache occupancy |
| 523system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id 524system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 525system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 526system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id 527system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id | 523system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id 524system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 525system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 526system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id 527system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id |
| 528system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses 529system.cpu.icache.tags.data_accesses 55716427 # Number of data accesses 530system.cpu.icache.ReadReq_hits::cpu.inst 27857009 # number of ReadReq hits 531system.cpu.icache.ReadReq_hits::total 27857009 # number of ReadReq hits 532system.cpu.icache.demand_hits::cpu.inst 27857009 # number of demand (read+write) hits 533system.cpu.icache.demand_hits::total 27857009 # number of demand (read+write) hits 534system.cpu.icache.overall_hits::cpu.inst 27857009 # number of overall hits 535system.cpu.icache.overall_hits::total 27857009 # number of overall hits | 528system.cpu.icache.tags.tag_accesses 55716465 # Number of tag accesses 529system.cpu.icache.tags.data_accesses 55716465 # Number of data accesses 530system.cpu.icache.ReadReq_hits::cpu.inst 27857028 # number of ReadReq hits 531system.cpu.icache.ReadReq_hits::total 27857028 # number of ReadReq hits 532system.cpu.icache.demand_hits::cpu.inst 27857028 # number of demand (read+write) hits 533system.cpu.icache.demand_hits::total 27857028 # number of demand (read+write) hits 534system.cpu.icache.overall_hits::cpu.inst 27857028 # number of overall hits 535system.cpu.icache.overall_hits::total 27857028 # number of overall hits |
| 536system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses 537system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses 538system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 539system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses 540system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses 541system.cpu.icache.overall_misses::total 803 # number of overall misses | 536system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses 537system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses 538system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 539system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses 540system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses 541system.cpu.icache.overall_misses::total 803 # number of overall misses |
| 542system.cpu.icache.ReadReq_miss_latency::cpu.inst 55346748 # number of ReadReq miss cycles 543system.cpu.icache.ReadReq_miss_latency::total 55346748 # number of ReadReq miss cycles 544system.cpu.icache.demand_miss_latency::cpu.inst 55346748 # number of demand (read+write) miss cycles 545system.cpu.icache.demand_miss_latency::total 55346748 # number of demand (read+write) miss cycles 546system.cpu.icache.overall_miss_latency::cpu.inst 55346748 # number of overall miss cycles 547system.cpu.icache.overall_miss_latency::total 55346748 # number of overall miss cycles 548system.cpu.icache.ReadReq_accesses::cpu.inst 27857812 # number of ReadReq accesses(hits+misses) 549system.cpu.icache.ReadReq_accesses::total 27857812 # number of ReadReq accesses(hits+misses) 550system.cpu.icache.demand_accesses::cpu.inst 27857812 # number of demand (read+write) accesses 551system.cpu.icache.demand_accesses::total 27857812 # number of demand (read+write) accesses 552system.cpu.icache.overall_accesses::cpu.inst 27857812 # number of overall (read+write) accesses 553system.cpu.icache.overall_accesses::total 27857812 # number of overall (read+write) accesses | 542system.cpu.icache.ReadReq_miss_latency::cpu.inst 61138997 # number of ReadReq miss cycles 543system.cpu.icache.ReadReq_miss_latency::total 61138997 # number of ReadReq miss cycles 544system.cpu.icache.demand_miss_latency::cpu.inst 61138997 # number of demand (read+write) miss cycles 545system.cpu.icache.demand_miss_latency::total 61138997 # number of demand (read+write) miss cycles 546system.cpu.icache.overall_miss_latency::cpu.inst 61138997 # number of overall miss cycles 547system.cpu.icache.overall_miss_latency::total 61138997 # number of overall miss cycles 548system.cpu.icache.ReadReq_accesses::cpu.inst 27857831 # number of ReadReq accesses(hits+misses) 549system.cpu.icache.ReadReq_accesses::total 27857831 # number of ReadReq accesses(hits+misses) 550system.cpu.icache.demand_accesses::cpu.inst 27857831 # number of demand (read+write) accesses 551system.cpu.icache.demand_accesses::total 27857831 # number of demand (read+write) accesses 552system.cpu.icache.overall_accesses::cpu.inst 27857831 # number of overall (read+write) accesses 553system.cpu.icache.overall_accesses::total 27857831 # number of overall (read+write) accesses |
| 554system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 555system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 556system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 557system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 558system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 559system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses | 554system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 555system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 556system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 557system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 558system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 559system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses |
| 560system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68924.966376 # average ReadReq miss latency 561system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376 # average ReadReq miss latency 562system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency 563system.cpu.icache.demand_avg_miss_latency::total 68924.966376 # average overall miss latency 564system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency 565system.cpu.icache.overall_avg_miss_latency::total 68924.966376 # average overall miss latency | 560system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76138.227895 # average ReadReq miss latency 561system.cpu.icache.ReadReq_avg_miss_latency::total 76138.227895 # average ReadReq miss latency 562system.cpu.icache.demand_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency 563system.cpu.icache.demand_avg_miss_latency::total 76138.227895 # average overall miss latency 564system.cpu.icache.overall_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency 565system.cpu.icache.overall_avg_miss_latency::total 76138.227895 # average overall miss latency |
| 566system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 567system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 568system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 569system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 570system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 571system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 572system.cpu.icache.fast_writes 0 # number of fast writes performed 573system.cpu.icache.cache_copies 0 # number of cache copies performed 574system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses 575system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses 576system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 577system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses 578system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 579system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses | 566system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 567system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 568system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 569system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 570system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 571system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 572system.cpu.icache.fast_writes 0 # number of fast writes performed 573system.cpu.icache.cache_copies 0 # number of cache copies performed 574system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses 575system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses 576system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 577system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses 578system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 579system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses |
| 580system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53408252 # number of ReadReq MSHR miss cycles 581system.cpu.icache.ReadReq_mshr_miss_latency::total 53408252 # number of ReadReq MSHR miss cycles 582system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53408252 # number of demand (read+write) MSHR miss cycles 583system.cpu.icache.demand_mshr_miss_latency::total 53408252 # number of demand (read+write) MSHR miss cycles 584system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53408252 # number of overall MSHR miss cycles 585system.cpu.icache.overall_mshr_miss_latency::total 53408252 # number of overall MSHR miss cycles | 580system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59598503 # number of ReadReq MSHR miss cycles 581system.cpu.icache.ReadReq_mshr_miss_latency::total 59598503 # number of ReadReq MSHR miss cycles 582system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59598503 # number of demand (read+write) MSHR miss cycles 583system.cpu.icache.demand_mshr_miss_latency::total 59598503 # number of demand (read+write) MSHR miss cycles 584system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59598503 # number of overall MSHR miss cycles 585system.cpu.icache.overall_mshr_miss_latency::total 59598503 # number of overall MSHR miss cycles |
| 586system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 587system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 588system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 589system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 590system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 591system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses | 586system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 587system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 588system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 589system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 590system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 591system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses |
| 592system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency 593system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency 594system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency 595system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency 596system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency 597system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency | 592system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74219.804483 # average ReadReq mshr miss latency 593system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74219.804483 # average ReadReq mshr miss latency 594system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency 595system.cpu.icache.demand_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency 596system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency 597system.cpu.icache.overall_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency |
| 598system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 599system.cpu.l2cache.tags.replacements 0 # number of replacements | 598system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 599system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 600system.cpu.l2cache.tags.tagsinuse 10247.121902 # Cycle average of tags in use 601system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks. | 600system.cpu.l2cache.tags.tagsinuse 10238.643668 # Cycle average of tags in use 601system.cpu.l2cache.tags.total_refs 1831333 # Total number of references to valid blocks. |
| 602system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. | 602system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. |
| 603system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. | 603system.cpu.l2cache.tags.avg_refs 117.710053 # Average number of references to valid blocks. |
| 604system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 604system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 605system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor 606system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.415381 # Average occupied blocks per requestor 607system.cpu.l2cache.tags.occ_blocks::cpu.data 215.469913 # Average occupied blocks per requestor 608system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy 609system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020612 # Average percentage of cache occupancy 610system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy 611system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy | 605system.cpu.l2cache.tags.occ_blocks::writebacks 9347.860585 # Average occupied blocks per requestor 606system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.375683 # Average occupied blocks per requestor 607system.cpu.l2cache.tags.occ_blocks::cpu.data 215.407400 # Average occupied blocks per requestor 608system.cpu.l2cache.tags.occ_percent::writebacks 0.285274 # Average percentage of cache occupancy 609system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020611 # Average percentage of cache occupancy 610system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy 611system.cpu.l2cache.tags.occ_percent::total 0.312459 # Average percentage of cache occupancy |
| 612system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id 613system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 614system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 615system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 616system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id 617system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id 618system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id 619system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses 620system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses | 612system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id 613system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 614system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 615system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 616system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id 617system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id 618system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id 619system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses 620system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses |
| 621system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits | 621system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits |
| 622system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits | 622system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits |
| 623system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits | 623system.cpu.l2cache.ReadReq_hits::total 903198 # number of ReadReq hits |
| 624system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits 625system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits 626system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits 627system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits | 624system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits 625system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits 626system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits 627system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits |
| 628system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits | 628system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits |
| 629system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits | 629system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits |
| 630system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits 631system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits | 630system.cpu.l2cache.demand_hits::total 935422 # number of demand (read+write) hits 631system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits |
| 632system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits | 632system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits |
| 633system.cpu.l2cache.overall_hits::total 935423 # number of overall hits 634system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses | 633system.cpu.l2cache.overall_hits::total 935422 # number of overall hits 634system.cpu.l2cache.ReadReq_misses::cpu.inst 778 # number of ReadReq misses |
| 635system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses | 635system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses |
| 636system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses | 636system.cpu.l2cache.ReadReq_misses::total 1040 # number of ReadReq misses |
| 637system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses 638system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses | 637system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses 638system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses |
| 639system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses | 639system.cpu.l2cache.demand_misses::cpu.inst 778 # number of demand (read+write) misses |
| 640system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses | 640system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses |
| 641system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses 642system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses | 641system.cpu.l2cache.demand_misses::total 15584 # number of demand (read+write) misses 642system.cpu.l2cache.overall_misses::cpu.inst 778 # number of overall misses |
| 643system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses | 643system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses |
| 644system.cpu.l2cache.overall_misses::total 15583 # number of overall misses 645system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52344250 # number of ReadReq miss cycles 646system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19360000 # number of ReadReq miss cycles 647system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles 648system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 958084250 # number of ReadExReq miss cycles 649system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles 650system.cpu.l2cache.demand_miss_latency::cpu.inst 52344250 # number of demand (read+write) miss cycles 651system.cpu.l2cache.demand_miss_latency::cpu.data 977444250 # number of demand (read+write) miss cycles 652system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles 653system.cpu.l2cache.overall_miss_latency::cpu.inst 52344250 # number of overall miss cycles 654system.cpu.l2cache.overall_miss_latency::cpu.data 977444250 # number of overall miss cycles 655system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles | 644system.cpu.l2cache.overall_misses::total 15584 # number of overall misses 645system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58533000 # number of ReadReq miss cycles 646system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267750 # number of ReadReq miss cycles 647system.cpu.l2cache.ReadReq_miss_latency::total 80800750 # number of ReadReq miss cycles 648system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073909000 # number of ReadExReq miss cycles 649system.cpu.l2cache.ReadExReq_miss_latency::total 1073909000 # number of ReadExReq miss cycles 650system.cpu.l2cache.demand_miss_latency::cpu.inst 58533000 # number of demand (read+write) miss cycles 651system.cpu.l2cache.demand_miss_latency::cpu.data 1096176750 # number of demand (read+write) miss cycles 652system.cpu.l2cache.demand_miss_latency::total 1154709750 # number of demand (read+write) miss cycles 653system.cpu.l2cache.overall_miss_latency::cpu.inst 58533000 # number of overall miss cycles 654system.cpu.l2cache.overall_miss_latency::cpu.data 1096176750 # number of overall miss cycles 655system.cpu.l2cache.overall_miss_latency::total 1154709750 # number of overall miss cycles |
| 656system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses) 657system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses) 658system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) 659system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) 660system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses) 661system.cpu.l2cache.ReadExReq_accesses::cpu.data 46768 # number of ReadExReq accesses(hits+misses) 662system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses) 663system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses 664system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses 665system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses 666system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses 667system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses 668system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses | 656system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses) 657system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses) 658system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) 659system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) 660system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses) 661system.cpu.l2cache.ReadExReq_accesses::cpu.data 46768 # number of ReadExReq accesses(hits+misses) 662system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses) 663system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses 664system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses 665system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses 666system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses 667system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses 668system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses |
| 669system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967621 # miss rate for ReadReq accesses | 669system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses |
| 670system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses | 670system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses |
| 671system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses | 671system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses |
| 672system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses 673system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses | 672system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses 673system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses |
| 674system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967621 # miss rate for demand accesses | 674system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses |
| 675system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses | 675system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses |
| 676system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses 677system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967621 # miss rate for overall accesses | 676system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses 677system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses |
| 678system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses | 678system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses |
| 679system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses 680system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67367.117117 # average ReadReq miss latency 681system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73893.129771 # average ReadReq miss latency 682system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency 683system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65874.879675 # average ReadExReq miss latency 684system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency 685system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency 686system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency 687system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency 688system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency 689system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency 690system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency | 679system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses 680system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75235.218509 # average ReadReq miss latency 681system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84991.412214 # average ReadReq miss latency 682system.cpu.l2cache.ReadReq_avg_miss_latency::total 77693.028846 # average ReadReq miss latency 683system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73838.627613 # average ReadExReq miss latency 684system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73838.627613 # average ReadExReq miss latency 685system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency 686system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency 687system.cpu.l2cache.demand_avg_miss_latency::total 74095.851514 # average overall miss latency 688system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency 689system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency 690system.cpu.l2cache.overall_avg_miss_latency::total 74095.851514 # average overall miss latency |
| 691system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 692system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 693system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 694system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 695system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 696system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 697system.cpu.l2cache.fast_writes 0 # number of fast writes performed 698system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 691system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 692system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 693system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 694system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 695system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 696system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 697system.cpu.l2cache.fast_writes 0 # number of fast writes performed 698system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 699system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits | 699system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits |
| 700system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits | 700system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits |
| 701system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits 702system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits | 701system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 702system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits |
| 703system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits | 703system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits |
| 704system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 705system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits | 704system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits 705system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits |
| 706system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits | 706system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits |
| 707system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits | 707system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits |
| 708system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses 709system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses 710system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses 711system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses 712system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 713system.cpu.l2cache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses 714system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses 715system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses 716system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses 717system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses 718system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses | 708system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses 709system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses 710system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses 711system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses 712system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 713system.cpu.l2cache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses 714system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses 715system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses 716system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses 717system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses 718system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses |
| 719system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42469000 # number of ReadReq MSHR miss cycles 720system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15862000 # number of ReadReq MSHR miss cycles 721system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles 722system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 774515250 # number of ReadExReq MSHR miss cycles 723system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles 724system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42469000 # number of demand (read+write) MSHR miss cycles 725system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 790377250 # number of demand (read+write) MSHR miss cycles 726system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles 727system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42469000 # number of overall MSHR miss cycles 728system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 790377250 # number of overall MSHR miss cycles 729system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles | 719system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48659000 # number of ReadReq MSHR miss cycles 720system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18669250 # number of ReadReq MSHR miss cycles 721system.cpu.l2cache.ReadReq_mshr_miss_latency::total 67328250 # number of ReadReq MSHR miss cycles 722system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 892098500 # number of ReadExReq MSHR miss cycles 723system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 892098500 # number of ReadExReq MSHR miss cycles 724system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48659000 # number of demand (read+write) MSHR miss cycles 725system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910767750 # number of demand (read+write) MSHR miss cycles 726system.cpu.l2cache.demand_mshr_miss_latency::total 959426750 # number of demand (read+write) MSHR miss cycles 727system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48659000 # number of overall MSHR miss cycles 728system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910767750 # number of overall MSHR miss cycles 729system.cpu.l2cache.overall_mshr_miss_latency::total 959426750 # number of overall MSHR miss cycles |
| 730system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses 731system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses 732system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses 733system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310982 # mshr miss rate for ReadExReq accesses 734system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses 735system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses 736system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses 737system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 738system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses 739system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses 740system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses | 730system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses 731system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses 732system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses 733system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310982 # mshr miss rate for ReadExReq accesses 734system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses 735system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses 736system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses 737system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 738system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses 739system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses 740system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses |
| 741system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.709677 # average ReadReq mshr miss latency 742system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61960.937500 # average ReadReq mshr miss latency 743system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency 744system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53253.248762 # average ReadExReq mshr miss latency 745system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency 746system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency 747system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency 748system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency 749system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency 750system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency 751system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency | 741system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62785.806452 # average ReadReq mshr miss latency 742system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72926.757812 # average ReadReq mshr miss latency 743system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65303.831232 # average ReadReq mshr miss latency 744system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61337.905666 # average ReadExReq mshr miss latency 745system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61337.905666 # average ReadExReq mshr miss latency 746system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency 747system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency 748system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency 749system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency 750system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency 751system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency |
| 752system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 753system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution 754system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution 755system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution 756system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution 757system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution 758system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) 759system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes) 760system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes) 761system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) 762system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes) 763system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) 764system.cpu.toL2Bus.snoops 0 # Total snoops (count) 765system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram | 752system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 753system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution 754system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution 755system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution 756system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution 757system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution 758system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) 759system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes) 760system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes) 761system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) 762system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes) 763system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) 764system.cpu.toL2Bus.snoops 0 # Total snoops (count) 765system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram |
| 766system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram | 766system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram |
| 767system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 768system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 769system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 770system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 771system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 767system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 768system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 769system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 770system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 771system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 772system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 773system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 774system.cpu.toL2Bus.snoop_fanout::5 1894292 100.00% 100.00% # Request fanout histogram 775system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram | 772system.cpu.toL2Bus.snoop_fanout::3 1894292 100.00% 100.00% # Request fanout histogram 773system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram |
| 776system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 774system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 777system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 778system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram | 775system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 776system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram |
| 779system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram 780system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks) 781system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) | 777system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram 778system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks) 779system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) |
| 782system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks) | 780system.cpu.toL2Bus.respLayer0.occupancy 1372497 # Layer occupancy (ticks) |
| 783system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 781system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 784system.cpu.toL2Bus.respLayer1.occupancy 1428672244 # Layer occupancy (ticks) | 782system.cpu.toL2Bus.respLayer1.occupancy 1428682244 # Layer occupancy (ticks) |
| 785system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 786system.membus.trans_dist::ReadReq 1031 # Transaction distribution 787system.membus.trans_dist::ReadResp 1031 # Transaction distribution 788system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 789system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 790system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes) 791system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes) 792system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 797system.membus.snoop_fanout::stdev 0 # Request fanout histogram 798system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 799system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram 800system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 801system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 802system.membus.snoop_fanout::min_value 0 # Request fanout histogram 803system.membus.snoop_fanout::max_value 0 # Request fanout histogram 804system.membus.snoop_fanout::total 15575 # Request fanout histogram | 783system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 784system.membus.trans_dist::ReadReq 1031 # Transaction distribution 785system.membus.trans_dist::ReadResp 1031 # Transaction distribution 786system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 787system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 788system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes) 789system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes) 790system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 795system.membus.snoop_fanout::stdev 0 # Request fanout histogram 796system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 797system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram 798system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 799system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 800system.membus.snoop_fanout::min_value 0 # Request fanout histogram 801system.membus.snoop_fanout::max_value 0 # Request fanout histogram 802system.membus.snoop_fanout::total 15575 # Request fanout histogram |
| 805system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks) | 803system.membus.reqLayer0.occupancy 21632500 # Layer occupancy (ticks) |
| 806system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 804system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 807system.membus.respLayer1.occupancy 146201750 # Layer occupancy (ticks) 808system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 805system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks) 806system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 809 810---------- End Simulation Statistics ---------- | 807 808---------- End Simulation Statistics ---------- |