| stats.txt (10585:1c9d5d9417b3) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061494 # Number of seconds simulated 4sim_ticks 61493732000 # Number of ticks simulated 5final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061494 # Number of seconds simulated 4sim_ticks 61493732000 # Number of ticks simulated 5final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 280016 # Simulator instruction rate (inst/s) 8host_op_rate 281410 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 190051649 # Simulator tick rate (ticks/s) 10host_mem_usage 385752 # Number of bytes of host memory used 11host_seconds 323.56 # Real time elapsed on the host | 7host_inst_rate 271090 # Simulator instruction rate (inst/s) 8host_op_rate 272440 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 183993432 # Simulator tick rate (ticks/s) 10host_mem_usage 445016 # Number of bytes of host memory used 11host_seconds 334.22 # Real time elapsed on the host |
| 12sim_insts 90602849 # Number of instructions simulated 13sim_ops 91054080 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 996800 # Number of bytes read from this memory 17system.physmem.bytes_read::total 996800 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory --- 171 unchanged lines hidden (view full) --- 191system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation | 12sim_insts 90602849 # Number of instructions simulated 13sim_ops 91054080 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 996800 # Number of bytes read from this memory 17system.physmem.bytes_read::total 996800 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory --- 171 unchanged lines hidden (view full) --- 191system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation |
| 199system.physmem.totQLat 73246500 # Total ticks spent queuing 200system.physmem.totMemAccLat 365277750 # Total ticks spent from burst creation until serviced by the DRAM | 199system.physmem.totQLat 73247750 # Total ticks spent queuing 200system.physmem.totMemAccLat 365279000 # Total ticks spent from burst creation until serviced by the DRAM |
| 201system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers | 201system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers |
| 202system.physmem.avgQLat 4702.83 # Average queueing delay per DRAM burst | 202system.physmem.avgQLat 4702.91 # Average queueing delay per DRAM burst |
| 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 204system.physmem.avgMemAccLat 23452.83 # Average memory access latency per DRAM burst | 204system.physmem.avgMemAccLat 23452.91 # Average memory access latency per DRAM burst |
| 205system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.13 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 215system.physmem.readRowHits 14031 # Number of row buffer hits during reads 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes 217system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 3948227.51 # Average gap between requests 220system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined | 205system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.13 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 215system.physmem.readRowHits 14031 # Number of row buffer hits during reads 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes 217system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 3948227.51 # Average gap between requests 220system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined |
| 221system.physmem.memoryStateTime::IDLE 56242943250 # Time in different power states 222system.physmem.memoryStateTime::REF 2053220000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 224system.physmem.memoryStateTime::ACT 3193793750 # Time in different power states 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 226system.physmem.actEnergy::0 6320160 # Energy for activate commands per rank (pJ) 227system.physmem.actEnergy::1 5261760 # Energy for activate commands per rank (pJ) 228system.physmem.preEnergy::0 3448500 # Energy for precharge commands per rank (pJ) 229system.physmem.preEnergy::1 2871000 # Energy for precharge commands per rank (pJ) 230system.physmem.readEnergy::0 63663600 # Energy for read commands per rank (pJ) 231system.physmem.readEnergy::1 57462600 # Energy for read commands per rank (pJ) 232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 234system.physmem.refreshEnergy::0 4016098320 # Energy for refresh commands per rank (pJ) 235system.physmem.refreshEnergy::1 4016098320 # Energy for refresh commands per rank (pJ) 236system.physmem.actBackEnergy::0 2490497865 # Energy for active background per rank (pJ) 237system.physmem.actBackEnergy::1 2514078765 # Energy for active background per rank (pJ) 238system.physmem.preBackEnergy::0 34708310250 # Energy for precharge background per rank (pJ) 239system.physmem.preBackEnergy::1 34687625250 # Energy for precharge background per rank (pJ) 240system.physmem.totalEnergy::0 41288338695 # Total energy per rank (pJ) 241system.physmem.totalEnergy::1 41283397695 # Total energy per rank (pJ) 242system.physmem.averagePower::0 671.483256 # Core power per rank (mW) 243system.physmem.averagePower::1 671.402899 # Core power per rank (mW) | 221system.physmem_0.actEnergy 6320160 # Energy for activate commands per rank (pJ) 222system.physmem_0.preEnergy 3448500 # Energy for precharge commands per rank (pJ) 223system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) 224system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 225system.physmem_0.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) 226system.physmem_0.actBackEnergy 2490640650 # Energy for active background per rank (pJ) 227system.physmem_0.preBackEnergy 34708185000 # Energy for precharge background per rank (pJ) 228system.physmem_0.totalEnergy 41288356230 # Total energy per rank (pJ) 229system.physmem_0.averagePower 671.483541 # Core power per rank (mW) 230system.physmem_0.memoryStateTime::IDLE 57732029500 # Time in different power states 231system.physmem_0.memoryStateTime::REF 2053220000 # Time in different power states 232system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 233system.physmem_0.memoryStateTime::ACT 1704707500 # Time in different power states 234system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 235system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) 236system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) 237system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) 238system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 239system.physmem_1.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) 240system.physmem_1.actBackEnergy 2514095865 # Energy for active background per rank (pJ) 241system.physmem_1.preBackEnergy 34687610250 # Energy for precharge background per rank (pJ) 242system.physmem_1.totalEnergy 41283399795 # Total energy per rank (pJ) 243system.physmem_1.averagePower 671.402933 # Core power per rank (mW) 244system.physmem_1.memoryStateTime::IDLE 57698939250 # Time in different power states 245system.physmem_1.memoryStateTime::REF 2053220000 # Time in different power states 246system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 247system.physmem_1.memoryStateTime::ACT 1738589750 # Time in different power states 248system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 244system.cpu.branchPred.lookups 20789429 # Number of BP lookups 245system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted 246system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect 247system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups 248system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits 249system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 250system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage 251system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target. 252system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 253system.cpu_clk_domain.clock 500 # Clock period in ticks | 249system.cpu.branchPred.lookups 20789429 # Number of BP lookups 250system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted 251system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect 252system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups 253system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits 254system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 255system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage 256system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target. 257system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 258system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 259system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 260system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 261system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 262system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 263system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 254system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 255system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 256system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 257system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 258system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 259system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 267system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 268system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 269system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 270system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 271system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 272system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 273system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 274system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 267system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 268system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 269system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 270system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 271system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 272system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 273system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 274system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 280system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 281system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 282system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 283system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 284system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 285system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 286system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 287system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 288system.cpu.dtb.walker.walks 0 # Table walker walks requested 289system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 290system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 291system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 292system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 293system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 294system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 295system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 275system.cpu.dtb.inst_hits 0 # ITB inst hits 276system.cpu.dtb.inst_misses 0 # ITB inst misses 277system.cpu.dtb.read_hits 0 # DTB read hits 278system.cpu.dtb.read_misses 0 # DTB read misses 279system.cpu.dtb.write_hits 0 # DTB write hits 280system.cpu.dtb.write_misses 0 # DTB write misses 281system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 282system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 288system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.dtb.read_accesses 0 # DTB read accesses 291system.cpu.dtb.write_accesses 0 # DTB write accesses 292system.cpu.dtb.inst_accesses 0 # ITB inst accesses 293system.cpu.dtb.hits 0 # DTB hits 294system.cpu.dtb.misses 0 # DTB misses 295system.cpu.dtb.accesses 0 # DTB accesses | 296system.cpu.dtb.inst_hits 0 # ITB inst hits 297system.cpu.dtb.inst_misses 0 # ITB inst misses 298system.cpu.dtb.read_hits 0 # DTB read hits 299system.cpu.dtb.read_misses 0 # DTB read misses 300system.cpu.dtb.write_hits 0 # DTB write hits 301system.cpu.dtb.write_misses 0 # DTB write misses 302system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 303system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 309system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 310system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 311system.cpu.dtb.read_accesses 0 # DTB read accesses 312system.cpu.dtb.write_accesses 0 # DTB write accesses 313system.cpu.dtb.inst_accesses 0 # ITB inst accesses 314system.cpu.dtb.hits 0 # DTB hits 315system.cpu.dtb.misses 0 # DTB misses 316system.cpu.dtb.accesses 0 # DTB accesses |
| 317system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 318system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 319system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 320system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 321system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 322system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 323system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 324system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 296system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 297system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 298system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 299system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 300system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 301system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 302system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 303system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 309system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 310system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 311system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 312system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 313system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 314system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 315system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 316system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 325system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 326system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 327system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 328system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 329system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 330system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 331system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 332system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 338system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 339system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 340system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 341system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 342system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 343system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 344system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 345system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 346system.cpu.itb.walker.walks 0 # Table walker walks requested 347system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 350system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 353system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 317system.cpu.itb.inst_hits 0 # ITB inst hits 318system.cpu.itb.inst_misses 0 # ITB inst misses 319system.cpu.itb.read_hits 0 # DTB read hits 320system.cpu.itb.read_misses 0 # DTB read misses 321system.cpu.itb.write_hits 0 # DTB write hits 322system.cpu.itb.write_misses 0 # DTB write misses 323system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 324system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 53 unchanged lines hidden (view full) --- 378system.cpu.dcache.ReadReq_misses::cpu.inst 914958 # number of ReadReq misses 379system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses 380system.cpu.dcache.WriteReq_misses::cpu.inst 73908 # number of WriteReq misses 381system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses 382system.cpu.dcache.demand_misses::cpu.inst 988866 # number of demand (read+write) misses 383system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses 384system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses 385system.cpu.dcache.overall_misses::total 988866 # number of overall misses | 354system.cpu.itb.inst_hits 0 # ITB inst hits 355system.cpu.itb.inst_misses 0 # ITB inst misses 356system.cpu.itb.read_hits 0 # DTB read hits 357system.cpu.itb.read_misses 0 # DTB read misses 358system.cpu.itb.write_hits 0 # DTB write hits 359system.cpu.itb.write_misses 0 # DTB write misses 360system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 361system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 53 unchanged lines hidden (view full) --- 415system.cpu.dcache.ReadReq_misses::cpu.inst 914958 # number of ReadReq misses 416system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses 417system.cpu.dcache.WriteReq_misses::cpu.inst 73908 # number of WriteReq misses 418system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses 419system.cpu.dcache.demand_misses::cpu.inst 988866 # number of demand (read+write) misses 420system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses 421system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses 422system.cpu.dcache.overall_misses::total 988866 # number of overall misses |
| 386system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910311744 # number of ReadReq miss cycles 387system.cpu.dcache.ReadReq_miss_latency::total 11910311744 # number of ReadReq miss cycles 388system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345697500 # number of WriteReq miss cycles 389system.cpu.dcache.WriteReq_miss_latency::total 2345697500 # number of WriteReq miss cycles 390system.cpu.dcache.demand_miss_latency::cpu.inst 14256009244 # number of demand (read+write) miss cycles 391system.cpu.dcache.demand_miss_latency::total 14256009244 # number of demand (read+write) miss cycles 392system.cpu.dcache.overall_miss_latency::cpu.inst 14256009244 # number of overall miss cycles 393system.cpu.dcache.overall_miss_latency::total 14256009244 # number of overall miss cycles | 423system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910296994 # number of ReadReq miss cycles 424system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles 425system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345727500 # number of WriteReq miss cycles 426system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles 427system.cpu.dcache.demand_miss_latency::cpu.inst 14256024494 # number of demand (read+write) miss cycles 428system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles 429system.cpu.dcache.overall_miss_latency::cpu.inst 14256024494 # number of overall miss cycles 430system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles |
| 394system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses) 395system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) 396system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) 397system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 398system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) 399system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 400system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) 401system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 406system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040640 # miss rate for ReadReq accesses 407system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses 408system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015609 # miss rate for WriteReq accesses 409system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses 410system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses 411system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses 412system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses 413system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses | 431system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses) 432system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) 433system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) 434system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 435system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) 436system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 437system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) 438system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 443system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040640 # miss rate for ReadReq accesses 444system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses 445system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015609 # miss rate for WriteReq accesses 446system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses 447system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses 448system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses 449system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses 450system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses |
| 414system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.331663 # average ReadReq miss latency 415system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.331663 # average ReadReq miss latency 416system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.073010 # average WriteReq miss latency 417system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.073010 # average WriteReq miss latency 418system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency 419system.cpu.dcache.demand_avg_miss_latency::total 14416.522809 # average overall miss latency 420system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency 421system.cpu.dcache.overall_avg_miss_latency::total 14416.522809 # average overall miss latency | 451system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.315542 # average ReadReq miss latency 452system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency 453system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.478920 # average WriteReq miss latency 454system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency 455system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency 456system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency 457system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency 458system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency |
| 422system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 423system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 424system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 425system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 426system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 427system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 428system.cpu.dcache.fast_writes 0 # number of fast writes performed 429system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 440system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903435 # number of ReadReq MSHR misses 441system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses 442system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46768 # number of WriteReq MSHR misses 443system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses 444system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 # number of demand (read+write) MSHR misses 445system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses 446system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses 447system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses | 459system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 460system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 461system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 462system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 463system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 464system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 465system.cpu.dcache.fast_writes 0 # number of fast writes performed 466system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 477system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903435 # number of ReadReq MSHR misses 478system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses 479system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46768 # number of WriteReq MSHR misses 480system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses 481system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 # number of demand (read+write) MSHR misses 482system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses 483system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses 484system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses |
| 448system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958869756 # number of ReadReq MSHR miss cycles 449system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958869756 # number of ReadReq MSHR miss cycles 450system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333434750 # number of WriteReq MSHR miss cycles 451system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333434750 # number of WriteReq MSHR miss cycles 452system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292304506 # number of demand (read+write) MSHR miss cycles 453system.cpu.dcache.demand_mshr_miss_latency::total 11292304506 # number of demand (read+write) MSHR miss cycles 454system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292304506 # number of overall MSHR miss cycles 455system.cpu.dcache.overall_mshr_miss_latency::total 11292304506 # number of overall MSHR miss cycles | 485system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958855506 # number of ReadReq MSHR miss cycles 486system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles 487system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333449750 # number of WriteReq MSHR miss cycles 488system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles 489system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292305256 # number of demand (read+write) MSHR miss cycles 490system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles 491system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292305256 # number of overall MSHR miss cycles 492system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles |
| 456system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses 457system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses 458system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses 459system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses 460system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for demand accesses 461system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses 462system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses 463system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses | 493system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses 494system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses 495system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses 496system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses 497system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for demand accesses 498system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses 499system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses 500system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses |
| 464system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.338432 # average ReadReq mshr miss latency 465system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.338432 # average ReadReq mshr miss latency 466system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28511.690686 # average WriteReq mshr miss latency 467system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28511.690686 # average WriteReq mshr miss latency 468system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency 469system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency 470system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency 471system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency | 501system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.322659 # average ReadReq mshr miss latency 502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency 503system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28512.011418 # average WriteReq mshr miss latency 504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency 505system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency 506system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency 507system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency |
| 472system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 473system.cpu.icache.tags.replacements 5 # number of replacements | 509system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 510system.cpu.icache.tags.replacements 5 # number of replacements |
| 474system.cpu.icache.tags.tagsinuse 690.411179 # Cycle average of tags in use | 511system.cpu.icache.tags.tagsinuse 690.411182 # Cycle average of tags in use |
| 475system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks. 476system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. 477system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks. 478system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 512system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks. 513system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. 514system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks. 515system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 479system.cpu.icache.tags.occ_blocks::cpu.inst 690.411179 # Average occupied blocks per requestor | 516system.cpu.icache.tags.occ_blocks::cpu.inst 690.411182 # Average occupied blocks per requestor |
| 480system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy 481system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy 482system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id 483system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 484system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 485system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id 486system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id 487system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses --- 63 unchanged lines hidden (view full) --- 551system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency 552system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency 553system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency 554system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency 555system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency 556system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency 557system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 558system.cpu.l2cache.tags.replacements 0 # number of replacements | 517system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy 518system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy 519system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id 520system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 521system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 522system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id 523system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id 524system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses --- 63 unchanged lines hidden (view full) --- 588system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency 589system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency 590system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency 591system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency 592system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency 593system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency 594system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 595system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 559system.cpu.l2cache.tags.tagsinuse 10247.121792 # Cycle average of tags in use | 596system.cpu.l2cache.tags.tagsinuse 10247.121902 # Cycle average of tags in use |
| 560system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks. 561system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. 562system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. 563system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 597system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks. 598system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. 599system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. 600system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 564system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236502 # Average occupied blocks per requestor 565system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885290 # Average occupied blocks per requestor | 601system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor 602system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885294 # Average occupied blocks per requestor |
| 566system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy 567system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy 568system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy 569system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id 570system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 571system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 572system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 573system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id --- 14 unchanged lines hidden (view full) --- 588system.cpu.l2cache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses 589system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses 590system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses 591system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses 592system.cpu.l2cache.demand_misses::cpu.inst 15583 # number of demand (read+write) misses 593system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses 594system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses 595system.cpu.l2cache.overall_misses::total 15583 # number of overall misses | 603system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy 604system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy 605system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy 606system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id 607system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 608system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 609system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 610system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id --- 14 unchanged lines hidden (view full) --- 625system.cpu.l2cache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses 626system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses 627system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses 628system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses 629system.cpu.l2cache.demand_misses::cpu.inst 15583 # number of demand (read+write) misses 630system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses 631system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses 632system.cpu.l2cache.overall_misses::total 15583 # number of overall misses |
| 596system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71718500 # number of ReadReq miss cycles 597system.cpu.l2cache.ReadReq_miss_latency::total 71718500 # number of ReadReq miss cycles 598system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958069250 # number of ReadExReq miss cycles 599system.cpu.l2cache.ReadExReq_miss_latency::total 958069250 # number of ReadExReq miss cycles 600system.cpu.l2cache.demand_miss_latency::cpu.inst 1029787750 # number of demand (read+write) miss cycles 601system.cpu.l2cache.demand_miss_latency::total 1029787750 # number of demand (read+write) miss cycles 602system.cpu.l2cache.overall_miss_latency::cpu.inst 1029787750 # number of overall miss cycles 603system.cpu.l2cache.overall_miss_latency::total 1029787750 # number of overall miss cycles | 633system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71704250 # number of ReadReq miss cycles 634system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles 635system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958084250 # number of ReadExReq miss cycles 636system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles 637system.cpu.l2cache.demand_miss_latency::cpu.inst 1029788500 # number of demand (read+write) miss cycles 638system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles 639system.cpu.l2cache.overall_miss_latency::cpu.inst 1029788500 # number of overall miss cycles 640system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles |
| 604system.cpu.l2cache.ReadReq_accesses::cpu.inst 904238 # number of ReadReq accesses(hits+misses) 605system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) 606system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) 607system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses) 608system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46768 # number of ReadExReq accesses(hits+misses) 609system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses) 610system.cpu.l2cache.demand_accesses::cpu.inst 951006 # number of demand (read+write) accesses 611system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses 612system.cpu.l2cache.overall_accesses::cpu.inst 951006 # number of overall (read+write) accesses 613system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses 614system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001149 # miss rate for ReadReq accesses 615system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses 616system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310982 # miss rate for ReadExReq accesses 617system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses 618system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses 619system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses 620system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses 621system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses | 641system.cpu.l2cache.ReadReq_accesses::cpu.inst 904238 # number of ReadReq accesses(hits+misses) 642system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) 643system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) 644system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses) 645system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46768 # number of ReadExReq accesses(hits+misses) 646system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses) 647system.cpu.l2cache.demand_accesses::cpu.inst 951006 # number of demand (read+write) accesses 648system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses 649system.cpu.l2cache.overall_accesses::cpu.inst 951006 # number of overall (read+write) accesses 650system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses 651system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001149 # miss rate for ReadReq accesses 652system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses 653system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310982 # miss rate for ReadExReq accesses 654system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses 655system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses 656system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses 657system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses 658system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses |
| 622system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69026.467757 # average ReadReq miss latency 623system.cpu.l2cache.ReadReq_avg_miss_latency::total 69026.467757 # average ReadReq miss latency 624system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65873.848322 # average ReadExReq miss latency 625system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65873.848322 # average ReadExReq miss latency 626system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency 627system.cpu.l2cache.demand_avg_miss_latency::total 66084.049926 # average overall miss latency 628system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency 629system.cpu.l2cache.overall_avg_miss_latency::total 66084.049926 # average overall miss latency | 659system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69012.752647 # average ReadReq miss latency 660system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency 661system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65874.879675 # average ReadExReq miss latency 662system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency 663system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency 664system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency 665system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency 666system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency |
| 630system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 631system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 633system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 634system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 635system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.l2cache.fast_writes 0 # number of fast writes performed 637system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 644system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1031 # number of ReadReq MSHR misses 645system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses 646system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses 647system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 648system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 # number of demand (read+write) MSHR misses 649system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses 650system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses 651system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses | 667system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 668system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 669system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 670system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 671system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 672system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 673system.cpu.l2cache.fast_writes 0 # number of fast writes performed 674system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 681system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1031 # number of ReadReq MSHR misses 682system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses 683system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses 684system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 685system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 # number of demand (read+write) MSHR misses 686system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses 687system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses 688system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses |
| 652system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58344750 # number of ReadReq MSHR miss cycles 653system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58344750 # number of ReadReq MSHR miss cycles 654system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774500250 # number of ReadExReq MSHR miss cycles 655system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774500250 # number of ReadExReq MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832845000 # number of demand (read+write) MSHR miss cycles 657system.cpu.l2cache.demand_mshr_miss_latency::total 832845000 # number of demand (read+write) MSHR miss cycles 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832845000 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::total 832845000 # number of overall MSHR miss cycles | 689system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58331000 # number of ReadReq MSHR miss cycles 690system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles 691system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774515250 # number of ReadExReq MSHR miss cycles 692system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles 693system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832846250 # number of demand (read+write) MSHR miss cycles 694system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles 695system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832846250 # number of overall MSHR miss cycles 696system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles |
| 660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses 661system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses 662system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses 663system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses 664system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses 665system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 666system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses 667system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses | 697system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses 699system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses 700system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses 701system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses 702system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 703system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses 704system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses |
| 668system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56590.446169 # average ReadReq mshr miss latency 669system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56590.446169 # average ReadReq mshr miss latency 670system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53252.217409 # average ReadExReq mshr miss latency 671system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53252.217409 # average ReadExReq mshr miss latency 672system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency 673system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency 674system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency 675system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency | 705system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577.109602 # average ReadReq mshr miss latency 706system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency 707system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53253.248762 # average ReadExReq mshr miss latency 708system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency 709system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency 710system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency 711system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency 712system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency |
| 676system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 677system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution 678system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution 679system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution 680system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution 681system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution 682system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) 683system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes) --- 16 unchanged lines hidden (view full) --- 700system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 701system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 702system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 703system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram 704system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks) 705system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) 706system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks) 707system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 713system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 714system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution 715system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution 716system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution 717system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution 718system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution 719system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) 720system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes) --- 16 unchanged lines hidden (view full) --- 737system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 738system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 739system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 740system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram 741system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks) 742system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) 743system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks) 744system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 708system.cpu.toL2Bus.respLayer1.occupancy 1428672494 # Layer occupancy (ticks) | 745system.cpu.toL2Bus.respLayer1.occupancy 1428672244 # Layer occupancy (ticks) |
| 709system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 710system.membus.trans_dist::ReadReq 1031 # Transaction distribution 711system.membus.trans_dist::ReadResp 1031 # Transaction distribution 712system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 713system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 714system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes) 715system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes) 716system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 723system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram 724system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 725system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 726system.membus.snoop_fanout::min_value 0 # Request fanout histogram 727system.membus.snoop_fanout::max_value 0 # Request fanout histogram 728system.membus.snoop_fanout::total 15575 # Request fanout histogram 729system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks) 730system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 746system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 747system.membus.trans_dist::ReadReq 1031 # Transaction distribution 748system.membus.trans_dist::ReadResp 1031 # Transaction distribution 749system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 750system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 751system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes) 752system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes) 753system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 760system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram 761system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 762system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 763system.membus.snoop_fanout::min_value 0 # Request fanout histogram 764system.membus.snoop_fanout::max_value 0 # Request fanout histogram 765system.membus.snoop_fanout::total 15575 # Request fanout histogram 766system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks) 767system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 731system.membus.respLayer1.occupancy 146202000 # Layer occupancy (ticks) | 768system.membus.respLayer1.occupancy 146201750 # Layer occupancy (ticks) |
| 732system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 733 734---------- End Simulation Statistics ---------- | 769system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 770 771---------- End Simulation Statistics ---------- |