| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061144 # Number of seconds simulated 4sim_ticks 61144411500 # Number of ticks simulated 5final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061144 # Number of seconds simulated 4sim_ticks 61144411500 # Number of ticks simulated 5final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 253751 # Simulator instruction rate (inst/s) 8host_op_rate 255015 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 171247115 # Simulator tick rate (ticks/s) 10host_mem_usage 451144 # Number of bytes of host memory used 11host_seconds 357.05 # Real time elapsed on the host | 7host_inst_rate 269135 # Simulator instruction rate (inst/s) 8host_op_rate 270476 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 181629122 # Simulator tick rate (ticks/s) 10host_mem_usage 440052 # Number of bytes of host memory used 11host_seconds 336.64 # Real time elapsed on the host |
| 12sim_insts 90602849 # Number of instructions simulated 13sim_ops 91054080 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 996736 # Number of bytes read from this memory 17system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory --- 171 unchanged lines hidden (view full) --- 191system.physmem.bytesPerActivate::256-383 94 6.14% 32.66% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 77 5.03% 37.69% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 65 4.25% 41.93% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 106 6.92% 48.86% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation | 12sim_insts 90602849 # Number of instructions simulated 13sim_ops 91054080 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 996736 # Number of bytes read from this memory 17system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory --- 171 unchanged lines hidden (view full) --- 191system.physmem.bytesPerActivate::256-383 94 6.14% 32.66% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 77 5.03% 37.69% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 65 4.25% 41.93% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 106 6.92% 48.86% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation |
| 199system.physmem.totQLat 71444000 # Total ticks spent queuing 200system.physmem.totMemAccLat 363456500 # Total ticks spent from burst creation until serviced by the DRAM | 199system.physmem.totQLat 71490500 # Total ticks spent queuing 200system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM |
| 201system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers | 201system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers |
| 202system.physmem.avgQLat 4587.39 # Average queueing delay per DRAM burst | 202system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst |
| 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 204system.physmem.avgMemAccLat 23337.39 # Average memory access latency per DRAM burst | 204system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst |
| 205system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.13 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 3926051.34 # Average gap between requests 220system.physmem.pageHitRate 90.11 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 55905599000 # Time in different power states 222system.physmem.memoryStateTime::REF 2041520000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 224system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 205system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.13 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 3926051.34 # Average gap between requests 220system.physmem.pageHitRate 90.11 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 55905599000 # Time in different power states 222system.physmem.memoryStateTime::REF 2041520000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 224system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 226system.membus.throughput 16301343 # Throughput (bytes/s) | |
| 227system.membus.trans_dist::ReadReq 1030 # Transaction distribution 228system.membus.trans_dist::ReadResp 1030 # Transaction distribution 229system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 230system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 231system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) 232system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) | 226system.membus.trans_dist::ReadReq 1030 # Transaction distribution 227system.membus.trans_dist::ReadResp 1030 # Transaction distribution 228system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 229system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) 231system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) |
| 233system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) 234system.membus.tot_pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) 235system.membus.data_through_bus 996736 # Total data (bytes) 236system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 237system.membus.reqLayer0.occupancy 21821000 # Layer occupancy (ticks) | 232system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) 233system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) 234system.membus.snoops 0 # Total snoops (count) 235system.membus.snoop_fanout::samples 15574 # Request fanout histogram 236system.membus.snoop_fanout::mean 0 # Request fanout histogram 237system.membus.snoop_fanout::stdev 0 # Request fanout histogram 238system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 239system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 240system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 241system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 242system.membus.snoop_fanout::min_value 0 # Request fanout histogram 243system.membus.snoop_fanout::max_value 0 # Request fanout histogram 244system.membus.snoop_fanout::total 15574 # Request fanout histogram 245system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks) |
| 238system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 246system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 239system.membus.respLayer1.occupancy 149563500 # Layer occupancy (ticks) | 247system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks) |
| 240system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 241system.cpu_clk_domain.clock 500 # Clock period in ticks | 248system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 249system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 242system.cpu.branchPred.lookups 20748985 # Number of BP lookups 243system.cpu.branchPred.condPredicted 17053333 # Number of conditional branches predicted | 250system.cpu.branchPred.lookups 20748984 # Number of BP lookups 251system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted |
| 244system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect 245system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups 246system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits 247system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 248system.cpu.branchPred.BTBHitPct 98.625162 # BTB Hit Percentage 249system.cpu.branchPred.usedRAS 62305 # Number of times the RAS was used to get a target. 250system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 251system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits --- 85 unchanged lines hidden (view full) --- 337system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 338system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 339system.cpu.committedInsts 90602849 # Number of instructions committed 340system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed 341system.cpu.discardedOps 2027782 # Number of ops (including micro ops) which were discarded before commit 342system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 343system.cpu.cpi 1.349724 # CPI: cycles per instruction 344system.cpu.ipc 0.740892 # IPC: instructions per cycle | 252system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect 253system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups 254system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits 255system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 256system.cpu.branchPred.BTBHitPct 98.625162 # BTB Hit Percentage 257system.cpu.branchPred.usedRAS 62305 # Number of times the RAS was used to get a target. 258system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 259system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits --- 85 unchanged lines hidden (view full) --- 345system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 346system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 347system.cpu.committedInsts 90602849 # Number of instructions committed 348system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed 349system.cpu.discardedOps 2027782 # Number of ops (including micro ops) which were discarded before commit 350system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 351system.cpu.cpi 1.349724 # CPI: cycles per instruction 352system.cpu.ipc 0.740892 # IPC: instructions per cycle |
| 345system.cpu.tickCycles 109176310 # Number of cycles that the object actually ticked 346system.cpu.idleCycles 13112513 # Total number of cycles that the object has spent stopped | 353system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked 354system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped |
| 347system.cpu.icache.tags.replacements 5 # number of replacements | 355system.cpu.icache.tags.replacements 5 # number of replacements |
| 348system.cpu.icache.tags.tagsinuse 690.927528 # Cycle average of tags in use 349system.cpu.icache.tags.total_refs 27773576 # Total number of references to valid blocks. | 356system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use 357system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks. |
| 350system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. | 358system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. |
| 351system.cpu.icache.tags.avg_refs 34587.267746 # Average number of references to valid blocks. | 359system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks. |
| 352system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 360system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 353system.cpu.icache.tags.occ_blocks::cpu.inst 690.927528 # Average occupied blocks per requestor | 361system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor |
| 354system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy 355system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy 356system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id 360system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id | 362system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy 364system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id 368system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id |
| 361system.cpu.icache.tags.tag_accesses 55549561 # Number of tag accesses 362system.cpu.icache.tags.data_accesses 55549561 # Number of data accesses 363system.cpu.icache.ReadReq_hits::cpu.inst 27773576 # number of ReadReq hits 364system.cpu.icache.ReadReq_hits::total 27773576 # number of ReadReq hits 365system.cpu.icache.demand_hits::cpu.inst 27773576 # number of demand (read+write) hits 366system.cpu.icache.demand_hits::total 27773576 # number of demand (read+write) hits 367system.cpu.icache.overall_hits::cpu.inst 27773576 # number of overall hits 368system.cpu.icache.overall_hits::total 27773576 # number of overall hits | 369system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses 370system.cpu.icache.tags.data_accesses 55549557 # Number of data accesses 371system.cpu.icache.ReadReq_hits::cpu.inst 27773574 # number of ReadReq hits 372system.cpu.icache.ReadReq_hits::total 27773574 # number of ReadReq hits 373system.cpu.icache.demand_hits::cpu.inst 27773574 # number of demand (read+write) hits 374system.cpu.icache.demand_hits::total 27773574 # number of demand (read+write) hits 375system.cpu.icache.overall_hits::cpu.inst 27773574 # number of overall hits 376system.cpu.icache.overall_hits::total 27773574 # number of overall hits |
| 369system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses 370system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses 371system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 372system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses 373system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses 374system.cpu.icache.overall_misses::total 803 # number of overall misses | 377system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses 378system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses 379system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 380system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses 381system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses 382system.cpu.icache.overall_misses::total 803 # number of overall misses |
| 375system.cpu.icache.ReadReq_miss_latency::cpu.inst 55308998 # number of ReadReq miss cycles 376system.cpu.icache.ReadReq_miss_latency::total 55308998 # number of ReadReq miss cycles 377system.cpu.icache.demand_miss_latency::cpu.inst 55308998 # number of demand (read+write) miss cycles 378system.cpu.icache.demand_miss_latency::total 55308998 # number of demand (read+write) miss cycles 379system.cpu.icache.overall_miss_latency::cpu.inst 55308998 # number of overall miss cycles 380system.cpu.icache.overall_miss_latency::total 55308998 # number of overall miss cycles 381system.cpu.icache.ReadReq_accesses::cpu.inst 27774379 # number of ReadReq accesses(hits+misses) 382system.cpu.icache.ReadReq_accesses::total 27774379 # number of ReadReq accesses(hits+misses) 383system.cpu.icache.demand_accesses::cpu.inst 27774379 # number of demand (read+write) accesses 384system.cpu.icache.demand_accesses::total 27774379 # number of demand (read+write) accesses 385system.cpu.icache.overall_accesses::cpu.inst 27774379 # number of overall (read+write) accesses 386system.cpu.icache.overall_accesses::total 27774379 # number of overall (read+write) accesses | 383system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles 384system.cpu.icache.ReadReq_miss_latency::total 55313498 # number of ReadReq miss cycles 385system.cpu.icache.demand_miss_latency::cpu.inst 55313498 # number of demand (read+write) miss cycles 386system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles 387system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles 388system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles 389system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses) 390system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses) 391system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses 392system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses 393system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses 394system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses |
| 387system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 388system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 389system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 390system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 391system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 392system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses | 395system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 396system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 397system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 398system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 399system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 400system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses |
| 393system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68877.955168 # average ReadReq miss latency 394system.cpu.icache.ReadReq_avg_miss_latency::total 68877.955168 # average ReadReq miss latency 395system.cpu.icache.demand_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency 396system.cpu.icache.demand_avg_miss_latency::total 68877.955168 # average overall miss latency 397system.cpu.icache.overall_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency 398system.cpu.icache.overall_avg_miss_latency::total 68877.955168 # average overall miss latency | 401system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency 402system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency 403system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency 404system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency 405system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency 406system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency |
| 399system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 400system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 401system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 402system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 403system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 404system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.cpu.icache.fast_writes 0 # number of fast writes performed 406system.cpu.icache.cache_copies 0 # number of cache copies performed 407system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses 408system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses 409system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 410system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses 411system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 412system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses | 407system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 408system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 409system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 410system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 411system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 412system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 413system.cpu.icache.fast_writes 0 # number of fast writes performed 414system.cpu.icache.cache_copies 0 # number of cache copies performed 415system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses 416system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses 417system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 418system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses 419system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 420system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses |
| 413system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53368002 # number of ReadReq MSHR miss cycles 414system.cpu.icache.ReadReq_mshr_miss_latency::total 53368002 # number of ReadReq MSHR miss cycles 415system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53368002 # number of demand (read+write) MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::total 53368002 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53368002 # number of overall MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::total 53368002 # number of overall MSHR miss cycles | 421system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles 422system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles 423system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles 424system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles 425system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles 426system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles |
| 419system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 420system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 421system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 422system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 423system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 424system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses | 427system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 428system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 429system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 430system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 431system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 432system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses |
| 425system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66460.774595 # average ReadReq mshr miss latency 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66460.774595 # average ReadReq mshr miss latency 427system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency 429system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency | 433system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910 # average ReadReq mshr miss latency 434system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910 # average ReadReq mshr miss latency 435system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency 436system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency 437system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency 438system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency |
| 431system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 439system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 432system.cpu.toL2Bus.throughput 1982677223 # Throughput (bytes/s) | |
| 433system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadExReq 46761 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::ReadExResp 46761 # Transaction distribution 438system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843551 # Packet count per connected master and slave (bytes) 440system.cpu.toL2Bus.pkt_count::total 2845157 # Packet count per connected master and slave (bytes) | 440system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution 441system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution 442system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadExReq 46761 # Transaction distribution 444system.cpu.toL2Bus.trans_dist::ReadExResp 46761 # Transaction distribution 445system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843551 # Packet count per connected master and slave (bytes) 447system.cpu.toL2Bus.pkt_count::total 2845157 # Packet count per connected master and slave (bytes) |
| 441system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) 442system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes) 443system.cpu.toL2Bus.tot_pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes) 444system.cpu.toL2Bus.data_through_bus 121229632 # Total data (bytes) 445system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 448system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes) 450system.cpu.toL2Bus.pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes) 451system.cpu.toL2Bus.snoops 0 # Total snoops (count) 452system.cpu.toL2Bus.snoop_fanout::samples 1894213 # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 459system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 461system.cpu.toL2Bus.snoop_fanout::5 1894213 100.00% 100.00% # Request fanout histogram 462system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 463system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 464system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 465system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 466system.cpu.toL2Bus.snoop_fanout::total 1894213 # Request fanout histogram |
| 446system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks) 447system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) | 467system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks) 468system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) |
| 448system.cpu.toL2Bus.respLayer0.occupancy 1371998 # Layer occupancy (ticks) | 469system.cpu.toL2Bus.respLayer0.occupancy 1371498 # Layer occupancy (ticks) |
| 449system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 470system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 450system.cpu.toL2Bus.respLayer1.occupancy 1428578994 # Layer occupancy (ticks) | 471system.cpu.toL2Bus.respLayer1.occupancy 1428579494 # Layer occupancy (ticks) |
| 451system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 452system.cpu.l2cache.tags.replacements 0 # number of replacements | 472system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 473system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 453system.cpu.l2cache.tags.tagsinuse 10264.635484 # Cycle average of tags in use | 474system.cpu.l2cache.tags.tagsinuse 10264.635477 # Cycle average of tags in use |
| 454system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks. 455system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. 456system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks. 457system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 458system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor | 475system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks. 476system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. 477system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks. 478system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 479system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor |
| 459system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976615 # Average occupied blocks per requestor | 480system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976609 # Average occupied blocks per requestor |
| 460system.cpu.l2cache.tags.occ_percent::writebacks 0.286061 # Average percentage of cache occupancy 461system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027190 # Average percentage of cache occupancy 462system.cpu.l2cache.tags.occ_percent::total 0.313252 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id 464system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 465system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id --- 14 unchanged lines hidden (view full) --- 482system.cpu.l2cache.ReadReq_misses::cpu.inst 1038 # number of ReadReq misses 483system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses 484system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses 485system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses 486system.cpu.l2cache.demand_misses::cpu.inst 15582 # number of demand (read+write) misses 487system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses 488system.cpu.l2cache.overall_misses::cpu.inst 15582 # number of overall misses 489system.cpu.l2cache.overall_misses::total 15582 # number of overall misses | 481system.cpu.l2cache.tags.occ_percent::writebacks 0.286061 # Average percentage of cache occupancy 482system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027190 # Average percentage of cache occupancy 483system.cpu.l2cache.tags.occ_percent::total 0.313252 # Average percentage of cache occupancy 484system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id 485system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 486system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 487system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 488system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id --- 14 unchanged lines hidden (view full) --- 503system.cpu.l2cache.ReadReq_misses::cpu.inst 1038 # number of ReadReq misses 504system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses 505system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses 506system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses 507system.cpu.l2cache.demand_misses::cpu.inst 15582 # number of demand (read+write) misses 508system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses 509system.cpu.l2cache.overall_misses::cpu.inst 15582 # number of overall misses 510system.cpu.l2cache.overall_misses::total 15582 # number of overall misses |
| 490system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71727250 # number of ReadReq miss cycles 491system.cpu.l2cache.ReadReq_miss_latency::total 71727250 # number of ReadReq miss cycles 492system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959621000 # number of ReadExReq miss cycles 493system.cpu.l2cache.ReadExReq_miss_latency::total 959621000 # number of ReadExReq miss cycles 494system.cpu.l2cache.demand_miss_latency::cpu.inst 1031348250 # number of demand (read+write) miss cycles 495system.cpu.l2cache.demand_miss_latency::total 1031348250 # number of demand (read+write) miss cycles 496system.cpu.l2cache.overall_miss_latency::cpu.inst 1031348250 # number of overall miss cycles 497system.cpu.l2cache.overall_miss_latency::total 1031348250 # number of overall miss cycles | 511system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71732750 # number of ReadReq miss cycles 512system.cpu.l2cache.ReadReq_miss_latency::total 71732750 # number of ReadReq miss cycles 513system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959611500 # number of ReadExReq miss cycles 514system.cpu.l2cache.ReadExReq_miss_latency::total 959611500 # number of ReadExReq miss cycles 515system.cpu.l2cache.demand_miss_latency::cpu.inst 1031344250 # number of demand (read+write) miss cycles 516system.cpu.l2cache.demand_miss_latency::total 1031344250 # number of demand (read+write) miss cycles 517system.cpu.l2cache.overall_miss_latency::cpu.inst 1031344250 # number of overall miss cycles 518system.cpu.l2cache.overall_miss_latency::total 1031344250 # number of overall miss cycles |
| 498system.cpu.l2cache.ReadReq_accesses::cpu.inst 904183 # number of ReadReq accesses(hits+misses) 499system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses) 500system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses) 501system.cpu.l2cache.Writeback_accesses::total 943269 # number of Writeback accesses(hits+misses) 502system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46761 # number of ReadExReq accesses(hits+misses) 503system.cpu.l2cache.ReadExReq_accesses::total 46761 # number of ReadExReq accesses(hits+misses) 504system.cpu.l2cache.demand_accesses::cpu.inst 950944 # number of demand (read+write) accesses 505system.cpu.l2cache.demand_accesses::total 950944 # number of demand (read+write) accesses 506system.cpu.l2cache.overall_accesses::cpu.inst 950944 # number of overall (read+write) accesses 507system.cpu.l2cache.overall_accesses::total 950944 # number of overall (read+write) accesses 508system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001148 # miss rate for ReadReq accesses 509system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses 510system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.311028 # miss rate for ReadExReq accesses 511system.cpu.l2cache.ReadExReq_miss_rate::total 0.311028 # miss rate for ReadExReq accesses 512system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses 513system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses 514system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses 515system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses | 519system.cpu.l2cache.ReadReq_accesses::cpu.inst 904183 # number of ReadReq accesses(hits+misses) 520system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses) 521system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses) 522system.cpu.l2cache.Writeback_accesses::total 943269 # number of Writeback accesses(hits+misses) 523system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46761 # number of ReadExReq accesses(hits+misses) 524system.cpu.l2cache.ReadExReq_accesses::total 46761 # number of ReadExReq accesses(hits+misses) 525system.cpu.l2cache.demand_accesses::cpu.inst 950944 # number of demand (read+write) accesses 526system.cpu.l2cache.demand_accesses::total 950944 # number of demand (read+write) accesses 527system.cpu.l2cache.overall_accesses::cpu.inst 950944 # number of overall (read+write) accesses 528system.cpu.l2cache.overall_accesses::total 950944 # number of overall (read+write) accesses 529system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001148 # miss rate for ReadReq accesses 530system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses 531system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.311028 # miss rate for ReadExReq accesses 532system.cpu.l2cache.ReadExReq_miss_rate::total 0.311028 # miss rate for ReadExReq accesses 533system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses 534system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses 535system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses 536system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses |
| 516system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69101.396917 # average ReadReq miss latency 517system.cpu.l2cache.ReadReq_avg_miss_latency::total 69101.396917 # average ReadReq miss latency 518system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65980.541804 # average ReadExReq miss latency 519system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65980.541804 # average ReadExReq miss latency 520system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency 521system.cpu.l2cache.demand_avg_miss_latency::total 66188.438583 # average overall miss latency 522system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency 523system.cpu.l2cache.overall_avg_miss_latency::total 66188.438583 # average overall miss latency | 537system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568 # average ReadReq miss latency 538system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568 # average ReadReq miss latency 539system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614 # average ReadExReq miss latency 540system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614 # average ReadExReq miss latency 541system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency 542system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877 # average overall miss latency 543system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency 544system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877 # average overall miss latency |
| 524system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 525system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 526system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 527system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 528system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 529system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 530system.cpu.l2cache.fast_writes 0 # number of fast writes performed 531system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 538system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses 539system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses 540system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses 541system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 542system.cpu.l2cache.demand_mshr_misses::cpu.inst 15574 # number of demand (read+write) MSHR misses 543system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 544system.cpu.l2cache.overall_mshr_misses::cpu.inst 15574 # number of overall MSHR misses 545system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses | 545system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 546system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 547system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 548system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 549system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 550system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 551system.cpu.l2cache.fast_writes 0 # number of fast writes performed 552system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 559system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses 560system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses 561system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses 562system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 563system.cpu.l2cache.demand_mshr_misses::cpu.inst 15574 # number of demand (read+write) MSHR misses 564system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 565system.cpu.l2cache.overall_mshr_misses::cpu.inst 15574 # number of overall MSHR misses 566system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses |
| 546system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58365000 # number of ReadReq MSHR miss cycles 547system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58365000 # number of ReadReq MSHR miss cycles 548system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772683000 # number of ReadExReq MSHR miss cycles 549system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772683000 # number of ReadExReq MSHR miss cycles 550system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831048000 # number of demand (read+write) MSHR miss cycles 551system.cpu.l2cache.demand_mshr_miss_latency::total 831048000 # number of demand (read+write) MSHR miss cycles 552system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831048000 # number of overall MSHR miss cycles 553system.cpu.l2cache.overall_mshr_miss_latency::total 831048000 # number of overall MSHR miss cycles | 567system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58370500 # number of ReadReq MSHR miss cycles 568system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58370500 # number of ReadReq MSHR miss cycles 569system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772672000 # number of ReadExReq MSHR miss cycles 570system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772672000 # number of ReadExReq MSHR miss cycles 571system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831042500 # number of demand (read+write) MSHR miss cycles 572system.cpu.l2cache.demand_mshr_miss_latency::total 831042500 # number of demand (read+write) MSHR miss cycles 573system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831042500 # number of overall MSHR miss cycles 574system.cpu.l2cache.overall_mshr_miss_latency::total 831042500 # number of overall MSHR miss cycles |
| 554system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses 555system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses 556system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses 557system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311028 # mshr miss rate for ReadExReq accesses 558system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses 559system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 560system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses 561system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses | 575system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses 576system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses 577system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses 578system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311028 # mshr miss rate for ReadExReq accesses 579system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses 580system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 581system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses 582system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses |
| 562system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56665.048544 # average ReadReq mshr miss latency 563system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56665.048544 # average ReadReq mshr miss latency 564system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53127.268977 # average ReadExReq mshr miss latency 565system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53127.268977 # average ReadExReq mshr miss latency 566system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency 567system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency 568system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency 569system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency | 583system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56670.388350 # average ReadReq mshr miss latency 584system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56670.388350 # average ReadReq mshr miss latency 585system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651 # average ReadExReq mshr miss latency 586system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651 # average ReadExReq mshr miss latency 587system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency 588system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency 589system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency 590system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency |
| 570system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 571system.cpu.dcache.tags.replacements 946045 # number of replacements 572system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use 573system.cpu.dcache.tags.total_refs 26265609 # Total number of references to valid blocks. 574system.cpu.dcache.tags.sampled_refs 950141 # Sample count of references to valid blocks. 575system.cpu.dcache.tags.avg_refs 27.643907 # Average number of references to valid blocks. 576system.cpu.dcache.tags.warmup_cycle 20427116250 # Cycle when the warmup percentage was hit. 577system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.157159 # Average occupied blocks per requestor --- 23 unchanged lines hidden (view full) --- 601system.cpu.dcache.WriteReq_misses::cpu.inst 73896 # number of WriteReq misses 602system.cpu.dcache.WriteReq_misses::total 73896 # number of WriteReq misses 603system.cpu.dcache.demand_misses::cpu.inst 988793 # number of demand (read+write) misses 604system.cpu.dcache.demand_misses::total 988793 # number of demand (read+write) misses 605system.cpu.dcache.overall_misses::cpu.inst 988793 # number of overall misses 606system.cpu.dcache.overall_misses::total 988793 # number of overall misses 607system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11909486494 # number of ReadReq miss cycles 608system.cpu.dcache.ReadReq_miss_latency::total 11909486494 # number of ReadReq miss cycles | 591system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 592system.cpu.dcache.tags.replacements 946045 # number of replacements 593system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use 594system.cpu.dcache.tags.total_refs 26265609 # Total number of references to valid blocks. 595system.cpu.dcache.tags.sampled_refs 950141 # Sample count of references to valid blocks. 596system.cpu.dcache.tags.avg_refs 27.643907 # Average number of references to valid blocks. 597system.cpu.dcache.tags.warmup_cycle 20427116250 # Cycle when the warmup percentage was hit. 598system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.157159 # Average occupied blocks per requestor --- 23 unchanged lines hidden (view full) --- 622system.cpu.dcache.WriteReq_misses::cpu.inst 73896 # number of WriteReq misses 623system.cpu.dcache.WriteReq_misses::total 73896 # number of WriteReq misses 624system.cpu.dcache.demand_misses::cpu.inst 988793 # number of demand (read+write) misses 625system.cpu.dcache.demand_misses::total 988793 # number of demand (read+write) misses 626system.cpu.dcache.overall_misses::cpu.inst 988793 # number of overall misses 627system.cpu.dcache.overall_misses::total 988793 # number of overall misses 628system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11909486494 # number of ReadReq miss cycles 629system.cpu.dcache.ReadReq_miss_latency::total 11909486494 # number of ReadReq miss cycles |
| 609system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342585500 # number of WriteReq miss cycles 610system.cpu.dcache.WriteReq_miss_latency::total 2342585500 # number of WriteReq miss cycles 611system.cpu.dcache.demand_miss_latency::cpu.inst 14252071994 # number of demand (read+write) miss cycles 612system.cpu.dcache.demand_miss_latency::total 14252071994 # number of demand (read+write) miss cycles 613system.cpu.dcache.overall_miss_latency::cpu.inst 14252071994 # number of overall miss cycles 614system.cpu.dcache.overall_miss_latency::total 14252071994 # number of overall miss cycles | 630system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342568500 # number of WriteReq miss cycles 631system.cpu.dcache.WriteReq_miss_latency::total 2342568500 # number of WriteReq miss cycles 632system.cpu.dcache.demand_miss_latency::cpu.inst 14252054994 # number of demand (read+write) miss cycles 633system.cpu.dcache.demand_miss_latency::total 14252054994 # number of demand (read+write) miss cycles 634system.cpu.dcache.overall_miss_latency::cpu.inst 14252054994 # number of overall miss cycles 635system.cpu.dcache.overall_miss_latency::total 14252054994 # number of overall miss cycles |
| 615system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses) 616system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses) 617system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) 618system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 619system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) 620system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 621system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) 622system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 629system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015606 # miss rate for WriteReq accesses 630system.cpu.dcache.WriteReq_miss_rate::total 0.015606 # miss rate for WriteReq accesses 631system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses 632system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses 633system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses 634system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses 635system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency 636system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency | 636system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses) 637system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses) 638system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) 639system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 640system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) 641system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 642system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) 643system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 650system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015606 # miss rate for WriteReq accesses 651system.cpu.dcache.WriteReq_miss_rate::total 0.015606 # miss rate for WriteReq accesses 652system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses 653system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses 654system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses 655system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses 656system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency 657system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency |
| 637system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31701.113727 # average WriteReq miss latency 638system.cpu.dcache.WriteReq_avg_miss_latency::total 31701.113727 # average WriteReq miss latency 639system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency 640system.cpu.dcache.demand_avg_miss_latency::total 14413.605268 # average overall miss latency 641system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency 642system.cpu.dcache.overall_avg_miss_latency::total 14413.605268 # average overall miss latency | 658system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674 # average WriteReq miss latency 659system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674 # average WriteReq miss latency 660system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency 661system.cpu.dcache.demand_avg_miss_latency::total 14413.588076 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::total 14413.588076 # average overall miss latency |
| 643system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 644system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 645system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 646system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 647system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 648system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 649system.cpu.dcache.fast_writes 0 # number of fast writes performed 650system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 663system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46761 # number of WriteReq MSHR misses 664system.cpu.dcache.WriteReq_mshr_misses::total 46761 # number of WriteReq MSHR misses 665system.cpu.dcache.demand_mshr_misses::cpu.inst 950141 # number of demand (read+write) MSHR misses 666system.cpu.dcache.demand_mshr_misses::total 950141 # number of demand (read+write) MSHR misses 667system.cpu.dcache.overall_mshr_misses::cpu.inst 950141 # number of overall MSHR misses 668system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses 669system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles 670system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles | 664system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 665system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 666system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 667system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 668system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 669system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 670system.cpu.dcache.fast_writes 0 # number of fast writes performed 671system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 684system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46761 # number of WriteReq MSHR misses 685system.cpu.dcache.WriteReq_mshr_misses::total 46761 # number of WriteReq MSHR misses 686system.cpu.dcache.demand_mshr_misses::cpu.inst 950141 # number of demand (read+write) MSHR misses 687system.cpu.dcache.demand_mshr_misses::total 950141 # number of demand (read+write) MSHR misses 688system.cpu.dcache.overall_mshr_misses::cpu.inst 950141 # number of overall MSHR misses 689system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses 690system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles |
| 671system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334905750 # number of WriteReq MSHR miss cycles 672system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334905750 # number of WriteReq MSHR miss cycles 673system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293231006 # number of demand (read+write) MSHR miss cycles 674system.cpu.dcache.demand_mshr_miss_latency::total 11293231006 # number of demand (read+write) MSHR miss cycles 675system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293231006 # number of overall MSHR miss cycles 676system.cpu.dcache.overall_mshr_miss_latency::total 11293231006 # number of overall MSHR miss cycles | 692system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334896250 # number of WriteReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334896250 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293221506 # number of demand (read+write) MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::total 11293221506 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293221506 # number of overall MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::total 11293221506 # number of overall MSHR miss cycles |
| 677system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses 678system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses 679system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses 680system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 681system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for demand accesses 682system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses 683system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for overall accesses 684system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses 685system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency 686system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency | 698system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses 699system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses 700system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses 701system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 702system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for demand accesses 703system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses 704system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for overall accesses 705system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency |
| 687system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.416651 # average WriteReq mshr miss latency 688system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.416651 # average WriteReq mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency 690system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency 692system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency | 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490 # average WriteReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490 # average WriteReq mshr miss latency 710system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency 711system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency 712system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency 713system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency |
| 693system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 694 695---------- End Simulation Statistics ---------- | 714system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 715 716---------- End Simulation Statistics ---------- |