Cross Reference: /gem5/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt

Deleted Added

sdiff udiff text old ( 11754:c209cb86278a ) new ( 11860:67dee11badea )

full compact

3,5c3,5
< sim_seconds 0.062553 # Number of seconds simulated
< sim_ticks 62553193500 # Number of ticks simulated
< final_tick 62553193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.062555 # Number of seconds simulated
> sim_ticks 62555455500 # Number of ticks simulated
> final_tick 62555455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 434587 # Simulator instruction rate (inst/s)
< host_op_rate 436752 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 300043763 # Simulator tick rate (ticks/s)
< host_mem_usage 405580 # Number of bytes of host memory used
< host_seconds 208.48 # Real time elapsed on the host
---
> host_inst_rate 428742 # Simulator instruction rate (inst/s)
> host_op_rate 430877 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 296018745 # Simulator tick rate (ticks/s)
> host_mem_usage 404460 # Number of bytes of host memory used
> host_seconds 211.32 # Real time elapsed on the host
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory
19,22c19,22
< system.physmem.bytes_read::total 996736 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory
24,33c24,33
< system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 790879 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 15143336 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15934214 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 790879 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 790879 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 790879 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 15143336 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 15934214 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15574 # Number of read requests accepted
---
> system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 791873 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 15142788 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15934661 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 791873 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 791873 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 791873 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 15142788 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 15934661 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15575 # Number of read requests accepted
35c35
< system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
37c37
< system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM
40c40
< system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side
51c51
< system.physmem.perBankRdBursts::6 1087 # Per bank write bursts
---
> system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
79c79
< system.physmem.totGap 62553092500 # Total gap between requests
---
> system.physmem.totGap 62555354500 # Total gap between requests
86c86
< system.physmem.readPktSize::6 15574 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 15575 # Read request sizes (log2)
94c94
< system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 15455 # What read queue length does an incoming req see
192,193c192,193
< system.physmem.bytesPerActivate::gmean 437.476336 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 402.605762 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 437.465548 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 402.658643 # Bytes accessed per row activation
195,196c195,196
< system.physmem.bytesPerActivate::128-255 178 11.56% 28.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 79 5.13% 33.51% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::128-255 177 11.49% 28.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 80 5.19% 33.51% # Bytes accessed per row activation
200,201c200,201
< system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::768-895 40 2.60% 50.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 67 4.35% 55.06% # Bytes accessed per row activation
204,207c204,207
< system.physmem.totQLat 211075250 # Total ticks spent queuing
< system.physmem.totMemAccLat 503087750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 13553.05 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 211097500 # Total ticks spent queuing
> system.physmem.totMemAccLat 503128750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 13553.61 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 32303.05 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 32303.61 # Average memory access latency per DRAM burst
220c220
< system.physmem.readRowHits 14027 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 14028 # Number of row buffer hits during reads
224c224
< system.physmem.avgGap 4016507.80 # Average gap between requests
---
> system.physmem.avgGap 4016395.15 # Average gap between requests
228c228
< system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 58540860 # Energy for read commands per rank (pJ)
231,238c231,238
< system.physmem_0.actBackEnergy 136590810 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 8775360 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 736795110 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 212078880 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 14428861800 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 15801707760 # Total energy per rank (pJ)
< system.physmem_0.averagePower 252.612326 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 62230723750 # Total Idle time Per DRAM Rank
---
> system.physmem_0.actBackEnergy 136590240 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 8764320 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 737385060 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 211641120 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 14429375100 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 15802368780 # Total energy per rank (pJ)
> system.physmem_0.averagePower 252.613756 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 62232966250 # Total Idle time Per DRAM Rank
241,244c241,244
< system.physmem_0.memoryStateTime::SREF 60062733500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states
---
> system.physmem_0.memoryStateTime::SREF 60064867500 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 551102250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 223150500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 1617057250 # Time in different power states
250,257c250,257
< system.physmem_1.actBackEnergy 136418100 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 13273920 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 827375520 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 248165280 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 14377479765 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 15920005755 # Total energy per rank (pJ)
< system.physmem_1.averagePower 254.503484 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 62218080000 # Total Idle time Per DRAM Rank
---
> system.physmem_1.actBackEnergy 136410120 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 13262400 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 827323080 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 248273280 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 14377994265 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 15920556885 # Total energy per rank (pJ)
> system.physmem_1.averagePower 254.503090 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 62220218000 # Total Idle time Per DRAM Rank
260,269c260,269
< system.physmem_1.memoryStateTime::SREF 59758619500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 646225750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 203975250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 1814542000 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 20808248 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 8965663 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 8840828 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::SREF 59760759500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 646525750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 203991750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 1814347500 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 20806620 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17114048 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 756880 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 8968258 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 8843232 # Number of BTB hits
271,272c271,272
< system.cpu.branchPred.BTBHitPct 98.607632 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 98.605905 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 61975 # Number of times the RAS was used to get a target.
275,277c275,277
< system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectHits 24793 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 1418 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 666 # Number of mispredicted indirect branches.
279c279
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
309c309
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
339c339
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
369c369
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
400,401c400,401
< system.cpu.pwrStateResidencyTicks::ON 62553193500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 125106387 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 62555455500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 125110911 # number of cpu cycles simulated
406c406
< system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2181045 # Number of ops (including micro ops) which were discarded before commit
408,409c408,409
< system.cpu.cpi 1.380822 # CPI: cycles per instruction
< system.cpu.ipc 0.724206 # IPC: instructions per cycle
---
> system.cpu.cpi 1.380872 # CPI: cycles per instruction
> system.cpu.ipc 0.724180 # IPC: instructions per cycle
449,460c449,460
< system.cpu.tickCycles 110521789 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 14584598 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 946101 # number of replacements
< system.cpu.dcache.tags.tagsinuse 3621.109986 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 26274729 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 27.651875 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3621.109986 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy
---
> system.cpu.tickCycles 110528679 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 14582232 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 946104 # number of replacements
> system.cpu.dcache.tags.tagsinuse 3621.120784 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 26274613 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 950200 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 27.651666 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 20754332500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3621.120784 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.884063 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.884063 # Average percentage of cache occupancy
463,464c463,464
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 2202 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 2198 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 1666 # Occupied blocks per task id
466,472c466,472
< system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 21605780 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 21605780 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 55461064 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 55461064 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 21605665 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 21605665 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4660666 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4660666 # number of WriteReq hits
479,486c479,486
< system.cpu.dcache.demand_hits::cpu.data 26266447 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 26266447 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 26266955 # number of overall hits
< system.cpu.dcache.overall_hits::total 26266955 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 906496 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 906496 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 26266331 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 26266331 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 26266839 # number of overall hits
> system.cpu.dcache.overall_hits::total 26266839 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 906500 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 906500 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 74315 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 74315 # number of WriteReq misses
489,502c489,502
< system.cpu.dcache.demand_misses::cpu.data 980810 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 980810 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 980814 # number of overall misses
< system.cpu.dcache.overall_misses::total 980814 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832179000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11832179000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760205500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2760205500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14592384500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14592384500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14592384500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14592384500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 980815 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 980815 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 980819 # number of overall misses
> system.cpu.dcache.overall_misses::total 980819 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832236000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11832236000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760278000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2760278000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14592514000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14592514000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14592514000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14592514000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 22512165 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 22512165 # number of ReadReq accesses(hits+misses)
511,514c511,514
< system.cpu.dcache.demand_accesses::cpu.data 27247257 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 27247146 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 27247146 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 27247658 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 27247658 # number of overall (read+write) accesses
525,532c525,532
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14877.891233 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14877.830557 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.659680 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.659680 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.945570 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.945570 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.947421 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14877.947421 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.886746 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14877.886746 # average overall miss latency
539,550c539,550
< system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks
< system.cpu.dcache.writebacks::total 943282 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3066 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 3066 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 30616 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 30616 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 30616 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 30616 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks
> system.cpu.dcache.writebacks::total 943285 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3067 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 3067 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27551 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 27551 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 30618 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 30618 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 30618 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 30618 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses
555,562c555,562
< system.cpu.dcache.demand_mshr_misses::cpu.data 950194 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889871500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889871500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596189500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596189500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 950197 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 950197 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 950200 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 950200 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889912000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889912000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596274500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596274500 # number of WriteReq MSHR miss cycles
565,568c565,568
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486061000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12486061000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486231000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12486231000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486186500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12486186500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486356500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12486356500 # number of overall MSHR miss cycles
577,582c577,582
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301 # average WriteReq mshr miss latency
---
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.034873 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.923202 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.923202 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34134.686939 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34134.686939 # average WriteReq mshr miss latency
585,589c585,589
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.629259 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.629259 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.766681 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.766681 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
591,594c591,594
< system.cpu.icache.tags.tagsinuse 689.568187 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 689.583421 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 27839479 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 34712.567332 # Average number of references to valid blocks.
596,599c596,599
< system.cpu.icache.tags.occ_blocks::cpu.inst 689.568187 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 689.583421 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.336711 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.336711 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id
601c601
< system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
604,631c604,631
< system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 27835083 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 27835083 # number of overall hits
< system.cpu.icache.overall_hits::total 27835083 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses
< system.cpu.icache.overall_misses::total 801 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 71410500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 71410500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 71410500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 71410500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 71410500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 27835884 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 27835884 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 27835884 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 27835884 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 27835884 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 27835884 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 55681364 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 55681364 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 27839479 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 27839479 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 27839479 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 27839479 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 27839479 # number of overall hits
> system.cpu.icache.overall_hits::total 27839479 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
> system.cpu.icache.overall_misses::total 802 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 71421000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 71421000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 71421000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 71421000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 71421000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 71421000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 27840281 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 27840281 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 27840281 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 27840281 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 27840281 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 27840281 # number of overall (read+write) accesses
638,643c638,643
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.685393 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 89151.685393 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 89151.685393 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 89151.685393 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89053.615960 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 89053.615960 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 89053.615960 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 89053.615960 # average overall miss latency
652,663c652,663
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 70609500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 70609500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 70609500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70619000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 70619000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70619000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 70619000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70619000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 70619000 # number of overall MSHR miss cycles
670,676c670,676
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.685393 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.685393 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88053.615960 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88053.615960 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88053.615960 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 88053.615960 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88053.615960 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 88053.615960 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
678,681c678,681
< system.cpu.l2cache.tags.tagsinuse 11307.993669 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 11308.105127 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1881379 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 15575 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 120.794799 # Average number of references to valid blocks.
683,688c683,688
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.573080 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.420588 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020586 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.324506 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.345093 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.588306 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.516821 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.324509 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.345096 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15575 # Occupied blocks per task id
691c691
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
694,699c694,699
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475311 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 15191263 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 15191263 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 943285 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 943285 # number of WritebackDirty hits
706,707c706,707
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903170 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 903170 # number of ReadSharedReq hits
---
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903173 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 903173 # number of ReadSharedReq hits
709,710c709,710
< system.cpu.l2cache.demand_hits::cpu.data 935390 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 935417 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 935393 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 935420 # number of demand (read+write) hits
712,713c712,713
< system.cpu.l2cache.overall_hits::cpu.data 935390 # number of overall hits
< system.cpu.l2cache.overall_hits::total 935417 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 935393 # number of overall hits
> system.cpu.l2cache.overall_hits::total 935420 # number of overall hits
716,717c716,717
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 774 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 774 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 775 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 775 # number of ReadCleanReq misses
720c720
< system.cpu.l2cache.demand_misses::cpu.inst 774 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 775 # number of demand (read+write) misses
722,723c722,723
< system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 775 # number of overall misses
725,739c725,739
< system.cpu.l2cache.overall_misses::total 15581 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182247000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1182247000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69101000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 69101000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49237000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 49237000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 69101000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1231484000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1300585000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 69101000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1231484000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1300585000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182333500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1182333500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69109000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 69109000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49239000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 49239000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 69109000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1231572500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1300681500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 69109000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1231572500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1300681500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 943285 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 943285 # number of WritebackDirty accesses(hits+misses)
744,753c744,753
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903433 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 903433 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 950197 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 950998 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 950197 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 950998 # number of overall (read+write) accesses
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903436 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 903436 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 950200 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 951002 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 950200 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 951002 # number of overall (read+write) accesses
756,757c756,757
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966292 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966292 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966334 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966334 # miss rate for ReadCleanReq accesses
760c760
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966292 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966334 # miss rate for demand accesses
762,763c762,763
< system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966334 # miss rate for overall accesses
765,777c765,777
< system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81293.557481 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81293.557481 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89172.903226 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89172.903226 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187220.532319 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187220.532319 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 83473.334617 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 83473.334617 # average overall miss latency
796,797c796,797
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 774 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 774 # number of ReadCleanReq MSHR misses
800c800
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses
802,803c802,803
< system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses
805,817c805,817
< system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036807000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036807000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083041000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 1144338500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083041000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 1144338500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036893500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036893500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61295500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61295500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46236000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46236000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61295500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083129500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 1144425000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61295500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083129500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 1144425000 # number of overall MSHR miss cycles
820,821c820,821
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses
824c824
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses
826,827c826,827
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses
829,843c829,843
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71293.557481 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71293.557481 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79193.152455 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79193.152455 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179906.614786 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179906.614786 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 1897111 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 946125 # Number of requests hitting in the snoop filter with a single holder of the requested data.
848,850c848,850
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 943285 # Transaction distribution
855,862c855,862
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846495 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 2848102 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182656 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 121234240 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 903436 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846504 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 2848113 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183040 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
865c865
< system.cpu.toL2Bus.snoop_fanout::samples 950998 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 951002 # Request fanout histogram
869c869
< system.cpu.toL2Bus.snoop_fanout::0 950832 99.98% 99.98% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 950836 99.98% 99.98% # Request fanout histogram
875,876c875,876
< system.cpu.toL2Bus.snoop_fanout::total 950998 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 1891839000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 951002 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 1891845500 # Layer occupancy (ticks)
878c878
< system.cpu.toL2Bus.respLayer0.occupancy 1201999 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1203499 # Layer occupancy (ticks)
880c880
< system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1425302994 # Layer occupancy (ticks)
882c882
< system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter.
---
> system.membus.snoop_filter.tot_requests 15575 # Total number of requests made to the snoop filter.
888,889c888,889
< system.membus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 1030 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 1031 # Transaction distribution
892,896c892,896
< system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 1031 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes)
899c899
< system.membus.snoop_fanout::samples 15574 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 15575 # Request fanout histogram
903c903
< system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram
908,909c908,909
< system.membus.snoop_fanout::total 15574 # Request fanout histogram
< system.membus.reqLayer0.occupancy 21778500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 15575 # Request fanout histogram
> system.membus.reqLayer0.occupancy 21782500 # Layer occupancy (ticks)
911c911
< system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 82144500 # Layer occupancy (ticks)