4,5c4,5
< sim_ticks 62552970500 # Number of ticks simulated
< final_tick 62552970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 62553193500 # Number of ticks simulated
> final_tick 62553193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 423901 # Simulator instruction rate (inst/s)
< host_op_rate 426012 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 292664487 # Simulator tick rate (ticks/s)
< host_mem_usage 404124 # Number of bytes of host memory used
< host_seconds 213.74 # Real time elapsed on the host
---
> host_inst_rate 434587 # Simulator instruction rate (inst/s)
> host_op_rate 436752 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 300043763 # Simulator tick rate (ticks/s)
> host_mem_usage 405580 # Number of bytes of host memory used
> host_seconds 208.48 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 790882 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 15143390 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15934271 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 790882 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 790882 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 790882 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 15143390 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 15934271 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 790879 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 15143336 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15934214 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 790879 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 790879 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 790879 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 15143336 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 15934214 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 62552869500 # Total gap between requests
---
> system.physmem.totGap 62553092500 # Total gap between requests
204,205c204,205
< system.physmem.totQLat 211081250 # Total ticks spent queuing
< system.physmem.totMemAccLat 503093750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 211075250 # Total ticks spent queuing
> system.physmem.totMemAccLat 503087750 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 13553.44 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13553.05 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 32303.44 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 32303.05 # Average memory access latency per DRAM burst
224c224
< system.physmem.avgGap 4016493.48 # Average gap between requests
---
> system.physmem.avgGap 4016507.80 # Average gap between requests
231,238c231,238
< system.physmem_0.actBackEnergy 136599930 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 8776800 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 736788270 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 212075520 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 14428808400 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 15801654720 # Total energy per rank (pJ)
< system.physmem_0.averagePower 252.612376 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 62230500750 # Total Idle time Per DRAM Rank
---
> system.physmem_0.actBackEnergy 136590810 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 8775360 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 736795110 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 212078880 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 14428861800 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 15801707760 # Total energy per rank (pJ)
> system.physmem_0.averagePower 252.612326 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 62230723750 # Total Idle time Per DRAM Rank
241c241
< system.physmem_0.memoryStateTime::SREF 60062510500 # Time in different power states
---
> system.physmem_0.memoryStateTime::SREF 60062733500 # Time in different power states
250,257c250,257
< system.physmem_1.actBackEnergy 136420380 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 13274400 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 827381220 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 248160000 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 14377425165 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 15919954335 # Total energy per rank (pJ)
< system.physmem_1.averagePower 254.503567 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 62217855000 # Total Idle time Per DRAM Rank
---
> system.physmem_1.actBackEnergy 136418100 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 13273920 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 827375520 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 248165280 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 14377479765 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 15920005755 # Total energy per rank (pJ)
> system.physmem_1.averagePower 254.503484 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 62218080000 # Total Idle time Per DRAM Rank
260,264c260,264
< system.physmem_1.memoryStateTime::SREF 59758396500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 646214750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 203977250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 1814551000 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.physmem_1.memoryStateTime::SREF 59758619500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 646225750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 203975250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 1814542000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
279c279
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
309c309
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
339c339
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
369c369
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
400,401c400,401
< system.cpu.pwrStateResidencyTicks::ON 62552970500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 125105941 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 62553193500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 125106387 # number of cpu cycles simulated
408,409c408,409
< system.cpu.cpi 1.380817 # CPI: cycles per instruction
< system.cpu.ipc 0.724209 # IPC: instructions per cycle
---
> system.cpu.cpi 1.380822 # CPI: cycles per instruction
> system.cpu.ipc 0.724206 # IPC: instructions per cycle
449,451c449,451
< system.cpu.tickCycles 110521627 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 14584314 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 110521789 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 14584598 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
453,454c453,454
< system.cpu.dcache.tags.tagsinuse 3621.108293 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 26274912 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3621.109986 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 26274729 # Total number of references to valid blocks.
456c456
< system.cpu.dcache.tags.avg_refs 27.652068 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 27.651875 # Average number of references to valid blocks.
458c458
< system.cpu.dcache.tags.occ_blocks::cpu.data 3621.108293 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3621.109986 # Average occupied blocks per requestor
468,470c468,470
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 21605963 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 21605963 # number of ReadReq hits
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 21605780 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 21605780 # number of ReadReq hits
479,484c479,484
< system.cpu.dcache.demand_hits::cpu.data 26266630 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 26266630 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 26267138 # number of overall hits
< system.cpu.dcache.overall_hits::total 26267138 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 906313 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 906313 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 26266447 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 26266447 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 26266955 # number of overall hits
> system.cpu.dcache.overall_hits::total 26266955 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 906496 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 906496 # number of ReadReq misses
489,500c489,500
< system.cpu.dcache.demand_misses::cpu.data 980627 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 980627 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 980631 # number of overall misses
< system.cpu.dcache.overall_misses::total 980631 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11831745500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11831745500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760211000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2760211000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14591956500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14591956500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14591956500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14591956500 # number of overall miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 980810 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 980810 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 980814 # number of overall misses
> system.cpu.dcache.overall_misses::total 980814 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832179000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11832179000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760205500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2760205500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14592384500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14592384500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14592384500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14592384500 # number of overall miss cycles
515,516c515,516
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses
521,532c521,532
< system.cpu.dcache.demand_miss_rate::cpu.data 0.035990 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.035990 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13054.811638 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13054.811638 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.543801 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.543801 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14880.231219 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14880.231219 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14880.170523 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14880.170523 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14877.891233 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14877.830557 # average overall miss latency
541,542c541,542
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2883 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2883 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3066 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 3066 # number of ReadReq MSHR hits
545,548c545,548
< system.cpu.dcache.demand_mshr_hits::cpu.data 30433 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 30433 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 30433 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 30433 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 30616 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 30616 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 30616 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 30616 # number of overall MSHR hits
559,562c559,562
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889954000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889954000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596188500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596188500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889871500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889871500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596189500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596189500 # number of WriteReq MSHR miss cycles
565,568c565,568
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486142500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12486142500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486312500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12486312500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486061000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12486061000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486231000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12486231000 # number of overall MSHR miss cycles
579,582c579,582
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12054.009719 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12054.009719 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.847917 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.847917 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301 # average WriteReq mshr miss latency
585,589c585,589
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.624441 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.624441 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.761863 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.761863 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
591c591
< system.cpu.icache.tags.tagsinuse 689.568004 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 689.568187 # Cycle average of tags in use
596c596
< system.cpu.icache.tags.occ_blocks::cpu.inst 689.568004 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 689.568187 # Average occupied blocks per requestor
607c607
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
620,625c620,625
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 71410000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 71410000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 71410000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 71410000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 71410000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 71410500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 71410500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 71410500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 71410500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 71410500 # number of overall miss cycles
638,643c638,643
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.061174 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 89151.061174 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 89151.061174 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 89151.061174 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.685393 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 89151.685393 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 89151.685393 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 89151.685393 # average overall miss latency
658,663c658,663
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 70609000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 70609000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 70609000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 70609500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 70609500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 70609500 # number of overall MSHR miss cycles
670,676c670,676
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.061174 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.061174 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.685393 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.685393 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
678c678
< system.cpu.l2cache.tags.tagsinuse 11307.978899 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 11307.993669 # Cycle average of tags in use
683,684c683,684
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.572897 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.406002 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.573080 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.420588 # Average occupied blocks per requestor
687c687
< system.cpu.l2cache.tags.occ_percent::total 0.345092 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.345093 # Average percentage of cache occupancy
697c697
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
726,729c726,729
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182252000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1182252000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69100500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 69100500 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182247000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1182247000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69101000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 69101000 # number of ReadCleanReq miss cycles
732,737c732,737
< system.cpu.l2cache.demand_miss_latency::cpu.inst 69100500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1231489000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1300589500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 69100500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1231489000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1300589500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 69101000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1231484000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1300585000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 69101000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1231484000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1300585000 # number of overall miss cycles
766,769c766,769
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.953795 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.953795 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.131783 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.131783 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778 # average ReadCleanReq miss latency
772,777c772,777
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 83472.787369 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 83472.787369 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556 # average overall miss latency
806,809c806,809
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036812000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036812000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036807000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036807000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297500 # number of ReadCleanReq MSHR miss cycles
812,817c812,817
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083046000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 1144343000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083046000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 1144343000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083041000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 1144338500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083041000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 1144338500 # number of overall MSHR miss cycles
830,833c830,833
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.953795 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.953795 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79297.542044 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79297.542044 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875 # average ReadCleanReq mshr miss latency
836,841c836,841
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency
848c848
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
888c888
< system.membus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
909c909
< system.membus.reqLayer0.occupancy 21777000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 21778500 # Layer occupancy (ticks)
< sim_ticks 62552970500 # Number of ticks simulated
< final_tick 62552970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 62553193500 # Number of ticks simulated
> final_tick 62553193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 423901 # Simulator instruction rate (inst/s)
< host_op_rate 426012 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 292664487 # Simulator tick rate (ticks/s)
< host_mem_usage 404124 # Number of bytes of host memory used
< host_seconds 213.74 # Real time elapsed on the host
---
> host_inst_rate 434587 # Simulator instruction rate (inst/s)
> host_op_rate 436752 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 300043763 # Simulator tick rate (ticks/s)
> host_mem_usage 405580 # Number of bytes of host memory used
> host_seconds 208.48 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 790882 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 15143390 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15934271 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 790882 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 790882 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 790882 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 15143390 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 15934271 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 790879 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 15143336 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15934214 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 790879 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 790879 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 790879 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 15143336 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 15934214 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 62552869500 # Total gap between requests
---
> system.physmem.totGap 62553092500 # Total gap between requests
204,205c204,205
< system.physmem.totQLat 211081250 # Total ticks spent queuing
< system.physmem.totMemAccLat 503093750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 211075250 # Total ticks spent queuing
> system.physmem.totMemAccLat 503087750 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 13553.44 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13553.05 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 32303.44 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 32303.05 # Average memory access latency per DRAM burst
224c224
< system.physmem.avgGap 4016493.48 # Average gap between requests
---
> system.physmem.avgGap 4016507.80 # Average gap between requests
231,238c231,238
< system.physmem_0.actBackEnergy 136599930 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 8776800 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 736788270 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 212075520 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 14428808400 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 15801654720 # Total energy per rank (pJ)
< system.physmem_0.averagePower 252.612376 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 62230500750 # Total Idle time Per DRAM Rank
---
> system.physmem_0.actBackEnergy 136590810 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 8775360 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 736795110 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 212078880 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 14428861800 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 15801707760 # Total energy per rank (pJ)
> system.physmem_0.averagePower 252.612326 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 62230723750 # Total Idle time Per DRAM Rank
241c241
< system.physmem_0.memoryStateTime::SREF 60062510500 # Time in different power states
---
> system.physmem_0.memoryStateTime::SREF 60062733500 # Time in different power states
250,257c250,257
< system.physmem_1.actBackEnergy 136420380 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 13274400 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 827381220 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 248160000 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 14377425165 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 15919954335 # Total energy per rank (pJ)
< system.physmem_1.averagePower 254.503567 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 62217855000 # Total Idle time Per DRAM Rank
---
> system.physmem_1.actBackEnergy 136418100 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 13273920 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 827375520 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 248165280 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 14377479765 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 15920005755 # Total energy per rank (pJ)
> system.physmem_1.averagePower 254.503484 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 62218080000 # Total Idle time Per DRAM Rank
260,264c260,264
< system.physmem_1.memoryStateTime::SREF 59758396500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 646214750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 203977250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 1814551000 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.physmem_1.memoryStateTime::SREF 59758619500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 646225750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 203975250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 1814542000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
279c279
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
309c309
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
339c339
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
369c369
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
400,401c400,401
< system.cpu.pwrStateResidencyTicks::ON 62552970500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 125105941 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 62553193500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 125106387 # number of cpu cycles simulated
408,409c408,409
< system.cpu.cpi 1.380817 # CPI: cycles per instruction
< system.cpu.ipc 0.724209 # IPC: instructions per cycle
---
> system.cpu.cpi 1.380822 # CPI: cycles per instruction
> system.cpu.ipc 0.724206 # IPC: instructions per cycle
449,451c449,451
< system.cpu.tickCycles 110521627 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 14584314 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 110521789 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 14584598 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
453,454c453,454
< system.cpu.dcache.tags.tagsinuse 3621.108293 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 26274912 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3621.109986 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 26274729 # Total number of references to valid blocks.
456c456
< system.cpu.dcache.tags.avg_refs 27.652068 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 27.651875 # Average number of references to valid blocks.
458c458
< system.cpu.dcache.tags.occ_blocks::cpu.data 3621.108293 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3621.109986 # Average occupied blocks per requestor
468,470c468,470
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 21605963 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 21605963 # number of ReadReq hits
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 21605780 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 21605780 # number of ReadReq hits
479,484c479,484
< system.cpu.dcache.demand_hits::cpu.data 26266630 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 26266630 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 26267138 # number of overall hits
< system.cpu.dcache.overall_hits::total 26267138 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 906313 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 906313 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 26266447 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 26266447 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 26266955 # number of overall hits
> system.cpu.dcache.overall_hits::total 26266955 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 906496 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 906496 # number of ReadReq misses
489,500c489,500
< system.cpu.dcache.demand_misses::cpu.data 980627 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 980627 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 980631 # number of overall misses
< system.cpu.dcache.overall_misses::total 980631 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11831745500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11831745500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760211000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2760211000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14591956500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14591956500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14591956500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14591956500 # number of overall miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 980810 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 980810 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 980814 # number of overall misses
> system.cpu.dcache.overall_misses::total 980814 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832179000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11832179000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760205500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2760205500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14592384500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14592384500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14592384500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14592384500 # number of overall miss cycles
515,516c515,516
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses
521,532c521,532
< system.cpu.dcache.demand_miss_rate::cpu.data 0.035990 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.035990 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13054.811638 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13054.811638 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.543801 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.543801 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14880.231219 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14880.231219 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14880.170523 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14880.170523 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14877.891233 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14877.830557 # average overall miss latency
541,542c541,542
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2883 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2883 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3066 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 3066 # number of ReadReq MSHR hits
545,548c545,548
< system.cpu.dcache.demand_mshr_hits::cpu.data 30433 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 30433 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 30433 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 30433 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 30616 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 30616 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 30616 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 30616 # number of overall MSHR hits
559,562c559,562
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889954000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889954000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596188500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596188500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889871500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889871500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596189500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596189500 # number of WriteReq MSHR miss cycles
565,568c565,568
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486142500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12486142500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486312500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12486312500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486061000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12486061000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486231000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12486231000 # number of overall MSHR miss cycles
579,582c579,582
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12054.009719 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12054.009719 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.847917 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.847917 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301 # average WriteReq mshr miss latency
585,589c585,589
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.624441 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.624441 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.761863 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.761863 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
591c591
< system.cpu.icache.tags.tagsinuse 689.568004 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 689.568187 # Cycle average of tags in use
596c596
< system.cpu.icache.tags.occ_blocks::cpu.inst 689.568004 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 689.568187 # Average occupied blocks per requestor
607c607
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
620,625c620,625
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 71410000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 71410000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 71410000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 71410000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 71410000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 71410500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 71410500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 71410500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 71410500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 71410500 # number of overall miss cycles
638,643c638,643
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.061174 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 89151.061174 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 89151.061174 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.061174 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 89151.061174 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.685393 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 89151.685393 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 89151.685393 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 89151.685393 # average overall miss latency
658,663c658,663
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 70609000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 70609000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 70609000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 70609500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 70609500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 70609500 # number of overall MSHR miss cycles
670,676c670,676
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.061174 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.061174 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.061174 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.061174 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.685393 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.685393 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
678c678
< system.cpu.l2cache.tags.tagsinuse 11307.978899 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 11307.993669 # Cycle average of tags in use
683,684c683,684
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.572897 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.406002 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.573080 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.420588 # Average occupied blocks per requestor
687c687
< system.cpu.l2cache.tags.occ_percent::total 0.345092 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.345093 # Average percentage of cache occupancy
697c697
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
726,729c726,729
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182252000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1182252000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69100500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 69100500 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182247000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1182247000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69101000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 69101000 # number of ReadCleanReq miss cycles
732,737c732,737
< system.cpu.l2cache.demand_miss_latency::cpu.inst 69100500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1231489000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1300589500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 69100500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1231489000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1300589500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 69101000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1231484000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1300585000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 69101000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1231484000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1300585000 # number of overall miss cycles
766,769c766,769
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.953795 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.953795 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.131783 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.131783 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778 # average ReadCleanReq miss latency
772,777c772,777
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 83472.787369 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.131783 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.379348 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 83472.787369 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556 # average overall miss latency
806,809c806,809
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036812000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036812000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036807000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036807000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297500 # number of ReadCleanReq MSHR miss cycles
812,817c812,817
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083046000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 1144343000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083046000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 1144343000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083041000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 1144338500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083041000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 1144338500 # number of overall MSHR miss cycles
830,833c830,833
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.953795 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.953795 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79297.542044 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79297.542044 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875 # average ReadCleanReq mshr miss latency
836,841c836,841
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79297.542044 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.839605 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.783485 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency
848c848
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
888c888
< system.membus.pwrStateResidencyTicks::UNDEFINED 62552970500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states
909c909
< system.membus.reqLayer0.occupancy 21777000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 21778500 # Layer occupancy (ticks)