3,5c3,5
< sim_seconds 0.062409 # Number of seconds simulated
< sim_ticks 62408957500 # Number of ticks simulated
< final_tick 62408957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.062421 # Number of seconds simulated
> sim_ticks 62420912500 # Number of ticks simulated
> final_tick 62420912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 176281 # Simulator instruction rate (inst/s)
< host_op_rate 177159 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 121425676 # Simulator tick rate (ticks/s)
< host_mem_usage 399932 # Number of bytes of host memory used
< host_seconds 513.97 # Real time elapsed on the host
---
> host_inst_rate 255603 # Simulator instruction rate (inst/s)
> host_op_rate 256876 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 176097831 # Simulator tick rate (ticks/s)
> host_mem_usage 405340 # Number of bytes of host memory used
> host_seconds 354.47 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 792707 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 15178334 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15971041 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 792707 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 792707 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 792707 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 15178334 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 15971041 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 792555 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 15175427 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15967982 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 792555 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 792555 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 792555 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 15175427 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 15967982 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 62408863500 # Total gap between requests
---
> system.physmem.totGap 62420817500 # Total gap between requests
94,95c94,95
< system.physmem.rdQLenPdf::0 15459 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 15458 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see
190,205c190,205
< system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 642.437702 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 437.017774 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 401.182344 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 251 16.20% 16.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 185 11.94% 28.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 90 5.81% 33.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 67 4.33% 38.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 77 4.97% 43.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 93 6.00% 49.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 42 2.71% 51.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 43 2.78% 54.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 701 45.26% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation
< system.physmem.totQLat 75120250 # Total ticks spent queuing
< system.physmem.totMemAccLat 367132750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 645.984416 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 440.038624 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 401.127365 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 251 16.30% 16.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 179 11.62% 27.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 84 5.45% 33.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 75 4.87% 38.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 76 4.94% 43.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 73 4.74% 47.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 57 3.70% 51.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 48 3.12% 54.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 697 45.26% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
> system.physmem.totQLat 72080000 # Total ticks spent queuing
> system.physmem.totMemAccLat 364092500 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 4823.44 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 4628.23 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 23573.44 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 23378.23 # Average memory access latency per DRAM burst
220c220
< system.physmem.readRowHits 14020 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 14024 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads
224,228c224,228
< system.physmem.avgGap 4007246.92 # Average gap between requests
< system.physmem.pageHitRate 90.02 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 6395760 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 3489750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 4008014.48 # Average gap between requests
> system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 6335280 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 3456750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 63648000 # Energy for read commands per rank (pJ)
230,236c230,236
< system.physmem_0.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 2565881505 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 35193459000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 41909107215 # Total energy per rank (pJ)
< system.physmem_0.averagePower 671.544396 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 58537353750 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2083900000 # Time in different power states
---
> system.physmem_0.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2557911195 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 35205114000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 41913082185 # Total energy per rank (pJ)
> system.physmem_0.averagePower 671.524455 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 58558754750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2084160000 # Time in different power states
238c238
< system.physmem_0.memoryStateTime::ACT 1785901250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1773814250 # Time in different power states
240,242c240,242
< system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 5292000 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2887500 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
244,250c244,250
< system.physmem_1.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 2571480045 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 35188548000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 41901860400 # Total energy per rank (pJ)
< system.physmem_1.averagePower 671.428274 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 58529558500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2083900000 # Time in different power states
---
> system.physmem_1.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2600892900 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 35167410750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 41910562710 # Total energy per rank (pJ)
> system.physmem_1.averagePower 671.484088 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 58497118250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2084160000 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 1793609000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1836331750 # Time in different power states
254,256c254,256
< system.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 20808236 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17115622 # Number of conditional branches predicted
---
> system.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 20808241 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17115627 # Number of conditional branches predicted
258,259c258,259
< system.cpu.branchPred.BTBLookups 8965652 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 8840815 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 8965661 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 8840824 # Number of BTB hits
261c261
< system.cpu.branchPred.BTBHitPct 98.607608 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 98.607610 # BTB Hit Percentage
269c269
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
299c299
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
329c329
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
359c359
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
390,391c390,391
< system.cpu.pwrStateResidencyTicks::ON 62408957500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 124817915 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 62420912500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 124841825 # number of cpu cycles simulated
396c396
< system.cpu.discardedOps 2182474 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2182225 # Number of ops (including micro ops) which were discarded before commit
398,399c398,399
< system.cpu.cpi 1.377638 # CPI: cycles per instruction
< system.cpu.ipc 0.725880 # IPC: instructions per cycle
---
> system.cpu.cpi 1.377902 # CPI: cycles per instruction
> system.cpu.ipc 0.725741 # IPC: instructions per cycle
435,437c435,437
< system.cpu.tickCycles 110516717 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 14301198 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 110516273 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 14325552 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
439,440c439,440
< system.cpu.dcache.tags.tagsinuse 3621.431844 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 26274920 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3621.404220 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 26274921 # Total number of references to valid blocks.
442,446c442,446
< system.cpu.dcache.tags.avg_refs 27.652076 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 20702462500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3621.431844 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.884139 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.884139 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.avg_refs 27.652077 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 20706654500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3621.404220 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.884132 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.884132 # Average percentage of cache occupancy
449,450c449,450
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 2203 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 1651 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 2205 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id
452,458c452,458
< system.cpu.dcache.tags.tag_accesses 55461267 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 55461267 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 21605941 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 21605941 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4660697 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4660697 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 55461265 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 55461265 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 21605938 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 21605938 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4660701 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4660701 # number of WriteReq hits
465,472c465,472
< system.cpu.dcache.demand_hits::cpu.data 26266638 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 26266638 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 26267146 # number of overall hits
< system.cpu.dcache.overall_hits::total 26267146 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 906327 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 906327 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 74284 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 74284 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 26266639 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 26266639 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 26267147 # number of overall hits
> system.cpu.dcache.overall_hits::total 26267147 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 906329 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 906329 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 74280 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 74280 # number of WriteReq misses
475,488c475,488
< system.cpu.dcache.demand_misses::cpu.data 980611 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 980611 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 980615 # number of overall misses
< system.cpu.dcache.overall_misses::total 980615 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11805097500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11805097500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2540928500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2540928500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14346026000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14346026000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14346026000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14346026000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 22512268 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 22512268 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 980609 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 980609 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 980613 # number of overall misses
> system.cpu.dcache.overall_misses::total 980613 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11804222500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11804222500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566012000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2566012000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14370234500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14370234500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14370234500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14370234500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 22512267 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 22512267 # number of ReadReq accesses(hits+misses)
497,500c497,500
< system.cpu.dcache.demand_accesses::cpu.data 27247249 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 27247249 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 27247761 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 27247761 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 27247248 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 27247248 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 27247760 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 27247760 # number of overall (read+write) accesses
503,504c503,504
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015687 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.015687 # miss rate for WriteReq accesses
511,518c511,518
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.207789 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.207789 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34205.596091 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34205.596091 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14629.680883 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14629.680883 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14629.621207 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14629.621207 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13024.213613 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13024.213613 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34545.126548 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34545.126548 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.397930 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14654.397930 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.338154 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14654.338154 # average overall miss latency
527,534c527,534
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2897 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2897 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27520 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 27520 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 30417 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 30417 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 30417 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 30417 # number of overall MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2899 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 30415 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 30415 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 30415 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 30415 # number of overall MSHR hits
545,554c545,554
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10863020500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10863020500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1482579500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1482579500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345600000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12345600000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345756000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12345756000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862380000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862380000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1495373500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1495373500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 158000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 158000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12357753500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12357753500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12357911500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12357911500 # number of overall MSHR miss cycles
565,575c565,575
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12024.197226 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12024.197226 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31703.436404 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31703.436404 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.715172 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.715172 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.838327 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.838327 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.488261 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.488261 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31977.022924 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31977.022924 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52666.666667 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52666.666667 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13005.505718 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 13005.505718 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13005.630938 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 13005.630938 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
577,578c577,578
< system.cpu.icache.tags.tagsinuse 689.591924 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 27835291 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 689.589449 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 27835051 # Total number of references to valid blocks.
580c580
< system.cpu.icache.tags.avg_refs 34750.675406 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 34750.375780 # Average number of references to valid blocks.
582,584c582,584
< system.cpu.icache.tags.occ_blocks::cpu.inst 689.591924 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.336715 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.336715 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 689.589449 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.336714 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.336714 # Average percentage of cache occupancy
591,599c591,599
< system.cpu.icache.tags.tag_accesses 55672985 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 55672985 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 27835291 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 27835291 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 27835291 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 27835291 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 27835291 # number of overall hits
< system.cpu.icache.overall_hits::total 27835291 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 55672505 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 55672505 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 27835051 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 27835051 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 27835051 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 27835051 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 27835051 # number of overall hits
> system.cpu.icache.overall_hits::total 27835051 # number of overall hits
606,617c606,617
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 60446000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 60446000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 60446000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 60446000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 60446000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 60446000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 27836092 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 27836092 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 27836092 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 27836092 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 27836092 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 27836092 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 60780500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 60780500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 60780500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 60780500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 60780500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 60780500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 27835852 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 27835852 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 27835852 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 27835852 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 27835852 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 27835852 # number of overall (read+write) accesses
624,629c624,629
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75463.171036 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 75463.171036 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 75463.171036 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 75463.171036 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75880.774032 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 75880.774032 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 75880.774032 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 75880.774032 # average overall miss latency
644,649c644,649
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59645000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 59645000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59645000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 59645000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59645000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 59645000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59979500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 59979500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59979500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 59979500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59979500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 59979500 # number of overall MSHR miss cycles
656,662c656,662
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74463.171036 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74463.171036 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74880.774032 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74880.774032 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
664,667c664,667
< system.cpu.l2cache.tags.tagsinuse 10294.680667 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1834001 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 117.889117 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 11312.672856 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks.
669,672c669,670
< system.cpu.l2cache.tags.occ_blocks::writebacks 9404.439964 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.596313 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 215.644390 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.287001 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.593915 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10638.078941 # Average occupied blocks per requestor
674,676c672,674
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.006581 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.314169 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.324648 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.345235 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id
678,685c676,683
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 15237953 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 15237953 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
714,725c712,723
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1068633000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1068633000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58136500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 58136500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22289000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 22289000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 58136500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1090922000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1149058500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 58136500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1090922000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1149058500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1081439500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1081439500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58471000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 58471000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21652500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 21652500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 58471000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1103092000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1161563000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 58471000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1103092000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1161563000 # number of overall miss cycles
754,765c752,763
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73475.866337 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73475.866337 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75111.757106 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75111.757106 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84749.049430 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84749.049430 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73747.416725 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73747.416725 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74356.401265 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74356.401265 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75543.927649 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75543.927649 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82328.897338 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82328.897338 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74549.964701 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74549.964701 # average overall miss latency
794,805c792,803
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 923193000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 923193000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50340000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50340000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19328000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19328000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50340000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 942521000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 992861000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50340000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 942521000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 992861000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 935999500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 935999500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50673500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50673500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18685500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18685500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50673500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 954685000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 1005358500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50673500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 954685000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 1005358500 # number of overall MSHR miss cycles
818,829c816,827
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63475.866337 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63475.866337 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65122.897801 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65122.897801 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75206.225681 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75206.225681 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64356.401265 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64356.401265 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65554.333765 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65554.333765 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72706.225681 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72706.225681 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency
836c834
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
870c868,874
< system.membus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
891c895
< system.membus.reqLayer0.occupancy 21833000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 21795000 # Layer occupancy (ticks)
893c897
< system.membus.respLayer1.occupancy 82137750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 82138750 # Layer occupancy (ticks)
< sim_seconds 0.062409 # Number of seconds simulated
< sim_ticks 62408957500 # Number of ticks simulated
< final_tick 62408957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.062421 # Number of seconds simulated
> sim_ticks 62420912500 # Number of ticks simulated
> final_tick 62420912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 176281 # Simulator instruction rate (inst/s)
< host_op_rate 177159 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 121425676 # Simulator tick rate (ticks/s)
< host_mem_usage 399932 # Number of bytes of host memory used
< host_seconds 513.97 # Real time elapsed on the host
---
> host_inst_rate 255603 # Simulator instruction rate (inst/s)
> host_op_rate 256876 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 176097831 # Simulator tick rate (ticks/s)
> host_mem_usage 405340 # Number of bytes of host memory used
> host_seconds 354.47 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 792707 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 15178334 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15971041 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 792707 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 792707 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 792707 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 15178334 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 15971041 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 792555 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 15175427 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15967982 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 792555 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 792555 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 792555 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 15175427 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 15967982 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 62408863500 # Total gap between requests
---
> system.physmem.totGap 62420817500 # Total gap between requests
94,95c94,95
< system.physmem.rdQLenPdf::0 15459 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 15458 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see
190,205c190,205
< system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 642.437702 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 437.017774 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 401.182344 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 251 16.20% 16.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 185 11.94% 28.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 90 5.81% 33.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 67 4.33% 38.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 77 4.97% 43.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 93 6.00% 49.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 42 2.71% 51.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 43 2.78% 54.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 701 45.26% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation
< system.physmem.totQLat 75120250 # Total ticks spent queuing
< system.physmem.totMemAccLat 367132750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 645.984416 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 440.038624 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 401.127365 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 251 16.30% 16.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 179 11.62% 27.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 84 5.45% 33.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 75 4.87% 38.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 76 4.94% 43.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 73 4.74% 47.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 57 3.70% 51.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 48 3.12% 54.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 697 45.26% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
> system.physmem.totQLat 72080000 # Total ticks spent queuing
> system.physmem.totMemAccLat 364092500 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 4823.44 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 4628.23 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 23573.44 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 23378.23 # Average memory access latency per DRAM burst
220c220
< system.physmem.readRowHits 14020 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 14024 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads
224,228c224,228
< system.physmem.avgGap 4007246.92 # Average gap between requests
< system.physmem.pageHitRate 90.02 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 6395760 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 3489750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 4008014.48 # Average gap between requests
> system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 6335280 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 3456750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 63648000 # Energy for read commands per rank (pJ)
230,236c230,236
< system.physmem_0.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 2565881505 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 35193459000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 41909107215 # Total energy per rank (pJ)
< system.physmem_0.averagePower 671.544396 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 58537353750 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2083900000 # Time in different power states
---
> system.physmem_0.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2557911195 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 35205114000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 41913082185 # Total energy per rank (pJ)
> system.physmem_0.averagePower 671.524455 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 58558754750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2084160000 # Time in different power states
238c238
< system.physmem_0.memoryStateTime::ACT 1785901250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1773814250 # Time in different power states
240,242c240,242
< system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 5292000 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2887500 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
244,250c244,250
< system.physmem_1.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 2571480045 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 35188548000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 41901860400 # Total energy per rank (pJ)
< system.physmem_1.averagePower 671.428274 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 58529558500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2083900000 # Time in different power states
---
> system.physmem_1.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2600892900 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 35167410750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 41910562710 # Total energy per rank (pJ)
> system.physmem_1.averagePower 671.484088 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 58497118250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2084160000 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 1793609000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1836331750 # Time in different power states
254,256c254,256
< system.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 20808236 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17115622 # Number of conditional branches predicted
---
> system.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 20808241 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17115627 # Number of conditional branches predicted
258,259c258,259
< system.cpu.branchPred.BTBLookups 8965652 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 8840815 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 8965661 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 8840824 # Number of BTB hits
261c261
< system.cpu.branchPred.BTBHitPct 98.607608 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 98.607610 # BTB Hit Percentage
269c269
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
299c299
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
329c329
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
359c359
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
390,391c390,391
< system.cpu.pwrStateResidencyTicks::ON 62408957500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 124817915 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 62420912500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 124841825 # number of cpu cycles simulated
396c396
< system.cpu.discardedOps 2182474 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2182225 # Number of ops (including micro ops) which were discarded before commit
398,399c398,399
< system.cpu.cpi 1.377638 # CPI: cycles per instruction
< system.cpu.ipc 0.725880 # IPC: instructions per cycle
---
> system.cpu.cpi 1.377902 # CPI: cycles per instruction
> system.cpu.ipc 0.725741 # IPC: instructions per cycle
435,437c435,437
< system.cpu.tickCycles 110516717 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 14301198 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 110516273 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 14325552 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
439,440c439,440
< system.cpu.dcache.tags.tagsinuse 3621.431844 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 26274920 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 3621.404220 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 26274921 # Total number of references to valid blocks.
442,446c442,446
< system.cpu.dcache.tags.avg_refs 27.652076 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 20702462500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3621.431844 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.884139 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.884139 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.avg_refs 27.652077 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 20706654500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3621.404220 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.884132 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.884132 # Average percentage of cache occupancy
449,450c449,450
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 2203 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 1651 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 2205 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id
452,458c452,458
< system.cpu.dcache.tags.tag_accesses 55461267 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 55461267 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 21605941 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 21605941 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4660697 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4660697 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 55461265 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 55461265 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 21605938 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 21605938 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4660701 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4660701 # number of WriteReq hits
465,472c465,472
< system.cpu.dcache.demand_hits::cpu.data 26266638 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 26266638 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 26267146 # number of overall hits
< system.cpu.dcache.overall_hits::total 26267146 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 906327 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 906327 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 74284 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 74284 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 26266639 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 26266639 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 26267147 # number of overall hits
> system.cpu.dcache.overall_hits::total 26267147 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 906329 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 906329 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 74280 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 74280 # number of WriteReq misses
475,488c475,488
< system.cpu.dcache.demand_misses::cpu.data 980611 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 980611 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 980615 # number of overall misses
< system.cpu.dcache.overall_misses::total 980615 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11805097500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11805097500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2540928500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2540928500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14346026000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14346026000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14346026000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14346026000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 22512268 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 22512268 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 980609 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 980609 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 980613 # number of overall misses
> system.cpu.dcache.overall_misses::total 980613 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11804222500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11804222500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566012000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2566012000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14370234500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14370234500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14370234500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14370234500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 22512267 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 22512267 # number of ReadReq accesses(hits+misses)
497,500c497,500
< system.cpu.dcache.demand_accesses::cpu.data 27247249 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 27247249 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 27247761 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 27247761 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 27247248 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 27247248 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 27247760 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 27247760 # number of overall (read+write) accesses
503,504c503,504
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015687 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.015687 # miss rate for WriteReq accesses
511,518c511,518
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.207789 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.207789 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34205.596091 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34205.596091 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14629.680883 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14629.680883 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14629.621207 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14629.621207 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13024.213613 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13024.213613 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34545.126548 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34545.126548 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.397930 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14654.397930 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.338154 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14654.338154 # average overall miss latency
527,534c527,534
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2897 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2897 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27520 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 27520 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 30417 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 30417 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 30417 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 30417 # number of overall MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2899 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 30415 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 30415 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 30415 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 30415 # number of overall MSHR hits
545,554c545,554
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10863020500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10863020500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1482579500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1482579500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345600000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12345600000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345756000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12345756000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862380000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862380000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1495373500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1495373500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 158000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 158000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12357753500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12357753500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12357911500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12357911500 # number of overall MSHR miss cycles
565,575c565,575
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12024.197226 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12024.197226 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31703.436404 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31703.436404 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.715172 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.715172 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.838327 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.838327 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.488261 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.488261 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31977.022924 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31977.022924 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52666.666667 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52666.666667 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13005.505718 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 13005.505718 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13005.630938 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 13005.630938 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
577,578c577,578
< system.cpu.icache.tags.tagsinuse 689.591924 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 27835291 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 689.589449 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 27835051 # Total number of references to valid blocks.
580c580
< system.cpu.icache.tags.avg_refs 34750.675406 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 34750.375780 # Average number of references to valid blocks.
582,584c582,584
< system.cpu.icache.tags.occ_blocks::cpu.inst 689.591924 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.336715 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.336715 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 689.589449 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.336714 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.336714 # Average percentage of cache occupancy
591,599c591,599
< system.cpu.icache.tags.tag_accesses 55672985 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 55672985 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 27835291 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 27835291 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 27835291 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 27835291 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 27835291 # number of overall hits
< system.cpu.icache.overall_hits::total 27835291 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 55672505 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 55672505 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 27835051 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 27835051 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 27835051 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 27835051 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 27835051 # number of overall hits
> system.cpu.icache.overall_hits::total 27835051 # number of overall hits
606,617c606,617
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 60446000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 60446000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 60446000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 60446000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 60446000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 60446000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 27836092 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 27836092 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 27836092 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 27836092 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 27836092 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 27836092 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 60780500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 60780500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 60780500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 60780500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 60780500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 60780500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 27835852 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 27835852 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 27835852 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 27835852 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 27835852 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 27835852 # number of overall (read+write) accesses
624,629c624,629
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75463.171036 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 75463.171036 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 75463.171036 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 75463.171036 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75880.774032 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 75880.774032 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 75880.774032 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 75880.774032 # average overall miss latency
644,649c644,649
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59645000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 59645000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59645000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 59645000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59645000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 59645000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59979500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 59979500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59979500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 59979500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59979500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 59979500 # number of overall MSHR miss cycles
656,662c656,662
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74463.171036 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74463.171036 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74880.774032 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74880.774032 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
664,667c664,667
< system.cpu.l2cache.tags.tagsinuse 10294.680667 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1834001 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 117.889117 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 11312.672856 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks.
669,672c669,670
< system.cpu.l2cache.tags.occ_blocks::writebacks 9404.439964 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.596313 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 215.644390 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.287001 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.593915 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10638.078941 # Average occupied blocks per requestor
674,676c672,674
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.006581 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.314169 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.324648 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.345235 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id
678,685c676,683
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 15237953 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 15237953 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
714,725c712,723
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1068633000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1068633000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58136500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 58136500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22289000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 22289000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 58136500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1090922000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1149058500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 58136500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1090922000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1149058500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1081439500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1081439500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58471000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 58471000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21652500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 21652500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 58471000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1103092000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1161563000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 58471000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1103092000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1161563000 # number of overall miss cycles
754,765c752,763
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73475.866337 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73475.866337 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75111.757106 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75111.757106 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84749.049430 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84749.049430 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73747.416725 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73747.416725 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74356.401265 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74356.401265 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75543.927649 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75543.927649 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82328.897338 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82328.897338 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74549.964701 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74549.964701 # average overall miss latency
794,805c792,803
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 923193000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 923193000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50340000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50340000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19328000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19328000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50340000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 942521000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 992861000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50340000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 942521000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 992861000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 935999500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 935999500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50673500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50673500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18685500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18685500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50673500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 954685000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 1005358500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50673500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 954685000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 1005358500 # number of overall MSHR miss cycles
818,829c816,827
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63475.866337 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63475.866337 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65122.897801 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65122.897801 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75206.225681 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75206.225681 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64356.401265 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64356.401265 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65554.333765 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65554.333765 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72706.225681 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72706.225681 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency
836c834
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
870c868,874
< system.membus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
891c895
< system.membus.reqLayer0.occupancy 21833000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 21795000 # Layer occupancy (ticks)
893c897
< system.membus.respLayer1.occupancy 82137750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 82138750 # Layer occupancy (ticks)