4,5c4,5
< sim_ticks 61240850500 # Number of ticks simulated
< final_tick 61240850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 61241011500 # Number of ticks simulated
> final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 182783 # Simulator instruction rate (inst/s)
< host_op_rate 183693 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 123547949 # Simulator tick rate (ticks/s)
< host_mem_usage 442472 # Number of bytes of host memory used
< host_seconds 495.69 # Real time elapsed on the host
---
> host_inst_rate 252391 # Simulator instruction rate (inst/s)
> host_op_rate 253648 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 170598134 # Simulator tick rate (ticks/s)
> host_mem_usage 450980 # Number of bytes of host memory used
> host_seconds 358.98 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 808872 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 15466800 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 16275672 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 808872 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 808872 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 808872 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 15466800 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 16275672 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 808870 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 15466760 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 16275629 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 808870 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 808870 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 808870 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 15466760 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 16275629 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 61240757000 # Total gap between requests
---
> system.physmem.totGap 61240917000 # Total gap between requests
189,204c189,204
< system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 644.601036 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 438.502120 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 402.393837 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 247 16.00% 16.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 189 12.24% 28.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 92 5.96% 34.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 68 4.40% 38.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 69 4.47% 43.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 87 5.63% 48.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 40 2.59% 51.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 47 3.04% 54.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 705 45.66% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation
< system.physmem.totQLat 73458500 # Total ticks spent queuing
< system.physmem.totMemAccLat 365471000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 1543 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 644.935839 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 438.870546 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 402.302511 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 247 16.01% 16.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 187 12.12% 28.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 93 6.03% 34.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 68 4.41% 38.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 69 4.47% 43.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 87 5.64% 48.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation
> system.physmem.totQLat 73241750 # Total ticks spent queuing
> system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 4716.74 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 23466.74 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst
223c223
< system.physmem.avgGap 3932243.29 # Average gap between requests
---
> system.physmem.avgGap 3932253.56 # Average gap between requests
227c227
< system.physmem_0.readEnergy 63780600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
230,234c230,234
< system.physmem_0.actBackEnergy 2494978920 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 34554891750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 41123220960 # Total energy per rank (pJ)
< system.physmem_0.averagePower 671.518851 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 57475186750 # Time in different power states
---
> system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ)
> system.physmem_0.averagePower 671.511702 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1719043250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 5367600 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2928750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
244,248c244,248
< system.physmem_1.actBackEnergy 2555622360 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 34501695750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 41122956060 # Total energy per rank (pJ)
< system.physmem_1.averagePower 671.514525 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 57387265750 # Time in different power states
---
> system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ)
> system.physmem_1.averagePower 671.513254 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1807269750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states
380c380
< system.cpu.numCycles 122481701 # number of cpu cycles simulated
---
> system.cpu.numCycles 122482023 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 2176622 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2176623 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 1.351853 # CPI: cycles per instruction
< system.cpu.ipc 0.739726 # IPC: instructions per cycle
< system.cpu.tickCycles 109255125 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 13226576 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.351856 # CPI: cycles per instruction
> system.cpu.ipc 0.739724 # IPC: instructions per cycle
> system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped
392c392
< system.cpu.dcache.tags.tagsinuse 3616.871508 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 3616.871508 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.883025 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.883025 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3616.872758 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.883026 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.883026 # Average percentage of cache occupancy
401,402c401,402
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 2246 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id
431,438c431,438
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918942500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11918942500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542548000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2542548000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14461490500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14461490500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14461490500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14461490500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles
463,470c463,470
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.220234 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.220234 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34224.172511 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34224.172511 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.128563 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14619.128563 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.069450 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14619.069450 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency
499,502c499,502
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865257500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865257500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481584500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481584500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles
505,508c505,508
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346842000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12346842000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346998500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12346998500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles
519,522c519,522
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.739906 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.739906 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31681.481877 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31681.481877 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency
525,528c525,528
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.076974 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.076974 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.200652 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.200652 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency
531,532c531,532
< system.cpu.icache.tags.tagsinuse 689.439690 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 27770466 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 27770468 # Total number of references to valid blocks.
534c534
< system.cpu.icache.tags.avg_refs 34626.516209 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 34626.518703 # Average number of references to valid blocks.
536,538c536,538
< system.cpu.icache.tags.occ_blocks::cpu.inst 689.439690 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.336640 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.336640 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 689.439811 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.336641 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.336641 # Average percentage of cache occupancy
544,551c544,551
< system.cpu.icache.tags.tag_accesses 55543338 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 55543338 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 27770466 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 27770466 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 27770466 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 27770466 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 27770466 # number of overall hits
< system.cpu.icache.overall_hits::total 27770466 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 55543342 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 55543342 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 27770468 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 27770468 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 27770468 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 27770468 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 27770468 # number of overall hits
> system.cpu.icache.overall_hits::total 27770468 # number of overall hits
558,569c558,569
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 60107000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 60107000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 60107000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 60107000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 60107000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 60107000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 27771268 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 27771268 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 27771268 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 27771268 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 27771268 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 27771268 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 59898000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 59898000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 59898000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 59898000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 59898000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 59898000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 27771270 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 27771270 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 27771270 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 27771270 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 27771270 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 27771270 # number of overall (read+write) accesses
576,581c576,581
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74946.384040 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 74946.384040 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 74946.384040 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 74946.384040 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74685.785536 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74685.785536 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74685.785536 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74685.785536 # average overall miss latency
596,601c596,601
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59305000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 59305000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59305000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 59305000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59305000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 59305000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59096000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 59096000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59096000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 59096000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59096000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 59096000 # number of overall MSHR miss cycles
608,613c608,613
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73946.384040 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73946.384040 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73685.785536 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73685.785536 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency
616c616
< system.cpu.l2cache.tags.tagsinuse 10245.543243 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use
621,623c621,623
< system.cpu.l2cache.tags.occ_blocks::writebacks 9355.642515 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444420 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456307 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor
627c627
< system.cpu.l2cache.tags.occ_percent::total 0.312669 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.312670 # Average percentage of cache occupancy
663,674c663,674
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067640500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1067640500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57828000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 57828000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21914500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 21914500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 57828000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1089555000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1147383000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 57828000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1089555000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1147383000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles
701,712c701,712
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.625138 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.625138 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74520.618557 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74520.618557 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83643.129771 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83643.129771 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73635.155949 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73635.155949 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency
743,754c743,754
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922200500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922200500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49941000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49941000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18963500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18963500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49941000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941164000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 991105000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49941000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941164000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 991105000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles
767,778c767,778
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63407.625138 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63407.625138 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64523.255814 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64523.255814 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74076.171875 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74076.171875 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency
779a780,785
> system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
795,796c801,802
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram
798,799c804,805
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1897097 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram
802c808
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
830c836
< system.membus.reqLayer0.occupancy 21739500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks)
832c838
< system.membus.respLayer1.occupancy 82130500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks)
< sim_ticks 61240850500 # Number of ticks simulated
< final_tick 61240850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 61241011500 # Number of ticks simulated
> final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 182783 # Simulator instruction rate (inst/s)
< host_op_rate 183693 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 123547949 # Simulator tick rate (ticks/s)
< host_mem_usage 442472 # Number of bytes of host memory used
< host_seconds 495.69 # Real time elapsed on the host
---
> host_inst_rate 252391 # Simulator instruction rate (inst/s)
> host_op_rate 253648 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 170598134 # Simulator tick rate (ticks/s)
> host_mem_usage 450980 # Number of bytes of host memory used
> host_seconds 358.98 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 808872 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 15466800 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 16275672 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 808872 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 808872 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 808872 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 15466800 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 16275672 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 808870 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 15466760 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 16275629 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 808870 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 808870 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 808870 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 15466760 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 16275629 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 61240757000 # Total gap between requests
---
> system.physmem.totGap 61240917000 # Total gap between requests
189,204c189,204
< system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 644.601036 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 438.502120 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 402.393837 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 247 16.00% 16.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 189 12.24% 28.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 92 5.96% 34.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 68 4.40% 38.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 69 4.47% 43.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 87 5.63% 48.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 40 2.59% 51.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 47 3.04% 54.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 705 45.66% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation
< system.physmem.totQLat 73458500 # Total ticks spent queuing
< system.physmem.totMemAccLat 365471000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 1543 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 644.935839 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 438.870546 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 402.302511 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 247 16.01% 16.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 187 12.12% 28.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 93 6.03% 34.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 68 4.41% 38.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 69 4.47% 43.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 87 5.64% 48.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation
> system.physmem.totQLat 73241750 # Total ticks spent queuing
> system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 4716.74 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 23466.74 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst
223c223
< system.physmem.avgGap 3932243.29 # Average gap between requests
---
> system.physmem.avgGap 3932253.56 # Average gap between requests
227c227
< system.physmem_0.readEnergy 63780600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
230,234c230,234
< system.physmem_0.actBackEnergy 2494978920 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 34554891750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 41123220960 # Total energy per rank (pJ)
< system.physmem_0.averagePower 671.518851 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 57475186750 # Time in different power states
---
> system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ)
> system.physmem_0.averagePower 671.511702 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1719043250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 5367600 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2928750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
244,248c244,248
< system.physmem_1.actBackEnergy 2555622360 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 34501695750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 41122956060 # Total energy per rank (pJ)
< system.physmem_1.averagePower 671.514525 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 57387265750 # Time in different power states
---
> system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ)
> system.physmem_1.averagePower 671.513254 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1807269750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states
380c380
< system.cpu.numCycles 122481701 # number of cpu cycles simulated
---
> system.cpu.numCycles 122482023 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 2176622 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2176623 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 1.351853 # CPI: cycles per instruction
< system.cpu.ipc 0.739726 # IPC: instructions per cycle
< system.cpu.tickCycles 109255125 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 13226576 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.351856 # CPI: cycles per instruction
> system.cpu.ipc 0.739724 # IPC: instructions per cycle
> system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped
392c392
< system.cpu.dcache.tags.tagsinuse 3616.871508 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 3616.871508 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.883025 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.883025 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 3616.872758 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.883026 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.883026 # Average percentage of cache occupancy
401,402c401,402
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 2246 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id
431,438c431,438
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918942500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11918942500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542548000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2542548000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14461490500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14461490500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14461490500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14461490500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles
463,470c463,470
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.220234 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.220234 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34224.172511 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34224.172511 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.128563 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14619.128563 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.069450 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14619.069450 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency
499,502c499,502
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865257500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865257500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481584500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481584500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles
505,508c505,508
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346842000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12346842000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346998500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12346998500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles
519,522c519,522
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.739906 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.739906 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31681.481877 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31681.481877 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency
525,528c525,528
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.076974 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.076974 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.200652 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.200652 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency
531,532c531,532
< system.cpu.icache.tags.tagsinuse 689.439690 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 27770466 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 27770468 # Total number of references to valid blocks.
534c534
< system.cpu.icache.tags.avg_refs 34626.516209 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 34626.518703 # Average number of references to valid blocks.
536,538c536,538
< system.cpu.icache.tags.occ_blocks::cpu.inst 689.439690 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.336640 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.336640 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 689.439811 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.336641 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.336641 # Average percentage of cache occupancy
544,551c544,551
< system.cpu.icache.tags.tag_accesses 55543338 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 55543338 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 27770466 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 27770466 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 27770466 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 27770466 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 27770466 # number of overall hits
< system.cpu.icache.overall_hits::total 27770466 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 55543342 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 55543342 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 27770468 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 27770468 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 27770468 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 27770468 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 27770468 # number of overall hits
> system.cpu.icache.overall_hits::total 27770468 # number of overall hits
558,569c558,569
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 60107000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 60107000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 60107000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 60107000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 60107000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 60107000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 27771268 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 27771268 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 27771268 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 27771268 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 27771268 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 27771268 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 59898000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 59898000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 59898000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 59898000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 59898000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 59898000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 27771270 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 27771270 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 27771270 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 27771270 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 27771270 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 27771270 # number of overall (read+write) accesses
576,581c576,581
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74946.384040 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 74946.384040 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 74946.384040 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 74946.384040 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74685.785536 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74685.785536 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74685.785536 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74685.785536 # average overall miss latency
596,601c596,601
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59305000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 59305000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59305000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 59305000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59305000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 59305000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59096000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 59096000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59096000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 59096000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59096000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 59096000 # number of overall MSHR miss cycles
608,613c608,613
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73946.384040 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73946.384040 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73685.785536 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73685.785536 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency
616c616
< system.cpu.l2cache.tags.tagsinuse 10245.543243 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use
621,623c621,623
< system.cpu.l2cache.tags.occ_blocks::writebacks 9355.642515 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444420 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456307 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor
627c627
< system.cpu.l2cache.tags.occ_percent::total 0.312669 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.312670 # Average percentage of cache occupancy
663,674c663,674
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067640500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1067640500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57828000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 57828000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21914500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 21914500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 57828000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1089555000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1147383000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 57828000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1089555000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1147383000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles
701,712c701,712
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.625138 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.625138 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74520.618557 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74520.618557 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83643.129771 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83643.129771 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73635.155949 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73635.155949 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency
743,754c743,754
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922200500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922200500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49941000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49941000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18963500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18963500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49941000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941164000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 991105000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49941000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941164000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 991105000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles
767,778c767,778
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63407.625138 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63407.625138 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64523.255814 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64523.255814 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74076.171875 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74076.171875 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency
779a780,785
> system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
795,796c801,802
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram
798,799c804,805
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1897097 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram
802c808
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
830c836
< system.membus.reqLayer0.occupancy 21739500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks)
832c838
< system.membus.respLayer1.occupancy 82130500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks)