3,5c3,5
< sim_seconds 0.061594 # Number of seconds simulated
< sim_ticks 61594138500 # Number of ticks simulated
< final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.061296 # Number of seconds simulated
> sim_ticks 61295518500 # Number of ticks simulated
> final_tick 61295518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,9c7,9
< host_inst_rate 265976 # Simulator instruction rate (inst/s)
< host_op_rate 267300 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 180817037 # Simulator tick rate (ticks/s)
---
> host_inst_rate 265745 # Simulator instruction rate (inst/s)
> host_op_rate 267069 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 179784475 # Simulator tick rate (ticks/s)
11c11
< host_seconds 340.64 # Real time elapsed on the host
---
> host_seconds 340.94 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 804232 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 15378087 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 16182319 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 804232 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 804232 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 804232 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 15378087 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 16182319 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 808150 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 15453006 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 16261156 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 808150 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 808150 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 808150 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 15453006 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 16261156 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 61594044000 # Total gap between requests
---
> system.physmem.totGap 61295424000 # Total gap between requests
189,204c189,204
< system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 646.025974 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 441.784218 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 399.527843 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 247 16.04% 16.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 180 11.69% 27.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 88 5.71% 33.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 68 4.42% 37.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 78 5.06% 42.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 95 6.17% 49.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 49 3.18% 52.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 35 2.27% 54.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 700 45.45% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
< system.physmem.totQLat 76216750 # Total ticks spent queuing
< system.physmem.totMemAccLat 368229250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 651.693517 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 447.533847 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 399.021267 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 238 15.59% 15.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 181 11.85% 27.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 84 5.50% 32.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 68 4.45% 37.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 71 4.65% 42.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 87 5.70% 47.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 52 3.41% 51.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 56 3.67% 54.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 690 45.19% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation
> system.physmem.totQLat 75432750 # Total ticks spent queuing
> system.physmem.totMemAccLat 367445250 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 4893.85 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 4843.51 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 23643.85 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 23593.51 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 16.26 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 16.26 # Average system read bandwidth in MiByte/s
219c219
< system.physmem.readRowHits 14024 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 14042 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads
223,227c223,227
< system.physmem.avgGap 3954927.70 # Average gap between requests
< system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 6327720 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 3452625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 63655800 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 3935753.44 # Average gap between requests
> system.physmem.pageHitRate 90.16 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
229,235c229,235
< system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 2561139675 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 34707076500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 41364361920 # Total energy per rank (pJ)
< system.physmem_0.averagePower 671.614039 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 57728641000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states
---
> system.physmem_0.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2494246185 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 34588236750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 41159350290 # Total energy per rank (pJ)
> system.physmem_0.averagePower 671.511167 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 57530940500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2046720000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1804854500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1716061500 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 5299560 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
243,249c243,249
< system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 2570808870 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 34698594750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 41357767005 # Total energy per rank (pJ)
< system.physmem_1.averagePower 671.506960 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 57715756250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states
---
> system.physmem_1.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2575259145 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 34517172750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 41161458375 # Total energy per rank (pJ)
> system.physmem_1.averagePower 671.545560 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 57412676250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2046720000 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1818578750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1834237500 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 20791997 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17093861 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 766355 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 8982065 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 8866075 # Number of BTB hits
---
> system.cpu.branchPred.lookups 20766617 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17069689 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 765538 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 8958723 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 8857106 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 98.708649 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 62635 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 98.865720 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 62714 # Number of times the RAS was used to get a target.
380c380
< system.cpu.numCycles 123188277 # number of cpu cycles simulated
---
> system.cpu.numCycles 122591037 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 2070154 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2197459 # Number of ops (including micro ops) which were discarded before commit
387,399c387,399
< system.cpu.cpi 1.359651 # CPI: cycles per instruction
< system.cpu.ipc 0.735483 # IPC: instructions per cycle
< system.cpu.tickCycles 109833647 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 13354630 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 946088 # number of replacements
< system.cpu.dcache.tags.tagsinuse 3616.165317 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 26267708 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 950184 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 27.644865 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 20660513250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3616.165317 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.882853 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.882853 # Average percentage of cache occupancy
---
> system.cpu.cpi 1.353059 # CPI: cycles per instruction
> system.cpu.ipc 0.739066 # IPC: instructions per cycle
> system.cpu.tickCycles 109335027 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 13256010 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 946108 # number of replacements
> system.cpu.dcache.tags.tagsinuse 3616.919530 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 26267744 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 950204 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 27.644321 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 20526719250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3616.919530 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.883037 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.883037 # Average percentage of cache occupancy
401,403c401,403
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id
405,410c405,410
< system.cpu.dcache.tags.tag_accesses 55463792 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 55463792 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 21598607 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 21598607 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4660819 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4660819 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 55463926 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 55463926 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 21598657 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 21598657 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4660805 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4660805 # number of WriteReq hits
417,424c417,424
< system.cpu.dcache.demand_hits::cpu.data 26259426 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 26259426 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 26259934 # number of overall hits
< system.cpu.dcache.overall_hits::total 26259934 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 914930 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 914930 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 74162 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 74162 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 26259462 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 26259462 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 26259970 # number of overall hits
> system.cpu.dcache.overall_hits::total 26259970 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 914937 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 914937 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 74176 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 74176 # number of WriteReq misses
427,440c427,440
< system.cpu.dcache.demand_misses::cpu.data 989092 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 989092 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 989096 # number of overall misses
< system.cpu.dcache.overall_misses::total 989096 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918229494 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11918229494 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2567046500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2567046500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14485275994 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14485275994 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14485275994 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14485275994 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 22513537 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 22513537 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 989113 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 989113 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 989117 # number of overall misses
> system.cpu.dcache.overall_misses::total 989117 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11917910744 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11917910744 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566961500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2566961500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14484872244 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14484872244 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14484872244 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14484872244 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 22513594 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 22513594 # number of ReadReq accesses(hits+misses)
449,452c449,452
< system.cpu.dcache.demand_accesses::cpu.data 27248518 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 27248518 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 27249030 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 27249030 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 27248575 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 27248575 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 27249087 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 27249087 # number of overall (read+write) accesses
455,456c455,456
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015663 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.015663 # miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015666 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.015666 # miss rate for WriteReq accesses
459,470c459,470
< system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.036298 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.036298 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.383979 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.383979 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34614.040883 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34614.040883 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14645.023915 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14645.023915 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.964689 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14644.964689 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.036300 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.036300 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.935932 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.935932 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34606.361896 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34606.361896 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.304790 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14644.304790 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.245569 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14644.245569 # average overall miss latency
479,492c479,492
< system.cpu.dcache.writebacks::writebacks 943266 # number of writebacks
< system.cpu.dcache.writebacks::total 943266 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11513 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 11513 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27398 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 27398 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 38911 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 38911 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 38911 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 38911 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903417 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 903417 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 943289 # number of writebacks
> system.cpu.dcache.writebacks::total 943289 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11503 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 11503 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27409 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 27409 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 38912 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 38912 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 38912 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 38912 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903434 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 903434 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses
495,502c495,502
< system.cpu.dcache.demand_mshr_misses::cpu.data 950181 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 950181 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 950184 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 950184 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412913006 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412913006 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464006500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464006500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 950201 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 950201 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 950204 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 950204 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412555256 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412555256 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464079000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464079000 # number of WriteReq MSHR miss cycles
505,508c505,508
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876919506 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11876919506 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877075006 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11877075006 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876634256 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11876634256 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11876789756 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11876789756 # number of overall MSHR miss cycles
511,512c511,512
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses
515,522c515,522
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034870 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.034870 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.142419 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.142419 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31306.271919 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31306.271919 # average WriteReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11525.529542 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11525.529542 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31305.813929 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31305.813929 # average WriteReq mshr miss latency
525,528c525,528
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.639022 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.639022 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.763210 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.763210 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.075728 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.075728 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.199915 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.199915 # average overall mshr miss latency
531,532c531,532
< system.cpu.icache.tags.tagsinuse 690.351832 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 27857021 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 690.424253 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 27792420 # Total number of references to valid blocks.
534c534
< system.cpu.icache.tags.avg_refs 34734.440150 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 34653.890274 # Average number of references to valid blocks.
536,538c536,538
< system.cpu.icache.tags.occ_blocks::cpu.inst 690.351832 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.337086 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.337086 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 690.424253 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.337121 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.337121 # Average percentage of cache occupancy
544,551c544,551
< system.cpu.icache.tags.tag_accesses 55716448 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 55716448 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 27857021 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 27857021 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 27857021 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 27857021 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 27857021 # number of overall hits
< system.cpu.icache.overall_hits::total 27857021 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 55587246 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 55587246 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 27792420 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 27792420 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 27792420 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 27792420 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 27792420 # number of overall hits
> system.cpu.icache.overall_hits::total 27792420 # number of overall hits
558,569c558,569
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 60516997 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 60516997 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 60516997 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 60516997 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 60516997 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 60516997 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 27857823 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 27857823 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 27857823 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 27857823 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 27857823 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 27857823 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 60382998 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 60382998 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 60382998 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 60382998 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 60382998 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 60382998 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 27793222 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 27793222 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 27793222 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 27793222 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 27793222 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 27793222 # number of overall (read+write) accesses
576,581c576,581
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75457.602244 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 75457.602244 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 75457.602244 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 75457.602244 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75290.521197 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 75290.521197 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 75290.521197 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 75290.521197 # average overall miss latency
596,601c596,601
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58977003 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 58977003 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58977003 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 58977003 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58977003 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 58977003 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58841002 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 58841002 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58841002 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 58841002 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58841002 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 58841002 # number of overall MSHR miss cycles
608,613c608,613
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73537.410224 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73537.410224 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73367.832918 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73367.832918 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency
616,617c616,617
< system.cpu.l2cache.tags.tagsinuse 10237.784168 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1831298 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 10245.234608 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1831338 # Total number of references to valid blocks.
619c619
< system.cpu.l2cache.tags.avg_refs 117.715369 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 117.717940 # Average number of references to valid blocks.
621,625c621,625
< system.cpu.l2cache.tags.occ_blocks::writebacks 9347.997887 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.378262 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 215.408019 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.285278 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020580 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 9355.355364 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.450791 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 215.428453 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.285503 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020583 # Average percentage of cache occupancy
627c627
< system.cpu.l2cache.tags.occ_percent::total 0.312432 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.312660 # Average percentage of cache occupancy
632,633c632,633
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13877 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id
635,650c635,650
< system.cpu.l2cache.tags.tag_accesses 15216337 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 15216337 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 903158 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 903183 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 943266 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 943266 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 935378 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 935403 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 935378 # number of overall hits
< system.cpu.l2cache.overall_hits::total 935403 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses
---
> system.cpu.l2cache.tags.tag_accesses 15216684 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 15216684 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 903175 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 903201 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 943289 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 943289 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 935398 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 935424 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 935398 # number of overall hits
> system.cpu.l2cache.overall_hits::total 935424 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 776 # number of ReadReq misses
652c652
< system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses
655c655
< system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 776 # number of demand (read+write) misses
657,658c657,658
< system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses
660,671c660,671
< system.cpu.l2cache.overall_misses::total 15583 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57912500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22184500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 80097000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073519250 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1073519250 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 57912500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1095703750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1153616250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 57912500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1095703750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1153616250 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57766000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21545250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 79311250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073550250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1073550250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 57766000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1095095500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1152861500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 57766000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1095095500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1152861500 # number of overall miss cycles
673,678c673,678
< system.cpu.l2cache.ReadReq_accesses::cpu.data 903420 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 904222 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 943266 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 943266 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.data 903437 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 904239 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 943289 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 943289 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses)
680,681c680,681
< system.cpu.l2cache.demand_accesses::cpu.data 950184 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 950204 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses
683,685c683,685
< system.cpu.l2cache.overall_accesses::cpu.data 950184 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968828 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::cpu.data 950204 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadReq accesses
687,690c687,690
< system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968828 # miss rate for demand accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967581 # miss rate for demand accesses
692,693c692,693
< system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968828 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses
695,706c695,706
< system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74533.462033 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84673.664122 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 77090.471607 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73811.829620 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73811.829620 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74030.433806 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74030.433806 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74440.721649 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82233.778626 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 76407.755299 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73813.961084 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73813.961084 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73986.747529 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73986.747529 # average overall miss latency
715c715
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
717,718c717,718
< system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
720,721c720,721
< system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
723c723
< system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
---
> system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
735,745c735,745
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48052500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18582500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66635000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891707750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891707750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48052500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910290250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 958342750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48052500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910290250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 958342750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 47928250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17945750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65874000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891746250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891746250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47928250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 909692000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 957620250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47928250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 909692000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 957620250 # number of overall MSHR miss cycles
749,750c749,750
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses
753c753
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses
756,767c756,767
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62083.333333 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72587.890625 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64694.174757 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61311.038916 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61311.038916 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61922.803618 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70100.585938 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63955.339806 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61313.686056 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61313.686056 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency
769,773c769,773
< system.cpu.toL2Bus.trans_dist::ReadReq 904222 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 904222 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 943266 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 943289 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution
775,776c775,776
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843634 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 2845238 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843697 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 2845301 # Packet count per connected master and slave (bytes)
778,779c778,779
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121180800 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183552 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 121234880 # Cumulative packet size per connected master and slave (bytes)
781c781
< system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 1894295 # Request fanout histogram
786c786
< system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 1894295 100.00% 100.00% # Request fanout histogram
791,792c791,792
< system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1894295 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 1890436500 # Layer occupancy (ticks)
794c794
< system.cpu.toL2Bus.respLayer0.occupancy 1371497 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1372498 # Layer occupancy (ticks)
796c796
< system.cpu.toL2Bus.respLayer1.occupancy 1428656494 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1428685244 # Layer occupancy (ticks)
817c817
< system.membus.reqLayer0.occupancy 21629000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 21690500 # Layer occupancy (ticks)
819c819
< system.membus.respLayer1.occupancy 82142750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 82133750 # Layer occupancy (ticks)
< sim_seconds 0.061594 # Number of seconds simulated
< sim_ticks 61594138500 # Number of ticks simulated
< final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.061296 # Number of seconds simulated
> sim_ticks 61295518500 # Number of ticks simulated
> final_tick 61295518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,9c7,9
< host_inst_rate 265976 # Simulator instruction rate (inst/s)
< host_op_rate 267300 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 180817037 # Simulator tick rate (ticks/s)
---
> host_inst_rate 265745 # Simulator instruction rate (inst/s)
> host_op_rate 267069 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 179784475 # Simulator tick rate (ticks/s)
11c11
< host_seconds 340.64 # Real time elapsed on the host
---
> host_seconds 340.94 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 804232 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 15378087 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 16182319 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 804232 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 804232 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 804232 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 15378087 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 16182319 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 808150 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 15453006 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 16261156 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 808150 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 808150 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 808150 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 15453006 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 16261156 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 61594044000 # Total gap between requests
---
> system.physmem.totGap 61295424000 # Total gap between requests
189,204c189,204
< system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 646.025974 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 441.784218 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 399.527843 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 247 16.04% 16.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 180 11.69% 27.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 88 5.71% 33.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 68 4.42% 37.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 78 5.06% 42.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 95 6.17% 49.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 49 3.18% 52.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 35 2.27% 54.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 700 45.45% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
< system.physmem.totQLat 76216750 # Total ticks spent queuing
< system.physmem.totMemAccLat 368229250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 651.693517 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 447.533847 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 399.021267 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 238 15.59% 15.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 181 11.85% 27.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 84 5.50% 32.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 68 4.45% 37.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 71 4.65% 42.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 87 5.70% 47.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 52 3.41% 51.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 56 3.67% 54.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 690 45.19% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation
> system.physmem.totQLat 75432750 # Total ticks spent queuing
> system.physmem.totMemAccLat 367445250 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 4893.85 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 4843.51 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 23643.85 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 23593.51 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 16.26 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 16.26 # Average system read bandwidth in MiByte/s
219c219
< system.physmem.readRowHits 14024 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 14042 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads
223,227c223,227
< system.physmem.avgGap 3954927.70 # Average gap between requests
< system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 6327720 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 3452625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 63655800 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 3935753.44 # Average gap between requests
> system.physmem.pageHitRate 90.16 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
229,235c229,235
< system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 2561139675 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 34707076500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 41364361920 # Total energy per rank (pJ)
< system.physmem_0.averagePower 671.614039 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 57728641000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states
---
> system.physmem_0.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 2494246185 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 34588236750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 41159350290 # Total energy per rank (pJ)
> system.physmem_0.averagePower 671.511167 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 57530940500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2046720000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1804854500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1716061500 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 5299560 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
243,249c243,249
< system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 2570808870 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 34698594750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 41357767005 # Total energy per rank (pJ)
< system.physmem_1.averagePower 671.506960 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 57715756250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states
---
> system.physmem_1.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2575259145 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 34517172750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 41161458375 # Total energy per rank (pJ)
> system.physmem_1.averagePower 671.545560 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 57412676250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2046720000 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1818578750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1834237500 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 20791997 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17093861 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 766355 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 8982065 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 8866075 # Number of BTB hits
---
> system.cpu.branchPred.lookups 20766617 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17069689 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 765538 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 8958723 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 8857106 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 98.708649 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 62635 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 98.865720 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 62714 # Number of times the RAS was used to get a target.
380c380
< system.cpu.numCycles 123188277 # number of cpu cycles simulated
---
> system.cpu.numCycles 122591037 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 2070154 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2197459 # Number of ops (including micro ops) which were discarded before commit
387,399c387,399
< system.cpu.cpi 1.359651 # CPI: cycles per instruction
< system.cpu.ipc 0.735483 # IPC: instructions per cycle
< system.cpu.tickCycles 109833647 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 13354630 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 946088 # number of replacements
< system.cpu.dcache.tags.tagsinuse 3616.165317 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 26267708 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 950184 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 27.644865 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 20660513250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 3616.165317 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.882853 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.882853 # Average percentage of cache occupancy
---
> system.cpu.cpi 1.353059 # CPI: cycles per instruction
> system.cpu.ipc 0.739066 # IPC: instructions per cycle
> system.cpu.tickCycles 109335027 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 13256010 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 946108 # number of replacements
> system.cpu.dcache.tags.tagsinuse 3616.919530 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 26267744 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 950204 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 27.644321 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 20526719250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 3616.919530 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.883037 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.883037 # Average percentage of cache occupancy
401,403c401,403
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id
405,410c405,410
< system.cpu.dcache.tags.tag_accesses 55463792 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 55463792 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 21598607 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 21598607 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4660819 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4660819 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 55463926 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 55463926 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 21598657 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 21598657 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4660805 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4660805 # number of WriteReq hits
417,424c417,424
< system.cpu.dcache.demand_hits::cpu.data 26259426 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 26259426 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 26259934 # number of overall hits
< system.cpu.dcache.overall_hits::total 26259934 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 914930 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 914930 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 74162 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 74162 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 26259462 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 26259462 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 26259970 # number of overall hits
> system.cpu.dcache.overall_hits::total 26259970 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 914937 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 914937 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 74176 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 74176 # number of WriteReq misses
427,440c427,440
< system.cpu.dcache.demand_misses::cpu.data 989092 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 989092 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 989096 # number of overall misses
< system.cpu.dcache.overall_misses::total 989096 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918229494 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11918229494 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2567046500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2567046500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 14485275994 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14485275994 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 14485275994 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14485275994 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 22513537 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 22513537 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 989113 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 989113 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 989117 # number of overall misses
> system.cpu.dcache.overall_misses::total 989117 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11917910744 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11917910744 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566961500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2566961500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 14484872244 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14484872244 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 14484872244 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14484872244 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 22513594 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 22513594 # number of ReadReq accesses(hits+misses)
449,452c449,452
< system.cpu.dcache.demand_accesses::cpu.data 27248518 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 27248518 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 27249030 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 27249030 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 27248575 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 27248575 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 27249087 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 27249087 # number of overall (read+write) accesses
455,456c455,456
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015663 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.015663 # miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015666 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.015666 # miss rate for WriteReq accesses
459,470c459,470
< system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.036298 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.036298 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.383979 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.383979 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34614.040883 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34614.040883 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 14645.023915 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14645.023915 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.964689 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14644.964689 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.036300 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.036300 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.935932 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.935932 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34606.361896 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34606.361896 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.304790 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14644.304790 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.245569 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14644.245569 # average overall miss latency
479,492c479,492
< system.cpu.dcache.writebacks::writebacks 943266 # number of writebacks
< system.cpu.dcache.writebacks::total 943266 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11513 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 11513 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27398 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 27398 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 38911 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 38911 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 38911 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 38911 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903417 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 903417 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 943289 # number of writebacks
> system.cpu.dcache.writebacks::total 943289 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11503 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 11503 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27409 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 27409 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 38912 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 38912 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 38912 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 38912 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903434 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 903434 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses
495,502c495,502
< system.cpu.dcache.demand_mshr_misses::cpu.data 950181 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 950181 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 950184 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 950184 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412913006 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412913006 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464006500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464006500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 950201 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 950201 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 950204 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 950204 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412555256 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412555256 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464079000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464079000 # number of WriteReq MSHR miss cycles
505,508c505,508
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876919506 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11876919506 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877075006 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11877075006 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876634256 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11876634256 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11876789756 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11876789756 # number of overall MSHR miss cycles
511,512c511,512
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses
515,522c515,522
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034870 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.034870 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.142419 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.142419 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31306.271919 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31306.271919 # average WriteReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11525.529542 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11525.529542 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31305.813929 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31305.813929 # average WriteReq mshr miss latency
525,528c525,528
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.639022 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.639022 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.763210 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.763210 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.075728 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.075728 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.199915 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.199915 # average overall mshr miss latency
531,532c531,532
< system.cpu.icache.tags.tagsinuse 690.351832 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 27857021 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 690.424253 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 27792420 # Total number of references to valid blocks.
534c534
< system.cpu.icache.tags.avg_refs 34734.440150 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 34653.890274 # Average number of references to valid blocks.
536,538c536,538
< system.cpu.icache.tags.occ_blocks::cpu.inst 690.351832 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.337086 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.337086 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 690.424253 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.337121 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.337121 # Average percentage of cache occupancy
544,551c544,551
< system.cpu.icache.tags.tag_accesses 55716448 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 55716448 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 27857021 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 27857021 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 27857021 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 27857021 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 27857021 # number of overall hits
< system.cpu.icache.overall_hits::total 27857021 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 55587246 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 55587246 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 27792420 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 27792420 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 27792420 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 27792420 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 27792420 # number of overall hits
> system.cpu.icache.overall_hits::total 27792420 # number of overall hits
558,569c558,569
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 60516997 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 60516997 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 60516997 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 60516997 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 60516997 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 60516997 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 27857823 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 27857823 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 27857823 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 27857823 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 27857823 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 27857823 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 60382998 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 60382998 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 60382998 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 60382998 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 60382998 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 60382998 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 27793222 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 27793222 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 27793222 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 27793222 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 27793222 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 27793222 # number of overall (read+write) accesses
576,581c576,581
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75457.602244 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 75457.602244 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 75457.602244 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 75457.602244 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75290.521197 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 75290.521197 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 75290.521197 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 75290.521197 # average overall miss latency
596,601c596,601
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58977003 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 58977003 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58977003 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 58977003 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58977003 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 58977003 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58841002 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 58841002 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58841002 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 58841002 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58841002 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 58841002 # number of overall MSHR miss cycles
608,613c608,613
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73537.410224 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73537.410224 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73367.832918 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73367.832918 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency
616,617c616,617
< system.cpu.l2cache.tags.tagsinuse 10237.784168 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1831298 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 10245.234608 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1831338 # Total number of references to valid blocks.
619c619
< system.cpu.l2cache.tags.avg_refs 117.715369 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 117.717940 # Average number of references to valid blocks.
621,625c621,625
< system.cpu.l2cache.tags.occ_blocks::writebacks 9347.997887 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.378262 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 215.408019 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.285278 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020580 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 9355.355364 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.450791 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 215.428453 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.285503 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020583 # Average percentage of cache occupancy
627c627
< system.cpu.l2cache.tags.occ_percent::total 0.312432 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.312660 # Average percentage of cache occupancy
632,633c632,633
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13877 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id
635,650c635,650
< system.cpu.l2cache.tags.tag_accesses 15216337 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 15216337 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 903158 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 903183 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 943266 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 943266 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 935378 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 935403 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 935378 # number of overall hits
< system.cpu.l2cache.overall_hits::total 935403 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses
---
> system.cpu.l2cache.tags.tag_accesses 15216684 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 15216684 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 903175 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 903201 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 943289 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 943289 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 935398 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 935424 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 935398 # number of overall hits
> system.cpu.l2cache.overall_hits::total 935424 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 776 # number of ReadReq misses
652c652
< system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses
655c655
< system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 776 # number of demand (read+write) misses
657,658c657,658
< system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses
660,671c660,671
< system.cpu.l2cache.overall_misses::total 15583 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57912500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22184500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 80097000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073519250 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 1073519250 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 57912500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 1095703750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1153616250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 57912500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 1095703750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1153616250 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57766000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21545250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 79311250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073550250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 1073550250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 57766000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 1095095500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1152861500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 57766000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 1095095500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1152861500 # number of overall miss cycles
673,678c673,678
< system.cpu.l2cache.ReadReq_accesses::cpu.data 903420 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 904222 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 943266 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 943266 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.data 903437 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 904239 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 943289 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 943289 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses)
680,681c680,681
< system.cpu.l2cache.demand_accesses::cpu.data 950184 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 950204 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses
683,685c683,685
< system.cpu.l2cache.overall_accesses::cpu.data 950184 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968828 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::cpu.data 950204 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadReq accesses
687,690c687,690
< system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968828 # miss rate for demand accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967581 # miss rate for demand accesses
692,693c692,693
< system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968828 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses
695,706c695,706
< system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74533.462033 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84673.664122 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 77090.471607 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73811.829620 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73811.829620 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74030.433806 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74030.433806 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74440.721649 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82233.778626 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 76407.755299 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73813.961084 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73813.961084 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73986.747529 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73986.747529 # average overall miss latency
715c715
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
717,718c717,718
< system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
720,721c720,721
< system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
723c723
< system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
---
> system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
735,745c735,745
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48052500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18582500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66635000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891707750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891707750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48052500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910290250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 958342750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48052500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910290250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 958342750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 47928250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17945750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65874000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891746250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891746250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47928250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 909692000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 957620250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47928250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 909692000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 957620250 # number of overall MSHR miss cycles
749,750c749,750
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses
753c753
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses
756,767c756,767
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62083.333333 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72587.890625 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64694.174757 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61311.038916 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61311.038916 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61922.803618 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70100.585938 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63955.339806 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61313.686056 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61313.686056 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency
769,773c769,773
< system.cpu.toL2Bus.trans_dist::ReadReq 904222 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 904222 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 943266 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 943289 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution
775,776c775,776
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843634 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 2845238 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843697 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 2845301 # Packet count per connected master and slave (bytes)
778,779c778,779
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121180800 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183552 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 121234880 # Cumulative packet size per connected master and slave (bytes)
781c781
< system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 1894295 # Request fanout histogram
786c786
< system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 1894295 100.00% 100.00% # Request fanout histogram
791,792c791,792
< system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1894295 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 1890436500 # Layer occupancy (ticks)
794c794
< system.cpu.toL2Bus.respLayer0.occupancy 1371497 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1372498 # Layer occupancy (ticks)
796c796
< system.cpu.toL2Bus.respLayer1.occupancy 1428656494 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1428685244 # Layer occupancy (ticks)
817c817
< system.membus.reqLayer0.occupancy 21629000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 21690500 # Layer occupancy (ticks)
819c819
< system.membus.respLayer1.occupancy 82142750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 82133750 # Layer occupancy (ticks)