7,11c7,11
< host_inst_rate 253751 # Simulator instruction rate (inst/s)
< host_op_rate 255015 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 171247115 # Simulator tick rate (ticks/s)
< host_mem_usage 451144 # Number of bytes of host memory used
< host_seconds 357.05 # Real time elapsed on the host
---
> host_inst_rate 269135 # Simulator instruction rate (inst/s)
> host_op_rate 270476 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 181629122 # Simulator tick rate (ticks/s)
> host_mem_usage 440052 # Number of bytes of host memory used
> host_seconds 336.64 # Real time elapsed on the host
199,200c199,200
< system.physmem.totQLat 71444000 # Total ticks spent queuing
< system.physmem.totMemAccLat 363456500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 71490500 # Total ticks spent queuing
> system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM
202c202
< system.physmem.avgQLat 4587.39 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst
204c204
< system.physmem.avgMemAccLat 23337.39 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst
226d225
< system.membus.throughput 16301343 # Throughput (bytes/s)
233,237c232,245
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 996736 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 21821000 # Layer occupancy (ticks)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 15574 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 15574 # Request fanout histogram
> system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks)
239c247
< system.membus.respLayer1.occupancy 149563500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks)
242,243c250,251
< system.cpu.branchPred.lookups 20748985 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17053333 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 20748984 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted
345,346c353,354
< system.cpu.tickCycles 109176310 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 13112513 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped
348,349c356,357
< system.cpu.icache.tags.tagsinuse 690.927528 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 27773576 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks.
351c359
< system.cpu.icache.tags.avg_refs 34587.267746 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks.
353c361
< system.cpu.icache.tags.occ_blocks::cpu.inst 690.927528 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor
361,368c369,376
< system.cpu.icache.tags.tag_accesses 55549561 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 55549561 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 27773576 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 27773576 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 27773576 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 27773576 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 27773576 # number of overall hits
< system.cpu.icache.overall_hits::total 27773576 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 55549557 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 27773574 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 27773574 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 27773574 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 27773574 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 27773574 # number of overall hits
> system.cpu.icache.overall_hits::total 27773574 # number of overall hits
375,386c383,394
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 55308998 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 55308998 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 55308998 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 55308998 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 55308998 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 55308998 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 27774379 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 27774379 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 27774379 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 27774379 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 27774379 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 27774379 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 55313498 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 55313498 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses
393,398c401,406
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68877.955168 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68877.955168 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68877.955168 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68877.955168 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency
413,418c421,426
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53368002 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 53368002 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53368002 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 53368002 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53368002 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 53368002 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles
425,430c433,438
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66460.774595 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66460.774595 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
432d439
< system.cpu.toL2Bus.throughput 1982677223 # Throughput (bytes/s)
441,445c448,466
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 121229632 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 1894213 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 1894213 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 1894213 # Request fanout histogram
448c469
< system.cpu.toL2Bus.respLayer0.occupancy 1371998 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1371498 # Layer occupancy (ticks)
450c471
< system.cpu.toL2Bus.respLayer1.occupancy 1428578994 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1428579494 # Layer occupancy (ticks)
453c474
< system.cpu.l2cache.tags.tagsinuse 10264.635484 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 10264.635477 # Cycle average of tags in use
459c480
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976615 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976609 # Average occupied blocks per requestor
490,497c511,518
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71727250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 71727250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959621000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 959621000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1031348250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1031348250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1031348250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1031348250 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71732750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 71732750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959611500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 959611500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1031344250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1031344250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1031344250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1031344250 # number of overall miss cycles
516,523c537,544
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69101.396917 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 69101.396917 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65980.541804 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65980.541804 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 66188.438583 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 66188.438583 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877 # average overall miss latency
546,553c567,574
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58365000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58365000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772683000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772683000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831048000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 831048000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831048000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 831048000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58370500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58370500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772672000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772672000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831042500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 831042500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831042500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 831042500 # number of overall MSHR miss cycles
562,569c583,590
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56665.048544 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56665.048544 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53127.268977 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53127.268977 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56670.388350 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56670.388350 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
609,614c630,635
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342585500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2342585500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 14252071994 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14252071994 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 14252071994 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14252071994 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342568500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2342568500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 14252054994 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14252054994 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 14252054994 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14252054994 # number of overall miss cycles
637,642c658,663
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31701.113727 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 31701.113727 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14413.605268 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14413.605268 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14413.588076 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14413.588076 # average overall miss latency
671,676c692,697
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334905750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334905750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293231006 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11293231006 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293231006 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11293231006 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334896250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334896250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293221506 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11293221506 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293221506 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11293221506 # number of overall MSHR miss cycles
687,692c708,713
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.416651 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.416651 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
< host_inst_rate 253751 # Simulator instruction rate (inst/s)
< host_op_rate 255015 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 171247115 # Simulator tick rate (ticks/s)
< host_mem_usage 451144 # Number of bytes of host memory used
< host_seconds 357.05 # Real time elapsed on the host
---
> host_inst_rate 269135 # Simulator instruction rate (inst/s)
> host_op_rate 270476 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 181629122 # Simulator tick rate (ticks/s)
> host_mem_usage 440052 # Number of bytes of host memory used
> host_seconds 336.64 # Real time elapsed on the host
199,200c199,200
< system.physmem.totQLat 71444000 # Total ticks spent queuing
< system.physmem.totMemAccLat 363456500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 71490500 # Total ticks spent queuing
> system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM
202c202
< system.physmem.avgQLat 4587.39 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst
204c204
< system.physmem.avgMemAccLat 23337.39 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst
226d225
< system.membus.throughput 16301343 # Throughput (bytes/s)
233,237c232,245
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 996736 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 21821000 # Layer occupancy (ticks)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 15574 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 15574 # Request fanout histogram
> system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks)
239c247
< system.membus.respLayer1.occupancy 149563500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks)
242,243c250,251
< system.cpu.branchPred.lookups 20748985 # Number of BP lookups
< system.cpu.branchPred.condPredicted 17053333 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 20748984 # Number of BP lookups
> system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted
345,346c353,354
< system.cpu.tickCycles 109176310 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 13112513 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped
348,349c356,357
< system.cpu.icache.tags.tagsinuse 690.927528 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 27773576 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks.
351c359
< system.cpu.icache.tags.avg_refs 34587.267746 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks.
353c361
< system.cpu.icache.tags.occ_blocks::cpu.inst 690.927528 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor
361,368c369,376
< system.cpu.icache.tags.tag_accesses 55549561 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 55549561 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 27773576 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 27773576 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 27773576 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 27773576 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 27773576 # number of overall hits
< system.cpu.icache.overall_hits::total 27773576 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 55549557 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 27773574 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 27773574 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 27773574 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 27773574 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 27773574 # number of overall hits
> system.cpu.icache.overall_hits::total 27773574 # number of overall hits
375,386c383,394
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 55308998 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 55308998 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 55308998 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 55308998 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 55308998 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 55308998 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 27774379 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 27774379 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 27774379 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 27774379 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 27774379 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 27774379 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 55313498 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 55313498 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses
393,398c401,406
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68877.955168 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68877.955168 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68877.955168 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68877.955168 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency
413,418c421,426
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53368002 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 53368002 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53368002 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 53368002 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53368002 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 53368002 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles
425,430c433,438
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66460.774595 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66460.774595 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
432d439
< system.cpu.toL2Bus.throughput 1982677223 # Throughput (bytes/s)
441,445c448,466
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 121229632 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 1894213 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 1894213 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 1894213 # Request fanout histogram
448c469
< system.cpu.toL2Bus.respLayer0.occupancy 1371998 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1371498 # Layer occupancy (ticks)
450c471
< system.cpu.toL2Bus.respLayer1.occupancy 1428578994 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1428579494 # Layer occupancy (ticks)
453c474
< system.cpu.l2cache.tags.tagsinuse 10264.635484 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 10264.635477 # Cycle average of tags in use
459c480
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976615 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976609 # Average occupied blocks per requestor
490,497c511,518
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71727250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 71727250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959621000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 959621000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1031348250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 1031348250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1031348250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 1031348250 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71732750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 71732750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959611500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 959611500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1031344250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 1031344250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1031344250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 1031344250 # number of overall miss cycles
516,523c537,544
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69101.396917 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 69101.396917 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65980.541804 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65980.541804 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 66188.438583 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 66188.438583 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877 # average overall miss latency
546,553c567,574
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58365000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58365000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772683000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772683000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831048000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 831048000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831048000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 831048000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58370500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58370500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772672000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772672000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831042500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 831042500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831042500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 831042500 # number of overall MSHR miss cycles
562,569c583,590
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56665.048544 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56665.048544 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53127.268977 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53127.268977 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56670.388350 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56670.388350 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
609,614c630,635
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342585500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2342585500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 14252071994 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 14252071994 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 14252071994 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 14252071994 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342568500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2342568500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 14252054994 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 14252054994 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 14252054994 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 14252054994 # number of overall miss cycles
637,642c658,663
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31701.113727 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 31701.113727 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 14413.605268 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14413.605268 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 14413.588076 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14413.588076 # average overall miss latency
671,676c692,697
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334905750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334905750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293231006 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11293231006 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293231006 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11293231006 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334896250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334896250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293221506 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11293221506 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293221506 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11293221506 # number of overall MSHR miss cycles
687,692c708,713
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.416651 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.416651 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency