Cross Reference: /gem5/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt

stats.txt (10812:bacaefeb126a)	stats.txt (10827:7f5467f2f8b8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061594 # Number of seconds simulated 4sim_ticks 61594138500 # Number of ticks simulated 5final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061594 # Number of seconds simulated 4sim_ticks 61594138500 # Number of ticks simulated 5final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 196979 # Simulator instruction rate (inst/s) 8host_op_rate 197960 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 133911114 # Simulator tick rate (ticks/s) 10host_mem_usage 438496 # Number of bytes of host memory used 11host_seconds 459.96 # Real time elapsed on the host	7host_inst_rate 265976 # Simulator instruction rate (inst/s) 8host_op_rate 267300 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 180817037 # Simulator tick rate (ticks/s) 10host_mem_usage 446692 # Number of bytes of host memory used 11host_seconds 340.64 # Real time elapsed on the host
12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory 18system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 804232 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 15378087 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 16182319 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 804232 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 804232 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 804232 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 15378087 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 16182319 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 15574 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 993 # Per bank write bursts 45system.physmem.perBankRdBursts::1 890 # Per bank write bursts 46system.physmem.perBankRdBursts::2 949 # Per bank write bursts 47system.physmem.perBankRdBursts::3 1028 # Per bank write bursts 48system.physmem.perBankRdBursts::4 1050 # Per bank write bursts 49system.physmem.perBankRdBursts::5 1113 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1087 # Per bank write bursts 51system.physmem.perBankRdBursts::7 1088 # Per bank write bursts 52system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 53system.physmem.perBankRdBursts::9 962 # Per bank write bursts 54system.physmem.perBankRdBursts::10 938 # Per bank write bursts 55system.physmem.perBankRdBursts::11 899 # Per bank write bursts 56system.physmem.perBankRdBursts::12 904 # Per bank write bursts 57system.physmem.perBankRdBursts::13 867 # Per bank write bursts 58system.physmem.perBankRdBursts::14 877 # Per bank write bursts 59system.physmem.perBankRdBursts::15 905 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 61594044000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 15574 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 646.025974 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 441.784218 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 399.527843 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 247 16.04% 16.04% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 180 11.69% 27.73% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 88 5.71% 33.44% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 68 4.42% 37.86% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 78 5.06% 42.92% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 95 6.17% 49.09% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 49 3.18% 52.27% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 35 2.27% 54.55% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 700 45.45% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation 203system.physmem.totQLat 76216750 # Total ticks spent queuing 204system.physmem.totMemAccLat 368229250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 4893.85 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 23643.85 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.13 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 14024 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 3954927.70 # Average gap between requests 224system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 6327720 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 3452625 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 63655800 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 2561139675 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 34707076500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 41364361920 # Total energy per rank (pJ) 233system.physmem_0.averagePower 671.614039 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 57728641000 # Time in different power states 235system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 1804854500 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 2570808870 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 34698594750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 41357767005 # Total energy per rank (pJ) 247system.physmem_1.averagePower 671.506960 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 57715756250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 1818578750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 20791997 # Number of BP lookups 254system.cpu.branchPred.condPredicted 17093861 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 766355 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 8982065 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 8866075 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 98.708649 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 62635 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 272system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 273system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 274system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 275system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 276system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 277system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 278system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 279system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 280system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 281system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 282system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 283system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 284system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 285system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 286system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 287system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 288system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 289system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 290system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 291system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 292system.cpu.dtb.walker.walks 0 # Table walker walks requested 293system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.inst_hits 0 # ITB inst hits 301system.cpu.dtb.inst_misses 0 # ITB inst misses 302system.cpu.dtb.read_hits 0 # DTB read hits 303system.cpu.dtb.read_misses 0 # DTB read misses 304system.cpu.dtb.write_hits 0 # DTB write hits 305system.cpu.dtb.write_misses 0 # DTB write misses 306system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 307system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 308system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 309system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 310system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 311system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 312system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 313system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 314system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 315system.cpu.dtb.read_accesses 0 # DTB read accesses 316system.cpu.dtb.write_accesses 0 # DTB write accesses 317system.cpu.dtb.inst_accesses 0 # ITB inst accesses 318system.cpu.dtb.hits 0 # DTB hits 319system.cpu.dtb.misses 0 # DTB misses 320system.cpu.dtb.accesses 0 # DTB accesses 321system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 322system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 325system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 330system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 331system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 332system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 333system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 334system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 335system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 336system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 337system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 338system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 339system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 340system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 341system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 342system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 343system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 344system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 345system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 346system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 347system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 348system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 349system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 350system.cpu.itb.walker.walks 0 # Table walker walks requested 351system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 354system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.inst_hits 0 # ITB inst hits 359system.cpu.itb.inst_misses 0 # ITB inst misses 360system.cpu.itb.read_hits 0 # DTB read hits 361system.cpu.itb.read_misses 0 # DTB read misses 362system.cpu.itb.write_hits 0 # DTB write hits 363system.cpu.itb.write_misses 0 # DTB write misses 364system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 365system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 366system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 367system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 368system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 369system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 370system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 371system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 442 # Number of system calls 380system.cpu.numCycles 123188277 # number of cpu cycles simulated 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 90602850 # Number of instructions committed 384system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed 385system.cpu.discardedOps 2070154 # Number of ops (including micro ops) which were discarded before commit 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 387system.cpu.cpi 1.359651 # CPI: cycles per instruction 388system.cpu.ipc 0.735483 # IPC: instructions per cycle 389system.cpu.tickCycles 109833647 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 13354630 # Total number of cycles that the object has spent stopped 391system.cpu.dcache.tags.replacements 946088 # number of replacements 392system.cpu.dcache.tags.tagsinuse 3616.165317 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 26267708 # Total number of references to valid blocks. 394system.cpu.dcache.tags.sampled_refs 950184 # Sample count of references to valid blocks. 395system.cpu.dcache.tags.avg_refs 27.644865 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 20660513250 # Cycle when the warmup percentage was hit. 397system.cpu.dcache.tags.occ_blocks::cpu.data 3616.165317 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.882853 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.882853 # Average percentage of cache occupancy 400system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id 404system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 405system.cpu.dcache.tags.tag_accesses 55463792 # Number of tag accesses 406system.cpu.dcache.tags.data_accesses 55463792 # Number of data accesses 407system.cpu.dcache.ReadReq_hits::cpu.data 21598607 # number of ReadReq hits 408system.cpu.dcache.ReadReq_hits::total 21598607 # number of ReadReq hits 409system.cpu.dcache.WriteReq_hits::cpu.data 4660819 # number of WriteReq hits 410system.cpu.dcache.WriteReq_hits::total 4660819 # number of WriteReq hits 411system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 412system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 413system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 414system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 415system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 416system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 417system.cpu.dcache.demand_hits::cpu.data 26259426 # number of demand (read+write) hits 418system.cpu.dcache.demand_hits::total 26259426 # number of demand (read+write) hits 419system.cpu.dcache.overall_hits::cpu.data 26259934 # number of overall hits 420system.cpu.dcache.overall_hits::total 26259934 # number of overall hits 421system.cpu.dcache.ReadReq_misses::cpu.data 914930 # number of ReadReq misses 422system.cpu.dcache.ReadReq_misses::total 914930 # number of ReadReq misses 423system.cpu.dcache.WriteReq_misses::cpu.data 74162 # number of WriteReq misses 424system.cpu.dcache.WriteReq_misses::total 74162 # number of WriteReq misses 425system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 426system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses 427system.cpu.dcache.demand_misses::cpu.data 989092 # number of demand (read+write) misses 428system.cpu.dcache.demand_misses::total 989092 # number of demand (read+write) misses 429system.cpu.dcache.overall_misses::cpu.data 989096 # number of overall misses 430system.cpu.dcache.overall_misses::total 989096 # number of overall misses 431system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918229494 # number of ReadReq miss cycles 432system.cpu.dcache.ReadReq_miss_latency::total 11918229494 # number of ReadReq miss cycles 433system.cpu.dcache.WriteReq_miss_latency::cpu.data 2567046500 # number of WriteReq miss cycles 434system.cpu.dcache.WriteReq_miss_latency::total 2567046500 # number of WriteReq miss cycles 435system.cpu.dcache.demand_miss_latency::cpu.data 14485275994 # number of demand (read+write) miss cycles 436system.cpu.dcache.demand_miss_latency::total 14485275994 # number of demand (read+write) miss cycles 437system.cpu.dcache.overall_miss_latency::cpu.data 14485275994 # number of overall miss cycles 438system.cpu.dcache.overall_miss_latency::total 14485275994 # number of overall miss cycles 439system.cpu.dcache.ReadReq_accesses::cpu.data 22513537 # number of ReadReq accesses(hits+misses) 440system.cpu.dcache.ReadReq_accesses::total 22513537 # number of ReadReq accesses(hits+misses) 441system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 442system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 443system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 444system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 445system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 446system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 447system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 448system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 449system.cpu.dcache.demand_accesses::cpu.data 27248518 # number of demand (read+write) accesses 450system.cpu.dcache.demand_accesses::total 27248518 # number of demand (read+write) accesses 451system.cpu.dcache.overall_accesses::cpu.data 27249030 # number of overall (read+write) accesses 452system.cpu.dcache.overall_accesses::total 27249030 # number of overall (read+write) accesses 453system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses 454system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses 455system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015663 # miss rate for WriteReq accesses 456system.cpu.dcache.WriteReq_miss_rate::total 0.015663 # miss rate for WriteReq accesses 457system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 458system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses 459system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses 460system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses 461system.cpu.dcache.overall_miss_rate::cpu.data 0.036298 # miss rate for overall accesses 462system.cpu.dcache.overall_miss_rate::total 0.036298 # miss rate for overall accesses 463system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.383979 # average ReadReq miss latency 464system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.383979 # average ReadReq miss latency 465system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34614.040883 # average WriteReq miss latency 466system.cpu.dcache.WriteReq_avg_miss_latency::total 34614.040883 # average WriteReq miss latency 467system.cpu.dcache.demand_avg_miss_latency::cpu.data 14645.023915 # average overall miss latency 468system.cpu.dcache.demand_avg_miss_latency::total 14645.023915 # average overall miss latency 469system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.964689 # average overall miss latency 470system.cpu.dcache.overall_avg_miss_latency::total 14644.964689 # average overall miss latency 471system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 472system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 473system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 476system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 477system.cpu.dcache.fast_writes 0 # number of fast writes performed 478system.cpu.dcache.cache_copies 0 # number of cache copies performed 479system.cpu.dcache.writebacks::writebacks 943266 # number of writebacks 480system.cpu.dcache.writebacks::total 943266 # number of writebacks 481system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11513 # number of ReadReq MSHR hits 482system.cpu.dcache.ReadReq_mshr_hits::total 11513 # number of ReadReq MSHR hits 483system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27398 # number of WriteReq MSHR hits 484system.cpu.dcache.WriteReq_mshr_hits::total 27398 # number of WriteReq MSHR hits 485system.cpu.dcache.demand_mshr_hits::cpu.data 38911 # number of demand (read+write) MSHR hits 486system.cpu.dcache.demand_mshr_hits::total 38911 # number of demand (read+write) MSHR hits 487system.cpu.dcache.overall_mshr_hits::cpu.data 38911 # number of overall MSHR hits 488system.cpu.dcache.overall_mshr_hits::total 38911 # number of overall MSHR hits 489system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903417 # number of ReadReq MSHR misses 490system.cpu.dcache.ReadReq_mshr_misses::total 903417 # number of ReadReq MSHR misses 491system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses 492system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses 493system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 494system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 495system.cpu.dcache.demand_mshr_misses::cpu.data 950181 # number of demand (read+write) MSHR misses 496system.cpu.dcache.demand_mshr_misses::total 950181 # number of demand (read+write) MSHR misses 497system.cpu.dcache.overall_mshr_misses::cpu.data 950184 # number of overall MSHR misses 498system.cpu.dcache.overall_mshr_misses::total 950184 # number of overall MSHR misses 499system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412913006 # number of ReadReq MSHR miss cycles 500system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412913006 # number of ReadReq MSHR miss cycles 501system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464006500 # number of WriteReq MSHR miss cycles 502system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464006500 # number of WriteReq MSHR miss cycles 503system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles 504system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles 505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876919506 # number of demand (read+write) MSHR miss cycles 506system.cpu.dcache.demand_mshr_miss_latency::total 11876919506 # number of demand (read+write) MSHR miss cycles 507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877075006 # number of overall MSHR miss cycles 508system.cpu.dcache.overall_mshr_miss_latency::total 11877075006 # number of overall MSHR miss cycles 509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses 510system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses 511system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 512system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 513system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 514system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 515system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses 516system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses 517system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034870 # mshr miss rate for overall accesses 518system.cpu.dcache.overall_mshr_miss_rate::total 0.034870 # mshr miss rate for overall accesses 519system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.142419 # average ReadReq mshr miss latency 520system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.142419 # average ReadReq mshr miss latency 521system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31306.271919 # average WriteReq mshr miss latency 522system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31306.271919 # average WriteReq mshr miss latency 523system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency 524system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency 525system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.639022 # average overall mshr miss latency 526system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.639022 # average overall mshr miss latency 527system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.763210 # average overall mshr miss latency 528system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.763210 # average overall mshr miss latency 529system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 530system.cpu.icache.tags.replacements 4 # number of replacements 531system.cpu.icache.tags.tagsinuse 690.351832 # Cycle average of tags in use 532system.cpu.icache.tags.total_refs 27857021 # Total number of references to valid blocks. 533system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. 534system.cpu.icache.tags.avg_refs 34734.440150 # Average number of references to valid blocks. 535system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 536system.cpu.icache.tags.occ_blocks::cpu.inst 690.351832 # Average occupied blocks per requestor 537system.cpu.icache.tags.occ_percent::cpu.inst 0.337086 # Average percentage of cache occupancy 538system.cpu.icache.tags.occ_percent::total 0.337086 # Average percentage of cache occupancy 539system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id 540system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 541system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id 543system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id 544system.cpu.icache.tags.tag_accesses 55716448 # Number of tag accesses 545system.cpu.icache.tags.data_accesses 55716448 # Number of data accesses 546system.cpu.icache.ReadReq_hits::cpu.inst 27857021 # number of ReadReq hits 547system.cpu.icache.ReadReq_hits::total 27857021 # number of ReadReq hits 548system.cpu.icache.demand_hits::cpu.inst 27857021 # number of demand (read+write) hits 549system.cpu.icache.demand_hits::total 27857021 # number of demand (read+write) hits 550system.cpu.icache.overall_hits::cpu.inst 27857021 # number of overall hits 551system.cpu.icache.overall_hits::total 27857021 # number of overall hits 552system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses 553system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses 554system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses 555system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses 556system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses 557system.cpu.icache.overall_misses::total 802 # number of overall misses 558system.cpu.icache.ReadReq_miss_latency::cpu.inst 60516997 # number of ReadReq miss cycles 559system.cpu.icache.ReadReq_miss_latency::total 60516997 # number of ReadReq miss cycles 560system.cpu.icache.demand_miss_latency::cpu.inst 60516997 # number of demand (read+write) miss cycles 561system.cpu.icache.demand_miss_latency::total 60516997 # number of demand (read+write) miss cycles 562system.cpu.icache.overall_miss_latency::cpu.inst 60516997 # number of overall miss cycles 563system.cpu.icache.overall_miss_latency::total 60516997 # number of overall miss cycles 564system.cpu.icache.ReadReq_accesses::cpu.inst 27857823 # number of ReadReq accesses(hits+misses) 565system.cpu.icache.ReadReq_accesses::total 27857823 # number of ReadReq accesses(hits+misses) 566system.cpu.icache.demand_accesses::cpu.inst 27857823 # number of demand (read+write) accesses 567system.cpu.icache.demand_accesses::total 27857823 # number of demand (read+write) accesses 568system.cpu.icache.overall_accesses::cpu.inst 27857823 # number of overall (read+write) accesses 569system.cpu.icache.overall_accesses::total 27857823 # number of overall (read+write) accesses 570system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 571system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 572system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 573system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 574system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 575system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses 576system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75457.602244 # average ReadReq miss latency 577system.cpu.icache.ReadReq_avg_miss_latency::total 75457.602244 # average ReadReq miss latency 578system.cpu.icache.demand_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency 579system.cpu.icache.demand_avg_miss_latency::total 75457.602244 # average overall miss latency 580system.cpu.icache.overall_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency 581system.cpu.icache.overall_avg_miss_latency::total 75457.602244 # average overall miss latency 582system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 583system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 584system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 585system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 586system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 587system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 588system.cpu.icache.fast_writes 0 # number of fast writes performed 589system.cpu.icache.cache_copies 0 # number of cache copies performed 590system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses 591system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses 592system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses 593system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses 594system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses 595system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses 596system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58977003 # number of ReadReq MSHR miss cycles 597system.cpu.icache.ReadReq_mshr_miss_latency::total 58977003 # number of ReadReq MSHR miss cycles 598system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58977003 # number of demand (read+write) MSHR miss cycles 599system.cpu.icache.demand_mshr_miss_latency::total 58977003 # number of demand (read+write) MSHR miss cycles 600system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58977003 # number of overall MSHR miss cycles 601system.cpu.icache.overall_mshr_miss_latency::total 58977003 # number of overall MSHR miss cycles 602system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 603system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 604system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 605system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 606system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 607system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses 608system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73537.410224 # average ReadReq mshr miss latency 609system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73537.410224 # average ReadReq mshr miss latency 610system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency 611system.cpu.icache.demand_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency 612system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency 613system.cpu.icache.overall_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency 614system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 615system.cpu.l2cache.tags.replacements 0 # number of replacements 616system.cpu.l2cache.tags.tagsinuse 10237.784168 # Cycle average of tags in use 617system.cpu.l2cache.tags.total_refs 1831298 # Total number of references to valid blocks. 618system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. 619system.cpu.l2cache.tags.avg_refs 117.715369 # Average number of references to valid blocks. 620system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 621system.cpu.l2cache.tags.occ_blocks::writebacks 9347.997887 # Average occupied blocks per requestor 622system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.378262 # Average occupied blocks per requestor 623system.cpu.l2cache.tags.occ_blocks::cpu.data 215.408019 # Average occupied blocks per requestor 624system.cpu.l2cache.tags.occ_percent::writebacks 0.285278 # Average percentage of cache occupancy 625system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020580 # Average percentage of cache occupancy 626system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy 627system.cpu.l2cache.tags.occ_percent::total 0.312432 # Average percentage of cache occupancy 628system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id 629system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 630system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 631system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 632system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id 633system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13877 # Occupied blocks per task id 634system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id 635system.cpu.l2cache.tags.tag_accesses 15216337 # Number of tag accesses 636system.cpu.l2cache.tags.data_accesses 15216337 # Number of data accesses 637system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits 638system.cpu.l2cache.ReadReq_hits::cpu.data 903158 # number of ReadReq hits 639system.cpu.l2cache.ReadReq_hits::total 903183 # number of ReadReq hits 640system.cpu.l2cache.Writeback_hits::writebacks 943266 # number of Writeback hits 641system.cpu.l2cache.Writeback_hits::total 943266 # number of Writeback hits 642system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 643system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 644system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits 645system.cpu.l2cache.demand_hits::cpu.data 935378 # number of demand (read+write) hits 646system.cpu.l2cache.demand_hits::total 935403 # number of demand (read+write) hits 647system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits 648system.cpu.l2cache.overall_hits::cpu.data 935378 # number of overall hits 649system.cpu.l2cache.overall_hits::total 935403 # number of overall hits 650system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses 651system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses 652system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses 653system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses 654system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses 655system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses 656system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses 657system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses 658system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses 659system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses 660system.cpu.l2cache.overall_misses::total 15583 # number of overall misses 661system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57912500 # number of ReadReq miss cycles 662system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22184500 # number of ReadReq miss cycles 663system.cpu.l2cache.ReadReq_miss_latency::total 80097000 # number of ReadReq miss cycles 664system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073519250 # number of ReadExReq miss cycles 665system.cpu.l2cache.ReadExReq_miss_latency::total 1073519250 # number of ReadExReq miss cycles 666system.cpu.l2cache.demand_miss_latency::cpu.inst 57912500 # number of demand (read+write) miss cycles 667system.cpu.l2cache.demand_miss_latency::cpu.data 1095703750 # number of demand (read+write) miss cycles 668system.cpu.l2cache.demand_miss_latency::total 1153616250 # number of demand (read+write) miss cycles 669system.cpu.l2cache.overall_miss_latency::cpu.inst 57912500 # number of overall miss cycles 670system.cpu.l2cache.overall_miss_latency::cpu.data 1095703750 # number of overall miss cycles 671system.cpu.l2cache.overall_miss_latency::total 1153616250 # number of overall miss cycles 672system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) 673system.cpu.l2cache.ReadReq_accesses::cpu.data 903420 # number of ReadReq accesses(hits+misses) 674system.cpu.l2cache.ReadReq_accesses::total 904222 # number of ReadReq accesses(hits+misses) 675system.cpu.l2cache.Writeback_accesses::writebacks 943266 # number of Writeback accesses(hits+misses) 676system.cpu.l2cache.Writeback_accesses::total 943266 # number of Writeback accesses(hits+misses) 677system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) 678system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) 679system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses 680system.cpu.l2cache.demand_accesses::cpu.data 950184 # number of demand (read+write) accesses 681system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses 682system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses 683system.cpu.l2cache.overall_accesses::cpu.data 950184 # number of overall (read+write) accesses 684system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses 685system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968828 # miss rate for ReadReq accesses 686system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses 687system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses 688system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses 689system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses 690system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968828 # miss rate for demand accesses 691system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses 692system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses 693system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968828 # miss rate for overall accesses 694system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses 695system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses 696system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74533.462033 # average ReadReq miss latency 697system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84673.664122 # average ReadReq miss latency 698system.cpu.l2cache.ReadReq_avg_miss_latency::total 77090.471607 # average ReadReq miss latency 699system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73811.829620 # average ReadExReq miss latency 700system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73811.829620 # average ReadExReq miss latency 701system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency 702system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency 703system.cpu.l2cache.demand_avg_miss_latency::total 74030.433806 # average overall miss latency 704system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency 705system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency 706system.cpu.l2cache.overall_avg_miss_latency::total 74030.433806 # average overall miss latency 707system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 708system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 709system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 710system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 711system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 712system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 713system.cpu.l2cache.fast_writes 0 # number of fast writes performed 714system.cpu.l2cache.cache_copies 0 # number of cache copies performed 715system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 716system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 717system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 718system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 719system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 720system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits 721system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 722system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 723system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits 724system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses 725system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses 726system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses 727system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses 728system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 729system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses 730system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses 731system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 732system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses 733system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses 734system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses 735system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48052500 # number of ReadReq MSHR miss cycles 736system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18582500 # number of ReadReq MSHR miss cycles 737system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66635000 # number of ReadReq MSHR miss cycles 738system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891707750 # number of ReadExReq MSHR miss cycles 739system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891707750 # number of ReadExReq MSHR miss cycles 740system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48052500 # number of demand (read+write) MSHR miss cycles 741system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910290250 # number of demand (read+write) MSHR miss cycles 742system.cpu.l2cache.demand_mshr_miss_latency::total 958342750 # number of demand (read+write) MSHR miss cycles 743system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48052500 # number of overall MSHR miss cycles 744system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910290250 # number of overall MSHR miss cycles 745system.cpu.l2cache.overall_mshr_miss_latency::total 958342750 # number of overall MSHR miss cycles 746system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadReq accesses 747system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses 748system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses 749system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses 750system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses 751system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses 752system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses 753system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 754system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses 755system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses 756system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses 757system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62083.333333 # average ReadReq mshr miss latency 758system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72587.890625 # average ReadReq mshr miss latency 759system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64694.174757 # average ReadReq mshr miss latency 760system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61311.038916 # average ReadExReq mshr miss latency 761system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61311.038916 # average ReadExReq mshr miss latency 762system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency 763system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency 764system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency 765system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency 766system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency 767system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency 768system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 769system.cpu.toL2Bus.trans_dist::ReadReq 904222 # Transaction distribution 770system.cpu.toL2Bus.trans_dist::ReadResp 904222 # Transaction distribution 771system.cpu.toL2Bus.trans_dist::Writeback 943266 # Transaction distribution 772system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 773system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 774system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes) 775system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843634 # Packet count per connected master and slave (bytes) 776system.cpu.toL2Bus.pkt_count::total 2845238 # Packet count per connected master and slave (bytes) 777system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) 778system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121180800 # Cumulative packet size per connected master and slave (bytes) 779system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes) 780system.cpu.toL2Bus.snoops 0 # Total snoops (count) 781system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram	12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory 18system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 804232 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 15378087 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 16182319 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 804232 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 804232 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 804232 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 15378087 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 16182319 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 15574 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 993 # Per bank write bursts 45system.physmem.perBankRdBursts::1 890 # Per bank write bursts 46system.physmem.perBankRdBursts::2 949 # Per bank write bursts 47system.physmem.perBankRdBursts::3 1028 # Per bank write bursts 48system.physmem.perBankRdBursts::4 1050 # Per bank write bursts 49system.physmem.perBankRdBursts::5 1113 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1087 # Per bank write bursts 51system.physmem.perBankRdBursts::7 1088 # Per bank write bursts 52system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 53system.physmem.perBankRdBursts::9 962 # Per bank write bursts 54system.physmem.perBankRdBursts::10 938 # Per bank write bursts 55system.physmem.perBankRdBursts::11 899 # Per bank write bursts 56system.physmem.perBankRdBursts::12 904 # Per bank write bursts 57system.physmem.perBankRdBursts::13 867 # Per bank write bursts 58system.physmem.perBankRdBursts::14 877 # Per bank write bursts 59system.physmem.perBankRdBursts::15 905 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 61594044000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 15574 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 646.025974 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 441.784218 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 399.527843 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 247 16.04% 16.04% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 180 11.69% 27.73% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 88 5.71% 33.44% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 68 4.42% 37.86% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 78 5.06% 42.92% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 95 6.17% 49.09% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 49 3.18% 52.27% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 35 2.27% 54.55% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 700 45.45% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation 203system.physmem.totQLat 76216750 # Total ticks spent queuing 204system.physmem.totMemAccLat 368229250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 4893.85 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 23643.85 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.13 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 14024 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 3954927.70 # Average gap between requests 224system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 6327720 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 3452625 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 63655800 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 2561139675 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 34707076500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 41364361920 # Total energy per rank (pJ) 233system.physmem_0.averagePower 671.614039 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 57728641000 # Time in different power states 235system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 1804854500 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 2570808870 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 34698594750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 41357767005 # Total energy per rank (pJ) 247system.physmem_1.averagePower 671.506960 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 57715756250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 1818578750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 20791997 # Number of BP lookups 254system.cpu.branchPred.condPredicted 17093861 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 766355 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 8982065 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 8866075 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 98.708649 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 62635 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 272system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 273system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 274system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 275system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 276system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 277system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 278system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 279system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 280system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 281system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 282system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 283system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 284system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 285system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 286system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 287system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 288system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 289system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 290system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 291system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 292system.cpu.dtb.walker.walks 0 # Table walker walks requested 293system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.inst_hits 0 # ITB inst hits 301system.cpu.dtb.inst_misses 0 # ITB inst misses 302system.cpu.dtb.read_hits 0 # DTB read hits 303system.cpu.dtb.read_misses 0 # DTB read misses 304system.cpu.dtb.write_hits 0 # DTB write hits 305system.cpu.dtb.write_misses 0 # DTB write misses 306system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 307system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 308system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 309system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 310system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 311system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 312system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 313system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 314system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 315system.cpu.dtb.read_accesses 0 # DTB read accesses 316system.cpu.dtb.write_accesses 0 # DTB write accesses 317system.cpu.dtb.inst_accesses 0 # ITB inst accesses 318system.cpu.dtb.hits 0 # DTB hits 319system.cpu.dtb.misses 0 # DTB misses 320system.cpu.dtb.accesses 0 # DTB accesses 321system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 322system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 325system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 330system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 331system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 332system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 333system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 334system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 335system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 336system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 337system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 338system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 339system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 340system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 341system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 342system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 343system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 344system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 345system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 346system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 347system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 348system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 349system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 350system.cpu.itb.walker.walks 0 # Table walker walks requested 351system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 354system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.inst_hits 0 # ITB inst hits 359system.cpu.itb.inst_misses 0 # ITB inst misses 360system.cpu.itb.read_hits 0 # DTB read hits 361system.cpu.itb.read_misses 0 # DTB read misses 362system.cpu.itb.write_hits 0 # DTB write hits 363system.cpu.itb.write_misses 0 # DTB write misses 364system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 365system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 366system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 367system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 368system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 369system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 370system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 371system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 442 # Number of system calls 380system.cpu.numCycles 123188277 # number of cpu cycles simulated 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 90602850 # Number of instructions committed 384system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed 385system.cpu.discardedOps 2070154 # Number of ops (including micro ops) which were discarded before commit 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 387system.cpu.cpi 1.359651 # CPI: cycles per instruction 388system.cpu.ipc 0.735483 # IPC: instructions per cycle 389system.cpu.tickCycles 109833647 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 13354630 # Total number of cycles that the object has spent stopped 391system.cpu.dcache.tags.replacements 946088 # number of replacements 392system.cpu.dcache.tags.tagsinuse 3616.165317 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 26267708 # Total number of references to valid blocks. 394system.cpu.dcache.tags.sampled_refs 950184 # Sample count of references to valid blocks. 395system.cpu.dcache.tags.avg_refs 27.644865 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 20660513250 # Cycle when the warmup percentage was hit. 397system.cpu.dcache.tags.occ_blocks::cpu.data 3616.165317 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.882853 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.882853 # Average percentage of cache occupancy 400system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id 404system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 405system.cpu.dcache.tags.tag_accesses 55463792 # Number of tag accesses 406system.cpu.dcache.tags.data_accesses 55463792 # Number of data accesses 407system.cpu.dcache.ReadReq_hits::cpu.data 21598607 # number of ReadReq hits 408system.cpu.dcache.ReadReq_hits::total 21598607 # number of ReadReq hits 409system.cpu.dcache.WriteReq_hits::cpu.data 4660819 # number of WriteReq hits 410system.cpu.dcache.WriteReq_hits::total 4660819 # number of WriteReq hits 411system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 412system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 413system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 414system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 415system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 416system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 417system.cpu.dcache.demand_hits::cpu.data 26259426 # number of demand (read+write) hits 418system.cpu.dcache.demand_hits::total 26259426 # number of demand (read+write) hits 419system.cpu.dcache.overall_hits::cpu.data 26259934 # number of overall hits 420system.cpu.dcache.overall_hits::total 26259934 # number of overall hits 421system.cpu.dcache.ReadReq_misses::cpu.data 914930 # number of ReadReq misses 422system.cpu.dcache.ReadReq_misses::total 914930 # number of ReadReq misses 423system.cpu.dcache.WriteReq_misses::cpu.data 74162 # number of WriteReq misses 424system.cpu.dcache.WriteReq_misses::total 74162 # number of WriteReq misses 425system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 426system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses 427system.cpu.dcache.demand_misses::cpu.data 989092 # number of demand (read+write) misses 428system.cpu.dcache.demand_misses::total 989092 # number of demand (read+write) misses 429system.cpu.dcache.overall_misses::cpu.data 989096 # number of overall misses 430system.cpu.dcache.overall_misses::total 989096 # number of overall misses 431system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918229494 # number of ReadReq miss cycles 432system.cpu.dcache.ReadReq_miss_latency::total 11918229494 # number of ReadReq miss cycles 433system.cpu.dcache.WriteReq_miss_latency::cpu.data 2567046500 # number of WriteReq miss cycles 434system.cpu.dcache.WriteReq_miss_latency::total 2567046500 # number of WriteReq miss cycles 435system.cpu.dcache.demand_miss_latency::cpu.data 14485275994 # number of demand (read+write) miss cycles 436system.cpu.dcache.demand_miss_latency::total 14485275994 # number of demand (read+write) miss cycles 437system.cpu.dcache.overall_miss_latency::cpu.data 14485275994 # number of overall miss cycles 438system.cpu.dcache.overall_miss_latency::total 14485275994 # number of overall miss cycles 439system.cpu.dcache.ReadReq_accesses::cpu.data 22513537 # number of ReadReq accesses(hits+misses) 440system.cpu.dcache.ReadReq_accesses::total 22513537 # number of ReadReq accesses(hits+misses) 441system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 442system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 443system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 444system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 445system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 446system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 447system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 448system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 449system.cpu.dcache.demand_accesses::cpu.data 27248518 # number of demand (read+write) accesses 450system.cpu.dcache.demand_accesses::total 27248518 # number of demand (read+write) accesses 451system.cpu.dcache.overall_accesses::cpu.data 27249030 # number of overall (read+write) accesses 452system.cpu.dcache.overall_accesses::total 27249030 # number of overall (read+write) accesses 453system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses 454system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses 455system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015663 # miss rate for WriteReq accesses 456system.cpu.dcache.WriteReq_miss_rate::total 0.015663 # miss rate for WriteReq accesses 457system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 458system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses 459system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses 460system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses 461system.cpu.dcache.overall_miss_rate::cpu.data 0.036298 # miss rate for overall accesses 462system.cpu.dcache.overall_miss_rate::total 0.036298 # miss rate for overall accesses 463system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.383979 # average ReadReq miss latency 464system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.383979 # average ReadReq miss latency 465system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34614.040883 # average WriteReq miss latency 466system.cpu.dcache.WriteReq_avg_miss_latency::total 34614.040883 # average WriteReq miss latency 467system.cpu.dcache.demand_avg_miss_latency::cpu.data 14645.023915 # average overall miss latency 468system.cpu.dcache.demand_avg_miss_latency::total 14645.023915 # average overall miss latency 469system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.964689 # average overall miss latency 470system.cpu.dcache.overall_avg_miss_latency::total 14644.964689 # average overall miss latency 471system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 472system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 473system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 476system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 477system.cpu.dcache.fast_writes 0 # number of fast writes performed 478system.cpu.dcache.cache_copies 0 # number of cache copies performed 479system.cpu.dcache.writebacks::writebacks 943266 # number of writebacks 480system.cpu.dcache.writebacks::total 943266 # number of writebacks 481system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11513 # number of ReadReq MSHR hits 482system.cpu.dcache.ReadReq_mshr_hits::total 11513 # number of ReadReq MSHR hits 483system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27398 # number of WriteReq MSHR hits 484system.cpu.dcache.WriteReq_mshr_hits::total 27398 # number of WriteReq MSHR hits 485system.cpu.dcache.demand_mshr_hits::cpu.data 38911 # number of demand (read+write) MSHR hits 486system.cpu.dcache.demand_mshr_hits::total 38911 # number of demand (read+write) MSHR hits 487system.cpu.dcache.overall_mshr_hits::cpu.data 38911 # number of overall MSHR hits 488system.cpu.dcache.overall_mshr_hits::total 38911 # number of overall MSHR hits 489system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903417 # number of ReadReq MSHR misses 490system.cpu.dcache.ReadReq_mshr_misses::total 903417 # number of ReadReq MSHR misses 491system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses 492system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses 493system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 494system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 495system.cpu.dcache.demand_mshr_misses::cpu.data 950181 # number of demand (read+write) MSHR misses 496system.cpu.dcache.demand_mshr_misses::total 950181 # number of demand (read+write) MSHR misses 497system.cpu.dcache.overall_mshr_misses::cpu.data 950184 # number of overall MSHR misses 498system.cpu.dcache.overall_mshr_misses::total 950184 # number of overall MSHR misses 499system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412913006 # number of ReadReq MSHR miss cycles 500system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412913006 # number of ReadReq MSHR miss cycles 501system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464006500 # number of WriteReq MSHR miss cycles 502system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464006500 # number of WriteReq MSHR miss cycles 503system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles 504system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles 505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876919506 # number of demand (read+write) MSHR miss cycles 506system.cpu.dcache.demand_mshr_miss_latency::total 11876919506 # number of demand (read+write) MSHR miss cycles 507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877075006 # number of overall MSHR miss cycles 508system.cpu.dcache.overall_mshr_miss_latency::total 11877075006 # number of overall MSHR miss cycles 509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses 510system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses 511system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 512system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 513system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 514system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 515system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses 516system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses 517system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034870 # mshr miss rate for overall accesses 518system.cpu.dcache.overall_mshr_miss_rate::total 0.034870 # mshr miss rate for overall accesses 519system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.142419 # average ReadReq mshr miss latency 520system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.142419 # average ReadReq mshr miss latency 521system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31306.271919 # average WriteReq mshr miss latency 522system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31306.271919 # average WriteReq mshr miss latency 523system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency 524system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency 525system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.639022 # average overall mshr miss latency 526system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.639022 # average overall mshr miss latency 527system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.763210 # average overall mshr miss latency 528system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.763210 # average overall mshr miss latency 529system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 530system.cpu.icache.tags.replacements 4 # number of replacements 531system.cpu.icache.tags.tagsinuse 690.351832 # Cycle average of tags in use 532system.cpu.icache.tags.total_refs 27857021 # Total number of references to valid blocks. 533system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. 534system.cpu.icache.tags.avg_refs 34734.440150 # Average number of references to valid blocks. 535system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 536system.cpu.icache.tags.occ_blocks::cpu.inst 690.351832 # Average occupied blocks per requestor 537system.cpu.icache.tags.occ_percent::cpu.inst 0.337086 # Average percentage of cache occupancy 538system.cpu.icache.tags.occ_percent::total 0.337086 # Average percentage of cache occupancy 539system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id 540system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 541system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id 543system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id 544system.cpu.icache.tags.tag_accesses 55716448 # Number of tag accesses 545system.cpu.icache.tags.data_accesses 55716448 # Number of data accesses 546system.cpu.icache.ReadReq_hits::cpu.inst 27857021 # number of ReadReq hits 547system.cpu.icache.ReadReq_hits::total 27857021 # number of ReadReq hits 548system.cpu.icache.demand_hits::cpu.inst 27857021 # number of demand (read+write) hits 549system.cpu.icache.demand_hits::total 27857021 # number of demand (read+write) hits 550system.cpu.icache.overall_hits::cpu.inst 27857021 # number of overall hits 551system.cpu.icache.overall_hits::total 27857021 # number of overall hits 552system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses 553system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses 554system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses 555system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses 556system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses 557system.cpu.icache.overall_misses::total 802 # number of overall misses 558system.cpu.icache.ReadReq_miss_latency::cpu.inst 60516997 # number of ReadReq miss cycles 559system.cpu.icache.ReadReq_miss_latency::total 60516997 # number of ReadReq miss cycles 560system.cpu.icache.demand_miss_latency::cpu.inst 60516997 # number of demand (read+write) miss cycles 561system.cpu.icache.demand_miss_latency::total 60516997 # number of demand (read+write) miss cycles 562system.cpu.icache.overall_miss_latency::cpu.inst 60516997 # number of overall miss cycles 563system.cpu.icache.overall_miss_latency::total 60516997 # number of overall miss cycles 564system.cpu.icache.ReadReq_accesses::cpu.inst 27857823 # number of ReadReq accesses(hits+misses) 565system.cpu.icache.ReadReq_accesses::total 27857823 # number of ReadReq accesses(hits+misses) 566system.cpu.icache.demand_accesses::cpu.inst 27857823 # number of demand (read+write) accesses 567system.cpu.icache.demand_accesses::total 27857823 # number of demand (read+write) accesses 568system.cpu.icache.overall_accesses::cpu.inst 27857823 # number of overall (read+write) accesses 569system.cpu.icache.overall_accesses::total 27857823 # number of overall (read+write) accesses 570system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 571system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 572system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 573system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 574system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 575system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses 576system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75457.602244 # average ReadReq miss latency 577system.cpu.icache.ReadReq_avg_miss_latency::total 75457.602244 # average ReadReq miss latency 578system.cpu.icache.demand_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency 579system.cpu.icache.demand_avg_miss_latency::total 75457.602244 # average overall miss latency 580system.cpu.icache.overall_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency 581system.cpu.icache.overall_avg_miss_latency::total 75457.602244 # average overall miss latency 582system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 583system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 584system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 585system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 586system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 587system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 588system.cpu.icache.fast_writes 0 # number of fast writes performed 589system.cpu.icache.cache_copies 0 # number of cache copies performed 590system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses 591system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses 592system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses 593system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses 594system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses 595system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses 596system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58977003 # number of ReadReq MSHR miss cycles 597system.cpu.icache.ReadReq_mshr_miss_latency::total 58977003 # number of ReadReq MSHR miss cycles 598system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58977003 # number of demand (read+write) MSHR miss cycles 599system.cpu.icache.demand_mshr_miss_latency::total 58977003 # number of demand (read+write) MSHR miss cycles 600system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58977003 # number of overall MSHR miss cycles 601system.cpu.icache.overall_mshr_miss_latency::total 58977003 # number of overall MSHR miss cycles 602system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 603system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 604system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 605system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 606system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 607system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses 608system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73537.410224 # average ReadReq mshr miss latency 609system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73537.410224 # average ReadReq mshr miss latency 610system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency 611system.cpu.icache.demand_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency 612system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency 613system.cpu.icache.overall_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency 614system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 615system.cpu.l2cache.tags.replacements 0 # number of replacements 616system.cpu.l2cache.tags.tagsinuse 10237.784168 # Cycle average of tags in use 617system.cpu.l2cache.tags.total_refs 1831298 # Total number of references to valid blocks. 618system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. 619system.cpu.l2cache.tags.avg_refs 117.715369 # Average number of references to valid blocks. 620system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 621system.cpu.l2cache.tags.occ_blocks::writebacks 9347.997887 # Average occupied blocks per requestor 622system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.378262 # Average occupied blocks per requestor 623system.cpu.l2cache.tags.occ_blocks::cpu.data 215.408019 # Average occupied blocks per requestor 624system.cpu.l2cache.tags.occ_percent::writebacks 0.285278 # Average percentage of cache occupancy 625system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020580 # Average percentage of cache occupancy 626system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy 627system.cpu.l2cache.tags.occ_percent::total 0.312432 # Average percentage of cache occupancy 628system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id 629system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 630system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 631system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 632system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id 633system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13877 # Occupied blocks per task id 634system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id 635system.cpu.l2cache.tags.tag_accesses 15216337 # Number of tag accesses 636system.cpu.l2cache.tags.data_accesses 15216337 # Number of data accesses 637system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits 638system.cpu.l2cache.ReadReq_hits::cpu.data 903158 # number of ReadReq hits 639system.cpu.l2cache.ReadReq_hits::total 903183 # number of ReadReq hits 640system.cpu.l2cache.Writeback_hits::writebacks 943266 # number of Writeback hits 641system.cpu.l2cache.Writeback_hits::total 943266 # number of Writeback hits 642system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 643system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 644system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits 645system.cpu.l2cache.demand_hits::cpu.data 935378 # number of demand (read+write) hits 646system.cpu.l2cache.demand_hits::total 935403 # number of demand (read+write) hits 647system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits 648system.cpu.l2cache.overall_hits::cpu.data 935378 # number of overall hits 649system.cpu.l2cache.overall_hits::total 935403 # number of overall hits 650system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses 651system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses 652system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses 653system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses 654system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses 655system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses 656system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses 657system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses 658system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses 659system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses 660system.cpu.l2cache.overall_misses::total 15583 # number of overall misses 661system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57912500 # number of ReadReq miss cycles 662system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22184500 # number of ReadReq miss cycles 663system.cpu.l2cache.ReadReq_miss_latency::total 80097000 # number of ReadReq miss cycles 664system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073519250 # number of ReadExReq miss cycles 665system.cpu.l2cache.ReadExReq_miss_latency::total 1073519250 # number of ReadExReq miss cycles 666system.cpu.l2cache.demand_miss_latency::cpu.inst 57912500 # number of demand (read+write) miss cycles 667system.cpu.l2cache.demand_miss_latency::cpu.data 1095703750 # number of demand (read+write) miss cycles 668system.cpu.l2cache.demand_miss_latency::total 1153616250 # number of demand (read+write) miss cycles 669system.cpu.l2cache.overall_miss_latency::cpu.inst 57912500 # number of overall miss cycles 670system.cpu.l2cache.overall_miss_latency::cpu.data 1095703750 # number of overall miss cycles 671system.cpu.l2cache.overall_miss_latency::total 1153616250 # number of overall miss cycles 672system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) 673system.cpu.l2cache.ReadReq_accesses::cpu.data 903420 # number of ReadReq accesses(hits+misses) 674system.cpu.l2cache.ReadReq_accesses::total 904222 # number of ReadReq accesses(hits+misses) 675system.cpu.l2cache.Writeback_accesses::writebacks 943266 # number of Writeback accesses(hits+misses) 676system.cpu.l2cache.Writeback_accesses::total 943266 # number of Writeback accesses(hits+misses) 677system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) 678system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) 679system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses 680system.cpu.l2cache.demand_accesses::cpu.data 950184 # number of demand (read+write) accesses 681system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses 682system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses 683system.cpu.l2cache.overall_accesses::cpu.data 950184 # number of overall (read+write) accesses 684system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses 685system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968828 # miss rate for ReadReq accesses 686system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses 687system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses 688system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses 689system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses 690system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968828 # miss rate for demand accesses 691system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses 692system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses 693system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968828 # miss rate for overall accesses 694system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses 695system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses 696system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74533.462033 # average ReadReq miss latency 697system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84673.664122 # average ReadReq miss latency 698system.cpu.l2cache.ReadReq_avg_miss_latency::total 77090.471607 # average ReadReq miss latency 699system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73811.829620 # average ReadExReq miss latency 700system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73811.829620 # average ReadExReq miss latency 701system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency 702system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency 703system.cpu.l2cache.demand_avg_miss_latency::total 74030.433806 # average overall miss latency 704system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency 705system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency 706system.cpu.l2cache.overall_avg_miss_latency::total 74030.433806 # average overall miss latency 707system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 708system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 709system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 710system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 711system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 712system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 713system.cpu.l2cache.fast_writes 0 # number of fast writes performed 714system.cpu.l2cache.cache_copies 0 # number of cache copies performed 715system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 716system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 717system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 718system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 719system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 720system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits 721system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 722system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 723system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits 724system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses 725system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses 726system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses 727system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses 728system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 729system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses 730system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses 731system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 732system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses 733system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses 734system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses 735system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48052500 # number of ReadReq MSHR miss cycles 736system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18582500 # number of ReadReq MSHR miss cycles 737system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66635000 # number of ReadReq MSHR miss cycles 738system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891707750 # number of ReadExReq MSHR miss cycles 739system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891707750 # number of ReadExReq MSHR miss cycles 740system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48052500 # number of demand (read+write) MSHR miss cycles 741system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910290250 # number of demand (read+write) MSHR miss cycles 742system.cpu.l2cache.demand_mshr_miss_latency::total 958342750 # number of demand (read+write) MSHR miss cycles 743system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48052500 # number of overall MSHR miss cycles 744system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910290250 # number of overall MSHR miss cycles 745system.cpu.l2cache.overall_mshr_miss_latency::total 958342750 # number of overall MSHR miss cycles 746system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadReq accesses 747system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses 748system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses 749system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses 750system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses 751system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses 752system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses 753system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 754system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses 755system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses 756system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses 757system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62083.333333 # average ReadReq mshr miss latency 758system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72587.890625 # average ReadReq mshr miss latency 759system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64694.174757 # average ReadReq mshr miss latency 760system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61311.038916 # average ReadExReq mshr miss latency 761system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61311.038916 # average ReadExReq mshr miss latency 762system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency 763system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency 764system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency 765system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency 766system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency 767system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency 768system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 769system.cpu.toL2Bus.trans_dist::ReadReq 904222 # Transaction distribution 770system.cpu.toL2Bus.trans_dist::ReadResp 904222 # Transaction distribution 771system.cpu.toL2Bus.trans_dist::Writeback 943266 # Transaction distribution 772system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 773system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 774system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes) 775system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843634 # Packet count per connected master and slave (bytes) 776system.cpu.toL2Bus.pkt_count::total 2845238 # Packet count per connected master and slave (bytes) 777system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) 778system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121180800 # Cumulative packet size per connected master and slave (bytes) 779system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes) 780system.cpu.toL2Bus.snoops 0 # Total snoops (count) 781system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram
782system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram	782system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
783system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 784system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 785system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram	783system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 784system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 785system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
786system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 787system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 788system.cpu.toL2Bus.snoop_fanout::3 1894252 100.00% 100.00% # Request fanout histogram 789system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram	786system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram 787system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
790system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram	788system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
791system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 792system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram	789system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 790system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
793system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram 794system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks) 795system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) 796system.cpu.toL2Bus.respLayer0.occupancy 1371497 # Layer occupancy (ticks) 797system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 798system.cpu.toL2Bus.respLayer1.occupancy 1428656494 # Layer occupancy (ticks) 799system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 800system.membus.trans_dist::ReadReq 1030 # Transaction distribution 801system.membus.trans_dist::ReadResp 1030 # Transaction distribution 802system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 803system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 804system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) 805system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) 806system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) 807system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) 808system.membus.snoops 0 # Total snoops (count) 809system.membus.snoop_fanout::samples 15574 # Request fanout histogram 810system.membus.snoop_fanout::mean 0 # Request fanout histogram 811system.membus.snoop_fanout::stdev 0 # Request fanout histogram 812system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 813system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 814system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 815system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 816system.membus.snoop_fanout::min_value 0 # Request fanout histogram 817system.membus.snoop_fanout::max_value 0 # Request fanout histogram 818system.membus.snoop_fanout::total 15574 # Request fanout histogram 819system.membus.reqLayer0.occupancy 21629000 # Layer occupancy (ticks) 820system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 821system.membus.respLayer1.occupancy 82142750 # Layer occupancy (ticks) 822system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 823 824---------- End Simulation Statistics ----------	791system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram 792system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks) 793system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) 794system.cpu.toL2Bus.respLayer0.occupancy 1371497 # Layer occupancy (ticks) 795system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 796system.cpu.toL2Bus.respLayer1.occupancy 1428656494 # Layer occupancy (ticks) 797system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 798system.membus.trans_dist::ReadReq 1030 # Transaction distribution 799system.membus.trans_dist::ReadResp 1030 # Transaction distribution 800system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 801system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 802system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) 803system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) 804system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) 805system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) 806system.membus.snoops 0 # Total snoops (count) 807system.membus.snoop_fanout::samples 15574 # Request fanout histogram 808system.membus.snoop_fanout::mean 0 # Request fanout histogram 809system.membus.snoop_fanout::stdev 0 # Request fanout histogram 810system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 811system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 812system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 813system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 814system.membus.snoop_fanout::min_value 0 # Request fanout histogram 815system.membus.snoop_fanout::max_value 0 # Request fanout histogram 816system.membus.snoop_fanout::total 15574 # Request fanout histogram 817system.membus.reqLayer0.occupancy 21629000 # Layer occupancy (ticks) 818system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 819system.membus.respLayer1.occupancy 82142750 # Layer occupancy (ticks) 820system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 821 822---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.061594 # Number of seconds simulated
4sim_ticks 61594138500 # Number of ticks simulated
5final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 196979 # Simulator instruction rate (inst/s)
8host_op_rate 197960 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 133911114 # Simulator tick rate (ticks/s)
10host_mem_usage 438496 # Number of bytes of host memory used
11host_seconds 459.96 # Real time elapsed on the host

7host_inst_rate 265976 # Simulator instruction rate (inst/s)
8host_op_rate 267300 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 180817037 # Simulator tick rate (ticks/s)
10host_mem_usage 446692 # Number of bytes of host memory used
11host_seconds 340.64 # Real time elapsed on the host

12sim_insts 90602850 # Number of instructions simulated
13sim_ops 91054081 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
18system.physmem.bytes_read::total 996736 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 804232 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 15378087 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 16182319 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 804232 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 804232 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 804232 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 15378087 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 16182319 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 15574 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 993 # Per bank write bursts
45system.physmem.perBankRdBursts::1 890 # Per bank write bursts
46system.physmem.perBankRdBursts::2 949 # Per bank write bursts
47system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
48system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
49system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
50system.physmem.perBankRdBursts::6 1087 # Per bank write bursts
51system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
52system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
53system.physmem.perBankRdBursts::9 962 # Per bank write bursts
54system.physmem.perBankRdBursts::10 938 # Per bank write bursts
55system.physmem.perBankRdBursts::11 899 # Per bank write bursts
56system.physmem.perBankRdBursts::12 904 # Per bank write bursts
57system.physmem.perBankRdBursts::13 867 # Per bank write bursts
58system.physmem.perBankRdBursts::14 877 # Per bank write bursts
59system.physmem.perBankRdBursts::15 905 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 61594044000 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 15574 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 646.025974 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 441.784218 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 399.527843 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 247 16.04% 16.04% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 180 11.69% 27.73% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 88 5.71% 33.44% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 68 4.42% 37.86% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 78 5.06% 42.92% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 95 6.17% 49.09% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 49 3.18% 52.27% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 35 2.27% 54.55% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 700 45.45% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
203system.physmem.totQLat 76216750 # Total ticks spent queuing
204system.physmem.totMemAccLat 368229250 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 4893.85 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 23643.85 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 0.13 # Data bus utilization in percentage
215system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 14024 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223system.physmem.avgGap 3954927.70 # Average gap between requests
224system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined
225system.physmem_0.actEnergy 6327720 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 3452625 # Energy for precharge commands per rank (pJ)
227system.physmem_0.readEnergy 63655800 # Energy for read commands per rank (pJ)
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
230system.physmem_0.actBackEnergy 2561139675 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 34707076500 # Energy for precharge background per rank (pJ)
232system.physmem_0.totalEnergy 41364361920 # Total energy per rank (pJ)
233system.physmem_0.averagePower 671.614039 # Core power per rank (mW)
234system.physmem_0.memoryStateTime::IDLE 57728641000 # Time in different power states
235system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237system.physmem_0.memoryStateTime::ACT 1804854500 # Time in different power states
238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 5299560 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
244system.physmem_1.actBackEnergy 2570808870 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 34698594750 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 41357767005 # Total energy per rank (pJ)
247system.physmem_1.averagePower 671.506960 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 57715756250 # Time in different power states
249system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 1818578750 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253system.cpu.branchPred.lookups 20791997 # Number of BP lookups
254system.cpu.branchPred.condPredicted 17093861 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 766355 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 8982065 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 8866075 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 98.708649 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 62635 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
262system.cpu_clk_domain.clock 500 # Clock period in ticks
263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
271system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
272system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
273system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
274system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
275system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
276system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
277system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
278system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
279system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
280system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
281system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
282system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
283system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
284system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
285system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
286system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
287system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
288system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
289system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
290system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
291system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
292system.cpu.dtb.walker.walks 0 # Table walker walks requested
293system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
294system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
295system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
296system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
297system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
298system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
299system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
300system.cpu.dtb.inst_hits 0 # ITB inst hits
301system.cpu.dtb.inst_misses 0 # ITB inst misses
302system.cpu.dtb.read_hits 0 # DTB read hits
303system.cpu.dtb.read_misses 0 # DTB read misses
304system.cpu.dtb.write_hits 0 # DTB write hits
305system.cpu.dtb.write_misses 0 # DTB write misses
306system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
307system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
308system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
309system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
310system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
311system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
312system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
313system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
314system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
315system.cpu.dtb.read_accesses 0 # DTB read accesses
316system.cpu.dtb.write_accesses 0 # DTB write accesses
317system.cpu.dtb.inst_accesses 0 # ITB inst accesses
318system.cpu.dtb.hits 0 # DTB hits
319system.cpu.dtb.misses 0 # DTB misses
320system.cpu.dtb.accesses 0 # DTB accesses
321system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
322system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
323system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
324system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
325system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
329system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
330system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
331system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
332system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
333system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
334system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
335system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
336system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
337system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
338system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
339system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
340system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
341system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
342system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
343system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
344system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
345system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
346system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
347system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
348system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
349system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
350system.cpu.itb.walker.walks 0 # Table walker walks requested
351system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
352system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
353system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
354system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
355system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
356system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
357system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
358system.cpu.itb.inst_hits 0 # ITB inst hits
359system.cpu.itb.inst_misses 0 # ITB inst misses
360system.cpu.itb.read_hits 0 # DTB read hits
361system.cpu.itb.read_misses 0 # DTB read misses
362system.cpu.itb.write_hits 0 # DTB write hits
363system.cpu.itb.write_misses 0 # DTB write misses
364system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
365system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
366system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
367system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
368system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
369system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
370system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
371system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
373system.cpu.itb.read_accesses 0 # DTB read accesses
374system.cpu.itb.write_accesses 0 # DTB write accesses
375system.cpu.itb.inst_accesses 0 # ITB inst accesses
376system.cpu.itb.hits 0 # DTB hits
377system.cpu.itb.misses 0 # DTB misses
378system.cpu.itb.accesses 0 # DTB accesses
379system.cpu.workload.num_syscalls 442 # Number of system calls
380system.cpu.numCycles 123188277 # number of cpu cycles simulated
381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
383system.cpu.committedInsts 90602850 # Number of instructions committed
384system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
385system.cpu.discardedOps 2070154 # Number of ops (including micro ops) which were discarded before commit
386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
387system.cpu.cpi 1.359651 # CPI: cycles per instruction
388system.cpu.ipc 0.735483 # IPC: instructions per cycle
389system.cpu.tickCycles 109833647 # Number of cycles that the object actually ticked
390system.cpu.idleCycles 13354630 # Total number of cycles that the object has spent stopped
391system.cpu.dcache.tags.replacements 946088 # number of replacements
392system.cpu.dcache.tags.tagsinuse 3616.165317 # Cycle average of tags in use
393system.cpu.dcache.tags.total_refs 26267708 # Total number of references to valid blocks.
394system.cpu.dcache.tags.sampled_refs 950184 # Sample count of references to valid blocks.
395system.cpu.dcache.tags.avg_refs 27.644865 # Average number of references to valid blocks.
396system.cpu.dcache.tags.warmup_cycle 20660513250 # Cycle when the warmup percentage was hit.
397system.cpu.dcache.tags.occ_blocks::cpu.data 3616.165317 # Average occupied blocks per requestor
398system.cpu.dcache.tags.occ_percent::cpu.data 0.882853 # Average percentage of cache occupancy
399system.cpu.dcache.tags.occ_percent::total 0.882853 # Average percentage of cache occupancy
400system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
401system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
402system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id
403system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id
404system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
405system.cpu.dcache.tags.tag_accesses 55463792 # Number of tag accesses
406system.cpu.dcache.tags.data_accesses 55463792 # Number of data accesses
407system.cpu.dcache.ReadReq_hits::cpu.data 21598607 # number of ReadReq hits
408system.cpu.dcache.ReadReq_hits::total 21598607 # number of ReadReq hits
409system.cpu.dcache.WriteReq_hits::cpu.data 4660819 # number of WriteReq hits
410system.cpu.dcache.WriteReq_hits::total 4660819 # number of WriteReq hits
411system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
412system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
413system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
414system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
415system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
416system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
417system.cpu.dcache.demand_hits::cpu.data 26259426 # number of demand (read+write) hits
418system.cpu.dcache.demand_hits::total 26259426 # number of demand (read+write) hits
419system.cpu.dcache.overall_hits::cpu.data 26259934 # number of overall hits
420system.cpu.dcache.overall_hits::total 26259934 # number of overall hits
421system.cpu.dcache.ReadReq_misses::cpu.data 914930 # number of ReadReq misses
422system.cpu.dcache.ReadReq_misses::total 914930 # number of ReadReq misses
423system.cpu.dcache.WriteReq_misses::cpu.data 74162 # number of WriteReq misses
424system.cpu.dcache.WriteReq_misses::total 74162 # number of WriteReq misses
425system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
426system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
427system.cpu.dcache.demand_misses::cpu.data 989092 # number of demand (read+write) misses
428system.cpu.dcache.demand_misses::total 989092 # number of demand (read+write) misses
429system.cpu.dcache.overall_misses::cpu.data 989096 # number of overall misses
430system.cpu.dcache.overall_misses::total 989096 # number of overall misses
431system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918229494 # number of ReadReq miss cycles
432system.cpu.dcache.ReadReq_miss_latency::total 11918229494 # number of ReadReq miss cycles
433system.cpu.dcache.WriteReq_miss_latency::cpu.data 2567046500 # number of WriteReq miss cycles
434system.cpu.dcache.WriteReq_miss_latency::total 2567046500 # number of WriteReq miss cycles
435system.cpu.dcache.demand_miss_latency::cpu.data 14485275994 # number of demand (read+write) miss cycles
436system.cpu.dcache.demand_miss_latency::total 14485275994 # number of demand (read+write) miss cycles
437system.cpu.dcache.overall_miss_latency::cpu.data 14485275994 # number of overall miss cycles
438system.cpu.dcache.overall_miss_latency::total 14485275994 # number of overall miss cycles
439system.cpu.dcache.ReadReq_accesses::cpu.data 22513537 # number of ReadReq accesses(hits+misses)
440system.cpu.dcache.ReadReq_accesses::total 22513537 # number of ReadReq accesses(hits+misses)
441system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
442system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
443system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
444system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses)
445system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
446system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
447system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
448system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
449system.cpu.dcache.demand_accesses::cpu.data 27248518 # number of demand (read+write) accesses
450system.cpu.dcache.demand_accesses::total 27248518 # number of demand (read+write) accesses
451system.cpu.dcache.overall_accesses::cpu.data 27249030 # number of overall (read+write) accesses
452system.cpu.dcache.overall_accesses::total 27249030 # number of overall (read+write) accesses
453system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses
454system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses
455system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015663 # miss rate for WriteReq accesses
456system.cpu.dcache.WriteReq_miss_rate::total 0.015663 # miss rate for WriteReq accesses
457system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
458system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
459system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses
460system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses
461system.cpu.dcache.overall_miss_rate::cpu.data 0.036298 # miss rate for overall accesses
462system.cpu.dcache.overall_miss_rate::total 0.036298 # miss rate for overall accesses
463system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.383979 # average ReadReq miss latency
464system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.383979 # average ReadReq miss latency
465system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34614.040883 # average WriteReq miss latency
466system.cpu.dcache.WriteReq_avg_miss_latency::total 34614.040883 # average WriteReq miss latency
467system.cpu.dcache.demand_avg_miss_latency::cpu.data 14645.023915 # average overall miss latency
468system.cpu.dcache.demand_avg_miss_latency::total 14645.023915 # average overall miss latency
469system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.964689 # average overall miss latency
470system.cpu.dcache.overall_avg_miss_latency::total 14644.964689 # average overall miss latency
471system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
472system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
473system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
474system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
475system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
476system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
477system.cpu.dcache.fast_writes 0 # number of fast writes performed
478system.cpu.dcache.cache_copies 0 # number of cache copies performed
479system.cpu.dcache.writebacks::writebacks 943266 # number of writebacks
480system.cpu.dcache.writebacks::total 943266 # number of writebacks
481system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11513 # number of ReadReq MSHR hits
482system.cpu.dcache.ReadReq_mshr_hits::total 11513 # number of ReadReq MSHR hits
483system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27398 # number of WriteReq MSHR hits
484system.cpu.dcache.WriteReq_mshr_hits::total 27398 # number of WriteReq MSHR hits
485system.cpu.dcache.demand_mshr_hits::cpu.data 38911 # number of demand (read+write) MSHR hits
486system.cpu.dcache.demand_mshr_hits::total 38911 # number of demand (read+write) MSHR hits
487system.cpu.dcache.overall_mshr_hits::cpu.data 38911 # number of overall MSHR hits
488system.cpu.dcache.overall_mshr_hits::total 38911 # number of overall MSHR hits
489system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903417 # number of ReadReq MSHR misses
490system.cpu.dcache.ReadReq_mshr_misses::total 903417 # number of ReadReq MSHR misses
491system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
492system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
493system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
494system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
495system.cpu.dcache.demand_mshr_misses::cpu.data 950181 # number of demand (read+write) MSHR misses
496system.cpu.dcache.demand_mshr_misses::total 950181 # number of demand (read+write) MSHR misses
497system.cpu.dcache.overall_mshr_misses::cpu.data 950184 # number of overall MSHR misses
498system.cpu.dcache.overall_mshr_misses::total 950184 # number of overall MSHR misses
499system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412913006 # number of ReadReq MSHR miss cycles
500system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412913006 # number of ReadReq MSHR miss cycles
501system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464006500 # number of WriteReq MSHR miss cycles
502system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464006500 # number of WriteReq MSHR miss cycles
503system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles
504system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles
505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876919506 # number of demand (read+write) MSHR miss cycles
506system.cpu.dcache.demand_mshr_miss_latency::total 11876919506 # number of demand (read+write) MSHR miss cycles
507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877075006 # number of overall MSHR miss cycles
508system.cpu.dcache.overall_mshr_miss_latency::total 11877075006 # number of overall MSHR miss cycles
509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses
510system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses
511system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
512system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
513system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
514system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
515system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses
516system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
517system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034870 # mshr miss rate for overall accesses
518system.cpu.dcache.overall_mshr_miss_rate::total 0.034870 # mshr miss rate for overall accesses
519system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.142419 # average ReadReq mshr miss latency
520system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.142419 # average ReadReq mshr miss latency
521system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31306.271919 # average WriteReq mshr miss latency
522system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31306.271919 # average WriteReq mshr miss latency
523system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency
524system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency
525system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.639022 # average overall mshr miss latency
526system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.639022 # average overall mshr miss latency
527system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.763210 # average overall mshr miss latency
528system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.763210 # average overall mshr miss latency
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533system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
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535system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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537system.cpu.icache.tags.occ_percent::cpu.inst 0.337086 # Average percentage of cache occupancy
538system.cpu.icache.tags.occ_percent::total 0.337086 # Average percentage of cache occupancy
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541system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
542system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
543system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
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547system.cpu.icache.ReadReq_hits::total 27857021 # number of ReadReq hits
548system.cpu.icache.demand_hits::cpu.inst 27857021 # number of demand (read+write) hits
549system.cpu.icache.demand_hits::total 27857021 # number of demand (read+write) hits
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551system.cpu.icache.overall_hits::total 27857021 # number of overall hits
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553system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
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555system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
556system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
557system.cpu.icache.overall_misses::total 802 # number of overall misses
558system.cpu.icache.ReadReq_miss_latency::cpu.inst 60516997 # number of ReadReq miss cycles
559system.cpu.icache.ReadReq_miss_latency::total 60516997 # number of ReadReq miss cycles
560system.cpu.icache.demand_miss_latency::cpu.inst 60516997 # number of demand (read+write) miss cycles
561system.cpu.icache.demand_miss_latency::total 60516997 # number of demand (read+write) miss cycles
562system.cpu.icache.overall_miss_latency::cpu.inst 60516997 # number of overall miss cycles
563system.cpu.icache.overall_miss_latency::total 60516997 # number of overall miss cycles
564system.cpu.icache.ReadReq_accesses::cpu.inst 27857823 # number of ReadReq accesses(hits+misses)
565system.cpu.icache.ReadReq_accesses::total 27857823 # number of ReadReq accesses(hits+misses)
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569system.cpu.icache.overall_accesses::total 27857823 # number of overall (read+write) accesses
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571system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
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573system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
574system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
575system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
576system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75457.602244 # average ReadReq miss latency
577system.cpu.icache.ReadReq_avg_miss_latency::total 75457.602244 # average ReadReq miss latency
578system.cpu.icache.demand_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency
579system.cpu.icache.demand_avg_miss_latency::total 75457.602244 # average overall miss latency
580system.cpu.icache.overall_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency
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587system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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589system.cpu.icache.cache_copies 0 # number of cache copies performed
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591system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses
592system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
593system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
594system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
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597system.cpu.icache.ReadReq_mshr_miss_latency::total 58977003 # number of ReadReq MSHR miss cycles
598system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58977003 # number of demand (read+write) MSHR miss cycles
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600system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58977003 # number of overall MSHR miss cycles
601system.cpu.icache.overall_mshr_miss_latency::total 58977003 # number of overall MSHR miss cycles
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603system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
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605system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
606system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
607system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
608system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73537.410224 # average ReadReq mshr miss latency
609system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73537.410224 # average ReadReq mshr miss latency
610system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency
611system.cpu.icache.demand_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency
612system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency
613system.cpu.icache.overall_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency
614system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
615system.cpu.l2cache.tags.replacements 0 # number of replacements
616system.cpu.l2cache.tags.tagsinuse 10237.784168 # Cycle average of tags in use
617system.cpu.l2cache.tags.total_refs 1831298 # Total number of references to valid blocks.
618system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
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620system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
621system.cpu.l2cache.tags.occ_blocks::writebacks 9347.997887 # Average occupied blocks per requestor
622system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.378262 # Average occupied blocks per requestor
623system.cpu.l2cache.tags.occ_blocks::cpu.data 215.408019 # Average occupied blocks per requestor
624system.cpu.l2cache.tags.occ_percent::writebacks 0.285278 # Average percentage of cache occupancy
625system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020580 # Average percentage of cache occupancy
626system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy
627system.cpu.l2cache.tags.occ_percent::total 0.312432 # Average percentage of cache occupancy
628system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id
629system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
630system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
631system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
632system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
633system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13877 # Occupied blocks per task id
634system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id
635system.cpu.l2cache.tags.tag_accesses 15216337 # Number of tag accesses
636system.cpu.l2cache.tags.data_accesses 15216337 # Number of data accesses
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638system.cpu.l2cache.ReadReq_hits::cpu.data 903158 # number of ReadReq hits
639system.cpu.l2cache.ReadReq_hits::total 903183 # number of ReadReq hits
640system.cpu.l2cache.Writeback_hits::writebacks 943266 # number of Writeback hits
641system.cpu.l2cache.Writeback_hits::total 943266 # number of Writeback hits
642system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits
643system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits
644system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits
645system.cpu.l2cache.demand_hits::cpu.data 935378 # number of demand (read+write) hits
646system.cpu.l2cache.demand_hits::total 935403 # number of demand (read+write) hits
647system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits
648system.cpu.l2cache.overall_hits::cpu.data 935378 # number of overall hits
649system.cpu.l2cache.overall_hits::total 935403 # number of overall hits
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652system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses
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654system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
655system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses
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658system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses
659system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses
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661system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57912500 # number of ReadReq miss cycles
662system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22184500 # number of ReadReq miss cycles
663system.cpu.l2cache.ReadReq_miss_latency::total 80097000 # number of ReadReq miss cycles
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665system.cpu.l2cache.ReadExReq_miss_latency::total 1073519250 # number of ReadExReq miss cycles
666system.cpu.l2cache.demand_miss_latency::cpu.inst 57912500 # number of demand (read+write) miss cycles
667system.cpu.l2cache.demand_miss_latency::cpu.data 1095703750 # number of demand (read+write) miss cycles
668system.cpu.l2cache.demand_miss_latency::total 1153616250 # number of demand (read+write) miss cycles
669system.cpu.l2cache.overall_miss_latency::cpu.inst 57912500 # number of overall miss cycles
670system.cpu.l2cache.overall_miss_latency::cpu.data 1095703750 # number of overall miss cycles
671system.cpu.l2cache.overall_miss_latency::total 1153616250 # number of overall miss cycles
672system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses)
673system.cpu.l2cache.ReadReq_accesses::cpu.data 903420 # number of ReadReq accesses(hits+misses)
674system.cpu.l2cache.ReadReq_accesses::total 904222 # number of ReadReq accesses(hits+misses)
675system.cpu.l2cache.Writeback_accesses::writebacks 943266 # number of Writeback accesses(hits+misses)
676system.cpu.l2cache.Writeback_accesses::total 943266 # number of Writeback accesses(hits+misses)
677system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses)
678system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses)
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684system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses
685system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968828 # miss rate for ReadReq accesses
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687system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses
688system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses
689system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses
690system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968828 # miss rate for demand accesses
691system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses
692system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
693system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968828 # miss rate for overall accesses
694system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
695system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
696system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74533.462033 # average ReadReq miss latency
697system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84673.664122 # average ReadReq miss latency
698system.cpu.l2cache.ReadReq_avg_miss_latency::total 77090.471607 # average ReadReq miss latency
699system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73811.829620 # average ReadExReq miss latency
700system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73811.829620 # average ReadExReq miss latency
701system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency
702system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency
703system.cpu.l2cache.demand_avg_miss_latency::total 74030.433806 # average overall miss latency
704system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency
705system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency
706system.cpu.l2cache.overall_avg_miss_latency::total 74030.433806 # average overall miss latency
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708system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
709system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
710system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
711system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
712system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
713system.cpu.l2cache.fast_writes 0 # number of fast writes performed
714system.cpu.l2cache.cache_copies 0 # number of cache copies performed
715system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
716system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
717system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
718system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
719system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
720system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
721system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
722system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
723system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
724system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses
725system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses
726system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses
727system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses
728system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
729system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses
730system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses
731system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses
732system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses
733system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
734system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
735system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48052500 # number of ReadReq MSHR miss cycles
736system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18582500 # number of ReadReq MSHR miss cycles
737system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66635000 # number of ReadReq MSHR miss cycles
738system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891707750 # number of ReadExReq MSHR miss cycles
739system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891707750 # number of ReadExReq MSHR miss cycles
740system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48052500 # number of demand (read+write) MSHR miss cycles
741system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910290250 # number of demand (read+write) MSHR miss cycles
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743system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48052500 # number of overall MSHR miss cycles
744system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910290250 # number of overall MSHR miss cycles
745system.cpu.l2cache.overall_mshr_miss_latency::total 958342750 # number of overall MSHR miss cycles
746system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadReq accesses
747system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses
748system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses
749system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
750system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
751system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses
752system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses
753system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
754system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses
755system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
756system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
757system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62083.333333 # average ReadReq mshr miss latency
758system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72587.890625 # average ReadReq mshr miss latency
759system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64694.174757 # average ReadReq mshr miss latency
760system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61311.038916 # average ReadExReq mshr miss latency
761system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61311.038916 # average ReadExReq mshr miss latency
762system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency
763system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency
764system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency
765system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency
766system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency
767system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency
768system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
769system.cpu.toL2Bus.trans_dist::ReadReq 904222 # Transaction distribution
770system.cpu.toL2Bus.trans_dist::ReadResp 904222 # Transaction distribution
771system.cpu.toL2Bus.trans_dist::Writeback 943266 # Transaction distribution
772system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
773system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
774system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes)
775system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843634 # Packet count per connected master and slave (bytes)
776system.cpu.toL2Bus.pkt_count::total 2845238 # Packet count per connected master and slave (bytes)
777system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
778system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121180800 # Cumulative packet size per connected master and slave (bytes)
779system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes)
780system.cpu.toL2Bus.snoops 0 # Total snoops (count)
781system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram

782system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram

782system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram

783system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
784system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
785system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

786system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
787system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
788system.cpu.toL2Bus.snoop_fanout::3 1894252 100.00% 100.00% # Request fanout histogram
789system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram

786system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram
787system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram

790system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

788system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

791system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
792system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

789system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
790system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram