1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.061144 # Number of seconds simulated
4sim_ticks 61144411500 # Number of ticks simulated
5final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 271316 # Simulator instruction rate (inst/s)
8host_op_rate 272668 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 183101149 # Simulator tick rate (ticks/s)
10host_mem_usage 442968 # Number of bytes of host memory used
11host_seconds 333.94 # Real time elapsed on the host
12sim_insts 90602849 # Number of instructions simulated
13sim_ops 91054080 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 996736 # Number of bytes read from this memory
17system.physmem.bytes_read::total 996736 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory
20system.physmem.num_reads::cpu.inst 15574 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 16301343 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::total 16301343 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_inst_read::cpu.inst 811194 # Instruction read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::total 811194 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_total::cpu.inst 16301343 # Total bandwidth to/from this memory (bytes/s)
27system.physmem.bw_total::total 16301343 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.readReqs 15574 # Number of read requests accepted
29system.physmem.writeReqs 0 # Number of write requests accepted
30system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
32system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM
33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
35system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side
36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
40system.physmem.perBankRdBursts::0 993 # Per bank write bursts
41system.physmem.perBankRdBursts::1 890 # Per bank write bursts
42system.physmem.perBankRdBursts::2 950 # Per bank write bursts
43system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
44system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
45system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
46system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
47system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
48system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
49system.physmem.perBankRdBursts::9 962 # Per bank write bursts
50system.physmem.perBankRdBursts::10 938 # Per bank write bursts
51system.physmem.perBankRdBursts::11 899 # Per bank write bursts
52system.physmem.perBankRdBursts::12 903 # Per bank write bursts
53system.physmem.perBankRdBursts::13 867 # Per bank write bursts
54system.physmem.perBankRdBursts::14 877 # Per bank write bursts
55system.physmem.perBankRdBursts::15 904 # Per bank write bursts
56system.physmem.perBankWrBursts::0 0 # Per bank write bursts
57system.physmem.perBankWrBursts::1 0 # Per bank write bursts
58system.physmem.perBankWrBursts::2 0 # Per bank write bursts
59system.physmem.perBankWrBursts::3 0 # Per bank write bursts
60system.physmem.perBankWrBursts::4 0 # Per bank write bursts
61system.physmem.perBankWrBursts::5 0 # Per bank write bursts
62system.physmem.perBankWrBursts::6 0 # Per bank write bursts
63system.physmem.perBankWrBursts::7 0 # Per bank write bursts
64system.physmem.perBankWrBursts::8 0 # Per bank write bursts
65system.physmem.perBankWrBursts::9 0 # Per bank write bursts
66system.physmem.perBankWrBursts::10 0 # Per bank write bursts
67system.physmem.perBankWrBursts::11 0 # Per bank write bursts
68system.physmem.perBankWrBursts::12 0 # Per bank write bursts
69system.physmem.perBankWrBursts::13 0 # Per bank write bursts
70system.physmem.perBankWrBursts::14 0 # Per bank write bursts
71system.physmem.perBankWrBursts::15 0 # Per bank write bursts
72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
74system.physmem.totGap 61144323500 # Total gap between requests
75system.physmem.readPktSize::0 0 # Read request sizes (log2)
76system.physmem.readPktSize::1 0 # Read request sizes (log2)
77system.physmem.readPktSize::2 0 # Read request sizes (log2)
78system.physmem.readPktSize::3 0 # Read request sizes (log2)
79system.physmem.readPktSize::4 0 # Read request sizes (log2)
80system.physmem.readPktSize::5 0 # Read request sizes (log2)
81system.physmem.readPktSize::6 15574 # Read request sizes (log2)
82system.physmem.writePktSize::0 0 # Write request sizes (log2)
83system.physmem.writePktSize::1 0 # Write request sizes (log2)
84system.physmem.writePktSize::2 0 # Write request sizes (log2)
85system.physmem.writePktSize::3 0 # Write request sizes (log2)
86system.physmem.writePktSize::4 0 # Write request sizes (log2)
87system.physmem.writePktSize::5 0 # Write request sizes (log2)
88system.physmem.writePktSize::6 0 # Write request sizes (log2)
89system.physmem.rdQLenPdf::0 15451 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
--- 77 unchanged lines hidden (view full) ---
177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
185system.physmem.bytesPerActivate::samples 1531 # Bytes accessed per row activation
186system.physmem.bytesPerActivate::mean 649.865447 # Bytes accessed per row activation
187system.physmem.bytesPerActivate::gmean 447.084914 # Bytes accessed per row activation
188system.physmem.bytesPerActivate::stdev 397.724653 # Bytes accessed per row activation
189system.physmem.bytesPerActivate::0-127 242 15.81% 15.81% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::128-255 164 10.71% 26.52% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::256-383 94 6.14% 32.66% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::384-511 77 5.03% 37.69% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::512-639 65 4.25% 41.93% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::640-767 106 6.92% 48.86% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation
199system.physmem.totQLat 71490500 # Total ticks spent queuing
200system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM
201system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
202system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst
203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
204system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst
205system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s
206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
207system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s
208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
210system.physmem.busUtil 0.13 # Data bus utilization in percentage
211system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
213system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
215system.physmem.readRowHits 14033 # Number of row buffer hits during reads
216system.physmem.writeRowHits 0 # Number of row buffer hits during writes
217system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads
218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
219system.physmem.avgGap 3926051.34 # Average gap between requests
220system.physmem.pageHitRate 90.11 # Row buffer hit rate, read and write combined
221system.physmem.memoryStateTime::IDLE 55905599000 # Time in different power states
222system.physmem.memoryStateTime::REF 2041520000 # Time in different power states
223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
224system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states
225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
226system.physmem.actEnergy::0 6305040 # Energy for activate commands per rank (pJ)
227system.physmem.actEnergy::1 5254200 # Energy for activate commands per rank (pJ)
228system.physmem.preEnergy::0 3440250 # Energy for precharge commands per rank (pJ)
229system.physmem.preEnergy::1 2866875 # Energy for precharge commands per rank (pJ)
230system.physmem.readEnergy::0 63671400 # Energy for read commands per rank (pJ)
231system.physmem.readEnergy::1 57454800 # Energy for read commands per rank (pJ)
232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
234system.physmem.refreshEnergy::0 3993213120 # Energy for refresh commands per rank (pJ)
235system.physmem.refreshEnergy::1 3993213120 # Energy for refresh commands per rank (pJ)
236system.physmem.actBackEnergy::0 2474179335 # Energy for active background per rank (pJ)
237system.physmem.actBackEnergy::1 2524417425 # Energy for active background per rank (pJ)
238system.physmem.preBackEnergy::0 34512404250 # Energy for precharge background per rank (pJ)
239system.physmem.preBackEnergy::1 34468335750 # Energy for precharge background per rank (pJ)
240system.physmem.totalEnergy::0 41053213395 # Total energy per rank (pJ)
241system.physmem.totalEnergy::1 41051542170 # Total energy per rank (pJ)
242system.physmem.averagePower::0 671.485556 # Core power per rank (mW)
243system.physmem.averagePower::1 671.458220 # Core power per rank (mW)
244system.membus.trans_dist::ReadReq 1030 # Transaction distribution
245system.membus.trans_dist::ReadResp 1030 # Transaction distribution
246system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
247system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
248system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes)
249system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes)
250system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
251system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
252system.membus.snoops 0 # Total snoops (count)
253system.membus.snoop_fanout::samples 15574 # Request fanout histogram
254system.membus.snoop_fanout::mean 0 # Request fanout histogram
255system.membus.snoop_fanout::stdev 0 # Request fanout histogram
256system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
257system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram
258system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
259system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
260system.membus.snoop_fanout::min_value 0 # Request fanout histogram
261system.membus.snoop_fanout::max_value 0 # Request fanout histogram
262system.membus.snoop_fanout::total 15574 # Request fanout histogram
263system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks)
264system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
265system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks)
266system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
267system.cpu_clk_domain.clock 500 # Clock period in ticks
268system.cpu.branchPred.lookups 20748984 # Number of BP lookups
269system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted
270system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect
271system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups
272system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits
273system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
274system.cpu.branchPred.BTBHitPct 98.625162 # BTB Hit Percentage
275system.cpu.branchPred.usedRAS 62305 # Number of times the RAS was used to get a target.
276system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
277system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
278system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
279system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
280system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
281system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
282system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 69 unchanged lines hidden (view full) ---
354system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
355system.cpu.itb.read_accesses 0 # DTB read accesses
356system.cpu.itb.write_accesses 0 # DTB write accesses
357system.cpu.itb.inst_accesses 0 # ITB inst accesses
358system.cpu.itb.hits 0 # DTB hits
359system.cpu.itb.misses 0 # DTB misses
360system.cpu.itb.accesses 0 # DTB accesses
361system.cpu.workload.num_syscalls 442 # Number of system calls
362system.cpu.numCycles 122288823 # number of cpu cycles simulated
363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
364system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
365system.cpu.committedInsts 90602849 # Number of instructions committed
366system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
367system.cpu.discardedOps 2027782 # Number of ops (including micro ops) which were discarded before commit
368system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
369system.cpu.cpi 1.349724 # CPI: cycles per instruction
370system.cpu.ipc 0.740892 # IPC: instructions per cycle
371system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked
372system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped
373system.cpu.icache.tags.replacements 5 # number of replacements
374system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use
375system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks.
376system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
377system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks.
378system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
379system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor
380system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy
381system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy
382system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
383system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
384system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
385system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
386system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
387system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses
388system.cpu.icache.tags.data_accesses 55549557 # Number of data accesses
389system.cpu.icache.ReadReq_hits::cpu.inst 27773574 # number of ReadReq hits
390system.cpu.icache.ReadReq_hits::total 27773574 # number of ReadReq hits
391system.cpu.icache.demand_hits::cpu.inst 27773574 # number of demand (read+write) hits
392system.cpu.icache.demand_hits::total 27773574 # number of demand (read+write) hits
393system.cpu.icache.overall_hits::cpu.inst 27773574 # number of overall hits
394system.cpu.icache.overall_hits::total 27773574 # number of overall hits
395system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
396system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
397system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
398system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
399system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
400system.cpu.icache.overall_misses::total 803 # number of overall misses
401system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles
402system.cpu.icache.ReadReq_miss_latency::total 55313498 # number of ReadReq miss cycles
403system.cpu.icache.demand_miss_latency::cpu.inst 55313498 # number of demand (read+write) miss cycles
404system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles
405system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles
406system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles
407system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses)
408system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses)
409system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses
410system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses
411system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses
412system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses
413system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
414system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
415system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
416system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
417system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
418system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
419system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency
420system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency
421system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
422system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency
423system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
424system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency
425system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
426system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
427system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
428system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
429system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
430system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
431system.cpu.icache.fast_writes 0 # number of fast writes performed
432system.cpu.icache.cache_copies 0 # number of cache copies performed
433system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
434system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses
435system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
436system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
437system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
438system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
439system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles
440system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles
441system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles
442system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles
443system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles
444system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles
445system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
446system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
447system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
448system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
449system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
450system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
451system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910 # average ReadReq mshr miss latency
452system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910 # average ReadReq mshr miss latency
453system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
454system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
455system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
456system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
457system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
458system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution
459system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution
460system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution
461system.cpu.toL2Bus.trans_dist::ReadExReq 46761 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::ReadExResp 46761 # Transaction distribution
463system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
464system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843551 # Packet count per connected master and slave (bytes)
465system.cpu.toL2Bus.pkt_count::total 2845157 # Packet count per connected master and slave (bytes)
466system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
467system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes)
468system.cpu.toL2Bus.pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes)
469system.cpu.toL2Bus.snoops 0 # Total snoops (count)
470system.cpu.toL2Bus.snoop_fanout::samples 1894213 # Request fanout histogram
471system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
472system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
475system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
477system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
478system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
479system.cpu.toL2Bus.snoop_fanout::5 1894213 100.00% 100.00% # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
482system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
483system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
484system.cpu.toL2Bus.snoop_fanout::total 1894213 # Request fanout histogram
485system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks)
486system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
487system.cpu.toL2Bus.respLayer0.occupancy 1371498 # Layer occupancy (ticks)
488system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
489system.cpu.toL2Bus.respLayer1.occupancy 1428579494 # Layer occupancy (ticks)
490system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
491system.cpu.l2cache.tags.replacements 0 # number of replacements
492system.cpu.l2cache.tags.tagsinuse 10264.635477 # Cycle average of tags in use
493system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks.
494system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
495system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks.
496system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
497system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor
498system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976609 # Average occupied blocks per requestor
499system.cpu.l2cache.tags.occ_percent::writebacks 0.286061 # Average percentage of cache occupancy
500system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027190 # Average percentage of cache occupancy
501system.cpu.l2cache.tags.occ_percent::total 0.313252 # Average percentage of cache occupancy
502system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id
503system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
504system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
505system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
506system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
507system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
508system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id
509system.cpu.l2cache.tags.tag_accesses 15216022 # Number of tag accesses
510system.cpu.l2cache.tags.data_accesses 15216022 # Number of data accesses
511system.cpu.l2cache.ReadReq_hits::cpu.inst 903145 # number of ReadReq hits
512system.cpu.l2cache.ReadReq_hits::total 903145 # number of ReadReq hits
513system.cpu.l2cache.Writeback_hits::writebacks 943269 # number of Writeback hits
514system.cpu.l2cache.Writeback_hits::total 943269 # number of Writeback hits
515system.cpu.l2cache.ReadExReq_hits::cpu.inst 32217 # number of ReadExReq hits
516system.cpu.l2cache.ReadExReq_hits::total 32217 # number of ReadExReq hits
517system.cpu.l2cache.demand_hits::cpu.inst 935362 # number of demand (read+write) hits
518system.cpu.l2cache.demand_hits::total 935362 # number of demand (read+write) hits
519system.cpu.l2cache.overall_hits::cpu.inst 935362 # number of overall hits
520system.cpu.l2cache.overall_hits::total 935362 # number of overall hits
521system.cpu.l2cache.ReadReq_misses::cpu.inst 1038 # number of ReadReq misses
522system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses
523system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses
524system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
525system.cpu.l2cache.demand_misses::cpu.inst 15582 # number of demand (read+write) misses
526system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses
527system.cpu.l2cache.overall_misses::cpu.inst 15582 # number of overall misses
528system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
529system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71732750 # number of ReadReq miss cycles
530system.cpu.l2cache.ReadReq_miss_latency::total 71732750 # number of ReadReq miss cycles
531system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959611500 # number of ReadExReq miss cycles
532system.cpu.l2cache.ReadExReq_miss_latency::total 959611500 # number of ReadExReq miss cycles
533system.cpu.l2cache.demand_miss_latency::cpu.inst 1031344250 # number of demand (read+write) miss cycles
534system.cpu.l2cache.demand_miss_latency::total 1031344250 # number of demand (read+write) miss cycles
535system.cpu.l2cache.overall_miss_latency::cpu.inst 1031344250 # number of overall miss cycles
536system.cpu.l2cache.overall_miss_latency::total 1031344250 # number of overall miss cycles
537system.cpu.l2cache.ReadReq_accesses::cpu.inst 904183 # number of ReadReq accesses(hits+misses)
538system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses)
539system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses)
540system.cpu.l2cache.Writeback_accesses::total 943269 # number of Writeback accesses(hits+misses)
541system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46761 # number of ReadExReq accesses(hits+misses)
542system.cpu.l2cache.ReadExReq_accesses::total 46761 # number of ReadExReq accesses(hits+misses)
543system.cpu.l2cache.demand_accesses::cpu.inst 950944 # number of demand (read+write) accesses
544system.cpu.l2cache.demand_accesses::total 950944 # number of demand (read+write) accesses
545system.cpu.l2cache.overall_accesses::cpu.inst 950944 # number of overall (read+write) accesses
546system.cpu.l2cache.overall_accesses::total 950944 # number of overall (read+write) accesses
547system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001148 # miss rate for ReadReq accesses
548system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses
549system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.311028 # miss rate for ReadExReq accesses
550system.cpu.l2cache.ReadExReq_miss_rate::total 0.311028 # miss rate for ReadExReq accesses
551system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses
552system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
553system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses
554system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
555system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568 # average ReadReq miss latency
556system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568 # average ReadReq miss latency
557system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614 # average ReadExReq miss latency
558system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614 # average ReadExReq miss latency
559system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
560system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877 # average overall miss latency
561system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
562system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877 # average overall miss latency
563system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
564system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
565system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
566system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
567system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
568system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
569system.cpu.l2cache.fast_writes 0 # number of fast writes performed
570system.cpu.l2cache.cache_copies 0 # number of cache copies performed
571system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
572system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
573system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
574system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
575system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
576system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
577system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses
578system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses
579system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses
580system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
581system.cpu.l2cache.demand_mshr_misses::cpu.inst 15574 # number of demand (read+write) MSHR misses
582system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses
583system.cpu.l2cache.overall_mshr_misses::cpu.inst 15574 # number of overall MSHR misses
584system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
585system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58370500 # number of ReadReq MSHR miss cycles
586system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58370500 # number of ReadReq MSHR miss cycles
587system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772672000 # number of ReadExReq MSHR miss cycles
588system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772672000 # number of ReadExReq MSHR miss cycles
589system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831042500 # number of demand (read+write) MSHR miss cycles
590system.cpu.l2cache.demand_mshr_miss_latency::total 831042500 # number of demand (read+write) MSHR miss cycles
591system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831042500 # number of overall MSHR miss cycles
592system.cpu.l2cache.overall_mshr_miss_latency::total 831042500 # number of overall MSHR miss cycles
593system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses
594system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses
595system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses
596system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311028 # mshr miss rate for ReadExReq accesses
597system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses
598system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
599system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses
600system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
601system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56670.388350 # average ReadReq mshr miss latency
602system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56670.388350 # average ReadReq mshr miss latency
603system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651 # average ReadExReq mshr miss latency
604system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651 # average ReadExReq mshr miss latency
605system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
606system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
607system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
608system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
609system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
610system.cpu.dcache.tags.replacements 946045 # number of replacements
611system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use
612system.cpu.dcache.tags.total_refs 26265609 # Total number of references to valid blocks.
613system.cpu.dcache.tags.sampled_refs 950141 # Sample count of references to valid blocks.
614system.cpu.dcache.tags.avg_refs 27.643907 # Average number of references to valid blocks.
615system.cpu.dcache.tags.warmup_cycle 20427116250 # Cycle when the warmup percentage was hit.
616system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.157159 # Average occupied blocks per requestor
617system.cpu.dcache.tags.occ_percent::cpu.inst 0.883339 # Average percentage of cache occupancy
618system.cpu.dcache.tags.occ_percent::total 0.883339 # Average percentage of cache occupancy
619system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
620system.cpu.dcache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id
621system.cpu.dcache.tags.age_task_id_blocks_1024::1 2250 # Occupied blocks per task id
622system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id
623system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
624system.cpu.dcache.tags.tag_accesses 55458945 # Number of tag accesses
625system.cpu.dcache.tags.data_accesses 55458945 # Number of data accesses
626system.cpu.dcache.ReadReq_hits::cpu.inst 21596750 # number of ReadReq hits
627system.cpu.dcache.ReadReq_hits::total 21596750 # number of ReadReq hits
628system.cpu.dcache.WriteReq_hits::cpu.inst 4661085 # number of WriteReq hits
629system.cpu.dcache.WriteReq_hits::total 4661085 # number of WriteReq hits
630system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits
631system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
632system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits
633system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
634system.cpu.dcache.demand_hits::cpu.inst 26257835 # number of demand (read+write) hits
635system.cpu.dcache.demand_hits::total 26257835 # number of demand (read+write) hits
636system.cpu.dcache.overall_hits::cpu.inst 26257835 # number of overall hits
637system.cpu.dcache.overall_hits::total 26257835 # number of overall hits
638system.cpu.dcache.ReadReq_misses::cpu.inst 914897 # number of ReadReq misses
639system.cpu.dcache.ReadReq_misses::total 914897 # number of ReadReq misses
640system.cpu.dcache.WriteReq_misses::cpu.inst 73896 # number of WriteReq misses
641system.cpu.dcache.WriteReq_misses::total 73896 # number of WriteReq misses
642system.cpu.dcache.demand_misses::cpu.inst 988793 # number of demand (read+write) misses
643system.cpu.dcache.demand_misses::total 988793 # number of demand (read+write) misses
644system.cpu.dcache.overall_misses::cpu.inst 988793 # number of overall misses
645system.cpu.dcache.overall_misses::total 988793 # number of overall misses
646system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11909486494 # number of ReadReq miss cycles
647system.cpu.dcache.ReadReq_miss_latency::total 11909486494 # number of ReadReq miss cycles
648system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342568500 # number of WriteReq miss cycles
649system.cpu.dcache.WriteReq_miss_latency::total 2342568500 # number of WriteReq miss cycles
650system.cpu.dcache.demand_miss_latency::cpu.inst 14252054994 # number of demand (read+write) miss cycles
651system.cpu.dcache.demand_miss_latency::total 14252054994 # number of demand (read+write) miss cycles
652system.cpu.dcache.overall_miss_latency::cpu.inst 14252054994 # number of overall miss cycles
653system.cpu.dcache.overall_miss_latency::total 14252054994 # number of overall miss cycles
654system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses)
655system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses)
656system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses)
657system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
658system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses)
659system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
660system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses)
661system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
662system.cpu.dcache.demand_accesses::cpu.inst 27246628 # number of demand (read+write) accesses
663system.cpu.dcache.demand_accesses::total 27246628 # number of demand (read+write) accesses
664system.cpu.dcache.overall_accesses::cpu.inst 27246628 # number of overall (read+write) accesses
665system.cpu.dcache.overall_accesses::total 27246628 # number of overall (read+write) accesses
666system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040641 # miss rate for ReadReq accesses
667system.cpu.dcache.ReadReq_miss_rate::total 0.040641 # miss rate for ReadReq accesses
668system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015606 # miss rate for WriteReq accesses
669system.cpu.dcache.WriteReq_miss_rate::total 0.015606 # miss rate for WriteReq accesses
670system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses
671system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses
672system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses
673system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses
674system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency
675system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency
676system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674 # average WriteReq miss latency
677system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674 # average WriteReq miss latency
678system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
679system.cpu.dcache.demand_avg_miss_latency::total 14413.588076 # average overall miss latency
680system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
681system.cpu.dcache.overall_avg_miss_latency::total 14413.588076 # average overall miss latency
682system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
683system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
684system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
685system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
686system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
687system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
688system.cpu.dcache.fast_writes 0 # number of fast writes performed
689system.cpu.dcache.cache_copies 0 # number of cache copies performed
690system.cpu.dcache.writebacks::writebacks 943269 # number of writebacks
691system.cpu.dcache.writebacks::total 943269 # number of writebacks
692system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11517 # number of ReadReq MSHR hits
693system.cpu.dcache.ReadReq_mshr_hits::total 11517 # number of ReadReq MSHR hits
694system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27135 # number of WriteReq MSHR hits
695system.cpu.dcache.WriteReq_mshr_hits::total 27135 # number of WriteReq MSHR hits
696system.cpu.dcache.demand_mshr_hits::cpu.inst 38652 # number of demand (read+write) MSHR hits
697system.cpu.dcache.demand_mshr_hits::total 38652 # number of demand (read+write) MSHR hits
698system.cpu.dcache.overall_mshr_hits::cpu.inst 38652 # number of overall MSHR hits
699system.cpu.dcache.overall_mshr_hits::total 38652 # number of overall MSHR hits
700system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903380 # number of ReadReq MSHR misses
701system.cpu.dcache.ReadReq_mshr_misses::total 903380 # number of ReadReq MSHR misses
702system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46761 # number of WriteReq MSHR misses
703system.cpu.dcache.WriteReq_mshr_misses::total 46761 # number of WriteReq MSHR misses
704system.cpu.dcache.demand_mshr_misses::cpu.inst 950141 # number of demand (read+write) MSHR misses
705system.cpu.dcache.demand_mshr_misses::total 950141 # number of demand (read+write) MSHR misses
706system.cpu.dcache.overall_mshr_misses::cpu.inst 950141 # number of overall MSHR misses
707system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses
708system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles
709system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles
710system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334896250 # number of WriteReq MSHR miss cycles
711system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334896250 # number of WriteReq MSHR miss cycles
712system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293221506 # number of demand (read+write) MSHR miss cycles
713system.cpu.dcache.demand_mshr_miss_latency::total 11293221506 # number of demand (read+write) MSHR miss cycles
714system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293221506 # number of overall MSHR miss cycles
715system.cpu.dcache.overall_mshr_miss_latency::total 11293221506 # number of overall MSHR miss cycles
716system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses
717system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses
718system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses
719system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
720system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for demand accesses
721system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses
722system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for overall accesses
723system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses
724system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency
725system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency
726system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490 # average WriteReq mshr miss latency
727system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490 # average WriteReq mshr miss latency
728system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
729system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
730system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
731system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
732system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
733
734---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.061144 # Number of seconds simulated
4sim_ticks 61144411500 # Number of ticks simulated
5final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 271316 # Simulator instruction rate (inst/s)
8host_op_rate 272668 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 183101149 # Simulator tick rate (ticks/s)
10host_mem_usage 442968 # Number of bytes of host memory used
11host_seconds 333.94 # Real time elapsed on the host
12sim_insts 90602849 # Number of instructions simulated
13sim_ops 91054080 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 996736 # Number of bytes read from this memory
17system.physmem.bytes_read::total 996736 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory
20system.physmem.num_reads::cpu.inst 15574 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 16301343 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::total 16301343 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_inst_read::cpu.inst 811194 # Instruction read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::total 811194 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_total::cpu.inst 16301343 # Total bandwidth to/from this memory (bytes/s)
27system.physmem.bw_total::total 16301343 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.readReqs 15574 # Number of read requests accepted
29system.physmem.writeReqs 0 # Number of write requests accepted
30system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
32system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM
33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
35system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side
36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
40system.physmem.perBankRdBursts::0 993 # Per bank write bursts
41system.physmem.perBankRdBursts::1 890 # Per bank write bursts
42system.physmem.perBankRdBursts::2 950 # Per bank write bursts
43system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
44system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
45system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
46system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
47system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
48system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
49system.physmem.perBankRdBursts::9 962 # Per bank write bursts
50system.physmem.perBankRdBursts::10 938 # Per bank write bursts
51system.physmem.perBankRdBursts::11 899 # Per bank write bursts
52system.physmem.perBankRdBursts::12 903 # Per bank write bursts
53system.physmem.perBankRdBursts::13 867 # Per bank write bursts
54system.physmem.perBankRdBursts::14 877 # Per bank write bursts
55system.physmem.perBankRdBursts::15 904 # Per bank write bursts
56system.physmem.perBankWrBursts::0 0 # Per bank write bursts
57system.physmem.perBankWrBursts::1 0 # Per bank write bursts
58system.physmem.perBankWrBursts::2 0 # Per bank write bursts
59system.physmem.perBankWrBursts::3 0 # Per bank write bursts
60system.physmem.perBankWrBursts::4 0 # Per bank write bursts
61system.physmem.perBankWrBursts::5 0 # Per bank write bursts
62system.physmem.perBankWrBursts::6 0 # Per bank write bursts
63system.physmem.perBankWrBursts::7 0 # Per bank write bursts
64system.physmem.perBankWrBursts::8 0 # Per bank write bursts
65system.physmem.perBankWrBursts::9 0 # Per bank write bursts
66system.physmem.perBankWrBursts::10 0 # Per bank write bursts
67system.physmem.perBankWrBursts::11 0 # Per bank write bursts
68system.physmem.perBankWrBursts::12 0 # Per bank write bursts
69system.physmem.perBankWrBursts::13 0 # Per bank write bursts
70system.physmem.perBankWrBursts::14 0 # Per bank write bursts
71system.physmem.perBankWrBursts::15 0 # Per bank write bursts
72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
74system.physmem.totGap 61144323500 # Total gap between requests
75system.physmem.readPktSize::0 0 # Read request sizes (log2)
76system.physmem.readPktSize::1 0 # Read request sizes (log2)
77system.physmem.readPktSize::2 0 # Read request sizes (log2)
78system.physmem.readPktSize::3 0 # Read request sizes (log2)
79system.physmem.readPktSize::4 0 # Read request sizes (log2)
80system.physmem.readPktSize::5 0 # Read request sizes (log2)
81system.physmem.readPktSize::6 15574 # Read request sizes (log2)
82system.physmem.writePktSize::0 0 # Write request sizes (log2)
83system.physmem.writePktSize::1 0 # Write request sizes (log2)
84system.physmem.writePktSize::2 0 # Write request sizes (log2)
85system.physmem.writePktSize::3 0 # Write request sizes (log2)
86system.physmem.writePktSize::4 0 # Write request sizes (log2)
87system.physmem.writePktSize::5 0 # Write request sizes (log2)
88system.physmem.writePktSize::6 0 # Write request sizes (log2)
89system.physmem.rdQLenPdf::0 15451 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
--- 77 unchanged lines hidden (view full) ---
177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
185system.physmem.bytesPerActivate::samples 1531 # Bytes accessed per row activation
186system.physmem.bytesPerActivate::mean 649.865447 # Bytes accessed per row activation
187system.physmem.bytesPerActivate::gmean 447.084914 # Bytes accessed per row activation
188system.physmem.bytesPerActivate::stdev 397.724653 # Bytes accessed per row activation
189system.physmem.bytesPerActivate::0-127 242 15.81% 15.81% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::128-255 164 10.71% 26.52% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::256-383 94 6.14% 32.66% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::384-511 77 5.03% 37.69% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::512-639 65 4.25% 41.93% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::640-767 106 6.92% 48.86% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation
199system.physmem.totQLat 71490500 # Total ticks spent queuing
200system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM
201system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
202system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst
203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
204system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst
205system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s
206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
207system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s
208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
210system.physmem.busUtil 0.13 # Data bus utilization in percentage
211system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
213system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
215system.physmem.readRowHits 14033 # Number of row buffer hits during reads
216system.physmem.writeRowHits 0 # Number of row buffer hits during writes
217system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads
218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
219system.physmem.avgGap 3926051.34 # Average gap between requests
220system.physmem.pageHitRate 90.11 # Row buffer hit rate, read and write combined
221system.physmem.memoryStateTime::IDLE 55905599000 # Time in different power states
222system.physmem.memoryStateTime::REF 2041520000 # Time in different power states
223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
224system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states
225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
226system.physmem.actEnergy::0 6305040 # Energy for activate commands per rank (pJ)
227system.physmem.actEnergy::1 5254200 # Energy for activate commands per rank (pJ)
228system.physmem.preEnergy::0 3440250 # Energy for precharge commands per rank (pJ)
229system.physmem.preEnergy::1 2866875 # Energy for precharge commands per rank (pJ)
230system.physmem.readEnergy::0 63671400 # Energy for read commands per rank (pJ)
231system.physmem.readEnergy::1 57454800 # Energy for read commands per rank (pJ)
232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
234system.physmem.refreshEnergy::0 3993213120 # Energy for refresh commands per rank (pJ)
235system.physmem.refreshEnergy::1 3993213120 # Energy for refresh commands per rank (pJ)
236system.physmem.actBackEnergy::0 2474179335 # Energy for active background per rank (pJ)
237system.physmem.actBackEnergy::1 2524417425 # Energy for active background per rank (pJ)
238system.physmem.preBackEnergy::0 34512404250 # Energy for precharge background per rank (pJ)
239system.physmem.preBackEnergy::1 34468335750 # Energy for precharge background per rank (pJ)
240system.physmem.totalEnergy::0 41053213395 # Total energy per rank (pJ)
241system.physmem.totalEnergy::1 41051542170 # Total energy per rank (pJ)
242system.physmem.averagePower::0 671.485556 # Core power per rank (mW)
243system.physmem.averagePower::1 671.458220 # Core power per rank (mW)
244system.membus.trans_dist::ReadReq 1030 # Transaction distribution
245system.membus.trans_dist::ReadResp 1030 # Transaction distribution
246system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
247system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
248system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes)
249system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes)
250system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
251system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
252system.membus.snoops 0 # Total snoops (count)
253system.membus.snoop_fanout::samples 15574 # Request fanout histogram
254system.membus.snoop_fanout::mean 0 # Request fanout histogram
255system.membus.snoop_fanout::stdev 0 # Request fanout histogram
256system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
257system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram
258system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
259system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
260system.membus.snoop_fanout::min_value 0 # Request fanout histogram
261system.membus.snoop_fanout::max_value 0 # Request fanout histogram
262system.membus.snoop_fanout::total 15574 # Request fanout histogram
263system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks)
264system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
265system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks)
266system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
267system.cpu_clk_domain.clock 500 # Clock period in ticks
268system.cpu.branchPred.lookups 20748984 # Number of BP lookups
269system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted
270system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect
271system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups
272system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits
273system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
274system.cpu.branchPred.BTBHitPct 98.625162 # BTB Hit Percentage
275system.cpu.branchPred.usedRAS 62305 # Number of times the RAS was used to get a target.
276system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
277system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
278system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
279system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
280system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
281system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
282system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 69 unchanged lines hidden (view full) ---
354system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
355system.cpu.itb.read_accesses 0 # DTB read accesses
356system.cpu.itb.write_accesses 0 # DTB write accesses
357system.cpu.itb.inst_accesses 0 # ITB inst accesses
358system.cpu.itb.hits 0 # DTB hits
359system.cpu.itb.misses 0 # DTB misses
360system.cpu.itb.accesses 0 # DTB accesses
361system.cpu.workload.num_syscalls 442 # Number of system calls
362system.cpu.numCycles 122288823 # number of cpu cycles simulated
363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
364system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
365system.cpu.committedInsts 90602849 # Number of instructions committed
366system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
367system.cpu.discardedOps 2027782 # Number of ops (including micro ops) which were discarded before commit
368system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
369system.cpu.cpi 1.349724 # CPI: cycles per instruction
370system.cpu.ipc 0.740892 # IPC: instructions per cycle
371system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked
372system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped
373system.cpu.icache.tags.replacements 5 # number of replacements
374system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use
375system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks.
376system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
377system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks.
378system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
379system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor
380system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy
381system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy
382system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
383system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
384system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
385system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
386system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
387system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses
388system.cpu.icache.tags.data_accesses 55549557 # Number of data accesses
389system.cpu.icache.ReadReq_hits::cpu.inst 27773574 # number of ReadReq hits
390system.cpu.icache.ReadReq_hits::total 27773574 # number of ReadReq hits
391system.cpu.icache.demand_hits::cpu.inst 27773574 # number of demand (read+write) hits
392system.cpu.icache.demand_hits::total 27773574 # number of demand (read+write) hits
393system.cpu.icache.overall_hits::cpu.inst 27773574 # number of overall hits
394system.cpu.icache.overall_hits::total 27773574 # number of overall hits
395system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
396system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
397system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
398system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
399system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
400system.cpu.icache.overall_misses::total 803 # number of overall misses
401system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles
402system.cpu.icache.ReadReq_miss_latency::total 55313498 # number of ReadReq miss cycles
403system.cpu.icache.demand_miss_latency::cpu.inst 55313498 # number of demand (read+write) miss cycles
404system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles
405system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles
406system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles
407system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses)
408system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses)
409system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses
410system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses
411system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses
412system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses
413system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
414system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
415system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
416system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
417system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
418system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
419system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency
420system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency
421system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
422system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency
423system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
424system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency
425system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
426system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
427system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
428system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
429system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
430system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
431system.cpu.icache.fast_writes 0 # number of fast writes performed
432system.cpu.icache.cache_copies 0 # number of cache copies performed
433system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
434system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses
435system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
436system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
437system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
438system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
439system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles
440system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles
441system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles
442system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles
443system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles
444system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles
445system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
446system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
447system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
448system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
449system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
450system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
451system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910 # average ReadReq mshr miss latency
452system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910 # average ReadReq mshr miss latency
453system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
454system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
455system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
456system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
457system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
458system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution
459system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution
460system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution
461system.cpu.toL2Bus.trans_dist::ReadExReq 46761 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::ReadExResp 46761 # Transaction distribution
463system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
464system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843551 # Packet count per connected master and slave (bytes)
465system.cpu.toL2Bus.pkt_count::total 2845157 # Packet count per connected master and slave (bytes)
466system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
467system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes)
468system.cpu.toL2Bus.pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes)
469system.cpu.toL2Bus.snoops 0 # Total snoops (count)
470system.cpu.toL2Bus.snoop_fanout::samples 1894213 # Request fanout histogram
471system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
472system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
475system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
477system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
478system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
479system.cpu.toL2Bus.snoop_fanout::5 1894213 100.00% 100.00% # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
482system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
483system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
484system.cpu.toL2Bus.snoop_fanout::total 1894213 # Request fanout histogram
485system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks)
486system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
487system.cpu.toL2Bus.respLayer0.occupancy 1371498 # Layer occupancy (ticks)
488system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
489system.cpu.toL2Bus.respLayer1.occupancy 1428579494 # Layer occupancy (ticks)
490system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
491system.cpu.l2cache.tags.replacements 0 # number of replacements
492system.cpu.l2cache.tags.tagsinuse 10264.635477 # Cycle average of tags in use
493system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks.
494system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
495system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks.
496system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
497system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor
498system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976609 # Average occupied blocks per requestor
499system.cpu.l2cache.tags.occ_percent::writebacks 0.286061 # Average percentage of cache occupancy
500system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027190 # Average percentage of cache occupancy
501system.cpu.l2cache.tags.occ_percent::total 0.313252 # Average percentage of cache occupancy
502system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id
503system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
504system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
505system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
506system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
507system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
508system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id
509system.cpu.l2cache.tags.tag_accesses 15216022 # Number of tag accesses
510system.cpu.l2cache.tags.data_accesses 15216022 # Number of data accesses
511system.cpu.l2cache.ReadReq_hits::cpu.inst 903145 # number of ReadReq hits
512system.cpu.l2cache.ReadReq_hits::total 903145 # number of ReadReq hits
513system.cpu.l2cache.Writeback_hits::writebacks 943269 # number of Writeback hits
514system.cpu.l2cache.Writeback_hits::total 943269 # number of Writeback hits
515system.cpu.l2cache.ReadExReq_hits::cpu.inst 32217 # number of ReadExReq hits
516system.cpu.l2cache.ReadExReq_hits::total 32217 # number of ReadExReq hits
517system.cpu.l2cache.demand_hits::cpu.inst 935362 # number of demand (read+write) hits
518system.cpu.l2cache.demand_hits::total 935362 # number of demand (read+write) hits
519system.cpu.l2cache.overall_hits::cpu.inst 935362 # number of overall hits
520system.cpu.l2cache.overall_hits::total 935362 # number of overall hits
521system.cpu.l2cache.ReadReq_misses::cpu.inst 1038 # number of ReadReq misses
522system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses
523system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses
524system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
525system.cpu.l2cache.demand_misses::cpu.inst 15582 # number of demand (read+write) misses
526system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses
527system.cpu.l2cache.overall_misses::cpu.inst 15582 # number of overall misses
528system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
529system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71732750 # number of ReadReq miss cycles
530system.cpu.l2cache.ReadReq_miss_latency::total 71732750 # number of ReadReq miss cycles
531system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959611500 # number of ReadExReq miss cycles
532system.cpu.l2cache.ReadExReq_miss_latency::total 959611500 # number of ReadExReq miss cycles
533system.cpu.l2cache.demand_miss_latency::cpu.inst 1031344250 # number of demand (read+write) miss cycles
534system.cpu.l2cache.demand_miss_latency::total 1031344250 # number of demand (read+write) miss cycles
535system.cpu.l2cache.overall_miss_latency::cpu.inst 1031344250 # number of overall miss cycles
536system.cpu.l2cache.overall_miss_latency::total 1031344250 # number of overall miss cycles
537system.cpu.l2cache.ReadReq_accesses::cpu.inst 904183 # number of ReadReq accesses(hits+misses)
538system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses)
539system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses)
540system.cpu.l2cache.Writeback_accesses::total 943269 # number of Writeback accesses(hits+misses)
541system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46761 # number of ReadExReq accesses(hits+misses)
542system.cpu.l2cache.ReadExReq_accesses::total 46761 # number of ReadExReq accesses(hits+misses)
543system.cpu.l2cache.demand_accesses::cpu.inst 950944 # number of demand (read+write) accesses
544system.cpu.l2cache.demand_accesses::total 950944 # number of demand (read+write) accesses
545system.cpu.l2cache.overall_accesses::cpu.inst 950944 # number of overall (read+write) accesses
546system.cpu.l2cache.overall_accesses::total 950944 # number of overall (read+write) accesses
547system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001148 # miss rate for ReadReq accesses
548system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses
549system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.311028 # miss rate for ReadExReq accesses
550system.cpu.l2cache.ReadExReq_miss_rate::total 0.311028 # miss rate for ReadExReq accesses
551system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses
552system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
553system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses
554system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
555system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568 # average ReadReq miss latency
556system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568 # average ReadReq miss latency
557system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614 # average ReadExReq miss latency
558system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614 # average ReadExReq miss latency
559system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
560system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877 # average overall miss latency
561system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
562system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877 # average overall miss latency
563system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
564system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
565system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
566system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
567system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
568system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
569system.cpu.l2cache.fast_writes 0 # number of fast writes performed
570system.cpu.l2cache.cache_copies 0 # number of cache copies performed
571system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
572system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
573system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
574system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
575system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
576system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
577system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses
578system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses
579system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses
580system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
581system.cpu.l2cache.demand_mshr_misses::cpu.inst 15574 # number of demand (read+write) MSHR misses
582system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses
583system.cpu.l2cache.overall_mshr_misses::cpu.inst 15574 # number of overall MSHR misses
584system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
585system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58370500 # number of ReadReq MSHR miss cycles
586system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58370500 # number of ReadReq MSHR miss cycles
587system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772672000 # number of ReadExReq MSHR miss cycles
588system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772672000 # number of ReadExReq MSHR miss cycles
589system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831042500 # number of demand (read+write) MSHR miss cycles
590system.cpu.l2cache.demand_mshr_miss_latency::total 831042500 # number of demand (read+write) MSHR miss cycles
591system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831042500 # number of overall MSHR miss cycles
592system.cpu.l2cache.overall_mshr_miss_latency::total 831042500 # number of overall MSHR miss cycles
593system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses
594system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses
595system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses
596system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311028 # mshr miss rate for ReadExReq accesses
597system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses
598system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
599system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses
600system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
601system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56670.388350 # average ReadReq mshr miss latency
602system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56670.388350 # average ReadReq mshr miss latency
603system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651 # average ReadExReq mshr miss latency
604system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651 # average ReadExReq mshr miss latency
605system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
606system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
607system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
608system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
609system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
610system.cpu.dcache.tags.replacements 946045 # number of replacements
611system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use
612system.cpu.dcache.tags.total_refs 26265609 # Total number of references to valid blocks.
613system.cpu.dcache.tags.sampled_refs 950141 # Sample count of references to valid blocks.
614system.cpu.dcache.tags.avg_refs 27.643907 # Average number of references to valid blocks.
615system.cpu.dcache.tags.warmup_cycle 20427116250 # Cycle when the warmup percentage was hit.
616system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.157159 # Average occupied blocks per requestor
617system.cpu.dcache.tags.occ_percent::cpu.inst 0.883339 # Average percentage of cache occupancy
618system.cpu.dcache.tags.occ_percent::total 0.883339 # Average percentage of cache occupancy
619system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
620system.cpu.dcache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id
621system.cpu.dcache.tags.age_task_id_blocks_1024::1 2250 # Occupied blocks per task id
622system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id
623system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
624system.cpu.dcache.tags.tag_accesses 55458945 # Number of tag accesses
625system.cpu.dcache.tags.data_accesses 55458945 # Number of data accesses
626system.cpu.dcache.ReadReq_hits::cpu.inst 21596750 # number of ReadReq hits
627system.cpu.dcache.ReadReq_hits::total 21596750 # number of ReadReq hits
628system.cpu.dcache.WriteReq_hits::cpu.inst 4661085 # number of WriteReq hits
629system.cpu.dcache.WriteReq_hits::total 4661085 # number of WriteReq hits
630system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits
631system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
632system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits
633system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
634system.cpu.dcache.demand_hits::cpu.inst 26257835 # number of demand (read+write) hits
635system.cpu.dcache.demand_hits::total 26257835 # number of demand (read+write) hits
636system.cpu.dcache.overall_hits::cpu.inst 26257835 # number of overall hits
637system.cpu.dcache.overall_hits::total 26257835 # number of overall hits
638system.cpu.dcache.ReadReq_misses::cpu.inst 914897 # number of ReadReq misses
639system.cpu.dcache.ReadReq_misses::total 914897 # number of ReadReq misses
640system.cpu.dcache.WriteReq_misses::cpu.inst 73896 # number of WriteReq misses
641system.cpu.dcache.WriteReq_misses::total 73896 # number of WriteReq misses
642system.cpu.dcache.demand_misses::cpu.inst 988793 # number of demand (read+write) misses
643system.cpu.dcache.demand_misses::total 988793 # number of demand (read+write) misses
644system.cpu.dcache.overall_misses::cpu.inst 988793 # number of overall misses
645system.cpu.dcache.overall_misses::total 988793 # number of overall misses
646system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11909486494 # number of ReadReq miss cycles
647system.cpu.dcache.ReadReq_miss_latency::total 11909486494 # number of ReadReq miss cycles
648system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342568500 # number of WriteReq miss cycles
649system.cpu.dcache.WriteReq_miss_latency::total 2342568500 # number of WriteReq miss cycles
650system.cpu.dcache.demand_miss_latency::cpu.inst 14252054994 # number of demand (read+write) miss cycles
651system.cpu.dcache.demand_miss_latency::total 14252054994 # number of demand (read+write) miss cycles
652system.cpu.dcache.overall_miss_latency::cpu.inst 14252054994 # number of overall miss cycles
653system.cpu.dcache.overall_miss_latency::total 14252054994 # number of overall miss cycles
654system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses)
655system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses)
656system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses)
657system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
658system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses)
659system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
660system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses)
661system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
662system.cpu.dcache.demand_accesses::cpu.inst 27246628 # number of demand (read+write) accesses
663system.cpu.dcache.demand_accesses::total 27246628 # number of demand (read+write) accesses
664system.cpu.dcache.overall_accesses::cpu.inst 27246628 # number of overall (read+write) accesses
665system.cpu.dcache.overall_accesses::total 27246628 # number of overall (read+write) accesses
666system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040641 # miss rate for ReadReq accesses
667system.cpu.dcache.ReadReq_miss_rate::total 0.040641 # miss rate for ReadReq accesses
668system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015606 # miss rate for WriteReq accesses
669system.cpu.dcache.WriteReq_miss_rate::total 0.015606 # miss rate for WriteReq accesses
670system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses
671system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses
672system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses
673system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses
674system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency
675system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency
676system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674 # average WriteReq miss latency
677system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674 # average WriteReq miss latency
678system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
679system.cpu.dcache.demand_avg_miss_latency::total 14413.588076 # average overall miss latency
680system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
681system.cpu.dcache.overall_avg_miss_latency::total 14413.588076 # average overall miss latency
682system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
683system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
684system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
685system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
686system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
687system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
688system.cpu.dcache.fast_writes 0 # number of fast writes performed
689system.cpu.dcache.cache_copies 0 # number of cache copies performed
690system.cpu.dcache.writebacks::writebacks 943269 # number of writebacks
691system.cpu.dcache.writebacks::total 943269 # number of writebacks
692system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11517 # number of ReadReq MSHR hits
693system.cpu.dcache.ReadReq_mshr_hits::total 11517 # number of ReadReq MSHR hits
694system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27135 # number of WriteReq MSHR hits
695system.cpu.dcache.WriteReq_mshr_hits::total 27135 # number of WriteReq MSHR hits
696system.cpu.dcache.demand_mshr_hits::cpu.inst 38652 # number of demand (read+write) MSHR hits
697system.cpu.dcache.demand_mshr_hits::total 38652 # number of demand (read+write) MSHR hits
698system.cpu.dcache.overall_mshr_hits::cpu.inst 38652 # number of overall MSHR hits
699system.cpu.dcache.overall_mshr_hits::total 38652 # number of overall MSHR hits
700system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903380 # number of ReadReq MSHR misses
701system.cpu.dcache.ReadReq_mshr_misses::total 903380 # number of ReadReq MSHR misses
702system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46761 # number of WriteReq MSHR misses
703system.cpu.dcache.WriteReq_mshr_misses::total 46761 # number of WriteReq MSHR misses
704system.cpu.dcache.demand_mshr_misses::cpu.inst 950141 # number of demand (read+write) MSHR misses
705system.cpu.dcache.demand_mshr_misses::total 950141 # number of demand (read+write) MSHR misses
706system.cpu.dcache.overall_mshr_misses::cpu.inst 950141 # number of overall MSHR misses
707system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses
708system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles
709system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles
710system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334896250 # number of WriteReq MSHR miss cycles
711system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334896250 # number of WriteReq MSHR miss cycles
712system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293221506 # number of demand (read+write) MSHR miss cycles
713system.cpu.dcache.demand_mshr_miss_latency::total 11293221506 # number of demand (read+write) MSHR miss cycles
714system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293221506 # number of overall MSHR miss cycles
715system.cpu.dcache.overall_mshr_miss_latency::total 11293221506 # number of overall MSHR miss cycles
716system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses
717system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses
718system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses
719system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
720system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for demand accesses
721system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses
722system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for overall accesses
723system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses
724system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency
725system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency
726system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490 # average WriteReq mshr miss latency
727system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490 # average WriteReq mshr miss latency
728system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
729system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
730system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
731system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
732system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
733
734---------- End Simulation Statistics ----------