1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.061494 # Number of seconds simulated
4sim_ticks 61493732000 # Number of ticks simulated
5final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 280016 # Simulator instruction rate (inst/s)
8host_op_rate 281410 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 190051649 # Simulator tick rate (ticks/s)
10host_mem_usage 385752 # Number of bytes of host memory used
11host_seconds 323.56 # Real time elapsed on the host
12sim_insts 90602849 # Number of instructions simulated
13sim_ops 91054080 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 996800 # Number of bytes read from this memory
17system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory
20system.physmem.num_reads::cpu.inst 15575 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 16209782 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_total::cpu.inst 16209782 # Total bandwidth to/from this memory (bytes/s)
27system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.readReqs 15575 # Number of read requests accepted
29system.physmem.writeReqs 0 # Number of write requests accepted
30system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
32system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM
33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
35system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side
36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
40system.physmem.perBankRdBursts::0 993 # Per bank write bursts
41system.physmem.perBankRdBursts::1 890 # Per bank write bursts
42system.physmem.perBankRdBursts::2 949 # Per bank write bursts
43system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
44system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
45system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
46system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
47system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
48system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
49system.physmem.perBankRdBursts::9 962 # Per bank write bursts
50system.physmem.perBankRdBursts::10 938 # Per bank write bursts
51system.physmem.perBankRdBursts::11 899 # Per bank write bursts
52system.physmem.perBankRdBursts::12 904 # Per bank write bursts
53system.physmem.perBankRdBursts::13 867 # Per bank write bursts
54system.physmem.perBankRdBursts::14 877 # Per bank write bursts
55system.physmem.perBankRdBursts::15 905 # Per bank write bursts
56system.physmem.perBankWrBursts::0 0 # Per bank write bursts
57system.physmem.perBankWrBursts::1 0 # Per bank write bursts
58system.physmem.perBankWrBursts::2 0 # Per bank write bursts
59system.physmem.perBankWrBursts::3 0 # Per bank write bursts
60system.physmem.perBankWrBursts::4 0 # Per bank write bursts
61system.physmem.perBankWrBursts::5 0 # Per bank write bursts
62system.physmem.perBankWrBursts::6 0 # Per bank write bursts
63system.physmem.perBankWrBursts::7 0 # Per bank write bursts
64system.physmem.perBankWrBursts::8 0 # Per bank write bursts
65system.physmem.perBankWrBursts::9 0 # Per bank write bursts
66system.physmem.perBankWrBursts::10 0 # Per bank write bursts
67system.physmem.perBankWrBursts::11 0 # Per bank write bursts
68system.physmem.perBankWrBursts::12 0 # Per bank write bursts
69system.physmem.perBankWrBursts::13 0 # Per bank write bursts
70system.physmem.perBankWrBursts::14 0 # Per bank write bursts
71system.physmem.perBankWrBursts::15 0 # Per bank write bursts
72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
74system.physmem.totGap 61493643500 # Total gap between requests
75system.physmem.readPktSize::0 0 # Read request sizes (log2)
76system.physmem.readPktSize::1 0 # Read request sizes (log2)
77system.physmem.readPktSize::2 0 # Read request sizes (log2)
78system.physmem.readPktSize::3 0 # Read request sizes (log2)
79system.physmem.readPktSize::4 0 # Read request sizes (log2)
80system.physmem.readPktSize::5 0 # Read request sizes (log2)
81system.physmem.readPktSize::6 15575 # Read request sizes (log2)
82system.physmem.writePktSize::0 0 # Write request sizes (log2)
83system.physmem.writePktSize::1 0 # Write request sizes (log2)
84system.physmem.writePktSize::2 0 # Write request sizes (log2)
85system.physmem.writePktSize::3 0 # Write request sizes (log2)
86system.physmem.writePktSize::4 0 # Write request sizes (log2)
87system.physmem.writePktSize::5 0 # Write request sizes (log2)
88system.physmem.writePktSize::6 0 # Write request sizes (log2)
89system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 112 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
--- 77 unchanged lines hidden (view full) ---
177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
185system.physmem.bytesPerActivate::samples 1534 # Bytes accessed per row activation
186system.physmem.bytesPerActivate::mean 648.594524 # Bytes accessed per row activation
187system.physmem.bytesPerActivate::gmean 444.741065 # Bytes accessed per row activation
188system.physmem.bytesPerActivate::stdev 399.329877 # Bytes accessed per row activation
189system.physmem.bytesPerActivate::0-127 241 15.71% 15.71% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::128-255 178 11.60% 27.31% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation
199system.physmem.totQLat 73246500 # Total ticks spent queuing
200system.physmem.totMemAccLat 365277750 # Total ticks spent from burst creation until serviced by the DRAM
201system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
202system.physmem.avgQLat 4702.83 # Average queueing delay per DRAM burst
203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
204system.physmem.avgMemAccLat 23452.83 # Average memory access latency per DRAM burst
205system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s
206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
207system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s
208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
210system.physmem.busUtil 0.13 # Data bus utilization in percentage
211system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
213system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
215system.physmem.readRowHits 14031 # Number of row buffer hits during reads
216system.physmem.writeRowHits 0 # Number of row buffer hits during writes
217system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads
218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
219system.physmem.avgGap 3948227.51 # Average gap between requests
220system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined
221system.physmem.memoryStateTime::IDLE 56242943250 # Time in different power states
222system.physmem.memoryStateTime::REF 2053220000 # Time in different power states
223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
224system.physmem.memoryStateTime::ACT 3193793750 # Time in different power states
225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
226system.physmem.actEnergy::0 6320160 # Energy for activate commands per rank (pJ)
227system.physmem.actEnergy::1 5261760 # Energy for activate commands per rank (pJ)
228system.physmem.preEnergy::0 3448500 # Energy for precharge commands per rank (pJ)
229system.physmem.preEnergy::1 2871000 # Energy for precharge commands per rank (pJ)
230system.physmem.readEnergy::0 63663600 # Energy for read commands per rank (pJ)
231system.physmem.readEnergy::1 57462600 # Energy for read commands per rank (pJ)
232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
234system.physmem.refreshEnergy::0 4016098320 # Energy for refresh commands per rank (pJ)
235system.physmem.refreshEnergy::1 4016098320 # Energy for refresh commands per rank (pJ)
236system.physmem.actBackEnergy::0 2490497865 # Energy for active background per rank (pJ)
237system.physmem.actBackEnergy::1 2514078765 # Energy for active background per rank (pJ)
238system.physmem.preBackEnergy::0 34708310250 # Energy for precharge background per rank (pJ)
239system.physmem.preBackEnergy::1 34687625250 # Energy for precharge background per rank (pJ)
240system.physmem.totalEnergy::0 41288338695 # Total energy per rank (pJ)
241system.physmem.totalEnergy::1 41283397695 # Total energy per rank (pJ)
242system.physmem.averagePower::0 671.483256 # Core power per rank (mW)
243system.physmem.averagePower::1 671.402899 # Core power per rank (mW)
244system.cpu.branchPred.lookups 20789429 # Number of BP lookups
245system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted
246system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect
247system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups
248system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits
249system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
250system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage
251system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target.
252system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
253system.cpu_clk_domain.clock 500 # Clock period in ticks
254system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
255system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
256system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
257system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
258system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
259system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 69 unchanged lines hidden (view full) ---
331system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
332system.cpu.itb.read_accesses 0 # DTB read accesses
333system.cpu.itb.write_accesses 0 # DTB write accesses
334system.cpu.itb.inst_accesses 0 # ITB inst accesses
335system.cpu.itb.hits 0 # DTB hits
336system.cpu.itb.misses 0 # DTB misses
337system.cpu.itb.accesses 0 # DTB accesses
338system.cpu.workload.num_syscalls 442 # Number of system calls
339system.cpu.numCycles 122987464 # number of cpu cycles simulated
340system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
341system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
342system.cpu.committedInsts 90602849 # Number of instructions committed
343system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
344system.cpu.discardedOps 2068195 # Number of ops (including micro ops) which were discarded before commit
345system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
346system.cpu.cpi 1.357435 # CPI: cycles per instruction
347system.cpu.ipc 0.736684 # IPC: instructions per cycle
348system.cpu.tickCycles 109826570 # Number of cycles that the object actually ticked
349system.cpu.idleCycles 13160894 # Total number of cycles that the object has spent stopped
350system.cpu.dcache.tags.replacements 946107 # number of replacements
351system.cpu.dcache.tags.tagsinuse 3616.604238 # Cycle average of tags in use
352system.cpu.dcache.tags.total_refs 26267660 # Total number of references to valid blocks.
353system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks.
354system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks.
355system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit.
356system.cpu.dcache.tags.occ_blocks::cpu.inst 3616.604238 # Average occupied blocks per requestor
357system.cpu.dcache.tags.occ_percent::cpu.inst 0.882960 # Average percentage of cache occupancy
358system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy
359system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
360system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id
361system.cpu.dcache.tags.age_task_id_blocks_1024::1 2249 # Occupied blocks per task id
362system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id
363system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
364system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses
365system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses
366system.cpu.dcache.ReadReq_hits::cpu.inst 21598813 # number of ReadReq hits
367system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits
368system.cpu.dcache.WriteReq_hits::cpu.inst 4661073 # number of WriteReq hits
369system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits
370system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits
371system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
372system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits
373system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
374system.cpu.dcache.demand_hits::cpu.inst 26259886 # number of demand (read+write) hits
375system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits
376system.cpu.dcache.overall_hits::cpu.inst 26259886 # number of overall hits
377system.cpu.dcache.overall_hits::total 26259886 # number of overall hits
378system.cpu.dcache.ReadReq_misses::cpu.inst 914958 # number of ReadReq misses
379system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses
380system.cpu.dcache.WriteReq_misses::cpu.inst 73908 # number of WriteReq misses
381system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses
382system.cpu.dcache.demand_misses::cpu.inst 988866 # number of demand (read+write) misses
383system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses
384system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses
385system.cpu.dcache.overall_misses::total 988866 # number of overall misses
386system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910311744 # number of ReadReq miss cycles
387system.cpu.dcache.ReadReq_miss_latency::total 11910311744 # number of ReadReq miss cycles
388system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345697500 # number of WriteReq miss cycles
389system.cpu.dcache.WriteReq_miss_latency::total 2345697500 # number of WriteReq miss cycles
390system.cpu.dcache.demand_miss_latency::cpu.inst 14256009244 # number of demand (read+write) miss cycles
391system.cpu.dcache.demand_miss_latency::total 14256009244 # number of demand (read+write) miss cycles
392system.cpu.dcache.overall_miss_latency::cpu.inst 14256009244 # number of overall miss cycles
393system.cpu.dcache.overall_miss_latency::total 14256009244 # number of overall miss cycles
394system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses)
395system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses)
396system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses)
397system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
398system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses)
399system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
400system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses)
401system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
402system.cpu.dcache.demand_accesses::cpu.inst 27248752 # number of demand (read+write) accesses
403system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses
404system.cpu.dcache.overall_accesses::cpu.inst 27248752 # number of overall (read+write) accesses
405system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses
406system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040640 # miss rate for ReadReq accesses
407system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses
408system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015609 # miss rate for WriteReq accesses
409system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses
410system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses
411system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses
412system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses
413system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses
414system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.331663 # average ReadReq miss latency
415system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.331663 # average ReadReq miss latency
416system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.073010 # average WriteReq miss latency
417system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.073010 # average WriteReq miss latency
418system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency
419system.cpu.dcache.demand_avg_miss_latency::total 14416.522809 # average overall miss latency
420system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency
421system.cpu.dcache.overall_avg_miss_latency::total 14416.522809 # average overall miss latency
422system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
423system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
424system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
425system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
426system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
427system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
428system.cpu.dcache.fast_writes 0 # number of fast writes performed
429system.cpu.dcache.cache_copies 0 # number of cache copies performed
430system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks
431system.cpu.dcache.writebacks::total 943286 # number of writebacks
432system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11523 # number of ReadReq MSHR hits
433system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits
434system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits
435system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits
436system.cpu.dcache.demand_mshr_hits::cpu.inst 38663 # number of demand (read+write) MSHR hits
437system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits
438system.cpu.dcache.overall_mshr_hits::cpu.inst 38663 # number of overall MSHR hits
439system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits
440system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903435 # number of ReadReq MSHR misses
441system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses
442system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46768 # number of WriteReq MSHR misses
443system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses
444system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 # number of demand (read+write) MSHR misses
445system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses
446system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses
447system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses
448system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958869756 # number of ReadReq MSHR miss cycles
449system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958869756 # number of ReadReq MSHR miss cycles
450system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333434750 # number of WriteReq MSHR miss cycles
451system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333434750 # number of WriteReq MSHR miss cycles
452system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292304506 # number of demand (read+write) MSHR miss cycles
453system.cpu.dcache.demand_mshr_miss_latency::total 11292304506 # number of demand (read+write) MSHR miss cycles
454system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292304506 # number of overall MSHR miss cycles
455system.cpu.dcache.overall_mshr_miss_latency::total 11292304506 # number of overall MSHR miss cycles
456system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses
457system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses
458system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses
459system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses
460system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for demand accesses
461system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
462system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses
463system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
464system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.338432 # average ReadReq mshr miss latency
465system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.338432 # average ReadReq mshr miss latency
466system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28511.690686 # average WriteReq mshr miss latency
467system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28511.690686 # average WriteReq mshr miss latency
468system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency
469system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency
470system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency
471system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency
472system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
473system.cpu.icache.tags.replacements 5 # number of replacements
474system.cpu.icache.tags.tagsinuse 690.411179 # Cycle average of tags in use
475system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks.
476system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
477system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks.
478system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
479system.cpu.icache.tags.occ_blocks::cpu.inst 690.411179 # Average occupied blocks per requestor
480system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy
481system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy
482system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
483system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
484system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
485system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
486system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
487system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses
488system.cpu.icache.tags.data_accesses 55716427 # Number of data accesses
489system.cpu.icache.ReadReq_hits::cpu.inst 27857009 # number of ReadReq hits
490system.cpu.icache.ReadReq_hits::total 27857009 # number of ReadReq hits
491system.cpu.icache.demand_hits::cpu.inst 27857009 # number of demand (read+write) hits
492system.cpu.icache.demand_hits::total 27857009 # number of demand (read+write) hits
493system.cpu.icache.overall_hits::cpu.inst 27857009 # number of overall hits
494system.cpu.icache.overall_hits::total 27857009 # number of overall hits
495system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
496system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
497system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
498system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
499system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
500system.cpu.icache.overall_misses::total 803 # number of overall misses
501system.cpu.icache.ReadReq_miss_latency::cpu.inst 55346748 # number of ReadReq miss cycles
502system.cpu.icache.ReadReq_miss_latency::total 55346748 # number of ReadReq miss cycles
503system.cpu.icache.demand_miss_latency::cpu.inst 55346748 # number of demand (read+write) miss cycles
504system.cpu.icache.demand_miss_latency::total 55346748 # number of demand (read+write) miss cycles
505system.cpu.icache.overall_miss_latency::cpu.inst 55346748 # number of overall miss cycles
506system.cpu.icache.overall_miss_latency::total 55346748 # number of overall miss cycles
507system.cpu.icache.ReadReq_accesses::cpu.inst 27857812 # number of ReadReq accesses(hits+misses)
508system.cpu.icache.ReadReq_accesses::total 27857812 # number of ReadReq accesses(hits+misses)
509system.cpu.icache.demand_accesses::cpu.inst 27857812 # number of demand (read+write) accesses
510system.cpu.icache.demand_accesses::total 27857812 # number of demand (read+write) accesses
511system.cpu.icache.overall_accesses::cpu.inst 27857812 # number of overall (read+write) accesses
512system.cpu.icache.overall_accesses::total 27857812 # number of overall (read+write) accesses
513system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
514system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
515system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
516system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
517system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
518system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
519system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68924.966376 # average ReadReq miss latency
520system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376 # average ReadReq miss latency
521system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency
522system.cpu.icache.demand_avg_miss_latency::total 68924.966376 # average overall miss latency
523system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency
524system.cpu.icache.overall_avg_miss_latency::total 68924.966376 # average overall miss latency
525system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
526system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
527system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
528system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
529system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
530system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
531system.cpu.icache.fast_writes 0 # number of fast writes performed
532system.cpu.icache.cache_copies 0 # number of cache copies performed
533system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
534system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses
535system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
536system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
537system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
538system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
539system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53408252 # number of ReadReq MSHR miss cycles
540system.cpu.icache.ReadReq_mshr_miss_latency::total 53408252 # number of ReadReq MSHR miss cycles
541system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53408252 # number of demand (read+write) MSHR miss cycles
542system.cpu.icache.demand_mshr_miss_latency::total 53408252 # number of demand (read+write) MSHR miss cycles
543system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53408252 # number of overall MSHR miss cycles
544system.cpu.icache.overall_mshr_miss_latency::total 53408252 # number of overall MSHR miss cycles
545system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
546system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
547system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
548system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
549system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
550system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
551system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency
552system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency
553system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency
554system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency
555system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency
556system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency
557system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
558system.cpu.l2cache.tags.replacements 0 # number of replacements
559system.cpu.l2cache.tags.tagsinuse 10247.121792 # Cycle average of tags in use
560system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks.
561system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks.
562system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks.
563system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
564system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236502 # Average occupied blocks per requestor
565system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885290 # Average occupied blocks per requestor
566system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy
567system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy
568system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy
569system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id
570system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
571system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
572system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
573system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
574system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
575system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id
576system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses
577system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses
578system.cpu.l2cache.ReadReq_hits::cpu.inst 903199 # number of ReadReq hits
579system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits
580system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits
581system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits
582system.cpu.l2cache.ReadExReq_hits::cpu.inst 32224 # number of ReadExReq hits
583system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits
584system.cpu.l2cache.demand_hits::cpu.inst 935423 # number of demand (read+write) hits
585system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits
586system.cpu.l2cache.overall_hits::cpu.inst 935423 # number of overall hits
587system.cpu.l2cache.overall_hits::total 935423 # number of overall hits
588system.cpu.l2cache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses
589system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses
590system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses
591system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
592system.cpu.l2cache.demand_misses::cpu.inst 15583 # number of demand (read+write) misses
593system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses
594system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses
595system.cpu.l2cache.overall_misses::total 15583 # number of overall misses
596system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71718500 # number of ReadReq miss cycles
597system.cpu.l2cache.ReadReq_miss_latency::total 71718500 # number of ReadReq miss cycles
598system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958069250 # number of ReadExReq miss cycles
599system.cpu.l2cache.ReadExReq_miss_latency::total 958069250 # number of ReadExReq miss cycles
600system.cpu.l2cache.demand_miss_latency::cpu.inst 1029787750 # number of demand (read+write) miss cycles
601system.cpu.l2cache.demand_miss_latency::total 1029787750 # number of demand (read+write) miss cycles
602system.cpu.l2cache.overall_miss_latency::cpu.inst 1029787750 # number of overall miss cycles
603system.cpu.l2cache.overall_miss_latency::total 1029787750 # number of overall miss cycles
604system.cpu.l2cache.ReadReq_accesses::cpu.inst 904238 # number of ReadReq accesses(hits+misses)
605system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses)
606system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses)
607system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses)
608system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46768 # number of ReadExReq accesses(hits+misses)
609system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses)
610system.cpu.l2cache.demand_accesses::cpu.inst 951006 # number of demand (read+write) accesses
611system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses
612system.cpu.l2cache.overall_accesses::cpu.inst 951006 # number of overall (read+write) accesses
613system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses
614system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001149 # miss rate for ReadReq accesses
615system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses
616system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310982 # miss rate for ReadExReq accesses
617system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses
618system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses
619system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
620system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses
621system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
622system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69026.467757 # average ReadReq miss latency
623system.cpu.l2cache.ReadReq_avg_miss_latency::total 69026.467757 # average ReadReq miss latency
624system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65873.848322 # average ReadExReq miss latency
625system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65873.848322 # average ReadExReq miss latency
626system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency
627system.cpu.l2cache.demand_avg_miss_latency::total 66084.049926 # average overall miss latency
628system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency
629system.cpu.l2cache.overall_avg_miss_latency::total 66084.049926 # average overall miss latency
630system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
631system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
632system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
633system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
634system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
635system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
636system.cpu.l2cache.fast_writes 0 # number of fast writes performed
637system.cpu.l2cache.cache_copies 0 # number of cache copies performed
638system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
639system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
640system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
641system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
642system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
643system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
644system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1031 # number of ReadReq MSHR misses
645system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses
646system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses
647system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
648system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 # number of demand (read+write) MSHR misses
649system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses
650system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses
651system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
652system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58344750 # number of ReadReq MSHR miss cycles
653system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58344750 # number of ReadReq MSHR miss cycles
654system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774500250 # number of ReadExReq MSHR miss cycles
655system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774500250 # number of ReadExReq MSHR miss cycles
656system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832845000 # number of demand (read+write) MSHR miss cycles
657system.cpu.l2cache.demand_mshr_miss_latency::total 832845000 # number of demand (read+write) MSHR miss cycles
658system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832845000 # number of overall MSHR miss cycles
659system.cpu.l2cache.overall_mshr_miss_latency::total 832845000 # number of overall MSHR miss cycles
660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses
661system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses
662system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses
663system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses
664system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses
665system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
666system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses
667system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
668system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56590.446169 # average ReadReq mshr miss latency
669system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56590.446169 # average ReadReq mshr miss latency
670system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53252.217409 # average ReadExReq mshr miss latency
671system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53252.217409 # average ReadExReq mshr miss latency
672system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency
673system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency
674system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency
675system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency
676system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
677system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution
678system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
679system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution
680system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution
681system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution
682system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
683system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes)
684system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes)
685system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
686system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes)
687system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
688system.cpu.toL2Bus.snoops 0 # Total snoops (count)
689system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram
690system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
691system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
692system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
693system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
694system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
695system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
696system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
697system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
698system.cpu.toL2Bus.snoop_fanout::5 1894292 100.00% 100.00% # Request fanout histogram
699system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
700system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
701system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
702system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
703system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram
704system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks)
705system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
706system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks)
707system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
708system.cpu.toL2Bus.respLayer1.occupancy 1428672494 # Layer occupancy (ticks)
709system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
710system.membus.trans_dist::ReadReq 1031 # Transaction distribution
711system.membus.trans_dist::ReadResp 1031 # Transaction distribution
712system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
713system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
714system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes)
715system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes)
716system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes)
717system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes)
718system.membus.snoops 0 # Total snoops (count)
719system.membus.snoop_fanout::samples 15575 # Request fanout histogram
720system.membus.snoop_fanout::mean 0 # Request fanout histogram
721system.membus.snoop_fanout::stdev 0 # Request fanout histogram
722system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
723system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram
724system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
725system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
726system.membus.snoop_fanout::min_value 0 # Request fanout histogram
727system.membus.snoop_fanout::max_value 0 # Request fanout histogram
728system.membus.snoop_fanout::total 15575 # Request fanout histogram
729system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks)
730system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
731system.membus.respLayer1.occupancy 146202000 # Layer occupancy (ticks)
732system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
733
734---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.061494 # Number of seconds simulated
4sim_ticks 61493732000 # Number of ticks simulated
5final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 280016 # Simulator instruction rate (inst/s)
8host_op_rate 281410 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 190051649 # Simulator tick rate (ticks/s)
10host_mem_usage 385752 # Number of bytes of host memory used
11host_seconds 323.56 # Real time elapsed on the host
12sim_insts 90602849 # Number of instructions simulated
13sim_ops 91054080 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 996800 # Number of bytes read from this memory
17system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory
20system.physmem.num_reads::cpu.inst 15575 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 16209782 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_total::cpu.inst 16209782 # Total bandwidth to/from this memory (bytes/s)
27system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.readReqs 15575 # Number of read requests accepted
29system.physmem.writeReqs 0 # Number of write requests accepted
30system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
32system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM
33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
35system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side
36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
40system.physmem.perBankRdBursts::0 993 # Per bank write bursts
41system.physmem.perBankRdBursts::1 890 # Per bank write bursts
42system.physmem.perBankRdBursts::2 949 # Per bank write bursts
43system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
44system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
45system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
46system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
47system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
48system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
49system.physmem.perBankRdBursts::9 962 # Per bank write bursts
50system.physmem.perBankRdBursts::10 938 # Per bank write bursts
51system.physmem.perBankRdBursts::11 899 # Per bank write bursts
52system.physmem.perBankRdBursts::12 904 # Per bank write bursts
53system.physmem.perBankRdBursts::13 867 # Per bank write bursts
54system.physmem.perBankRdBursts::14 877 # Per bank write bursts
55system.physmem.perBankRdBursts::15 905 # Per bank write bursts
56system.physmem.perBankWrBursts::0 0 # Per bank write bursts
57system.physmem.perBankWrBursts::1 0 # Per bank write bursts
58system.physmem.perBankWrBursts::2 0 # Per bank write bursts
59system.physmem.perBankWrBursts::3 0 # Per bank write bursts
60system.physmem.perBankWrBursts::4 0 # Per bank write bursts
61system.physmem.perBankWrBursts::5 0 # Per bank write bursts
62system.physmem.perBankWrBursts::6 0 # Per bank write bursts
63system.physmem.perBankWrBursts::7 0 # Per bank write bursts
64system.physmem.perBankWrBursts::8 0 # Per bank write bursts
65system.physmem.perBankWrBursts::9 0 # Per bank write bursts
66system.physmem.perBankWrBursts::10 0 # Per bank write bursts
67system.physmem.perBankWrBursts::11 0 # Per bank write bursts
68system.physmem.perBankWrBursts::12 0 # Per bank write bursts
69system.physmem.perBankWrBursts::13 0 # Per bank write bursts
70system.physmem.perBankWrBursts::14 0 # Per bank write bursts
71system.physmem.perBankWrBursts::15 0 # Per bank write bursts
72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
74system.physmem.totGap 61493643500 # Total gap between requests
75system.physmem.readPktSize::0 0 # Read request sizes (log2)
76system.physmem.readPktSize::1 0 # Read request sizes (log2)
77system.physmem.readPktSize::2 0 # Read request sizes (log2)
78system.physmem.readPktSize::3 0 # Read request sizes (log2)
79system.physmem.readPktSize::4 0 # Read request sizes (log2)
80system.physmem.readPktSize::5 0 # Read request sizes (log2)
81system.physmem.readPktSize::6 15575 # Read request sizes (log2)
82system.physmem.writePktSize::0 0 # Write request sizes (log2)
83system.physmem.writePktSize::1 0 # Write request sizes (log2)
84system.physmem.writePktSize::2 0 # Write request sizes (log2)
85system.physmem.writePktSize::3 0 # Write request sizes (log2)
86system.physmem.writePktSize::4 0 # Write request sizes (log2)
87system.physmem.writePktSize::5 0 # Write request sizes (log2)
88system.physmem.writePktSize::6 0 # Write request sizes (log2)
89system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 112 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
--- 77 unchanged lines hidden (view full) ---
177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
185system.physmem.bytesPerActivate::samples 1534 # Bytes accessed per row activation
186system.physmem.bytesPerActivate::mean 648.594524 # Bytes accessed per row activation
187system.physmem.bytesPerActivate::gmean 444.741065 # Bytes accessed per row activation
188system.physmem.bytesPerActivate::stdev 399.329877 # Bytes accessed per row activation
189system.physmem.bytesPerActivate::0-127 241 15.71% 15.71% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::128-255 178 11.60% 27.31% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation
199system.physmem.totQLat 73246500 # Total ticks spent queuing
200system.physmem.totMemAccLat 365277750 # Total ticks spent from burst creation until serviced by the DRAM
201system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
202system.physmem.avgQLat 4702.83 # Average queueing delay per DRAM burst
203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
204system.physmem.avgMemAccLat 23452.83 # Average memory access latency per DRAM burst
205system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s
206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
207system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s
208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
210system.physmem.busUtil 0.13 # Data bus utilization in percentage
211system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
213system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
215system.physmem.readRowHits 14031 # Number of row buffer hits during reads
216system.physmem.writeRowHits 0 # Number of row buffer hits during writes
217system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads
218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
219system.physmem.avgGap 3948227.51 # Average gap between requests
220system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined
221system.physmem.memoryStateTime::IDLE 56242943250 # Time in different power states
222system.physmem.memoryStateTime::REF 2053220000 # Time in different power states
223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
224system.physmem.memoryStateTime::ACT 3193793750 # Time in different power states
225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
226system.physmem.actEnergy::0 6320160 # Energy for activate commands per rank (pJ)
227system.physmem.actEnergy::1 5261760 # Energy for activate commands per rank (pJ)
228system.physmem.preEnergy::0 3448500 # Energy for precharge commands per rank (pJ)
229system.physmem.preEnergy::1 2871000 # Energy for precharge commands per rank (pJ)
230system.physmem.readEnergy::0 63663600 # Energy for read commands per rank (pJ)
231system.physmem.readEnergy::1 57462600 # Energy for read commands per rank (pJ)
232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
234system.physmem.refreshEnergy::0 4016098320 # Energy for refresh commands per rank (pJ)
235system.physmem.refreshEnergy::1 4016098320 # Energy for refresh commands per rank (pJ)
236system.physmem.actBackEnergy::0 2490497865 # Energy for active background per rank (pJ)
237system.physmem.actBackEnergy::1 2514078765 # Energy for active background per rank (pJ)
238system.physmem.preBackEnergy::0 34708310250 # Energy for precharge background per rank (pJ)
239system.physmem.preBackEnergy::1 34687625250 # Energy for precharge background per rank (pJ)
240system.physmem.totalEnergy::0 41288338695 # Total energy per rank (pJ)
241system.physmem.totalEnergy::1 41283397695 # Total energy per rank (pJ)
242system.physmem.averagePower::0 671.483256 # Core power per rank (mW)
243system.physmem.averagePower::1 671.402899 # Core power per rank (mW)
244system.cpu.branchPred.lookups 20789429 # Number of BP lookups
245system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted
246system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect
247system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups
248system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits
249system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
250system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage
251system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target.
252system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
253system.cpu_clk_domain.clock 500 # Clock period in ticks
254system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
255system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
256system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
257system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
258system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
259system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 69 unchanged lines hidden (view full) ---
331system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
332system.cpu.itb.read_accesses 0 # DTB read accesses
333system.cpu.itb.write_accesses 0 # DTB write accesses
334system.cpu.itb.inst_accesses 0 # ITB inst accesses
335system.cpu.itb.hits 0 # DTB hits
336system.cpu.itb.misses 0 # DTB misses
337system.cpu.itb.accesses 0 # DTB accesses
338system.cpu.workload.num_syscalls 442 # Number of system calls
339system.cpu.numCycles 122987464 # number of cpu cycles simulated
340system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
341system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
342system.cpu.committedInsts 90602849 # Number of instructions committed
343system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
344system.cpu.discardedOps 2068195 # Number of ops (including micro ops) which were discarded before commit
345system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
346system.cpu.cpi 1.357435 # CPI: cycles per instruction
347system.cpu.ipc 0.736684 # IPC: instructions per cycle
348system.cpu.tickCycles 109826570 # Number of cycles that the object actually ticked
349system.cpu.idleCycles 13160894 # Total number of cycles that the object has spent stopped
350system.cpu.dcache.tags.replacements 946107 # number of replacements
351system.cpu.dcache.tags.tagsinuse 3616.604238 # Cycle average of tags in use
352system.cpu.dcache.tags.total_refs 26267660 # Total number of references to valid blocks.
353system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks.
354system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks.
355system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit.
356system.cpu.dcache.tags.occ_blocks::cpu.inst 3616.604238 # Average occupied blocks per requestor
357system.cpu.dcache.tags.occ_percent::cpu.inst 0.882960 # Average percentage of cache occupancy
358system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy
359system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
360system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id
361system.cpu.dcache.tags.age_task_id_blocks_1024::1 2249 # Occupied blocks per task id
362system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id
363system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
364system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses
365system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses
366system.cpu.dcache.ReadReq_hits::cpu.inst 21598813 # number of ReadReq hits
367system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits
368system.cpu.dcache.WriteReq_hits::cpu.inst 4661073 # number of WriteReq hits
369system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits
370system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits
371system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
372system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits
373system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
374system.cpu.dcache.demand_hits::cpu.inst 26259886 # number of demand (read+write) hits
375system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits
376system.cpu.dcache.overall_hits::cpu.inst 26259886 # number of overall hits
377system.cpu.dcache.overall_hits::total 26259886 # number of overall hits
378system.cpu.dcache.ReadReq_misses::cpu.inst 914958 # number of ReadReq misses
379system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses
380system.cpu.dcache.WriteReq_misses::cpu.inst 73908 # number of WriteReq misses
381system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses
382system.cpu.dcache.demand_misses::cpu.inst 988866 # number of demand (read+write) misses
383system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses
384system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses
385system.cpu.dcache.overall_misses::total 988866 # number of overall misses
386system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910311744 # number of ReadReq miss cycles
387system.cpu.dcache.ReadReq_miss_latency::total 11910311744 # number of ReadReq miss cycles
388system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345697500 # number of WriteReq miss cycles
389system.cpu.dcache.WriteReq_miss_latency::total 2345697500 # number of WriteReq miss cycles
390system.cpu.dcache.demand_miss_latency::cpu.inst 14256009244 # number of demand (read+write) miss cycles
391system.cpu.dcache.demand_miss_latency::total 14256009244 # number of demand (read+write) miss cycles
392system.cpu.dcache.overall_miss_latency::cpu.inst 14256009244 # number of overall miss cycles
393system.cpu.dcache.overall_miss_latency::total 14256009244 # number of overall miss cycles
394system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses)
395system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses)
396system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses)
397system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
398system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses)
399system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
400system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses)
401system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
402system.cpu.dcache.demand_accesses::cpu.inst 27248752 # number of demand (read+write) accesses
403system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses
404system.cpu.dcache.overall_accesses::cpu.inst 27248752 # number of overall (read+write) accesses
405system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses
406system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040640 # miss rate for ReadReq accesses
407system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses
408system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015609 # miss rate for WriteReq accesses
409system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses
410system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses
411system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses
412system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses
413system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses
414system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.331663 # average ReadReq miss latency
415system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.331663 # average ReadReq miss latency
416system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.073010 # average WriteReq miss latency
417system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.073010 # average WriteReq miss latency
418system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency
419system.cpu.dcache.demand_avg_miss_latency::total 14416.522809 # average overall miss latency
420system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency
421system.cpu.dcache.overall_avg_miss_latency::total 14416.522809 # average overall miss latency
422system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
423system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
424system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
425system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
426system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
427system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
428system.cpu.dcache.fast_writes 0 # number of fast writes performed
429system.cpu.dcache.cache_copies 0 # number of cache copies performed
430system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks
431system.cpu.dcache.writebacks::total 943286 # number of writebacks
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433system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits
434system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits
435system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits
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437system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits
438system.cpu.dcache.overall_mshr_hits::cpu.inst 38663 # number of overall MSHR hits
439system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits
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441system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses
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443system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses
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446system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses
447system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses
448system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958869756 # number of ReadReq MSHR miss cycles
449system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958869756 # number of ReadReq MSHR miss cycles
450system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333434750 # number of WriteReq MSHR miss cycles
451system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333434750 # number of WriteReq MSHR miss cycles
452system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292304506 # number of demand (read+write) MSHR miss cycles
453system.cpu.dcache.demand_mshr_miss_latency::total 11292304506 # number of demand (read+write) MSHR miss cycles
454system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292304506 # number of overall MSHR miss cycles
455system.cpu.dcache.overall_mshr_miss_latency::total 11292304506 # number of overall MSHR miss cycles
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457system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses
458system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses
459system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses
460system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for demand accesses
461system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
462system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses
463system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
464system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.338432 # average ReadReq mshr miss latency
465system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.338432 # average ReadReq mshr miss latency
466system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28511.690686 # average WriteReq mshr miss latency
467system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28511.690686 # average WriteReq mshr miss latency
468system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency
469system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency
470system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency
471system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency
472system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
473system.cpu.icache.tags.replacements 5 # number of replacements
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475system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks.
476system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
477system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks.
478system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
479system.cpu.icache.tags.occ_blocks::cpu.inst 690.411179 # Average occupied blocks per requestor
480system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy
481system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy
482system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
483system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
484system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
485system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
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488system.cpu.icache.tags.data_accesses 55716427 # Number of data accesses
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490system.cpu.icache.ReadReq_hits::total 27857009 # number of ReadReq hits
491system.cpu.icache.demand_hits::cpu.inst 27857009 # number of demand (read+write) hits
492system.cpu.icache.demand_hits::total 27857009 # number of demand (read+write) hits
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494system.cpu.icache.overall_hits::total 27857009 # number of overall hits
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496system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
497system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
498system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
499system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
500system.cpu.icache.overall_misses::total 803 # number of overall misses
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502system.cpu.icache.ReadReq_miss_latency::total 55346748 # number of ReadReq miss cycles
503system.cpu.icache.demand_miss_latency::cpu.inst 55346748 # number of demand (read+write) miss cycles
504system.cpu.icache.demand_miss_latency::total 55346748 # number of demand (read+write) miss cycles
505system.cpu.icache.overall_miss_latency::cpu.inst 55346748 # number of overall miss cycles
506system.cpu.icache.overall_miss_latency::total 55346748 # number of overall miss cycles
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508system.cpu.icache.ReadReq_accesses::total 27857812 # number of ReadReq accesses(hits+misses)
509system.cpu.icache.demand_accesses::cpu.inst 27857812 # number of demand (read+write) accesses
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514system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
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516system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
517system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
518system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
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520system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376 # average ReadReq miss latency
521system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency
522system.cpu.icache.demand_avg_miss_latency::total 68924.966376 # average overall miss latency
523system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency
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530system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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532system.cpu.icache.cache_copies 0 # number of cache copies performed
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535system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
536system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
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538system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
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540system.cpu.icache.ReadReq_mshr_miss_latency::total 53408252 # number of ReadReq MSHR miss cycles
541system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53408252 # number of demand (read+write) MSHR miss cycles
542system.cpu.icache.demand_mshr_miss_latency::total 53408252 # number of demand (read+write) MSHR miss cycles
543system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53408252 # number of overall MSHR miss cycles
544system.cpu.icache.overall_mshr_miss_latency::total 53408252 # number of overall MSHR miss cycles
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546system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
547system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
548system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
549system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
550system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
551system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency
552system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency
553system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency
554system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency
555system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency
556system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency
557system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
558system.cpu.l2cache.tags.replacements 0 # number of replacements
559system.cpu.l2cache.tags.tagsinuse 10247.121792 # Cycle average of tags in use
560system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks.
561system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks.
562system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks.
563system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
564system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236502 # Average occupied blocks per requestor
565system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885290 # Average occupied blocks per requestor
566system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy
567system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy
568system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy
569system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id
570system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
571system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
572system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
573system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
574system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
575system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id
576system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses
577system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses
578system.cpu.l2cache.ReadReq_hits::cpu.inst 903199 # number of ReadReq hits
579system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits
580system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits
581system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits
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583system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits
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585system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits
586system.cpu.l2cache.overall_hits::cpu.inst 935423 # number of overall hits
587system.cpu.l2cache.overall_hits::total 935423 # number of overall hits
588system.cpu.l2cache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses
589system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses
590system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses
591system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
592system.cpu.l2cache.demand_misses::cpu.inst 15583 # number of demand (read+write) misses
593system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses
594system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses
595system.cpu.l2cache.overall_misses::total 15583 # number of overall misses
596system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71718500 # number of ReadReq miss cycles
597system.cpu.l2cache.ReadReq_miss_latency::total 71718500 # number of ReadReq miss cycles
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599system.cpu.l2cache.ReadExReq_miss_latency::total 958069250 # number of ReadExReq miss cycles
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601system.cpu.l2cache.demand_miss_latency::total 1029787750 # number of demand (read+write) miss cycles
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603system.cpu.l2cache.overall_miss_latency::total 1029787750 # number of overall miss cycles
604system.cpu.l2cache.ReadReq_accesses::cpu.inst 904238 # number of ReadReq accesses(hits+misses)
605system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses)
606system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses)
607system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses)
608system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46768 # number of ReadExReq accesses(hits+misses)
609system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses)
610system.cpu.l2cache.demand_accesses::cpu.inst 951006 # number of demand (read+write) accesses
611system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses
612system.cpu.l2cache.overall_accesses::cpu.inst 951006 # number of overall (read+write) accesses
613system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses
614system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001149 # miss rate for ReadReq accesses
615system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses
616system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310982 # miss rate for ReadExReq accesses
617system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses
618system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses
619system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
620system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses
621system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
622system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69026.467757 # average ReadReq miss latency
623system.cpu.l2cache.ReadReq_avg_miss_latency::total 69026.467757 # average ReadReq miss latency
624system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65873.848322 # average ReadExReq miss latency
625system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65873.848322 # average ReadExReq miss latency
626system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency
627system.cpu.l2cache.demand_avg_miss_latency::total 66084.049926 # average overall miss latency
628system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency
629system.cpu.l2cache.overall_avg_miss_latency::total 66084.049926 # average overall miss latency
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632system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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634system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
635system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
636system.cpu.l2cache.fast_writes 0 # number of fast writes performed
637system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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639system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
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642system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
643system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
644system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1031 # number of ReadReq MSHR misses
645system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses
646system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses
647system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
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649system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses
650system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses
651system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
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653system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58344750 # number of ReadReq MSHR miss cycles
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655system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774500250 # number of ReadExReq MSHR miss cycles
656system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832845000 # number of demand (read+write) MSHR miss cycles
657system.cpu.l2cache.demand_mshr_miss_latency::total 832845000 # number of demand (read+write) MSHR miss cycles
658system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832845000 # number of overall MSHR miss cycles
659system.cpu.l2cache.overall_mshr_miss_latency::total 832845000 # number of overall MSHR miss cycles
660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses
661system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses
662system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses
663system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses
664system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses
665system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
666system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses
667system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
668system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56590.446169 # average ReadReq mshr miss latency
669system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56590.446169 # average ReadReq mshr miss latency
670system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53252.217409 # average ReadExReq mshr miss latency
671system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53252.217409 # average ReadExReq mshr miss latency
672system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency
673system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency
674system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency
675system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency
676system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
677system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution
678system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
679system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution
680system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution
681system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution
682system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
683system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes)
684system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes)
685system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
686system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes)
687system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
688system.cpu.toL2Bus.snoops 0 # Total snoops (count)
689system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram
690system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
691system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
692system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
693system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
694system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
695system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
696system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
697system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
698system.cpu.toL2Bus.snoop_fanout::5 1894292 100.00% 100.00% # Request fanout histogram
699system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
700system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
701system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
702system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
703system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram
704system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks)
705system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
706system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks)
707system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
708system.cpu.toL2Bus.respLayer1.occupancy 1428672494 # Layer occupancy (ticks)
709system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
710system.membus.trans_dist::ReadReq 1031 # Transaction distribution
711system.membus.trans_dist::ReadResp 1031 # Transaction distribution
712system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
713system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
714system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes)
715system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes)
716system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes)
717system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes)
718system.membus.snoops 0 # Total snoops (count)
719system.membus.snoop_fanout::samples 15575 # Request fanout histogram
720system.membus.snoop_fanout::mean 0 # Request fanout histogram
721system.membus.snoop_fanout::stdev 0 # Request fanout histogram
722system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
723system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram
724system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
725system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
726system.membus.snoop_fanout::min_value 0 # Request fanout histogram
727system.membus.snoop_fanout::max_value 0 # Request fanout histogram
728system.membus.snoop_fanout::total 15575 # Request fanout histogram
729system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks)
730system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
731system.membus.respLayer1.occupancy 146202000 # Layer occupancy (ticks)
732system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
733
734---------- End Simulation Statistics ----------