simout (8835:7c68f84d7c4e) simout (8983:8800b05e1cb3)
1gem5 Simulator System. http://gem5.org
2gem5 is copyrighted software; use the --copyright option for details.
3
1gem5 Simulator System. http://gem5.org
2gem5 is copyrighted software; use the --copyright option for details.
3
4gem5 compiled Feb 11 2012 13:08:33
5gem5 started Feb 11 2012 14:02:46
6gem5 executing on zizzer
7command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
4gem5 compiled May 8 2012 15:05:42
5gem5 started May 8 2012 15:49:20
6gem5 executing on piton
7command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
8Global frequency set at 2000000000 ticks per second
8Global frequency set at 2000000000 ticks per second
9info: No kernel set for full system simulation. Assuming you know what you're doing...
9info: No kernel set for full system simulation. Assuming you know what you're doing if not SPARC ISA
10 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
11
12 0: system.t1000.htod: Real-time clock set to 1230768000
10info: Entering event queue @ 0. Starting simulation...
11info: Ignoring write to SPARC ERROR regsiter
12info: Ignoring write to SPARC ERROR regsiter
13Exiting @ tick 2233777512 because m5_exit instruction encountered
13info: Entering event queue @ 0. Starting simulation...
14info: Ignoring write to SPARC ERROR regsiter
15info: Ignoring write to SPARC ERROR regsiter
16Exiting @ tick 2233777512 because m5_exit instruction encountered