config.json (11946:8eb1f2595a92) config.json (11950:8011fd8ce05c)
1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
16 "clk_domain": "system.clk_domain",
1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
16 "clk_domain": "system.clk_domain",
17 "power_model": null,
17 "latency_var": 0,
18 "bandwidth": "0.000000",
19 "conf_table_reported": true,
20 "cxx_class": "SimpleMemory",
21 "p_state_clk_gate_max": 2000000000,
22 "path": "system.rom",
23 "null": false,
24 "type": "SimpleMemory",

--- 16 unchanged lines hidden (view full) ---

41 "role": "SLAVE"
42 },
43 "name": "bridge",
44 "p_state_clk_gate_min": 2,
45 "p_state_clk_gate_bins": 20,
46 "cxx_class": "Bridge",
47 "req_size": 16,
48 "clk_domain": "system.clk_domain",
18 "latency_var": 0,
19 "bandwidth": "0.000000",
20 "conf_table_reported": true,
21 "cxx_class": "SimpleMemory",
22 "p_state_clk_gate_max": 2000000000,
23 "path": "system.rom",
24 "null": false,
25 "type": "SimpleMemory",

--- 16 unchanged lines hidden (view full) ---

42 "role": "SLAVE"
43 },
44 "name": "bridge",
45 "p_state_clk_gate_min": 2,
46 "p_state_clk_gate_bins": 20,
47 "cxx_class": "Bridge",
48 "req_size": 16,
49 "clk_domain": "system.clk_domain",
50 "power_model": null,
49 "delay": 100,
50 "eventq_index": 0,
51 "master": {
52 "peer": "system.iobus.slave[0]",
53 "role": "MASTER"
54 },
55 "default_p_state": "UNDEFINED",
56 "p_state_clk_gate_max": 2000000000,

--- 9 unchanged lines hidden (view full) ---

66 ],
67 "role": "SLAVE"
68 },
69 "name": "iobus",
70 "p_state_clk_gate_min": 2,
71 "p_state_clk_gate_bins": 20,
72 "cxx_class": "NoncoherentXBar",
73 "clk_domain": "system.clk_domain",
51 "delay": 100,
52 "eventq_index": 0,
53 "master": {
54 "peer": "system.iobus.slave[0]",
55 "role": "MASTER"
56 },
57 "default_p_state": "UNDEFINED",
58 "p_state_clk_gate_max": 2000000000,

--- 9 unchanged lines hidden (view full) ---

68 ],
69 "role": "SLAVE"
70 },
71 "name": "iobus",
72 "p_state_clk_gate_min": 2,
73 "p_state_clk_gate_bins": 20,
74 "cxx_class": "NoncoherentXBar",
75 "clk_domain": "system.clk_domain",
76 "power_model": null,
74 "width": 16,
75 "eventq_index": 0,
76 "master": {
77 "peer": [
78 "system.t1000.fake_clk.pio",
79 "system.t1000.fake_membnks.pio",
80 "system.t1000.fake_l2_1.pio",
81 "system.t1000.fake_l2_2.pio",

--- 26 unchanged lines hidden (view full) ---

108 "pio": {
109 "peer": "system.membus.master[1]",
110 "role": "SLAVE"
111 },
112 "p_state_clk_gate_bins": 20,
113 "cxx_class": "DumbTOD",
114 "pio_latency": 200,
115 "clk_domain": "system.clk_domain",
77 "width": 16,
78 "eventq_index": 0,
79 "master": {
80 "peer": [
81 "system.t1000.fake_clk.pio",
82 "system.t1000.fake_membnks.pio",
83 "system.t1000.fake_l2_1.pio",
84 "system.t1000.fake_l2_2.pio",

--- 26 unchanged lines hidden (view full) ---

111 "pio": {
112 "peer": "system.membus.master[1]",
113 "role": "SLAVE"
114 },
115 "p_state_clk_gate_bins": 20,
116 "cxx_class": "DumbTOD",
117 "pio_latency": 200,
118 "clk_domain": "system.clk_domain",
119 "power_model": null,
116 "system": "system",
117 "eventq_index": 0,
118 "time": "Thu Jan 1 00:00:00 2009",
119 "default_p_state": "UNDEFINED",
120 "p_state_clk_gate_max": 2000000000,
121 "path": "system.t1000.htod",
122 "pio_addr": 1099255906296,
123 "type": "DumbTOD"

--- 4 unchanged lines hidden (view full) ---

128 "pio": {
129 "peer": "system.iobus.master[12]",
130 "role": "SLAVE"
131 },
132 "p_state_clk_gate_bins": 20,
133 "cxx_class": "Uart8250",
134 "pio_latency": 200,
135 "clk_domain": "system.clk_domain",
120 "system": "system",
121 "eventq_index": 0,
122 "time": "Thu Jan 1 00:00:00 2009",
123 "default_p_state": "UNDEFINED",
124 "p_state_clk_gate_max": 2000000000,
125 "path": "system.t1000.htod",
126 "pio_addr": 1099255906296,
127 "type": "DumbTOD"

--- 4 unchanged lines hidden (view full) ---

132 "pio": {
133 "peer": "system.iobus.master[12]",
134 "role": "SLAVE"
135 },
136 "p_state_clk_gate_bins": 20,
137 "cxx_class": "Uart8250",
138 "pio_latency": 200,
139 "clk_domain": "system.clk_domain",
140 "power_model": null,
136 "system": "system",
137 "terminal": "system.t1000.pterm",
138 "platform": "system.t1000",
139 "eventq_index": 0,
140 "default_p_state": "UNDEFINED",
141 "p_state_clk_gate_max": 2000000000,
142 "path": "system.t1000.puart0",
143 "pio_addr": 133412421632,

--- 13 unchanged lines hidden (view full) ---

157 "warn_access": "",
158 "pio_latency": 200,
159 "system": "system",
160 "eventq_index": 0,
161 "default_p_state": "UNDEFINED",
162 "p_state_clk_gate_max": 2000000000,
163 "type": "IsaFake",
164 "p_state_clk_gate_min": 2,
141 "system": "system",
142 "terminal": "system.t1000.pterm",
143 "platform": "system.t1000",
144 "eventq_index": 0,
145 "default_p_state": "UNDEFINED",
146 "p_state_clk_gate_max": 2000000000,
147 "path": "system.t1000.puart0",
148 "pio_addr": 133412421632,

--- 13 unchanged lines hidden (view full) ---

162 "warn_access": "",
163 "pio_latency": 200,
164 "system": "system",
165 "eventq_index": 0,
166 "default_p_state": "UNDEFINED",
167 "p_state_clk_gate_max": 2000000000,
168 "type": "IsaFake",
169 "p_state_clk_gate_min": 2,
170 "power_model": null,
165 "ret_data32": 4294967295,
166 "path": "system.t1000.fake_membnks",
167 "ret_data16": 65535,
168 "ret_data8": 255,
169 "name": "fake_membnks",
170 "ret_bad_addr": false,
171 "pio_size": 16384,
172 "p_state_clk_gate_bins": 20

--- 13 unchanged lines hidden (view full) ---

186 "warn_access": "",
187 "pio_latency": 200,
188 "system": "system",
189 "eventq_index": 0,
190 "default_p_state": "UNDEFINED",
191 "p_state_clk_gate_max": 2000000000,
192 "type": "IsaFake",
193 "p_state_clk_gate_min": 2,
171 "ret_data32": 4294967295,
172 "path": "system.t1000.fake_membnks",
173 "ret_data16": 65535,
174 "ret_data8": 255,
175 "name": "fake_membnks",
176 "ret_bad_addr": false,
177 "pio_size": 16384,
178 "p_state_clk_gate_bins": 20

--- 13 unchanged lines hidden (view full) ---

192 "warn_access": "",
193 "pio_latency": 200,
194 "system": "system",
195 "eventq_index": 0,
196 "default_p_state": "UNDEFINED",
197 "p_state_clk_gate_max": 2000000000,
198 "type": "IsaFake",
199 "p_state_clk_gate_min": 2,
200 "power_model": null,
194 "ret_data32": 4294967295,
195 "path": "system.t1000.fake_jbi",
196 "ret_data16": 65535,
197 "ret_data8": 255,
198 "name": "fake_jbi",
199 "ret_bad_addr": false,
200 "pio_size": 4294967296,
201 "p_state_clk_gate_bins": 20

--- 13 unchanged lines hidden (view full) ---

215 "warn_access": "",
216 "pio_latency": 200,
217 "system": "system",
218 "eventq_index": 0,
219 "default_p_state": "UNDEFINED",
220 "p_state_clk_gate_max": 2000000000,
221 "type": "IsaFake",
222 "p_state_clk_gate_min": 2,
201 "ret_data32": 4294967295,
202 "path": "system.t1000.fake_jbi",
203 "ret_data16": 65535,
204 "ret_data8": 255,
205 "name": "fake_jbi",
206 "ret_bad_addr": false,
207 "pio_size": 4294967296,
208 "p_state_clk_gate_bins": 20

--- 13 unchanged lines hidden (view full) ---

222 "warn_access": "",
223 "pio_latency": 200,
224 "system": "system",
225 "eventq_index": 0,
226 "default_p_state": "UNDEFINED",
227 "p_state_clk_gate_max": 2000000000,
228 "type": "IsaFake",
229 "p_state_clk_gate_min": 2,
230 "power_model": null,
223 "ret_data32": 4294967295,
224 "path": "system.t1000.fake_l2esr_2",
225 "ret_data16": 65535,
226 "ret_data8": 255,
227 "name": "fake_l2esr_2",
228 "ret_bad_addr": false,
229 "pio_size": 8,
230 "p_state_clk_gate_bins": 20

--- 26 unchanged lines hidden (view full) ---

257 "warn_access": "",
258 "pio_latency": 200,
259 "system": "system",
260 "eventq_index": 0,
261 "default_p_state": "UNDEFINED",
262 "p_state_clk_gate_max": 2000000000,
263 "type": "IsaFake",
264 "p_state_clk_gate_min": 2,
231 "ret_data32": 4294967295,
232 "path": "system.t1000.fake_l2esr_2",
233 "ret_data16": 65535,
234 "ret_data8": 255,
235 "name": "fake_l2esr_2",
236 "ret_bad_addr": false,
237 "pio_size": 8,
238 "p_state_clk_gate_bins": 20

--- 26 unchanged lines hidden (view full) ---

265 "warn_access": "",
266 "pio_latency": 200,
267 "system": "system",
268 "eventq_index": 0,
269 "default_p_state": "UNDEFINED",
270 "p_state_clk_gate_max": 2000000000,
271 "type": "IsaFake",
272 "p_state_clk_gate_min": 2,
273 "power_model": null,
265 "ret_data32": 4294967295,
266 "path": "system.t1000.fake_l2_4",
267 "ret_data16": 65535,
268 "ret_data8": 255,
269 "name": "fake_l2_4",
270 "ret_bad_addr": false,
271 "pio_size": 8,
272 "p_state_clk_gate_bins": 20

--- 12 unchanged lines hidden (view full) ---

285 "warn_access": "",
286 "pio_latency": 200,
287 "system": "system",
288 "eventq_index": 0,
289 "default_p_state": "UNDEFINED",
290 "p_state_clk_gate_max": 2000000000,
291 "type": "IsaFake",
292 "p_state_clk_gate_min": 2,
274 "ret_data32": 4294967295,
275 "path": "system.t1000.fake_l2_4",
276 "ret_data16": 65535,
277 "ret_data8": 255,
278 "name": "fake_l2_4",
279 "ret_bad_addr": false,
280 "pio_size": 8,
281 "p_state_clk_gate_bins": 20

--- 12 unchanged lines hidden (view full) ---

294 "warn_access": "",
295 "pio_latency": 200,
296 "system": "system",
297 "eventq_index": 0,
298 "default_p_state": "UNDEFINED",
299 "p_state_clk_gate_max": 2000000000,
300 "type": "IsaFake",
301 "p_state_clk_gate_min": 2,
302 "power_model": null,
293 "ret_data32": 4294967295,
294 "path": "system.t1000.fake_l2_1",
295 "ret_data16": 65535,
296 "ret_data8": 255,
297 "name": "fake_l2_1",
298 "ret_bad_addr": false,
299 "pio_size": 8,
300 "p_state_clk_gate_bins": 20

--- 12 unchanged lines hidden (view full) ---

313 "warn_access": "",
314 "pio_latency": 200,
315 "system": "system",
316 "eventq_index": 0,
317 "default_p_state": "UNDEFINED",
318 "p_state_clk_gate_max": 2000000000,
319 "type": "IsaFake",
320 "p_state_clk_gate_min": 2,
303 "ret_data32": 4294967295,
304 "path": "system.t1000.fake_l2_1",
305 "ret_data16": 65535,
306 "ret_data8": 255,
307 "name": "fake_l2_1",
308 "ret_bad_addr": false,
309 "pio_size": 8,
310 "p_state_clk_gate_bins": 20

--- 12 unchanged lines hidden (view full) ---

323 "warn_access": "",
324 "pio_latency": 200,
325 "system": "system",
326 "eventq_index": 0,
327 "default_p_state": "UNDEFINED",
328 "p_state_clk_gate_max": 2000000000,
329 "type": "IsaFake",
330 "p_state_clk_gate_min": 2,
331 "power_model": null,
321 "ret_data32": 4294967295,
322 "path": "system.t1000.fake_l2_2",
323 "ret_data16": 65535,
324 "ret_data8": 255,
325 "name": "fake_l2_2",
326 "ret_bad_addr": false,
327 "pio_size": 8,
328 "p_state_clk_gate_bins": 20

--- 12 unchanged lines hidden (view full) ---

341 "warn_access": "",
342 "pio_latency": 200,
343 "system": "system",
344 "eventq_index": 0,
345 "default_p_state": "UNDEFINED",
346 "p_state_clk_gate_max": 2000000000,
347 "type": "IsaFake",
348 "p_state_clk_gate_min": 2,
332 "ret_data32": 4294967295,
333 "path": "system.t1000.fake_l2_2",
334 "ret_data16": 65535,
335 "ret_data8": 255,
336 "name": "fake_l2_2",
337 "ret_bad_addr": false,
338 "pio_size": 8,
339 "p_state_clk_gate_bins": 20

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352 "warn_access": "",
353 "pio_latency": 200,
354 "system": "system",
355 "eventq_index": 0,
356 "default_p_state": "UNDEFINED",
357 "p_state_clk_gate_max": 2000000000,
358 "type": "IsaFake",
359 "p_state_clk_gate_min": 2,
360 "power_model": null,
349 "ret_data32": 4294967295,
350 "path": "system.t1000.fake_l2_3",
351 "ret_data16": 65535,
352 "ret_data8": 255,
353 "name": "fake_l2_3",
354 "ret_bad_addr": false,
355 "pio_size": 8,
356 "p_state_clk_gate_bins": 20

--- 16 unchanged lines hidden (view full) ---

373 "pio": {
374 "peer": "system.membus.master[0]",
375 "role": "SLAVE"
376 },
377 "p_state_clk_gate_bins": 20,
378 "cxx_class": "Iob",
379 "pio_latency": 2,
380 "clk_domain": "system.clk_domain",
361 "ret_data32": 4294967295,
362 "path": "system.t1000.fake_l2_3",
363 "ret_data16": 65535,
364 "ret_data8": 255,
365 "name": "fake_l2_3",
366 "ret_bad_addr": false,
367 "pio_size": 8,
368 "p_state_clk_gate_bins": 20

--- 16 unchanged lines hidden (view full) ---

385 "pio": {
386 "peer": "system.membus.master[0]",
387 "role": "SLAVE"
388 },
389 "p_state_clk_gate_bins": 20,
390 "cxx_class": "Iob",
391 "pio_latency": 2,
392 "clk_domain": "system.clk_domain",
393 "power_model": null,
381 "system": "system",
382 "platform": "system.t1000",
383 "eventq_index": 0,
384 "default_p_state": "UNDEFINED",
385 "p_state_clk_gate_max": 2000000000,
386 "path": "system.t1000.iob",
387 "type": "Iob"
388 },
389 "hvuart": {
390 "name": "hvuart",
391 "p_state_clk_gate_min": 2,
392 "pio": {
393 "peer": "system.iobus.master[13]",
394 "role": "SLAVE"
395 },
396 "p_state_clk_gate_bins": 20,
397 "cxx_class": "Uart8250",
398 "pio_latency": 200,
399 "clk_domain": "system.clk_domain",
394 "system": "system",
395 "platform": "system.t1000",
396 "eventq_index": 0,
397 "default_p_state": "UNDEFINED",
398 "p_state_clk_gate_max": 2000000000,
399 "path": "system.t1000.iob",
400 "type": "Iob"
401 },
402 "hvuart": {
403 "name": "hvuart",
404 "p_state_clk_gate_min": 2,
405 "pio": {
406 "peer": "system.iobus.master[13]",
407 "role": "SLAVE"
408 },
409 "p_state_clk_gate_bins": 20,
410 "cxx_class": "Uart8250",
411 "pio_latency": 200,
412 "clk_domain": "system.clk_domain",
413 "power_model": null,
400 "system": "system",
401 "terminal": "system.t1000.hterm",
402 "platform": "system.t1000",
403 "eventq_index": 0,
404 "default_p_state": "UNDEFINED",
405 "p_state_clk_gate_max": 2000000000,
406 "path": "system.t1000.hvuart",
407 "pio_addr": 1099255955456,

--- 14 unchanged lines hidden (view full) ---

422 "warn_access": "",
423 "pio_latency": 200,
424 "system": "system",
425 "eventq_index": 0,
426 "default_p_state": "UNDEFINED",
427 "p_state_clk_gate_max": 2000000000,
428 "type": "IsaFake",
429 "p_state_clk_gate_min": 2,
414 "system": "system",
415 "terminal": "system.t1000.hterm",
416 "platform": "system.t1000",
417 "eventq_index": 0,
418 "default_p_state": "UNDEFINED",
419 "p_state_clk_gate_max": 2000000000,
420 "path": "system.t1000.hvuart",
421 "pio_addr": 1099255955456,

--- 14 unchanged lines hidden (view full) ---

436 "warn_access": "",
437 "pio_latency": 200,
438 "system": "system",
439 "eventq_index": 0,
440 "default_p_state": "UNDEFINED",
441 "p_state_clk_gate_max": 2000000000,
442 "type": "IsaFake",
443 "p_state_clk_gate_min": 2,
444 "power_model": null,
430 "ret_data32": 4294967295,
431 "path": "system.t1000.fake_l2esr_3",
432 "ret_data16": 65535,
433 "ret_data8": 255,
434 "name": "fake_l2esr_3",
435 "ret_bad_addr": false,
436 "pio_size": 8,
437 "p_state_clk_gate_bins": 20

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450 "warn_access": "",
451 "pio_latency": 200,
452 "system": "system",
453 "eventq_index": 0,
454 "default_p_state": "UNDEFINED",
455 "p_state_clk_gate_max": 2000000000,
456 "type": "IsaFake",
457 "p_state_clk_gate_min": 2,
445 "ret_data32": 4294967295,
446 "path": "system.t1000.fake_l2esr_3",
447 "ret_data16": 65535,
448 "ret_data8": 255,
449 "name": "fake_l2esr_3",
450 "ret_bad_addr": false,
451 "pio_size": 8,
452 "p_state_clk_gate_bins": 20

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465 "warn_access": "",
466 "pio_latency": 200,
467 "system": "system",
468 "eventq_index": 0,
469 "default_p_state": "UNDEFINED",
470 "p_state_clk_gate_max": 2000000000,
471 "type": "IsaFake",
472 "p_state_clk_gate_min": 2,
473 "power_model": null,
458 "ret_data32": 4294967295,
459 "path": "system.t1000.fake_ssi",
460 "ret_data16": 65535,
461 "ret_data8": 255,
462 "name": "fake_ssi",
463 "ret_bad_addr": false,
464 "pio_size": 268435456,
465 "p_state_clk_gate_bins": 20

--- 12 unchanged lines hidden (view full) ---

478 "warn_access": "",
479 "pio_latency": 200,
480 "system": "system",
481 "eventq_index": 0,
482 "default_p_state": "UNDEFINED",
483 "p_state_clk_gate_max": 2000000000,
484 "type": "IsaFake",
485 "p_state_clk_gate_min": 2,
474 "ret_data32": 4294967295,
475 "path": "system.t1000.fake_ssi",
476 "ret_data16": 65535,
477 "ret_data8": 255,
478 "name": "fake_ssi",
479 "ret_bad_addr": false,
480 "pio_size": 268435456,
481 "p_state_clk_gate_bins": 20

--- 12 unchanged lines hidden (view full) ---

494 "warn_access": "",
495 "pio_latency": 200,
496 "system": "system",
497 "eventq_index": 0,
498 "default_p_state": "UNDEFINED",
499 "p_state_clk_gate_max": 2000000000,
500 "type": "IsaFake",
501 "p_state_clk_gate_min": 2,
502 "power_model": null,
486 "ret_data32": 4294967295,
487 "path": "system.t1000.fake_l2esr_1",
488 "ret_data16": 65535,
489 "ret_data8": 255,
490 "name": "fake_l2esr_1",
491 "ret_bad_addr": false,
492 "pio_size": 8,
493 "p_state_clk_gate_bins": 20

--- 12 unchanged lines hidden (view full) ---

506 "warn_access": "",
507 "pio_latency": 200,
508 "system": "system",
509 "eventq_index": 0,
510 "default_p_state": "UNDEFINED",
511 "p_state_clk_gate_max": 2000000000,
512 "type": "IsaFake",
513 "p_state_clk_gate_min": 2,
503 "ret_data32": 4294967295,
504 "path": "system.t1000.fake_l2esr_1",
505 "ret_data16": 65535,
506 "ret_data8": 255,
507 "name": "fake_l2esr_1",
508 "ret_bad_addr": false,
509 "pio_size": 8,
510 "p_state_clk_gate_bins": 20

--- 12 unchanged lines hidden (view full) ---

523 "warn_access": "",
524 "pio_latency": 200,
525 "system": "system",
526 "eventq_index": 0,
527 "default_p_state": "UNDEFINED",
528 "p_state_clk_gate_max": 2000000000,
529 "type": "IsaFake",
530 "p_state_clk_gate_min": 2,
531 "power_model": null,
514 "ret_data32": 4294967295,
515 "path": "system.t1000.fake_l2esr_4",
516 "ret_data16": 65535,
517 "ret_data8": 255,
518 "name": "fake_l2esr_4",
519 "ret_bad_addr": false,
520 "pio_size": 8,
521 "p_state_clk_gate_bins": 20

--- 12 unchanged lines hidden (view full) ---

534 "warn_access": "",
535 "pio_latency": 200,
536 "system": "system",
537 "eventq_index": 0,
538 "default_p_state": "UNDEFINED",
539 "p_state_clk_gate_max": 2000000000,
540 "type": "IsaFake",
541 "p_state_clk_gate_min": 2,
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--- 12 unchanged lines hidden (view full) ---

552 "warn_access": "",
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--- 30 unchanged lines hidden (view full) ---

580 "range": "133445976064:133445984255",
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561 "ret_data32": 4294967295,
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564 "ret_data8": 255,
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--- 30 unchanged lines hidden (view full) ---

599 "range": "133445976064:133445984255",
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591 "cxx_class": "SimpleMemory",
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593 "path": "system.partition_desc",
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--- 20 unchanged lines hidden (view full) ---

616 "range": "133446500352:133446508543",
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611 "cxx_class": "SimpleMemory",
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613 "path": "system.partition_desc",
614 "null": false,
615 "type": "SimpleMemory",

--- 20 unchanged lines hidden (view full) ---

636 "range": "133446500352:133446508543",
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629 "path": "system.hypervisor_desc",
630 "null": false,
631 "type": "SimpleMemory",

--- 22 unchanged lines hidden (view full) ---

654 "warn_access": "",
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--- 22 unchanged lines hidden (view full) ---

675 "warn_access": "",
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666 "name": "badaddr_responder",
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668 "pio_size": 8,
669 "p_state_clk_gate_bins": 20

--- 25 unchanged lines hidden (view full) ---

695 "system.system_port",
696 "system.cpu.icache_port",
697 "system.cpu.dcache_port"
698 ],
699 "role": "SLAVE"
700 },
701 "p_state_clk_gate_min": 2,
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684 "ret_data32": 4294967295,
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690 "pio_size": 8,
691 "p_state_clk_gate_bins": 20

--- 25 unchanged lines hidden (view full) ---

717 "system.system_port",
718 "system.cpu.icache_port",
719 "system.cpu.dcache_port"
720 ],
721 "role": "SLAVE"
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725 "power_model": null,
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708 "role": "MASTER"
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713 "nvram": {
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726 "path": "system.membus",
727 "snoop_response_latency": 4,
728 "name": "membus",
729 "default": {
730 "peer": "system.membus.badaddr_responder.pio",
731 "role": "MASTER"
732 },
733 "p_state_clk_gate_bins": 20,
734 "use_default_range": false
735 },
736 "nvram": {
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740 "p_state_clk_gate_min": 2,
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744 "clk_domain": "system.clk_domain",
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722 "latency_var": 0,
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724 "conf_table_reported": true,
725 "cxx_class": "SimpleMemory",
726 "p_state_clk_gate_max": 2000000000,
727 "path": "system.nvram",
728 "null": false,
729 "type": "SimpleMemory",

--- 41 unchanged lines hidden (view full) ---

771 "range": "1048576:68157439",
772 "latency": 60,
773 "name": "physmem0",
774 "p_state_clk_gate_min": 2,
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777 "default_p_state": "UNDEFINED",
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749 "cxx_class": "SimpleMemory",
750 "p_state_clk_gate_max": 2000000000,
751 "path": "system.nvram",
752 "null": false,
753 "type": "SimpleMemory",

--- 41 unchanged lines hidden (view full) ---

795 "range": "1048576:68157439",
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783 "p_state_clk_gate_max": 2000000000,
784 "path": "system.physmem0",
785 "null": false,
786 "type": "SimpleMemory",

--- 7 unchanged lines hidden (view full) ---

794 "range": "2147483648:2415919103",
795 "latency": 60,
796 "name": "physmem1",
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809 "path": "system.physmem0",
810 "null": false,
811 "type": "SimpleMemory",

--- 7 unchanged lines hidden (view full) ---

819 "range": "2147483648:2415919103",
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821 "name": "physmem1",
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807 "path": "system.physmem1",
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810 "port": {
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812 "role": "SLAVE"
813 },
814 "in_addr_map": true
815 }
816 ],
828 "latency_var": 0,
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830 "conf_table_reported": true,
831 "cxx_class": "SimpleMemory",
832 "p_state_clk_gate_max": 2000000000,
833 "path": "system.physmem1",
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836 "port": {
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838 "role": "SLAVE"
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840 "in_addr_map": true
841 }
842 ],
843 "power_model": null,
817 "work_cpus_ckpt_count": 0,
818 "thermal_components": [],
819 "path": "system",
820 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
821 "cpu_clk_domain": {
822 "name": "cpu_clk_domain",
823 "clock": [
824 2

--- 57 unchanged lines hidden (view full) ---

882 "cxx_class": "SparcISA::Interrupts"
883 }
884 ],
885 "dcache_port": {
886 "peer": "system.membus.slave[2]",
887 "role": "MASTER"
888 },
889 "socket_id": 0,
844 "work_cpus_ckpt_count": 0,
845 "thermal_components": [],
846 "path": "system",
847 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
848 "cpu_clk_domain": {
849 "name": "cpu_clk_domain",
850 "clock": [
851 2

--- 57 unchanged lines hidden (view full) ---

909 "cxx_class": "SparcISA::Interrupts"
910 }
911 ],
912 "dcache_port": {
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894 "workload": [],
895 "name": "cpu",
896 "dtb": {
897 "name": "dtb",

--- 58 unchanged lines hidden (view full) ---

956 "path": "system.disk0.image",
957 "image_file": "",
958 "type": "CowDiskImage",
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960 },
961 "cxx_class": "MmDisk",
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922 "workload": [],
923 "name": "cpu",
924 "dtb": {
925 "name": "dtb",

--- 58 unchanged lines hidden (view full) ---

984 "path": "system.disk0.image",
985 "image_file": "",
986 "type": "CowDiskImage",
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989 "cxx_class": "MmDisk",
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991 "clk_domain": "system.clk_domain",
992 "power_model": null,
964 "system": "system",
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966 "default_p_state": "UNDEFINED",
967 "p_state_clk_gate_max": 2000000000,
968 "path": "system.disk0",
969 "pio_addr": 134217728000,
970 "type": "MmDisk"
971 },

--- 17 unchanged lines hidden --- 		993 "system": "system",
994 "eventq_index": 0,
995 "default_p_state": "UNDEFINED",
996 "p_state_clk_gate_max": 2000000000,
997 "path": "system.disk0",
998 "pio_addr": 134217728000,
999 "type": "MmDisk"
1000 },

--- 17 unchanged lines hidden ---