config.json (10315:9e02c14446bb) | config.json (10411:d96740732a61) |
---|---|
1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { | 1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { |
5 "bridge": { 6 "slave": { 7 "peer": "system.membus.master[2]", 8 "role": "SLAVE" 9 }, 10 "name": "bridge", 11 "req_size": 16, 12 "delay": 5.0000000000000004e-08, 13 "eventq_index": 0, 14 "master": { 15 "peer": "system.iobus.slave[0]", 16 "role": "MASTER" 17 }, 18 "cxx_class": "Bridge", 19 "path": "system.bridge", 20 "resp_size": 16, 21 "type": "Bridge" 22 }, | 5 "kernel": "", |
23 "kernel_addr_check": true, 24 "rom": { | 6 "kernel_addr_check": true, 7 "rom": { |
25 "latency": 3.0000000000000004e-08, | 8 "range": "1099243192320:1099251580927", 9 "latency": 60, |
26 "name": "rom", 27 "eventq_index": 0, | 10 "name": "rom", 11 "eventq_index": 0, |
28 "latency_var": 0.0, | 12 "clk_domain": "system.clk_domain", 13 "latency_var": 0, 14 "bandwidth": "0.000000", |
29 "conf_table_reported": true, 30 "cxx_class": "SimpleMemory", 31 "path": "system.rom", 32 "null": false, 33 "type": "SimpleMemory", 34 "port": { 35 "peer": "system.membus.master[3]", 36 "role": "SLAVE" 37 }, 38 "in_addr_map": true 39 }, | 15 "conf_table_reported": true, 16 "cxx_class": "SimpleMemory", 17 "path": "system.rom", 18 "null": false, 19 "type": "SimpleMemory", 20 "port": { 21 "peer": "system.membus.master[3]", 22 "role": "SLAVE" 23 }, 24 "in_addr_map": true 25 }, |
40 "membus": { | 26 "bridge": { 27 "ranges": [ 28 "133412421632:133412421639", 29 "134217728000:554050781183", 30 "644245094400:652835028991", 31 "725849473024:1095485095935", 32 "1099255955456:1099255955463" 33 ], |
41 "slave": { | 34 "slave": { |
42 "peer": [ 43 "system.system_port", 44 "system.cpu.icache_port", 45 "system.cpu.dcache_port" 46 ], | 35 "peer": "system.membus.master[2]", |
47 "role": "SLAVE" 48 }, | 36 "role": "SLAVE" 37 }, |
49 "name": "membus", 50 "badaddr_responder": { 51 "ret_data8": 255, 52 "name": "badaddr_responder", 53 "pio": { 54 "peer": "system.membus.default", 55 "role": "SLAVE" 56 }, 57 "ret_bad_addr": true, 58 "pio_latency": 1.0000000000000001e-07, 59 "fake_mem": false, 60 "pio_size": 8, 61 "ret_data32": 4294967295, 62 "eventq_index": 0, 63 "update_data": false, 64 "ret_data64": 18446744073709551615, 65 "cxx_class": "IsaFake", 66 "path": "system.membus.badaddr_responder", 67 "pio_addr": 0, 68 "type": "IsaFake", 69 "ret_data16": 65535 70 }, 71 "default": { 72 "peer": "system.membus.badaddr_responder.pio", 73 "role": "MASTER" 74 }, 75 "header_cycles": 1, 76 "width": 8, | 38 "name": "bridge", 39 "req_size": 16, 40 "clk_domain": "system.clk_domain", 41 "delay": 100, |
77 "eventq_index": 0, 78 "master": { | 42 "eventq_index": 0, 43 "master": { |
79 "peer": [ 80 "system.t1000.iob.pio", 81 "system.t1000.htod.pio", 82 "system.bridge.slave", 83 "system.rom.port", 84 "system.nvram.port", 85 "system.hypervisor_desc.port", 86 "system.partition_desc.port", 87 "system.physmem0.port", 88 "system.physmem1.port" 89 ], | 44 "peer": "system.iobus.slave[0]", |
90 "role": "MASTER" 91 }, | 45 "role": "MASTER" 46 }, |
92 "cxx_class": "CoherentBus", 93 "path": "system.membus", 94 "type": "CoherentBus", 95 "use_default_range": false | 47 "cxx_class": "Bridge", 48 "path": "system.bridge", 49 "resp_size": 16, 50 "type": "Bridge" |
96 }, 97 "iobus": { 98 "slave": { 99 "peer": [ 100 "system.bridge.master" 101 ], 102 "role": "SLAVE" 103 }, 104 "name": "iobus", | 51 }, 52 "iobus": { 53 "slave": { 54 "peer": [ 55 "system.bridge.master" 56 ], 57 "role": "SLAVE" 58 }, 59 "name": "iobus", |
60 "clk_domain": "system.clk_domain", |
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105 "header_cycles": 1, 106 "width": 8, 107 "eventq_index": 0, 108 "master": { 109 "peer": [ 110 "system.t1000.fake_clk.pio", 111 "system.t1000.fake_membnks.pio", 112 "system.t1000.fake_l2_1.pio", --- 7 unchanged lines hidden (view full) --- 120 "system.t1000.fake_ssi.pio", 121 "system.t1000.fake_jbi.pio", 122 "system.t1000.puart0.pio", 123 "system.t1000.hvuart.pio", 124 "system.disk0.pio" 125 ], 126 "role": "MASTER" 127 }, | 61 "header_cycles": 1, 62 "width": 8, 63 "eventq_index": 0, 64 "master": { 65 "peer": [ 66 "system.t1000.fake_clk.pio", 67 "system.t1000.fake_membnks.pio", 68 "system.t1000.fake_l2_1.pio", --- 7 unchanged lines hidden (view full) --- 76 "system.t1000.fake_ssi.pio", 77 "system.t1000.fake_jbi.pio", 78 "system.t1000.puart0.pio", 79 "system.t1000.hvuart.pio", 80 "system.disk0.pio" 81 ], 82 "role": "MASTER" 83 }, |
128 "cxx_class": "NoncoherentBus", | 84 "cxx_class": "NoncoherentXBar", |
129 "path": "system.iobus", | 85 "path": "system.iobus", |
130 "type": "NoncoherentBus", | 86 "type": "NoncoherentXBar", |
131 "use_default_range": false 132 }, 133 "t1000": { 134 "htod": { 135 "name": "htod", 136 "pio": { 137 "peer": "system.membus.master[1]", 138 "role": "SLAVE" 139 }, 140 "time": "Thu Jan 1 00:00:00 2009", | 87 "use_default_range": false 88 }, 89 "t1000": { 90 "htod": { 91 "name": "htod", 92 "pio": { 93 "peer": "system.membus.master[1]", 94 "role": "SLAVE" 95 }, 96 "time": "Thu Jan 1 00:00:00 2009", |
141 "pio_latency": 1.0000000000000001e-07, | 97 "pio_latency": 200, 98 "clk_domain": "system.clk_domain", 99 "system": "system", |
142 "eventq_index": 0, 143 "cxx_class": "DumbTOD", 144 "path": "system.t1000.htod", 145 "pio_addr": 1099255906296, 146 "type": "DumbTOD" 147 }, 148 "puart0": { 149 "name": "puart0", 150 "pio": { 151 "peer": "system.iobus.master[12]", 152 "role": "SLAVE" 153 }, | 100 "eventq_index": 0, 101 "cxx_class": "DumbTOD", 102 "path": "system.t1000.htod", 103 "pio_addr": 1099255906296, 104 "type": "DumbTOD" 105 }, 106 "puart0": { 107 "name": "puart0", 108 "pio": { 109 "peer": "system.iobus.master[12]", 110 "role": "SLAVE" 111 }, |
154 "pio_latency": 1.0000000000000001e-07, | 112 "pio_latency": 200, 113 "clk_domain": "system.clk_domain", 114 "system": "system", 115 "terminal": "system.t1000.pterm", 116 "platform": "system.t1000", |
155 "eventq_index": 0, 156 "cxx_class": "Uart8250", 157 "path": "system.t1000.puart0", 158 "pio_addr": 133412421632, 159 "type": "Uart8250" 160 }, 161 "fake_membnks": { | 117 "eventq_index": 0, 118 "cxx_class": "Uart8250", 119 "path": "system.t1000.puart0", 120 "pio_addr": 133412421632, 121 "type": "Uart8250" 122 }, 123 "fake_membnks": { |
124 "system": "system", |
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162 "ret_data8": 255, 163 "name": "fake_membnks", | 125 "ret_data8": 255, 126 "name": "fake_membnks", |
127 "warn_access": "", |
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164 "pio": { 165 "peer": "system.iobus.master[1]", 166 "role": "SLAVE" 167 }, 168 "ret_bad_addr": false, | 128 "pio": { 129 "peer": "system.iobus.master[1]", 130 "role": "SLAVE" 131 }, 132 "ret_bad_addr": false, |
169 "pio_latency": 1.0000000000000001e-07, | 133 "pio_latency": 200, 134 "clk_domain": "system.clk_domain", |
170 "fake_mem": false, 171 "pio_size": 16384, 172 "ret_data32": 4294967295, 173 "eventq_index": 0, 174 "update_data": false, 175 "ret_data64": 0, 176 "cxx_class": "IsaFake", 177 "path": "system.t1000.fake_membnks", 178 "pio_addr": 648540061696, 179 "type": "IsaFake", 180 "ret_data16": 65535 181 }, 182 "cxx_class": "T1000", 183 "fake_jbi": { | 135 "fake_mem": false, 136 "pio_size": 16384, 137 "ret_data32": 4294967295, 138 "eventq_index": 0, 139 "update_data": false, 140 "ret_data64": 0, 141 "cxx_class": "IsaFake", 142 "path": "system.t1000.fake_membnks", 143 "pio_addr": 648540061696, 144 "type": "IsaFake", 145 "ret_data16": 65535 146 }, 147 "cxx_class": "T1000", 148 "fake_jbi": { |
149 "system": "system", |
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184 "ret_data8": 255, 185 "name": "fake_jbi", | 150 "ret_data8": 255, 151 "name": "fake_jbi", |
152 "warn_access": "", |
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186 "pio": { 187 "peer": "system.iobus.master[11]", 188 "role": "SLAVE" 189 }, 190 "ret_bad_addr": false, | 153 "pio": { 154 "peer": "system.iobus.master[11]", 155 "role": "SLAVE" 156 }, 157 "ret_bad_addr": false, |
191 "pio_latency": 1.0000000000000001e-07, | 158 "pio_latency": 200, 159 "clk_domain": "system.clk_domain", |
192 "fake_mem": false, 193 "pio_size": 4294967296, 194 "ret_data32": 4294967295, 195 "eventq_index": 0, 196 "update_data": false, 197 "ret_data64": 18446744073709551615, 198 "cxx_class": "IsaFake", 199 "path": "system.t1000.fake_jbi", 200 "pio_addr": 549755813888, 201 "type": "IsaFake", 202 "ret_data16": 65535 203 }, | 160 "fake_mem": false, 161 "pio_size": 4294967296, 162 "ret_data32": 4294967295, 163 "eventq_index": 0, 164 "update_data": false, 165 "ret_data64": 18446744073709551615, 166 "cxx_class": "IsaFake", 167 "path": "system.t1000.fake_jbi", 168 "pio_addr": 549755813888, 169 "type": "IsaFake", 170 "ret_data16": 65535 171 }, |
172 "intrctrl": "system.intrctrl", |
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204 "fake_l2esr_2": { | 173 "fake_l2esr_2": { |
174 "system": "system", |
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205 "ret_data8": 255, 206 "name": "fake_l2esr_2", | 175 "ret_data8": 255, 176 "name": "fake_l2esr_2", |
177 "warn_access": "", |
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207 "pio": { 208 "peer": "system.iobus.master[7]", 209 "role": "SLAVE" 210 }, 211 "ret_bad_addr": false, | 178 "pio": { 179 "peer": "system.iobus.master[7]", 180 "role": "SLAVE" 181 }, 182 "ret_bad_addr": false, |
212 "pio_latency": 1.0000000000000001e-07, | 183 "pio_latency": 200, 184 "clk_domain": "system.clk_domain", |
213 "fake_mem": false, 214 "pio_size": 8, 215 "ret_data32": 4294967295, 216 "eventq_index": 0, 217 "update_data": true, 218 "ret_data64": 0, 219 "cxx_class": "IsaFake", 220 "path": "system.t1000.fake_l2esr_2", 221 "pio_addr": 734439407680, 222 "type": "IsaFake", 223 "ret_data16": 65535 224 }, | 185 "fake_mem": false, 186 "pio_size": 8, 187 "ret_data32": 4294967295, 188 "eventq_index": 0, 189 "update_data": true, 190 "ret_data64": 0, 191 "cxx_class": "IsaFake", 192 "path": "system.t1000.fake_l2esr_2", 193 "pio_addr": 734439407680, 194 "type": "IsaFake", 195 "ret_data16": 65535 196 }, |
197 "system": "system", |
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225 "eventq_index": 0, 226 "hterm": { 227 "name": "hterm", 228 "output": true, 229 "number": 0, | 198 "eventq_index": 0, 199 "hterm": { 200 "name": "hterm", 201 "output": true, 202 "number": 0, |
203 "intr_control": "system.intrctrl", |
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230 "eventq_index": 0, 231 "cxx_class": "Terminal", 232 "path": "system.t1000.hterm", 233 "type": "Terminal", 234 "port": 3456 235 }, 236 "type": "T1000", 237 "fake_l2_4": { | 204 "eventq_index": 0, 205 "cxx_class": "Terminal", 206 "path": "system.t1000.hterm", 207 "type": "Terminal", 208 "port": 3456 209 }, 210 "type": "T1000", 211 "fake_l2_4": { |
212 "system": "system", |
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238 "ret_data8": 255, 239 "name": "fake_l2_4", | 213 "ret_data8": 255, 214 "name": "fake_l2_4", |
215 "warn_access": "", |
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240 "pio": { 241 "peer": "system.iobus.master[5]", 242 "role": "SLAVE" 243 }, 244 "ret_bad_addr": false, | 216 "pio": { 217 "peer": "system.iobus.master[5]", 218 "role": "SLAVE" 219 }, 220 "ret_bad_addr": false, |
245 "pio_latency": 1.0000000000000001e-07, | 221 "pio_latency": 200, 222 "clk_domain": "system.clk_domain", |
246 "fake_mem": false, 247 "pio_size": 8, 248 "ret_data32": 4294967295, 249 "eventq_index": 0, 250 "update_data": true, 251 "ret_data64": 1, 252 "cxx_class": "IsaFake", 253 "path": "system.t1000.fake_l2_4", 254 "pio_addr": 725849473216, 255 "type": "IsaFake", 256 "ret_data16": 65535 257 }, 258 "fake_l2_1": { | 223 "fake_mem": false, 224 "pio_size": 8, 225 "ret_data32": 4294967295, 226 "eventq_index": 0, 227 "update_data": true, 228 "ret_data64": 1, 229 "cxx_class": "IsaFake", 230 "path": "system.t1000.fake_l2_4", 231 "pio_addr": 725849473216, 232 "type": "IsaFake", 233 "ret_data16": 65535 234 }, 235 "fake_l2_1": { |
236 "system": "system", |
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259 "ret_data8": 255, 260 "name": "fake_l2_1", | 237 "ret_data8": 255, 238 "name": "fake_l2_1", |
239 "warn_access": "", |
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261 "pio": { 262 "peer": "system.iobus.master[2]", 263 "role": "SLAVE" 264 }, 265 "ret_bad_addr": false, | 240 "pio": { 241 "peer": "system.iobus.master[2]", 242 "role": "SLAVE" 243 }, 244 "ret_bad_addr": false, |
266 "pio_latency": 1.0000000000000001e-07, | 245 "pio_latency": 200, 246 "clk_domain": "system.clk_domain", |
267 "fake_mem": false, 268 "pio_size": 8, 269 "ret_data32": 4294967295, 270 "eventq_index": 0, 271 "update_data": true, 272 "ret_data64": 1, 273 "cxx_class": "IsaFake", 274 "path": "system.t1000.fake_l2_1", 275 "pio_addr": 725849473024, 276 "type": "IsaFake", 277 "ret_data16": 65535 278 }, 279 "fake_l2_2": { | 247 "fake_mem": false, 248 "pio_size": 8, 249 "ret_data32": 4294967295, 250 "eventq_index": 0, 251 "update_data": true, 252 "ret_data64": 1, 253 "cxx_class": "IsaFake", 254 "path": "system.t1000.fake_l2_1", 255 "pio_addr": 725849473024, 256 "type": "IsaFake", 257 "ret_data16": 65535 258 }, 259 "fake_l2_2": { |
260 "system": "system", |
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280 "ret_data8": 255, 281 "name": "fake_l2_2", | 261 "ret_data8": 255, 262 "name": "fake_l2_2", |
263 "warn_access": "", |
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282 "pio": { 283 "peer": "system.iobus.master[3]", 284 "role": "SLAVE" 285 }, 286 "ret_bad_addr": false, | 264 "pio": { 265 "peer": "system.iobus.master[3]", 266 "role": "SLAVE" 267 }, 268 "ret_bad_addr": false, |
287 "pio_latency": 1.0000000000000001e-07, | 269 "pio_latency": 200, 270 "clk_domain": "system.clk_domain", |
288 "fake_mem": false, 289 "pio_size": 8, 290 "ret_data32": 4294967295, 291 "eventq_index": 0, 292 "update_data": true, 293 "ret_data64": 1, 294 "cxx_class": "IsaFake", 295 "path": "system.t1000.fake_l2_2", 296 "pio_addr": 725849473088, 297 "type": "IsaFake", 298 "ret_data16": 65535 299 }, 300 "fake_l2_3": { | 271 "fake_mem": false, 272 "pio_size": 8, 273 "ret_data32": 4294967295, 274 "eventq_index": 0, 275 "update_data": true, 276 "ret_data64": 1, 277 "cxx_class": "IsaFake", 278 "path": "system.t1000.fake_l2_2", 279 "pio_addr": 725849473088, 280 "type": "IsaFake", 281 "ret_data16": 65535 282 }, 283 "fake_l2_3": { |
284 "system": "system", |
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301 "ret_data8": 255, 302 "name": "fake_l2_3", | 285 "ret_data8": 255, 286 "name": "fake_l2_3", |
287 "warn_access": "", |
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303 "pio": { 304 "peer": "system.iobus.master[4]", 305 "role": "SLAVE" 306 }, 307 "ret_bad_addr": false, | 288 "pio": { 289 "peer": "system.iobus.master[4]", 290 "role": "SLAVE" 291 }, 292 "ret_bad_addr": false, |
308 "pio_latency": 1.0000000000000001e-07, | 293 "pio_latency": 200, 294 "clk_domain": "system.clk_domain", |
309 "fake_mem": false, 310 "pio_size": 8, 311 "ret_data32": 4294967295, 312 "eventq_index": 0, 313 "update_data": true, 314 "ret_data64": 1, 315 "cxx_class": "IsaFake", 316 "path": "system.t1000.fake_l2_3", 317 "pio_addr": 725849473152, 318 "type": "IsaFake", 319 "ret_data16": 65535 320 }, 321 "pterm": { 322 "name": "pterm", 323 "output": true, 324 "number": 0, | 295 "fake_mem": false, 296 "pio_size": 8, 297 "ret_data32": 4294967295, 298 "eventq_index": 0, 299 "update_data": true, 300 "ret_data64": 1, 301 "cxx_class": "IsaFake", 302 "path": "system.t1000.fake_l2_3", 303 "pio_addr": 725849473152, 304 "type": "IsaFake", 305 "ret_data16": 65535 306 }, 307 "pterm": { 308 "name": "pterm", 309 "output": true, 310 "number": 0, |
311 "intr_control": "system.intrctrl", |
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325 "eventq_index": 0, 326 "cxx_class": "Terminal", 327 "path": "system.t1000.pterm", 328 "type": "Terminal", 329 "port": 3456 330 }, 331 "path": "system.t1000", 332 "iob": { 333 "name": "iob", 334 "pio": { 335 "peer": "system.membus.master[0]", 336 "role": "SLAVE" 337 }, | 312 "eventq_index": 0, 313 "cxx_class": "Terminal", 314 "path": "system.t1000.pterm", 315 "type": "Terminal", 316 "port": 3456 317 }, 318 "path": "system.t1000", 319 "iob": { 320 "name": "iob", 321 "pio": { 322 "peer": "system.membus.master[0]", 323 "role": "SLAVE" 324 }, |
338 "pio_latency": 1e-09, | 325 "pio_latency": 2, 326 "clk_domain": "system.clk_domain", 327 "system": "system", 328 "platform": "system.t1000", |
339 "eventq_index": 0, 340 "cxx_class": "Iob", 341 "path": "system.t1000.iob", 342 "type": "Iob" 343 }, 344 "hvuart": { 345 "name": "hvuart", 346 "pio": { 347 "peer": "system.iobus.master[13]", 348 "role": "SLAVE" 349 }, | 329 "eventq_index": 0, 330 "cxx_class": "Iob", 331 "path": "system.t1000.iob", 332 "type": "Iob" 333 }, 334 "hvuart": { 335 "name": "hvuart", 336 "pio": { 337 "peer": "system.iobus.master[13]", 338 "role": "SLAVE" 339 }, |
350 "pio_latency": 1.0000000000000001e-07, | 340 "pio_latency": 200, 341 "clk_domain": "system.clk_domain", 342 "system": "system", 343 "terminal": "system.t1000.hterm", 344 "platform": "system.t1000", |
351 "eventq_index": 0, 352 "cxx_class": "Uart8250", 353 "path": "system.t1000.hvuart", 354 "pio_addr": 1099255955456, 355 "type": "Uart8250" 356 }, 357 "name": "t1000", 358 "fake_l2esr_3": { | 345 "eventq_index": 0, 346 "cxx_class": "Uart8250", 347 "path": "system.t1000.hvuart", 348 "pio_addr": 1099255955456, 349 "type": "Uart8250" 350 }, 351 "name": "t1000", 352 "fake_l2esr_3": { |
353 "system": "system", |
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359 "ret_data8": 255, 360 "name": "fake_l2esr_3", | 354 "ret_data8": 255, 355 "name": "fake_l2esr_3", |
356 "warn_access": "", |
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361 "pio": { 362 "peer": "system.iobus.master[8]", 363 "role": "SLAVE" 364 }, 365 "ret_bad_addr": false, | 357 "pio": { 358 "peer": "system.iobus.master[8]", 359 "role": "SLAVE" 360 }, 361 "ret_bad_addr": false, |
366 "pio_latency": 1.0000000000000001e-07, | 362 "pio_latency": 200, 363 "clk_domain": "system.clk_domain", |
367 "fake_mem": false, 368 "pio_size": 8, 369 "ret_data32": 4294967295, 370 "eventq_index": 0, 371 "update_data": true, 372 "ret_data64": 0, 373 "cxx_class": "IsaFake", 374 "path": "system.t1000.fake_l2esr_3", 375 "pio_addr": 734439407744, 376 "type": "IsaFake", 377 "ret_data16": 65535 378 }, 379 "fake_ssi": { | 364 "fake_mem": false, 365 "pio_size": 8, 366 "ret_data32": 4294967295, 367 "eventq_index": 0, 368 "update_data": true, 369 "ret_data64": 0, 370 "cxx_class": "IsaFake", 371 "path": "system.t1000.fake_l2esr_3", 372 "pio_addr": 734439407744, 373 "type": "IsaFake", 374 "ret_data16": 65535 375 }, 376 "fake_ssi": { |
377 "system": "system", |
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380 "ret_data8": 255, 381 "name": "fake_ssi", | 378 "ret_data8": 255, 379 "name": "fake_ssi", |
380 "warn_access": "", |
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382 "pio": { 383 "peer": "system.iobus.master[10]", 384 "role": "SLAVE" 385 }, 386 "ret_bad_addr": false, | 381 "pio": { 382 "peer": "system.iobus.master[10]", 383 "role": "SLAVE" 384 }, 385 "ret_bad_addr": false, |
387 "pio_latency": 1.0000000000000001e-07, | 386 "pio_latency": 200, 387 "clk_domain": "system.clk_domain", |
388 "fake_mem": false, 389 "pio_size": 268435456, 390 "ret_data32": 4294967295, 391 "eventq_index": 0, 392 "update_data": false, 393 "ret_data64": 18446744073709551615, 394 "cxx_class": "IsaFake", 395 "path": "system.t1000.fake_ssi", 396 "pio_addr": 1095216660480, 397 "type": "IsaFake", 398 "ret_data16": 65535 399 }, 400 "fake_l2esr_1": { | 388 "fake_mem": false, 389 "pio_size": 268435456, 390 "ret_data32": 4294967295, 391 "eventq_index": 0, 392 "update_data": false, 393 "ret_data64": 18446744073709551615, 394 "cxx_class": "IsaFake", 395 "path": "system.t1000.fake_ssi", 396 "pio_addr": 1095216660480, 397 "type": "IsaFake", 398 "ret_data16": 65535 399 }, 400 "fake_l2esr_1": { |
401 "system": "system", |
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401 "ret_data8": 255, 402 "name": "fake_l2esr_1", | 402 "ret_data8": 255, 403 "name": "fake_l2esr_1", |
404 "warn_access": "", |
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403 "pio": { 404 "peer": "system.iobus.master[6]", 405 "role": "SLAVE" 406 }, 407 "ret_bad_addr": false, | 405 "pio": { 406 "peer": "system.iobus.master[6]", 407 "role": "SLAVE" 408 }, 409 "ret_bad_addr": false, |
408 "pio_latency": 1.0000000000000001e-07, | 410 "pio_latency": 200, 411 "clk_domain": "system.clk_domain", |
409 "fake_mem": false, 410 "pio_size": 8, 411 "ret_data32": 4294967295, 412 "eventq_index": 0, 413 "update_data": true, 414 "ret_data64": 0, 415 "cxx_class": "IsaFake", 416 "path": "system.t1000.fake_l2esr_1", 417 "pio_addr": 734439407616, 418 "type": "IsaFake", 419 "ret_data16": 65535 420 }, 421 "fake_l2esr_4": { | 412 "fake_mem": false, 413 "pio_size": 8, 414 "ret_data32": 4294967295, 415 "eventq_index": 0, 416 "update_data": true, 417 "ret_data64": 0, 418 "cxx_class": "IsaFake", 419 "path": "system.t1000.fake_l2esr_1", 420 "pio_addr": 734439407616, 421 "type": "IsaFake", 422 "ret_data16": 65535 423 }, 424 "fake_l2esr_4": { |
425 "system": "system", |
|
422 "ret_data8": 255, 423 "name": "fake_l2esr_4", | 426 "ret_data8": 255, 427 "name": "fake_l2esr_4", |
428 "warn_access": "", |
|
424 "pio": { 425 "peer": "system.iobus.master[9]", 426 "role": "SLAVE" 427 }, 428 "ret_bad_addr": false, | 429 "pio": { 430 "peer": "system.iobus.master[9]", 431 "role": "SLAVE" 432 }, 433 "ret_bad_addr": false, |
429 "pio_latency": 1.0000000000000001e-07, | 434 "pio_latency": 200, 435 "clk_domain": "system.clk_domain", |
430 "fake_mem": false, 431 "pio_size": 8, 432 "ret_data32": 4294967295, 433 "eventq_index": 0, 434 "update_data": true, 435 "ret_data64": 0, 436 "cxx_class": "IsaFake", 437 "path": "system.t1000.fake_l2esr_4", 438 "pio_addr": 734439407808, 439 "type": "IsaFake", 440 "ret_data16": 65535 441 }, 442 "fake_clk": { | 436 "fake_mem": false, 437 "pio_size": 8, 438 "ret_data32": 4294967295, 439 "eventq_index": 0, 440 "update_data": true, 441 "ret_data64": 0, 442 "cxx_class": "IsaFake", 443 "path": "system.t1000.fake_l2esr_4", 444 "pio_addr": 734439407808, 445 "type": "IsaFake", 446 "ret_data16": 65535 447 }, 448 "fake_clk": { |
449 "system": "system", |
|
443 "ret_data8": 255, 444 "name": "fake_clk", | 450 "ret_data8": 255, 451 "name": "fake_clk", |
452 "warn_access": "", |
|
445 "pio": { 446 "peer": "system.iobus.master[0]", 447 "role": "SLAVE" 448 }, 449 "ret_bad_addr": false, | 453 "pio": { 454 "peer": "system.iobus.master[0]", 455 "role": "SLAVE" 456 }, 457 "ret_bad_addr": false, |
450 "pio_latency": 1.0000000000000001e-07, | 458 "pio_latency": 200, 459 "clk_domain": "system.clk_domain", |
451 "fake_mem": false, 452 "pio_size": 4294967296, 453 "ret_data32": 4294967295, 454 "eventq_index": 0, 455 "update_data": false, 456 "ret_data64": 18446744073709551615, 457 "cxx_class": "IsaFake", 458 "path": "system.t1000.fake_clk", 459 "pio_addr": 644245094400, 460 "type": "IsaFake", 461 "ret_data16": 65535 462 } 463 }, | 460 "fake_mem": false, 461 "pio_size": 4294967296, 462 "ret_data32": 4294967295, 463 "eventq_index": 0, 464 "update_data": false, 465 "ret_data64": 18446744073709551615, 466 "cxx_class": "IsaFake", 467 "path": "system.t1000.fake_clk", 468 "pio_addr": 644245094400, 469 "type": "IsaFake", 470 "ret_data16": 65535 471 } 472 }, |
464 "partition_desc_addr": 133445976064, 465 "physmem": [ 466 { 467 "latency": 3.0000000000000004e-08, 468 "name": "physmem0", 469 "eventq_index": 0, 470 "latency_var": 0.0, 471 "conf_table_reported": true, 472 "cxx_class": "SimpleMemory", 473 "path": "system.physmem0", 474 "null": false, 475 "type": "SimpleMemory", 476 "port": { 477 "peer": "system.membus.master[7]", 478 "role": "SLAVE" 479 }, 480 "in_addr_map": true 481 }, 482 { 483 "latency": 3.0000000000000004e-08, 484 "name": "physmem1", 485 "eventq_index": 0, 486 "latency_var": 0.0, 487 "conf_table_reported": true, 488 "cxx_class": "SimpleMemory", 489 "path": "system.physmem1", 490 "null": false, 491 "type": "SimpleMemory", 492 "port": { 493 "peer": "system.membus.master[8]", 494 "role": "SLAVE" 495 }, 496 "in_addr_map": true 497 } 498 ], | 473 "symbolfile": "", 474 "readfile": "/z/stever/hg/gem5/tests/halt.sh", |
499 "hypervisor_addr": 1099243257856, | 475 "hypervisor_addr": 1099243257856, |
476 "mem_ranges": [ 477 "1048576:68157439", 478 "2147483648:2415919103" 479 ], |
|
500 "cxx_class": "SparcSystem", 501 "load_offset": 0, | 480 "cxx_class": "SparcSystem", 481 "load_offset": 0, |
482 "reset_bin": "/dist/m5/system/binaries/reset_new.bin", |
|
502 "openboot_addr": 1099243716608, 503 "work_end_ckpt_count": 0, 504 "nvram_addr": 133429198848, | 483 "openboot_addr": 1099243716608, 484 "work_end_ckpt_count": 0, 485 "nvram_addr": 133429198848, |
486 "memories": [ 487 "system.hypervisor_desc", 488 "system.physmem1", 489 "system.partition_desc", 490 "system.physmem0", 491 "system.rom", 492 "system.nvram" 493 ], |
|
505 "work_begin_ckpt_count": 0, 506 "partition_desc": { | 494 "work_begin_ckpt_count": 0, 495 "partition_desc": { |
507 "latency": 3.0000000000000004e-08, | 496 "range": "133445976064:133445984255", 497 "latency": 60, |
508 "name": "partition_desc", 509 "eventq_index": 0, | 498 "name": "partition_desc", 499 "eventq_index": 0, |
510 "latency_var": 0.0, | 500 "clk_domain": "system.clk_domain", 501 "latency_var": 0, 502 "bandwidth": "0.000000", |
511 "conf_table_reported": true, 512 "cxx_class": "SimpleMemory", 513 "path": "system.partition_desc", 514 "null": false, 515 "type": "SimpleMemory", 516 "port": { 517 "peer": "system.membus.master[6]", 518 "role": "SLAVE" 519 }, 520 "in_addr_map": true 521 }, 522 "clk_domain": { 523 "name": "clk_domain", | 503 "conf_table_reported": true, 504 "cxx_class": "SimpleMemory", 505 "path": "system.partition_desc", 506 "null": false, 507 "type": "SimpleMemory", 508 "port": { 509 "peer": "system.membus.master[6]", 510 "role": "SLAVE" 511 }, 512 "in_addr_map": true 513 }, 514 "clk_domain": { 515 "name": "clk_domain", |
516 "clock": [ 517 2 518 ], |
|
524 "init_perf_level": 0, | 519 "init_perf_level": 0, |
520 "voltage_domain": "system.voltage_domain", |
|
525 "eventq_index": 0, 526 "cxx_class": "SrcClockDomain", 527 "path": "system.clk_domain", 528 "type": "SrcClockDomain", 529 "domain_id": -1 530 }, 531 "hypervisor_desc": { | 521 "eventq_index": 0, 522 "cxx_class": "SrcClockDomain", 523 "path": "system.clk_domain", 524 "type": "SrcClockDomain", 525 "domain_id": -1 526 }, 527 "hypervisor_desc": { |
532 "latency": 3.0000000000000004e-08, | 528 "range": "133446500352:133446508543", 529 "latency": 60, |
533 "name": "hypervisor_desc", 534 "eventq_index": 0, | 530 "name": "hypervisor_desc", 531 "eventq_index": 0, |
535 "latency_var": 0.0, | 532 "clk_domain": "system.clk_domain", 533 "latency_var": 0, 534 "bandwidth": "0.000000", |
536 "conf_table_reported": true, 537 "cxx_class": "SimpleMemory", 538 "path": "system.hypervisor_desc", 539 "null": false, 540 "type": "SimpleMemory", 541 "port": { 542 "peer": "system.membus.master[5]", 543 "role": "SLAVE" 544 }, 545 "in_addr_map": true 546 }, | 535 "conf_table_reported": true, 536 "cxx_class": "SimpleMemory", 537 "path": "system.hypervisor_desc", 538 "null": false, 539 "type": "SimpleMemory", 540 "port": { 541 "peer": "system.membus.master[5]", 542 "role": "SLAVE" 543 }, 544 "in_addr_map": true 545 }, |
546 "membus": { 547 "default": { 548 "peer": "system.membus.badaddr_responder.pio", 549 "role": "MASTER" 550 }, 551 "slave": { 552 "peer": [ 553 "system.system_port", 554 "system.cpu.icache_port", 555 "system.cpu.dcache_port" 556 ], 557 "role": "SLAVE" 558 }, 559 "name": "membus", 560 "badaddr_responder": { 561 "system": "system", 562 "ret_data8": 255, 563 "name": "badaddr_responder", 564 "warn_access": "", 565 "pio": { 566 "peer": "system.membus.default", 567 "role": "SLAVE" 568 }, 569 "ret_bad_addr": true, 570 "pio_latency": 200, 571 "clk_domain": "system.clk_domain", 572 "fake_mem": false, 573 "pio_size": 8, 574 "ret_data32": 4294967295, 575 "eventq_index": 0, 576 "update_data": false, 577 "ret_data64": 18446744073709551615, 578 "cxx_class": "IsaFake", 579 "path": "system.membus.badaddr_responder", 580 "pio_addr": 0, 581 "type": "IsaFake", 582 "ret_data16": 65535 583 }, 584 "snoop_filter": null, 585 "clk_domain": "system.clk_domain", 586 "header_cycles": 1, 587 "system": "system", 588 "width": 8, 589 "eventq_index": 0, 590 "master": { 591 "peer": [ 592 "system.t1000.iob.pio", 593 "system.t1000.htod.pio", 594 "system.bridge.slave", 595 "system.rom.port", 596 "system.nvram.port", 597 "system.hypervisor_desc.port", 598 "system.partition_desc.port", 599 "system.physmem0.port", 600 "system.physmem1.port" 601 ], 602 "role": "MASTER" 603 }, 604 "cxx_class": "CoherentXBar", 605 "path": "system.membus", 606 "type": "CoherentXBar", 607 "use_default_range": false 608 }, |
|
547 "nvram": { | 609 "nvram": { |
548 "latency": 3.0000000000000004e-08, | 610 "range": "133429198848:133429207039", 611 "latency": 60, |
549 "name": "nvram", 550 "eventq_index": 0, | 612 "name": "nvram", 613 "eventq_index": 0, |
551 "latency_var": 0.0, | 614 "clk_domain": "system.clk_domain", 615 "latency_var": 0, 616 "bandwidth": "0.000000", |
552 "conf_table_reported": true, 553 "cxx_class": "SimpleMemory", 554 "path": "system.nvram", 555 "null": false, 556 "type": "SimpleMemory", 557 "port": { 558 "peer": "system.membus.master[4]", 559 "role": "SLAVE" 560 }, 561 "in_addr_map": true 562 }, 563 "eventq_index": 0, | 617 "conf_table_reported": true, 618 "cxx_class": "SimpleMemory", 619 "path": "system.nvram", 620 "null": false, 621 "type": "SimpleMemory", 622 "port": { 623 "peer": "system.membus.master[4]", 624 "role": "SLAVE" 625 }, 626 "in_addr_map": true 627 }, 628 "eventq_index": 0, |
629 "work_begin_cpu_id_exit": -1, |
|
564 "dvfs_handler": { 565 "enable": false, 566 "name": "dvfs_handler", | 630 "dvfs_handler": { 631 "enable": false, 632 "name": "dvfs_handler", |
567 "transition_latency": 9.999999999999999e-05, | 633 "sys_clk_domain": "system.clk_domain", 634 "transition_latency": 200000, |
568 "eventq_index": 0, 569 "cxx_class": "DVFSHandler", | 635 "eventq_index": 0, 636 "cxx_class": "DVFSHandler", |
637 "domains": [], |
|
570 "path": "system.dvfs_handler", 571 "type": "DVFSHandler" 572 }, 573 "work_end_exit_count": 0, | 638 "path": "system.dvfs_handler", 639 "type": "DVFSHandler" 640 }, 641 "work_end_exit_count": 0, |
574 "type": "SparcSystem", | 642 "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin", 643 "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin", |
575 "voltage_domain": { | 644 "voltage_domain": { |
645 "name": "voltage_domain", |
|
576 "eventq_index": 0, | 646 "eventq_index": 0, |
647 "voltage": [ 648 "1.0" 649 ], 650 "cxx_class": "VoltageDomain", |
|
577 "path": "system.voltage_domain", | 651 "path": "system.voltage_domain", |
578 "type": "VoltageDomain", 579 "name": "voltage_domain", 580 "cxx_class": "VoltageDomain" | 652 "type": "VoltageDomain" |
581 }, 582 "cache_line_size": 64, | 653 }, 654 "cache_line_size": 64, |
655 "boot_osflags": "a", 656 "system_port": { 657 "peer": "system.membus.slave[0]", 658 "role": "MASTER" 659 }, 660 "physmem": [ 661 { 662 "range": "1048576:68157439", 663 "latency": 60, 664 "name": "physmem0", 665 "eventq_index": 0, 666 "clk_domain": "system.clk_domain", 667 "latency_var": 0, 668 "bandwidth": "0.000000", 669 "conf_table_reported": true, 670 "cxx_class": "SimpleMemory", 671 "path": "system.physmem0", 672 "null": false, 673 "type": "SimpleMemory", 674 "port": { 675 "peer": "system.membus.master[7]", 676 "role": "SLAVE" 677 }, 678 "in_addr_map": true 679 }, 680 { 681 "range": "2147483648:2415919103", 682 "latency": 60, 683 "name": "physmem1", 684 "eventq_index": 0, 685 "clk_domain": "system.clk_domain", 686 "latency_var": 0, 687 "bandwidth": "0.000000", 688 "conf_table_reported": true, 689 "cxx_class": "SimpleMemory", 690 "path": "system.physmem1", 691 "null": false, 692 "type": "SimpleMemory", 693 "port": { 694 "peer": "system.membus.master[8]", 695 "role": "SLAVE" 696 }, 697 "in_addr_map": true 698 } 699 ], |
|
583 "work_cpus_ckpt_count": 0, 584 "work_begin_exit_count": 0, | 700 "work_cpus_ckpt_count": 0, 701 "work_begin_exit_count": 0, |
585 "num_work_ids": 16, | |
586 "path": "system", | 702 "path": "system", |
703 "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin", |
|
587 "cpu_clk_domain": { 588 "name": "cpu_clk_domain", | 704 "cpu_clk_domain": { 705 "name": "cpu_clk_domain", |
706 "clock": [ 707 2 708 ], |
|
589 "init_perf_level": 0, | 709 "init_perf_level": 0, |
710 "voltage_domain": "system.voltage_domain", |
|
590 "eventq_index": 0, 591 "cxx_class": "SrcClockDomain", 592 "path": "system.cpu_clk_domain", 593 "type": "SrcClockDomain", 594 "domain_id": -1 595 }, | 711 "eventq_index": 0, 712 "cxx_class": "SrcClockDomain", 713 "path": "system.cpu_clk_domain", 714 "type": "SrcClockDomain", 715 "domain_id": -1 716 }, |
717 "nvram_bin": "/dist/m5/system/binaries/nvram1", |
|
596 "mem_mode": "atomic", 597 "name": "system", 598 "init_param": 0, | 718 "mem_mode": "atomic", 719 "name": "system", 720 "init_param": 0, |
599 "system_port": { 600 "peer": "system.membus.slave[0]", 601 "role": "MASTER" 602 }, | 721 "type": "SparcSystem", 722 "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin", |
603 "load_addr_mask": 1099511627775, 604 "cpu": { | 723 "load_addr_mask": 1099511627775, 724 "cpu": { |
605 "simpoint_interval": 100000000, | |
606 "do_statistics_insts": true, 607 "numThreads": 1, 608 "itb": { 609 "name": "itb", 610 "eventq_index": 0, 611 "cxx_class": "SparcISA::TLB", 612 "path": "system.cpu.itb", 613 "type": "SparcTLB", 614 "size": 64 615 }, | 725 "do_statistics_insts": true, 726 "numThreads": 1, 727 "itb": { 728 "name": "itb", 729 "eventq_index": 0, 730 "cxx_class": "SparcISA::TLB", 731 "path": "system.cpu.itb", 732 "type": "SparcTLB", 733 "size": 64 734 }, |
735 "simulate_data_stalls": false, |
|
616 "function_trace": false, 617 "do_checkpoint_insts": true, 618 "cxx_class": "AtomicSimpleCPU", 619 "max_loads_all_threads": 0, | 736 "function_trace": false, 737 "do_checkpoint_insts": true, 738 "cxx_class": "AtomicSimpleCPU", 739 "max_loads_all_threads": 0, |
620 "simpoint_profile": false, 621 "simulate_data_stalls": false, | 740 "system": "system", 741 "clk_domain": "system.cpu_clk_domain", |
622 "function_trace_start": 0, 623 "cpu_id": 0, 624 "width": 1, | 742 "function_trace_start": 0, 743 "cpu_id": 0, 744 "width": 1, |
745 "checker": null, |
|
625 "eventq_index": 0, 626 "do_quiesce": true, 627 "type": "AtomicSimpleCPU", 628 "fastmem": false, | 746 "eventq_index": 0, 747 "do_quiesce": true, 748 "type": "AtomicSimpleCPU", 749 "fastmem": false, |
629 "profile": 0.0, | 750 "profile": 0, |
630 "icache_port": { 631 "peer": "system.membus.slave[1]", 632 "role": "MASTER" 633 }, 634 "interrupts": { 635 "eventq_index": 0, 636 "path": "system.cpu.interrupts", 637 "type": "SparcInterrupts", 638 "name": "interrupts", 639 "cxx_class": "SparcISA::Interrupts" 640 }, | 751 "icache_port": { 752 "peer": "system.membus.slave[1]", 753 "role": "MASTER" 754 }, 755 "interrupts": { 756 "eventq_index": 0, 757 "path": "system.cpu.interrupts", 758 "type": "SparcInterrupts", 759 "name": "interrupts", 760 "cxx_class": "SparcISA::Interrupts" 761 }, |
762 "dcache_port": { 763 "peer": "system.membus.slave[2]", 764 "role": "MASTER" 765 }, |
|
641 "socket_id": 0, 642 "max_insts_all_threads": 0, 643 "path": "system.cpu", | 766 "socket_id": 0, 767 "max_insts_all_threads": 0, 768 "path": "system.cpu", |
644 "isa": [ 645 { 646 "eventq_index": 0, 647 "path": "system.cpu.isa", 648 "type": "SparcISA", 649 "name": "isa", 650 "cxx_class": "SparcISA::ISA" 651 } 652 ], | 769 "max_loads_any_thread": 0, |
653 "switched_out": false, | 770 "switched_out": false, |
771 "workload": [], |
|
654 "name": "cpu", 655 "dtb": { 656 "name": "dtb", 657 "eventq_index": 0, 658 "cxx_class": "SparcISA::TLB", 659 "path": "system.cpu.dtb", 660 "type": "SparcTLB", 661 "size": 64 662 }, | 772 "name": "cpu", 773 "dtb": { 774 "name": "dtb", 775 "eventq_index": 0, 776 "cxx_class": "SparcISA::TLB", 777 "path": "system.cpu.dtb", 778 "type": "SparcTLB", 779 "size": 64 780 }, |
781 "simpoint_start_insts": [], |
|
663 "max_insts_any_thread": 0, 664 "simulate_inst_stalls": false, | 782 "max_insts_any_thread": 0, 783 "simulate_inst_stalls": false, |
665 "progress_interval": 0.0, 666 "dcache_port": { 667 "peer": "system.membus.slave[2]", 668 "role": "MASTER" 669 }, 670 "max_loads_any_thread": 0, | 784 "progress_interval": 0, 785 "branchPred": null, 786 "isa": [ 787 { 788 "eventq_index": 0, 789 "path": "system.cpu.isa", 790 "type": "SparcISA", 791 "name": "isa", 792 "cxx_class": "SparcISA::ISA" 793 } 794 ], |
671 "tracer": { 672 "eventq_index": 0, 673 "path": "system.cpu.tracer", 674 "type": "ExeTracer", 675 "name": "tracer", 676 "cxx_class": "Trace::ExeTracer" 677 } 678 }, 679 "intrctrl": { | 795 "tracer": { 796 "eventq_index": 0, 797 "path": "system.cpu.tracer", 798 "type": "ExeTracer", 799 "name": "tracer", 800 "cxx_class": "Trace::ExeTracer" 801 } 802 }, 803 "intrctrl": { |
804 "name": "intrctrl", 805 "sys": "system", |
|
680 "eventq_index": 0, | 806 "eventq_index": 0, |
807 "cxx_class": "IntrControl", |
|
681 "path": "system.intrctrl", | 808 "path": "system.intrctrl", |
682 "type": "IntrControl", 683 "name": "intrctrl", 684 "cxx_class": "IntrControl" | 809 "type": "IntrControl" |
685 }, 686 "disk0": { 687 "name": "disk0", 688 "pio": { 689 "peer": "system.iobus.master[14]", 690 "role": "SLAVE" 691 }, 692 "image": { 693 "read_only": false, 694 "name": "image", | 810 }, 811 "disk0": { 812 "name": "disk0", 813 "pio": { 814 "peer": "system.iobus.master[14]", 815 "role": "SLAVE" 816 }, 817 "image": { 818 "read_only": false, 819 "name": "image", |
820 "cxx_class": "CowDiskImage", 821 "eventq_index": 0, |
|
695 "child": { 696 "read_only": true, 697 "name": "child", 698 "eventq_index": 0, 699 "cxx_class": "RawDiskImage", 700 "path": "system.disk0.image.child", | 822 "child": { 823 "read_only": true, 824 "name": "child", 825 "eventq_index": 0, 826 "cxx_class": "RawDiskImage", 827 "path": "system.disk0.image.child", |
828 "image_file": "/dist/m5/system/disks/disk.s10hw2", |
|
701 "type": "RawDiskImage" 702 }, | 829 "type": "RawDiskImage" 830 }, |
703 "eventq_index": 0, 704 "cxx_class": "CowDiskImage", | |
705 "path": "system.disk0.image", | 831 "path": "system.disk0.image", |
706 "table_size": 65536, 707 "type": "CowDiskImage" | 832 "image_file": "", 833 "type": "CowDiskImage", 834 "table_size": 65536 |
708 }, | 835 }, |
709 "pio_latency": 1.0000000000000001e-07, | 836 "pio_latency": 200, 837 "clk_domain": "system.clk_domain", 838 "system": "system", |
710 "eventq_index": 0, 711 "cxx_class": "MmDisk", 712 "path": "system.disk0", 713 "pio_addr": 134217728000, 714 "type": "MmDisk" 715 }, | 839 "eventq_index": 0, 840 "cxx_class": "MmDisk", 841 "path": "system.disk0", 842 "pio_addr": 134217728000, 843 "type": "MmDisk" 844 }, |
716 "hypervisor_desc_addr": 133446500352, | |
717 "reset_addr": 1099243192320, | 845 "reset_addr": 1099243192320, |
846 "hypervisor_desc_addr": 133446500352, 847 "partition_desc_addr": 133445976064, |
|
718 "work_item_id": -1, | 848 "work_item_id": -1, |
719 "work_begin_cpu_id_exit": -1 | 849 "num_work_ids": 16 |
720 }, | 850 }, |
721 "time_sync_period": 0.1, | 851 "time_sync_period": 200000000, |
722 "eventq_index": 0, | 852 "eventq_index": 0, |
723 "time_sync_spin_threshold": 9.999999999999999e-05, | 853 "time_sync_spin_threshold": 200000, |
724 "cxx_class": "Root", 725 "path": "root", 726 "time_sync_enable": false, 727 "type": "Root", 728 "full_system": true 729} | 854 "cxx_class": "Root", 855 "path": "root", 856 "time_sync_enable": false, 857 "type": "Root", 858 "full_system": true 859} |