config.json (10222:d51e31eef415) config.json (10315:9e02c14446bb)
1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "bridge": {
6 "slave": {
7 "peer": "system.membus.master[2]",
8 "role": "SLAVE"

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15 "peer": "system.iobus.slave[0]",
16 "role": "MASTER"
17 },
18 "cxx_class": "Bridge",
19 "path": "system.bridge",
20 "resp_size": 16,
21 "type": "Bridge"
22 },
1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "bridge": {
6 "slave": {
7 "peer": "system.membus.master[2]",
8 "role": "SLAVE"

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15 "peer": "system.iobus.slave[0]",
16 "role": "MASTER"
17 },
18 "cxx_class": "Bridge",
19 "path": "system.bridge",
20 "resp_size": 16,
21 "type": "Bridge"
22 },
23 "iobus": {
24 "slave": {
25 "peer": [
26 "system.bridge.master"
27 ],
28 "role": "SLAVE"
29 },
30 "name": "iobus",
31 "header_cycles": 1,
32 "width": 8,
33 "eventq_index": 0,
34 "master": {
35 "peer": [
36 "system.t1000.fake_clk.pio",
37 "system.t1000.fake_membnks.pio",
38 "system.t1000.fake_l2_1.pio",
39 "system.t1000.fake_l2_2.pio",
40 "system.t1000.fake_l2_3.pio",
41 "system.t1000.fake_l2_4.pio",
42 "system.t1000.fake_l2esr_1.pio",
43 "system.t1000.fake_l2esr_2.pio",
44 "system.t1000.fake_l2esr_3.pio",
45 "system.t1000.fake_l2esr_4.pio",
46 "system.t1000.fake_ssi.pio",
47 "system.t1000.fake_jbi.pio",
48 "system.t1000.puart0.pio",
49 "system.t1000.hvuart.pio",
50 "system.disk0.pio"
51 ],
52 "role": "MASTER"
53 },
54 "cxx_class": "NoncoherentBus",
55 "path": "system.iobus",
56 "type": "NoncoherentBus",
57 "use_default_range": false
58 },
23 "kernel_addr_check": true,
59 "rom": {
60 "latency": 3.0000000000000004e-08,
61 "name": "rom",
62 "eventq_index": 0,
63 "latency_var": 0.0,
64 "conf_table_reported": true,
65 "cxx_class": "SimpleMemory",
66 "path": "system.rom",

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124 ],
125 "role": "MASTER"
126 },
127 "cxx_class": "CoherentBus",
128 "path": "system.membus",
129 "type": "CoherentBus",
130 "use_default_range": false
131 },
24 "rom": {
25 "latency": 3.0000000000000004e-08,
26 "name": "rom",
27 "eventq_index": 0,
28 "latency_var": 0.0,
29 "conf_table_reported": true,
30 "cxx_class": "SimpleMemory",
31 "path": "system.rom",

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89 ],
90 "role": "MASTER"
91 },
92 "cxx_class": "CoherentBus",
93 "path": "system.membus",
94 "type": "CoherentBus",
95 "use_default_range": false
96 },
97 "iobus": {
98 "slave": {
99 "peer": [
100 "system.bridge.master"
101 ],
102 "role": "SLAVE"
103 },
104 "name": "iobus",
105 "header_cycles": 1,
106 "width": 8,
107 "eventq_index": 0,
108 "master": {
109 "peer": [
110 "system.t1000.fake_clk.pio",
111 "system.t1000.fake_membnks.pio",
112 "system.t1000.fake_l2_1.pio",
113 "system.t1000.fake_l2_2.pio",
114 "system.t1000.fake_l2_3.pio",
115 "system.t1000.fake_l2_4.pio",
116 "system.t1000.fake_l2esr_1.pio",
117 "system.t1000.fake_l2esr_2.pio",
118 "system.t1000.fake_l2esr_3.pio",
119 "system.t1000.fake_l2esr_4.pio",
120 "system.t1000.fake_ssi.pio",
121 "system.t1000.fake_jbi.pio",
122 "system.t1000.puart0.pio",
123 "system.t1000.hvuart.pio",
124 "system.disk0.pio"
125 ],
126 "role": "MASTER"
127 },
128 "cxx_class": "NoncoherentBus",
129 "path": "system.iobus",
130 "type": "NoncoherentBus",
131 "use_default_range": false
132 },
132 "t1000": {
133 "htod": {
134 "name": "htod",
135 "pio": {
136 "peer": "system.membus.master[1]",
137 "role": "SLAVE"
138 },
139 "time": "Thu Jan 1 00:00:00 2009",

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515 "port": {
516 "peer": "system.membus.master[6]",
517 "role": "SLAVE"
518 },
519 "in_addr_map": true
520 },
521 "clk_domain": {
522 "name": "clk_domain",
133 "t1000": {
134 "htod": {
135 "name": "htod",
136 "pio": {
137 "peer": "system.membus.master[1]",
138 "role": "SLAVE"
139 },
140 "time": "Thu Jan 1 00:00:00 2009",

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516 "port": {
517 "peer": "system.membus.master[6]",
518 "role": "SLAVE"
519 },
520 "in_addr_map": true
521 },
522 "clk_domain": {
523 "name": "clk_domain",
523 "clock": 1e-09,
524 "init_perf_level": 0,
524 "eventq_index": 0,
525 "cxx_class": "SrcClockDomain",
526 "path": "system.clk_domain",
525 "eventq_index": 0,
526 "cxx_class": "SrcClockDomain",
527 "path": "system.clk_domain",
527 "type": "SrcClockDomain"
528 "type": "SrcClockDomain",
529 "domain_id": -1
528 },
529 "hypervisor_desc": {
530 "latency": 3.0000000000000004e-08,
531 "name": "hypervisor_desc",
532 "eventq_index": 0,
533 "latency_var": 0.0,
534 "conf_table_reported": true,
535 "cxx_class": "SimpleMemory",

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554 "type": "SimpleMemory",
555 "port": {
556 "peer": "system.membus.master[4]",
557 "role": "SLAVE"
558 },
559 "in_addr_map": true
560 },
561 "eventq_index": 0,
530 },
531 "hypervisor_desc": {
532 "latency": 3.0000000000000004e-08,
533 "name": "hypervisor_desc",
534 "eventq_index": 0,
535 "latency_var": 0.0,
536 "conf_table_reported": true,
537 "cxx_class": "SimpleMemory",

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556 "type": "SimpleMemory",
557 "port": {
558 "peer": "system.membus.master[4]",
559 "role": "SLAVE"
560 },
561 "in_addr_map": true
562 },
563 "eventq_index": 0,
564 "dvfs_handler": {
565 "enable": false,
566 "name": "dvfs_handler",
567 "transition_latency": 9.999999999999999e-05,
568 "eventq_index": 0,
569 "cxx_class": "DVFSHandler",
570 "path": "system.dvfs_handler",
571 "type": "DVFSHandler"
572 },
562 "work_end_exit_count": 0,
563 "type": "SparcSystem",
564 "voltage_domain": {
565 "eventq_index": 0,
566 "path": "system.voltage_domain",
567 "type": "VoltageDomain",
568 "name": "voltage_domain",
569 "cxx_class": "VoltageDomain"
570 },
571 "cache_line_size": 64,
572 "work_cpus_ckpt_count": 0,
573 "work_begin_exit_count": 0,
574 "num_work_ids": 16,
575 "path": "system",
576 "cpu_clk_domain": {
577 "name": "cpu_clk_domain",
573 "work_end_exit_count": 0,
574 "type": "SparcSystem",
575 "voltage_domain": {
576 "eventq_index": 0,
577 "path": "system.voltage_domain",
578 "type": "VoltageDomain",
579 "name": "voltage_domain",
580 "cxx_class": "VoltageDomain"
581 },
582 "cache_line_size": 64,
583 "work_cpus_ckpt_count": 0,
584 "work_begin_exit_count": 0,
585 "num_work_ids": 16,
586 "path": "system",
587 "cpu_clk_domain": {
588 "name": "cpu_clk_domain",
578 "clock": 1e-09,
589 "init_perf_level": 0,
579 "eventq_index": 0,
580 "cxx_class": "SrcClockDomain",
581 "path": "system.cpu_clk_domain",
590 "eventq_index": 0,
591 "cxx_class": "SrcClockDomain",
592 "path": "system.cpu_clk_domain",
582 "type": "SrcClockDomain"
593 "type": "SrcClockDomain",
594 "domain_id": -1
583 },
584 "mem_mode": "atomic",
585 "name": "system",
586 "init_param": 0,
587 "system_port": {
588 "peer": "system.membus.slave[0]",
589 "role": "MASTER"
590 },

--- 127 unchanged lines hidden --- 		595 },
596 "mem_mode": "atomic",
597 "name": "system",
598 "init_param": 0,
599 "system_port": {
600 "peer": "system.membus.slave[0]",
601 "role": "MASTER"
602 },

--- 127 unchanged lines hidden ---