1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { 5 "kernel": "", 6 "mmap_using_noreserve": false, 7 "kernel_addr_check": true, 8 "rom": { 9 "range": "1099243192320:1099251580927", 10 "latency": 60, 11 "name": "rom",
|
12 "p_state_clk_gate_min": 2, |
13 "eventq_index": 0,
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14 "p_state_clk_gate_bins": 20, 15 "default_p_state": "UNDEFINED", |
16 "clk_domain": "system.clk_domain", 17 "latency_var": 0, 18 "bandwidth": "0.000000", 19 "conf_table_reported": true, 20 "cxx_class": "SimpleMemory",
|
21 "p_state_clk_gate_max": 2000000000, |
22 "path": "system.rom", 23 "null": false, 24 "type": "SimpleMemory", 25 "port": { 26 "peer": "system.membus.master[3]", 27 "role": "SLAVE" 28 }, 29 "in_addr_map": true 30 }, 31 "bridge": { 32 "ranges": [ 33 "133412421632:133412421639", 34 "134217728000:554050781183", 35 "644245094400:652835028991", 36 "725849473024:1095485095935", 37 "1099255955456:1099255955463" 38 ], 39 "slave": { 40 "peer": "system.membus.master[2]", 41 "role": "SLAVE" 42 }, 43 "name": "bridge",
|
44 "p_state_clk_gate_min": 2, 45 "p_state_clk_gate_bins": 20, 46 "cxx_class": "Bridge", |
47 "req_size": 16, 48 "clk_domain": "system.clk_domain", 49 "delay": 100, 50 "eventq_index": 0, 51 "master": { 52 "peer": "system.iobus.slave[0]", 53 "role": "MASTER" 54 },
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48 "cxx_class": "Bridge",
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55 "default_p_state": "UNDEFINED", 56 "p_state_clk_gate_max": 2000000000, |
57 "path": "system.bridge", 58 "resp_size": 16, 59 "type": "Bridge" 60 }, 61 "iobus": {
|
62 "forward_latency": 1, |
63 "slave": { 64 "peer": [ 65 "system.bridge.master" 66 ], 67 "role": "SLAVE" 68 }, 69 "name": "iobus",
|
61 "forward_latency": 1,
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70 "p_state_clk_gate_min": 2, 71 "p_state_clk_gate_bins": 20, 72 "cxx_class": "NoncoherentXBar", |
73 "clk_domain": "system.clk_domain", 74 "width": 16, 75 "eventq_index": 0, 76 "master": { 77 "peer": [ 78 "system.t1000.fake_clk.pio", 79 "system.t1000.fake_membnks.pio", 80 "system.t1000.fake_l2_1.pio", 81 "system.t1000.fake_l2_2.pio", 82 "system.t1000.fake_l2_3.pio", 83 "system.t1000.fake_l2_4.pio", 84 "system.t1000.fake_l2esr_1.pio", 85 "system.t1000.fake_l2esr_2.pio", 86 "system.t1000.fake_l2esr_3.pio", 87 "system.t1000.fake_l2esr_4.pio", 88 "system.t1000.fake_ssi.pio", 89 "system.t1000.fake_jbi.pio", 90 "system.t1000.puart0.pio", 91 "system.t1000.hvuart.pio", 92 "system.disk0.pio" 93 ], 94 "role": "MASTER" 95 }, 96 "response_latency": 2,
|
86 "cxx_class": "NoncoherentXBar",
|
97 "default_p_state": "UNDEFINED", 98 "p_state_clk_gate_max": 2000000000, |
99 "path": "system.iobus", 100 "type": "NoncoherentXBar", 101 "use_default_range": false, 102 "frontend_latency": 2 103 }, 104 "t1000": { 105 "htod": { 106 "name": "htod",
|
107 "p_state_clk_gate_min": 2, |
108 "pio": { 109 "peer": "system.membus.master[1]", 110 "role": "SLAVE" 111 },
|
99 "time": "Thu Jan 1 00:00:00 2009",
|
112 "p_state_clk_gate_bins": 20, 113 "cxx_class": "DumbTOD", |
114 "pio_latency": 200, 115 "clk_domain": "system.clk_domain", 116 "system": "system", 117 "eventq_index": 0,
|
104 "cxx_class": "DumbTOD",
|
118 "time": "Thu Jan 1 00:00:00 2009", 119 "default_p_state": "UNDEFINED", 120 "p_state_clk_gate_max": 2000000000, |
121 "path": "system.t1000.htod", 122 "pio_addr": 1099255906296, 123 "type": "DumbTOD" 124 }, 125 "puart0": { 126 "name": "puart0",
|
127 "p_state_clk_gate_min": 2, |
128 "pio": { 129 "peer": "system.iobus.master[12]", 130 "role": "SLAVE" 131 },
|
132 "p_state_clk_gate_bins": 20, 133 "cxx_class": "Uart8250", |
134 "pio_latency": 200, 135 "clk_domain": "system.clk_domain", 136 "system": "system", 137 "terminal": "system.t1000.pterm", 138 "platform": "system.t1000", 139 "eventq_index": 0,
|
121 "cxx_class": "Uart8250",
|
140 "default_p_state": "UNDEFINED", 141 "p_state_clk_gate_max": 2000000000, |
142 "path": "system.t1000.puart0", 143 "pio_addr": 133412421632, 144 "type": "Uart8250" 145 }, 146 "fake_membnks": {
|
127 "system": "system",
128 "ret_data8": 255,
129 "name": "fake_membnks",
130 "warn_access": "",
|
147 "pio": { 148 "peer": "system.iobus.master[1]", 149 "role": "SLAVE" 150 },
|
135 "ret_bad_addr": false,
136 "pio_latency": 200,
137 "clk_domain": "system.clk_domain",
138 "fake_mem": false,
139 "pio_size": 16384,
140 "ret_data32": 4294967295,
141 "eventq_index": 0,
142 "update_data": false,
|
151 "ret_data64": 0,
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152 "fake_mem": false, 153 "clk_domain": "system.clk_domain", |
154 "cxx_class": "IsaFake",
|
145 "path": "system.t1000.fake_membnks",
|
155 "pio_addr": 648540061696,
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156 "update_data": false, 157 "warn_access": "", 158 "pio_latency": 200, 159 "system": "system", 160 "eventq_index": 0, 161 "default_p_state": "UNDEFINED", 162 "p_state_clk_gate_max": 2000000000, |
163 "type": "IsaFake",
|
148 "ret_data16": 65535
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164 "p_state_clk_gate_min": 2, 165 "ret_data32": 4294967295, 166 "path": "system.t1000.fake_membnks", 167 "ret_data16": 65535, 168 "ret_data8": 255, 169 "name": "fake_membnks", 170 "ret_bad_addr": false, 171 "pio_size": 16384, 172 "p_state_clk_gate_bins": 20 |
173 }, 174 "cxx_class": "T1000", 175 "fake_jbi": {
|
152 "system": "system",
153 "ret_data8": 255,
154 "name": "fake_jbi",
155 "warn_access": "",
|
176 "pio": { 177 "peer": "system.iobus.master[11]", 178 "role": "SLAVE" 179 },
|
160 "ret_bad_addr": false,
161 "pio_latency": 200,
162 "clk_domain": "system.clk_domain",
163 "fake_mem": false,
164 "pio_size": 4294967296,
165 "ret_data32": 4294967295,
166 "eventq_index": 0,
167 "update_data": false,
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180 "ret_data64": 18446744073709551615,
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181 "fake_mem": false, 182 "clk_domain": "system.clk_domain", |
183 "cxx_class": "IsaFake",
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170 "path": "system.t1000.fake_jbi",
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184 "pio_addr": 549755813888,
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185 "update_data": false, 186 "warn_access": "", 187 "pio_latency": 200, 188 "system": "system", 189 "eventq_index": 0, 190 "default_p_state": "UNDEFINED", 191 "p_state_clk_gate_max": 2000000000, |
192 "type": "IsaFake",
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173 "ret_data16": 65535
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193 "p_state_clk_gate_min": 2, 194 "ret_data32": 4294967295, 195 "path": "system.t1000.fake_jbi", 196 "ret_data16": 65535, 197 "ret_data8": 255, 198 "name": "fake_jbi", 199 "ret_bad_addr": false, 200 "pio_size": 4294967296, 201 "p_state_clk_gate_bins": 20 |
202 }, 203 "intrctrl": "system.intrctrl", 204 "fake_l2esr_2": {
|
177 "system": "system",
178 "ret_data8": 255,
179 "name": "fake_l2esr_2",
180 "warn_access": "",
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205 "pio": { 206 "peer": "system.iobus.master[7]", 207 "role": "SLAVE" 208 },
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185 "ret_bad_addr": false,
186 "pio_latency": 200,
187 "clk_domain": "system.clk_domain",
188 "fake_mem": false,
189 "pio_size": 8,
190 "ret_data32": 4294967295,
191 "eventq_index": 0,
192 "update_data": true,
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209 "ret_data64": 0,
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210 "fake_mem": false, 211 "clk_domain": "system.clk_domain", |
212 "cxx_class": "IsaFake",
|
195 "path": "system.t1000.fake_l2esr_2",
|
213 "pio_addr": 734439407680,
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214 "update_data": true, 215 "warn_access": "", 216 "pio_latency": 200, 217 "system": "system", 218 "eventq_index": 0, 219 "default_p_state": "UNDEFINED", 220 "p_state_clk_gate_max": 2000000000, |
221 "type": "IsaFake",
|
198 "ret_data16": 65535
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222 "p_state_clk_gate_min": 2, 223 "ret_data32": 4294967295, 224 "path": "system.t1000.fake_l2esr_2", 225 "ret_data16": 65535, 226 "ret_data8": 255, 227 "name": "fake_l2esr_2", 228 "ret_bad_addr": false, 229 "pio_size": 8, 230 "p_state_clk_gate_bins": 20 |
231 }, 232 "system": "system", 233 "eventq_index": 0, 234 "hterm": { 235 "name": "hterm", 236 "output": true, 237 "number": 0, 238 "intr_control": "system.intrctrl", 239 "eventq_index": 0, 240 "cxx_class": "Terminal", 241 "path": "system.t1000.hterm", 242 "type": "Terminal", 243 "port": 3456 244 }, 245 "type": "T1000", 246 "fake_l2_4": {
|
215 "system": "system",
216 "ret_data8": 255,
217 "name": "fake_l2_4",
218 "warn_access": "",
|
247 "pio": { 248 "peer": "system.iobus.master[5]", 249 "role": "SLAVE" 250 },
|
223 "ret_bad_addr": false,
224 "pio_latency": 200,
225 "clk_domain": "system.clk_domain",
226 "fake_mem": false,
227 "pio_size": 8,
228 "ret_data32": 4294967295,
229 "eventq_index": 0,
230 "update_data": true,
|
251 "ret_data64": 1,
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252 "fake_mem": false, 253 "clk_domain": "system.clk_domain", |
254 "cxx_class": "IsaFake",
|
233 "path": "system.t1000.fake_l2_4",
|
255 "pio_addr": 725849473216,
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256 "update_data": true, 257 "warn_access": "", 258 "pio_latency": 200, 259 "system": "system", 260 "eventq_index": 0, 261 "default_p_state": "UNDEFINED", 262 "p_state_clk_gate_max": 2000000000, |
263 "type": "IsaFake",
|
236 "ret_data16": 65535
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264 "p_state_clk_gate_min": 2, 265 "ret_data32": 4294967295, 266 "path": "system.t1000.fake_l2_4", 267 "ret_data16": 65535, 268 "ret_data8": 255, 269 "name": "fake_l2_4", 270 "ret_bad_addr": false, 271 "pio_size": 8, 272 "p_state_clk_gate_bins": 20 |
273 }, 274 "fake_l2_1": {
|
239 "system": "system",
240 "ret_data8": 255,
241 "name": "fake_l2_1",
242 "warn_access": "",
|
275 "pio": { 276 "peer": "system.iobus.master[2]", 277 "role": "SLAVE" 278 },
|
247 "ret_bad_addr": false,
248 "pio_latency": 200,
249 "clk_domain": "system.clk_domain",
250 "fake_mem": false,
251 "pio_size": 8,
252 "ret_data32": 4294967295,
253 "eventq_index": 0,
254 "update_data": true,
|
279 "ret_data64": 1,
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280 "fake_mem": false, 281 "clk_domain": "system.clk_domain", |
282 "cxx_class": "IsaFake",
|
257 "path": "system.t1000.fake_l2_1",
|
283 "pio_addr": 725849473024,
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284 "update_data": true, 285 "warn_access": "", 286 "pio_latency": 200, 287 "system": "system", 288 "eventq_index": 0, 289 "default_p_state": "UNDEFINED", 290 "p_state_clk_gate_max": 2000000000, |
291 "type": "IsaFake",
|
260 "ret_data16": 65535
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292 "p_state_clk_gate_min": 2, 293 "ret_data32": 4294967295, 294 "path": "system.t1000.fake_l2_1", 295 "ret_data16": 65535, 296 "ret_data8": 255, 297 "name": "fake_l2_1", 298 "ret_bad_addr": false, 299 "pio_size": 8, 300 "p_state_clk_gate_bins": 20 |
301 }, 302 "fake_l2_2": {
|
263 "system": "system",
264 "ret_data8": 255,
265 "name": "fake_l2_2",
266 "warn_access": "",
|
303 "pio": { 304 "peer": "system.iobus.master[3]", 305 "role": "SLAVE" 306 },
|
271 "ret_bad_addr": false,
272 "pio_latency": 200,
273 "clk_domain": "system.clk_domain",
274 "fake_mem": false,
275 "pio_size": 8,
276 "ret_data32": 4294967295,
277 "eventq_index": 0,
278 "update_data": true,
|
307 "ret_data64": 1,
|
308 "fake_mem": false, 309 "clk_domain": "system.clk_domain", |
310 "cxx_class": "IsaFake",
|
281 "path": "system.t1000.fake_l2_2",
|
311 "pio_addr": 725849473088,
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312 "update_data": true, 313 "warn_access": "", 314 "pio_latency": 200, 315 "system": "system", 316 "eventq_index": 0, 317 "default_p_state": "UNDEFINED", 318 "p_state_clk_gate_max": 2000000000, |
319 "type": "IsaFake",
|
284 "ret_data16": 65535
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320 "p_state_clk_gate_min": 2, 321 "ret_data32": 4294967295, 322 "path": "system.t1000.fake_l2_2", 323 "ret_data16": 65535, 324 "ret_data8": 255, 325 "name": "fake_l2_2", 326 "ret_bad_addr": false, 327 "pio_size": 8, 328 "p_state_clk_gate_bins": 20 |
329 }, 330 "fake_l2_3": {
|
287 "system": "system",
288 "ret_data8": 255,
289 "name": "fake_l2_3",
290 "warn_access": "",
|
331 "pio": { 332 "peer": "system.iobus.master[4]", 333 "role": "SLAVE" 334 },
|
295 "ret_bad_addr": false,
296 "pio_latency": 200,
297 "clk_domain": "system.clk_domain",
298 "fake_mem": false,
299 "pio_size": 8,
300 "ret_data32": 4294967295,
301 "eventq_index": 0,
302 "update_data": true,
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335 "ret_data64": 1,
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336 "fake_mem": false, 337 "clk_domain": "system.clk_domain", |
338 "cxx_class": "IsaFake",
|
305 "path": "system.t1000.fake_l2_3",
|
339 "pio_addr": 725849473152,
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340 "update_data": true, 341 "warn_access": "", 342 "pio_latency": 200, 343 "system": "system", 344 "eventq_index": 0, 345 "default_p_state": "UNDEFINED", 346 "p_state_clk_gate_max": 2000000000, |
347 "type": "IsaFake",
|
308 "ret_data16": 65535
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348 "p_state_clk_gate_min": 2, 349 "ret_data32": 4294967295, 350 "path": "system.t1000.fake_l2_3", 351 "ret_data16": 65535, 352 "ret_data8": 255, 353 "name": "fake_l2_3", 354 "ret_bad_addr": false, 355 "pio_size": 8, 356 "p_state_clk_gate_bins": 20 |
357 }, 358 "pterm": { 359 "name": "pterm", 360 "output": true, 361 "number": 0, 362 "intr_control": "system.intrctrl", 363 "eventq_index": 0, 364 "cxx_class": "Terminal", 365 "path": "system.t1000.pterm", 366 "type": "Terminal", 367 "port": 3456 368 }, 369 "path": "system.t1000", 370 "iob": { 371 "name": "iob",
|
372 "p_state_clk_gate_min": 2, |
373 "pio": { 374 "peer": "system.membus.master[0]", 375 "role": "SLAVE" 376 },
|
377 "p_state_clk_gate_bins": 20, 378 "cxx_class": "Iob", |
379 "pio_latency": 2, 380 "clk_domain": "system.clk_domain", 381 "system": "system", 382 "platform": "system.t1000", 383 "eventq_index": 0,
|
333 "cxx_class": "Iob",
|
384 "default_p_state": "UNDEFINED", 385 "p_state_clk_gate_max": 2000000000, |
386 "path": "system.t1000.iob", 387 "type": "Iob" 388 }, 389 "hvuart": { 390 "name": "hvuart",
|
391 "p_state_clk_gate_min": 2, |
392 "pio": { 393 "peer": "system.iobus.master[13]", 394 "role": "SLAVE" 395 },
|
396 "p_state_clk_gate_bins": 20, 397 "cxx_class": "Uart8250", |
398 "pio_latency": 200, 399 "clk_domain": "system.clk_domain", 400 "system": "system", 401 "terminal": "system.t1000.hterm", 402 "platform": "system.t1000", 403 "eventq_index": 0,
|
349 "cxx_class": "Uart8250",
|
404 "default_p_state": "UNDEFINED", 405 "p_state_clk_gate_max": 2000000000, |
406 "path": "system.t1000.hvuart", 407 "pio_addr": 1099255955456, 408 "type": "Uart8250" 409 }, 410 "name": "t1000", 411 "fake_l2esr_3": {
|
356 "system": "system",
357 "ret_data8": 255,
358 "name": "fake_l2esr_3",
359 "warn_access": "",
|
412 "pio": { 413 "peer": "system.iobus.master[8]", 414 "role": "SLAVE" 415 },
|
364 "ret_bad_addr": false,
365 "pio_latency": 200,
366 "clk_domain": "system.clk_domain",
367 "fake_mem": false,
368 "pio_size": 8,
369 "ret_data32": 4294967295,
370 "eventq_index": 0,
371 "update_data": true,
|
416 "ret_data64": 0,
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417 "fake_mem": false, 418 "clk_domain": "system.clk_domain", |
419 "cxx_class": "IsaFake",
|
374 "path": "system.t1000.fake_l2esr_3",
|
420 "pio_addr": 734439407744,
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421 "update_data": true, 422 "warn_access": "", 423 "pio_latency": 200, 424 "system": "system", 425 "eventq_index": 0, 426 "default_p_state": "UNDEFINED", 427 "p_state_clk_gate_max": 2000000000, |
428 "type": "IsaFake",
|
377 "ret_data16": 65535
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429 "p_state_clk_gate_min": 2, 430 "ret_data32": 4294967295, 431 "path": "system.t1000.fake_l2esr_3", 432 "ret_data16": 65535, 433 "ret_data8": 255, 434 "name": "fake_l2esr_3", 435 "ret_bad_addr": false, 436 "pio_size": 8, 437 "p_state_clk_gate_bins": 20 |
438 }, 439 "fake_ssi": {
|
380 "system": "system",
381 "ret_data8": 255,
382 "name": "fake_ssi",
383 "warn_access": "",
|
440 "pio": { 441 "peer": "system.iobus.master[10]", 442 "role": "SLAVE" 443 },
|
388 "ret_bad_addr": false,
389 "pio_latency": 200,
390 "clk_domain": "system.clk_domain",
391 "fake_mem": false,
392 "pio_size": 268435456,
393 "ret_data32": 4294967295,
394 "eventq_index": 0,
395 "update_data": false,
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444 "ret_data64": 18446744073709551615,
|
445 "fake_mem": false, 446 "clk_domain": "system.clk_domain", |
447 "cxx_class": "IsaFake",
|
398 "path": "system.t1000.fake_ssi",
|
448 "pio_addr": 1095216660480,
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449 "update_data": false, 450 "warn_access": "", 451 "pio_latency": 200, 452 "system": "system", 453 "eventq_index": 0, 454 "default_p_state": "UNDEFINED", 455 "p_state_clk_gate_max": 2000000000, |
456 "type": "IsaFake",
|
401 "ret_data16": 65535
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457 "p_state_clk_gate_min": 2, 458 "ret_data32": 4294967295, 459 "path": "system.t1000.fake_ssi", 460 "ret_data16": 65535, 461 "ret_data8": 255, 462 "name": "fake_ssi", 463 "ret_bad_addr": false, 464 "pio_size": 268435456, 465 "p_state_clk_gate_bins": 20 |
466 }, 467 "fake_l2esr_1": {
|
404 "system": "system",
405 "ret_data8": 255,
406 "name": "fake_l2esr_1",
407 "warn_access": "",
|
468 "pio": { 469 "peer": "system.iobus.master[6]", 470 "role": "SLAVE" 471 },
|
412 "ret_bad_addr": false,
413 "pio_latency": 200,
414 "clk_domain": "system.clk_domain",
415 "fake_mem": false,
416 "pio_size": 8,
417 "ret_data32": 4294967295,
418 "eventq_index": 0,
419 "update_data": true,
|
472 "ret_data64": 0,
|
473 "fake_mem": false, 474 "clk_domain": "system.clk_domain", |
475 "cxx_class": "IsaFake",
|
422 "path": "system.t1000.fake_l2esr_1",
|
476 "pio_addr": 734439407616,
|
477 "update_data": true, 478 "warn_access": "", 479 "pio_latency": 200, 480 "system": "system", 481 "eventq_index": 0, 482 "default_p_state": "UNDEFINED", 483 "p_state_clk_gate_max": 2000000000, |
484 "type": "IsaFake",
|
425 "ret_data16": 65535
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485 "p_state_clk_gate_min": 2, 486 "ret_data32": 4294967295, 487 "path": "system.t1000.fake_l2esr_1", 488 "ret_data16": 65535, 489 "ret_data8": 255, 490 "name": "fake_l2esr_1", 491 "ret_bad_addr": false, 492 "pio_size": 8, 493 "p_state_clk_gate_bins": 20 |
494 }, 495 "fake_l2esr_4": {
|
428 "system": "system",
429 "ret_data8": 255,
430 "name": "fake_l2esr_4",
431 "warn_access": "",
|
496 "pio": { 497 "peer": "system.iobus.master[9]", 498 "role": "SLAVE" 499 },
|
436 "ret_bad_addr": false,
437 "pio_latency": 200,
438 "clk_domain": "system.clk_domain",
439 "fake_mem": false,
440 "pio_size": 8,
441 "ret_data32": 4294967295,
442 "eventq_index": 0,
443 "update_data": true,
|
500 "ret_data64": 0,
|
501 "fake_mem": false, 502 "clk_domain": "system.clk_domain", |
503 "cxx_class": "IsaFake",
|
446 "path": "system.t1000.fake_l2esr_4",
|
504 "pio_addr": 734439407808,
|
505 "update_data": true, 506 "warn_access": "", 507 "pio_latency": 200, 508 "system": "system", 509 "eventq_index": 0, 510 "default_p_state": "UNDEFINED", 511 "p_state_clk_gate_max": 2000000000, |
512 "type": "IsaFake",
|
449 "ret_data16": 65535
|
513 "p_state_clk_gate_min": 2, 514 "ret_data32": 4294967295, 515 "path": "system.t1000.fake_l2esr_4", 516 "ret_data16": 65535, 517 "ret_data8": 255, 518 "name": "fake_l2esr_4", 519 "ret_bad_addr": false, 520 "pio_size": 8, 521 "p_state_clk_gate_bins": 20 |
522 }, 523 "fake_clk": {
|
452 "system": "system",
453 "ret_data8": 255,
454 "name": "fake_clk",
455 "warn_access": "",
|
524 "pio": { 525 "peer": "system.iobus.master[0]", 526 "role": "SLAVE" 527 },
|
460 "ret_bad_addr": false,
461 "pio_latency": 200,
462 "clk_domain": "system.clk_domain",
463 "fake_mem": false,
464 "pio_size": 4294967296,
465 "ret_data32": 4294967295,
466 "eventq_index": 0,
467 "update_data": false,
|
528 "ret_data64": 18446744073709551615,
|
529 "fake_mem": false, 530 "clk_domain": "system.clk_domain", |
531 "cxx_class": "IsaFake",
|
470 "path": "system.t1000.fake_clk",
|
532 "pio_addr": 644245094400,
|
533 "update_data": false, 534 "warn_access": "", 535 "pio_latency": 200, 536 "system": "system", 537 "eventq_index": 0, 538 "default_p_state": "UNDEFINED", 539 "p_state_clk_gate_max": 2000000000, |
540 "type": "IsaFake",
|
473 "ret_data16": 65535
|
541 "p_state_clk_gate_min": 2, 542 "ret_data32": 4294967295, 543 "path": "system.t1000.fake_clk", 544 "ret_data16": 65535, 545 "ret_data8": 255, 546 "name": "fake_clk", 547 "ret_bad_addr": false, 548 "pio_size": 4294967296, 549 "p_state_clk_gate_bins": 20 |
550 } 551 }, 552 "partition_desc_addr": 133445976064, 553 "symbolfile": "",
|
478 "readfile": "/z/stever/hg/gem5/tests/halt.sh",
|
554 "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh", 555 "thermal_model": null, |
556 "hypervisor_addr": 1099243257856, 557 "mem_ranges": [ 558 "1048576:68157439", 559 "2147483648:2415919103" 560 ], 561 "cxx_class": "SparcSystem",
|
562 "work_begin_cpu_id_exit": -1, |
563 "load_offset": 0,
|
486 "reset_bin": "/dist/m5/system/binaries/reset_new.bin",
487 "openboot_addr": 1099243716608,
|
564 "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin", |
565 "work_end_ckpt_count": 0,
|
566 "work_begin_exit_count": 0, 567 "openboot_addr": 1099243716608, 568 "p_state_clk_gate_min": 2, |
569 "nvram_addr": 133429198848, 570 "memories": [ 571 "system.hypervisor_desc", 572 "system.nvram", 573 "system.partition_desc", 574 "system.physmem0", 575 "system.physmem1", 576 "system.rom" 577 ], 578 "work_begin_ckpt_count": 0, 579 "partition_desc": { 580 "range": "133445976064:133445984255", 581 "latency": 60, 582 "name": "partition_desc",
|
583 "p_state_clk_gate_min": 2, |
584 "eventq_index": 0,
|
585 "p_state_clk_gate_bins": 20, 586 "default_p_state": "UNDEFINED", |
587 "clk_domain": "system.clk_domain", 588 "latency_var": 0, 589 "bandwidth": "0.000000", 590 "conf_table_reported": true, 591 "cxx_class": "SimpleMemory",
|
592 "p_state_clk_gate_max": 2000000000, |
593 "path": "system.partition_desc", 594 "null": false, 595 "type": "SimpleMemory", 596 "port": { 597 "peer": "system.membus.master[6]", 598 "role": "SLAVE" 599 }, 600 "in_addr_map": true 601 }, 602 "clk_domain": { 603 "name": "clk_domain", 604 "clock": [ 605 2 606 ], 607 "init_perf_level": 0, 608 "voltage_domain": "system.voltage_domain", 609 "eventq_index": 0, 610 "cxx_class": "SrcClockDomain", 611 "path": "system.clk_domain", 612 "type": "SrcClockDomain", 613 "domain_id": -1 614 }, 615 "hypervisor_desc": { 616 "range": "133446500352:133446508543", 617 "latency": 60, 618 "name": "hypervisor_desc",
|
619 "p_state_clk_gate_min": 2, |
620 "eventq_index": 0,
|
621 "p_state_clk_gate_bins": 20, 622 "default_p_state": "UNDEFINED", |
623 "clk_domain": "system.clk_domain", 624 "latency_var": 0, 625 "bandwidth": "0.000000", 626 "conf_table_reported": true, 627 "cxx_class": "SimpleMemory",
|
628 "p_state_clk_gate_max": 2000000000, |
629 "path": "system.hypervisor_desc", 630 "null": false, 631 "type": "SimpleMemory", 632 "port": { 633 "peer": "system.membus.master[5]", 634 "role": "SLAVE" 635 }, 636 "in_addr_map": true 637 }, 638 "membus": {
|
551 "default": {
552 "peer": "system.membus.badaddr_responder.pio",
553 "role": "MASTER"
554 },
555 "slave": {
556 "peer": [
557 "system.system_port",
558 "system.cpu.icache_port",
559 "system.cpu.dcache_port"
560 ],
561 "role": "SLAVE"
562 },
563 "name": "membus",
|
639 "point_of_coherency": true, 640 "system": "system", 641 "response_latency": 2, 642 "cxx_class": "CoherentXBar", |
643 "badaddr_responder": {
|
565 "system": "system",
566 "ret_data8": 255,
567 "name": "badaddr_responder",
568 "warn_access": "",
|
644 "pio": { 645 "peer": "system.membus.default", 646 "role": "SLAVE" 647 },
|
573 "ret_bad_addr": true,
574 "pio_latency": 200,
575 "clk_domain": "system.clk_domain",
576 "fake_mem": false,
577 "pio_size": 8,
578 "ret_data32": 4294967295,
579 "eventq_index": 0,
580 "update_data": false,
|
648 "ret_data64": 18446744073709551615,
|
649 "fake_mem": false, 650 "clk_domain": "system.clk_domain", |
651 "cxx_class": "IsaFake",
|
583 "path": "system.membus.badaddr_responder",
|
652 "pio_addr": 0,
|
653 "update_data": false, 654 "warn_access": "", 655 "pio_latency": 200, 656 "system": "system", 657 "eventq_index": 0, 658 "default_p_state": "UNDEFINED", 659 "p_state_clk_gate_max": 2000000000, |
660 "type": "IsaFake",
|
586 "ret_data16": 65535
|
661 "p_state_clk_gate_min": 2, 662 "ret_data32": 4294967295, 663 "path": "system.membus.badaddr_responder", 664 "ret_data16": 65535, 665 "ret_data8": 255, 666 "name": "badaddr_responder", 667 "ret_bad_addr": true, 668 "pio_size": 8, 669 "p_state_clk_gate_bins": 20 |
670 },
|
588 "snoop_filter": null,
|
671 "forward_latency": 4, 672 "clk_domain": "system.clk_domain",
|
591 "system": "system",
|
673 "width": 16, 674 "eventq_index": 0,
|
675 "default_p_state": "UNDEFINED", 676 "p_state_clk_gate_max": 2000000000, |
677 "master": { 678 "peer": [ 679 "system.t1000.iob.pio", 680 "system.t1000.htod.pio", 681 "system.bridge.slave", 682 "system.rom.port", 683 "system.nvram.port", 684 "system.hypervisor_desc.port", 685 "system.partition_desc.port", 686 "system.physmem0.port", 687 "system.physmem1.port" 688 ], 689 "role": "MASTER" 690 },
|
608 "response_latency": 2,
609 "cxx_class": "CoherentXBar",
|
691 "type": "CoherentXBar", 692 "frontend_latency": 3, 693 "slave": { 694 "peer": [ 695 "system.system_port", 696 "system.cpu.icache_port", 697 "system.cpu.dcache_port" 698 ], 699 "role": "SLAVE" 700 }, 701 "p_state_clk_gate_min": 2, 702 "snoop_filter": null, |
703 "path": "system.membus", 704 "snoop_response_latency": 4,
|
612 "type": "CoherentXBar",
613 "use_default_range": false,
614 "frontend_latency": 3
|
705 "name": "membus", 706 "default": { 707 "peer": "system.membus.badaddr_responder.pio", 708 "role": "MASTER" 709 }, 710 "p_state_clk_gate_bins": 20, 711 "use_default_range": false |
712 }, 713 "nvram": { 714 "range": "133429198848:133429207039", 715 "latency": 60, 716 "name": "nvram",
|
717 "p_state_clk_gate_min": 2, |
718 "eventq_index": 0,
|
719 "p_state_clk_gate_bins": 20, 720 "default_p_state": "UNDEFINED", |
721 "clk_domain": "system.clk_domain", 722 "latency_var": 0, 723 "bandwidth": "0.000000", 724 "conf_table_reported": true, 725 "cxx_class": "SimpleMemory",
|
726 "p_state_clk_gate_max": 2000000000, |
727 "path": "system.nvram", 728 "null": false, 729 "type": "SimpleMemory", 730 "port": { 731 "peer": "system.membus.master[4]", 732 "role": "SLAVE" 733 }, 734 "in_addr_map": true 735 }, 736 "eventq_index": 0,
|
636 "work_begin_cpu_id_exit": -1,
|
737 "default_p_state": "UNDEFINED", 738 "p_state_clk_gate_max": 2000000000, |
739 "dvfs_handler": { 740 "enable": false, 741 "name": "dvfs_handler", 742 "sys_clk_domain": "system.clk_domain", 743 "transition_latency": 200000, 744 "eventq_index": 0, 745 "cxx_class": "DVFSHandler", 746 "domains": [], 747 "path": "system.dvfs_handler", 748 "type": "DVFSHandler" 749 }, 750 "work_end_exit_count": 0,
|
649 "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin",
650 "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin",
|
751 "hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin", 752 "openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin", |
753 "voltage_domain": { 754 "name": "voltage_domain", 755 "eventq_index": 0, 756 "voltage": [ 757 "1.0" 758 ], 759 "cxx_class": "VoltageDomain", 760 "path": "system.voltage_domain", 761 "type": "VoltageDomain" 762 }, 763 "cache_line_size": 64, 764 "boot_osflags": "a", 765 "system_port": { 766 "peer": "system.membus.slave[0]", 767 "role": "MASTER" 768 }, 769 "physmem": [ 770 { 771 "range": "1048576:68157439", 772 "latency": 60, 773 "name": "physmem0",
|
774 "p_state_clk_gate_min": 2, |
775 "eventq_index": 0,
|
776 "p_state_clk_gate_bins": 20, 777 "default_p_state": "UNDEFINED", |
778 "clk_domain": "system.clk_domain", 779 "latency_var": 0, 780 "bandwidth": "0.000000", 781 "conf_table_reported": true, 782 "cxx_class": "SimpleMemory",
|
783 "p_state_clk_gate_max": 2000000000, |
784 "path": "system.physmem0", 785 "null": false, 786 "type": "SimpleMemory", 787 "port": { 788 "peer": "system.membus.master[7]", 789 "role": "SLAVE" 790 }, 791 "in_addr_map": true 792 }, 793 { 794 "range": "2147483648:2415919103", 795 "latency": 60, 796 "name": "physmem1",
|
797 "p_state_clk_gate_min": 2, |
798 "eventq_index": 0,
|
799 "p_state_clk_gate_bins": 20, 800 "default_p_state": "UNDEFINED", |
801 "clk_domain": "system.clk_domain", 802 "latency_var": 0, 803 "bandwidth": "0.000000", 804 "conf_table_reported": true, 805 "cxx_class": "SimpleMemory",
|
806 "p_state_clk_gate_max": 2000000000, |
807 "path": "system.physmem1", 808 "null": false, 809 "type": "SimpleMemory", 810 "port": { 811 "peer": "system.membus.master[8]", 812 "role": "SLAVE" 813 }, 814 "in_addr_map": true 815 } 816 ], 817 "work_cpus_ckpt_count": 0,
|
708 "work_begin_exit_count": 0,
|
818 "thermal_components": [], |
819 "path": "system",
|
710 "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin",
|
820 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin", |
821 "cpu_clk_domain": { 822 "name": "cpu_clk_domain", 823 "clock": [ 824 2 825 ], 826 "init_perf_level": 0, 827 "voltage_domain": "system.voltage_domain", 828 "eventq_index": 0, 829 "cxx_class": "SrcClockDomain", 830 "path": "system.cpu_clk_domain", 831 "type": "SrcClockDomain", 832 "domain_id": -1 833 },
|
724 "nvram_bin": "/dist/m5/system/binaries/nvram1",
|
834 "nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1", |
835 "mem_mode": "atomic", 836 "name": "system", 837 "init_param": 0, 838 "type": "SparcSystem",
|
729 "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin",
|
839 "partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin", |
840 "load_addr_mask": 1099511627775, 841 "cpu": { 842 "do_statistics_insts": true, 843 "numThreads": 1, 844 "itb": { 845 "name": "itb", 846 "eventq_index": 0, 847 "cxx_class": "SparcISA::TLB", 848 "path": "system.cpu.itb", 849 "type": "SparcTLB", 850 "size": 64 851 }, 852 "simulate_data_stalls": false, 853 "function_trace": false, 854 "do_checkpoint_insts": true, 855 "cxx_class": "AtomicSimpleCPU", 856 "max_loads_all_threads": 0, 857 "system": "system", 858 "clk_domain": "system.cpu_clk_domain", 859 "function_trace_start": 0, 860 "cpu_id": 0, 861 "width": 1, 862 "checker": null, 863 "eventq_index": 0,
|
864 "default_p_state": "UNDEFINED", 865 "p_state_clk_gate_max": 2000000000, |
866 "do_quiesce": true, 867 "type": "AtomicSimpleCPU", 868 "fastmem": false, 869 "profile": 0, 870 "icache_port": { 871 "peer": "system.membus.slave[1]", 872 "role": "MASTER" 873 },
|
874 "p_state_clk_gate_bins": 20, 875 "p_state_clk_gate_min": 2, |
876 "interrupts": [ 877 { 878 "eventq_index": 0, 879 "path": "system.cpu.interrupts", 880 "type": "SparcInterrupts", 881 "name": "interrupts", 882 "cxx_class": "SparcISA::Interrupts" 883 } 884 ], 885 "dcache_port": { 886 "peer": "system.membus.slave[2]", 887 "role": "MASTER" 888 }, 889 "socket_id": 0, 890 "max_insts_all_threads": 0, 891 "path": "system.cpu", 892 "max_loads_any_thread": 0, 893 "switched_out": false, 894 "workload": [], 895 "name": "cpu", 896 "dtb": { 897 "name": "dtb", 898 "eventq_index": 0, 899 "cxx_class": "SparcISA::TLB", 900 "path": "system.cpu.dtb", 901 "type": "SparcTLB", 902 "size": 64 903 }, 904 "simpoint_start_insts": [], 905 "max_insts_any_thread": 0, 906 "simulate_inst_stalls": false, 907 "progress_interval": 0, 908 "branchPred": null, 909 "isa": [ 910 { 911 "eventq_index": 0, 912 "path": "system.cpu.isa", 913 "type": "SparcISA", 914 "name": "isa", 915 "cxx_class": "SparcISA::ISA" 916 } 917 ], 918 "tracer": { 919 "eventq_index": 0, 920 "path": "system.cpu.tracer", 921 "type": "ExeTracer", 922 "name": "tracer", 923 "cxx_class": "Trace::ExeTracer" 924 } 925 }, 926 "intrctrl": { 927 "name": "intrctrl", 928 "sys": "system", 929 "eventq_index": 0, 930 "cxx_class": "IntrControl", 931 "path": "system.intrctrl", 932 "type": "IntrControl" 933 }, 934 "disk0": { 935 "name": "disk0",
|
936 "p_state_clk_gate_min": 2, |
937 "pio": { 938 "peer": "system.iobus.master[14]", 939 "role": "SLAVE" 940 },
|
941 "p_state_clk_gate_bins": 20, |
942 "image": { 943 "read_only": false, 944 "name": "image", 945 "cxx_class": "CowDiskImage", 946 "eventq_index": 0, 947 "child": { 948 "read_only": true, 949 "name": "child", 950 "eventq_index": 0, 951 "cxx_class": "RawDiskImage", 952 "path": "system.disk0.image.child",
|
837 "image_file": "/dist/m5/system/disks/disk.s10hw2",
|
953 "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2", |
954 "type": "RawDiskImage" 955 }, 956 "path": "system.disk0.image", 957 "image_file": "", 958 "type": "CowDiskImage", 959 "table_size": 65536 960 },
|
961 "cxx_class": "MmDisk", |
962 "pio_latency": 200, 963 "clk_domain": "system.clk_domain", 964 "system": "system", 965 "eventq_index": 0,
|
849 "cxx_class": "MmDisk",
|
966 "default_p_state": "UNDEFINED", 967 "p_state_clk_gate_max": 2000000000, |
968 "path": "system.disk0", 969 "pio_addr": 134217728000, 970 "type": "MmDisk" 971 }, 972 "multi_thread": false, 973 "reset_addr": 1099243192320,
|
974 "p_state_clk_gate_bins": 20, |
975 "hypervisor_desc_addr": 133446500352, 976 "num_work_ids": 16, 977 "work_item_id": -1, 978 "exit_on_work_items": false 979 }, 980 "time_sync_period": 200000000, 981 "eventq_index": 0, 982 "time_sync_spin_threshold": 200000, 983 "cxx_class": "Root", 984 "path": "root", 985 "time_sync_enable": false, 986 "type": "Root", 987 "full_system": true 988}
|