1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { 5 "kernel": "", 6 "mmap_using_noreserve": false, 7 "kernel_addr_check": true, 8 "rom": { |
9 "range": "1099243192320:1099251580927:0:0:0:0", |
10 "latency": 60, 11 "name": "rom", 12 "p_state_clk_gate_min": 2, 13 "eventq_index": 0, 14 "p_state_clk_gate_bins": 20, 15 "default_p_state": "UNDEFINED", |
16 "kvm_map": true, |
17 "clk_domain": "system.clk_domain", 18 "power_model": null, 19 "latency_var": 0, 20 "bandwidth": "0.000000", 21 "conf_table_reported": true, 22 "cxx_class": "SimpleMemory", 23 "p_state_clk_gate_max": 2000000000, 24 "path": "system.rom", 25 "null": false, 26 "type": "SimpleMemory", 27 "port": { 28 "peer": "system.membus.master[3]", 29 "role": "SLAVE" 30 }, 31 "in_addr_map": true 32 }, 33 "bridge": { 34 "ranges": [ |
35 "133412421632:133412421639:0:0:0:0", 36 "134217728000:554050781183:0:0:0:0", 37 "644245094400:652835028991:0:0:0:0", 38 "725849473024:1095485095935:0:0:0:0", 39 "1099255955456:1099255955463:0:0:0:0" |
40 ], 41 "slave": { 42 "peer": "system.membus.master[2]", 43 "role": "SLAVE" 44 }, 45 "name": "bridge", 46 "p_state_clk_gate_min": 2, 47 "p_state_clk_gate_bins": 20, --- 522 unchanged lines hidden (view full) --- 570 } 571 }, 572 "partition_desc_addr": 133445976064, 573 "symbolfile": "", 574 "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh", 575 "thermal_model": null, 576 "hypervisor_addr": 1099243257856, 577 "mem_ranges": [ |
578 "1048576:68157439:0:0:0:0", 579 "2147483648:2415919103:0:0:0:0" |
580 ], 581 "cxx_class": "SparcSystem", 582 "work_begin_cpu_id_exit": -1, 583 "load_offset": 0, 584 "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin", 585 "work_end_ckpt_count": 0, 586 "work_begin_exit_count": 0, 587 "openboot_addr": 1099243716608, --- 4 unchanged lines hidden (view full) --- 592 "system.nvram", 593 "system.partition_desc", 594 "system.physmem0", 595 "system.physmem1", 596 "system.rom" 597 ], 598 "work_begin_ckpt_count": 0, 599 "partition_desc": { |
600 "range": "133445976064:133445984255:0:0:0:0", |
601 "latency": 60, 602 "name": "partition_desc", 603 "p_state_clk_gate_min": 2, 604 "eventq_index": 0, 605 "p_state_clk_gate_bins": 20, 606 "default_p_state": "UNDEFINED", |
607 "kvm_map": true, |
608 "clk_domain": "system.clk_domain", 609 "power_model": null, 610 "latency_var": 0, 611 "bandwidth": "0.000000", 612 "conf_table_reported": true, 613 "cxx_class": "SimpleMemory", 614 "p_state_clk_gate_max": 2000000000, 615 "path": "system.partition_desc", --- 14 unchanged lines hidden (view full) --- 630 "voltage_domain": "system.voltage_domain", 631 "eventq_index": 0, 632 "cxx_class": "SrcClockDomain", 633 "path": "system.clk_domain", 634 "type": "SrcClockDomain", 635 "domain_id": -1 636 }, 637 "hypervisor_desc": { |
638 "range": "133446500352:133446508543:0:0:0:0", |
639 "latency": 60, 640 "name": "hypervisor_desc", 641 "p_state_clk_gate_min": 2, 642 "eventq_index": 0, 643 "p_state_clk_gate_bins": 20, 644 "default_p_state": "UNDEFINED", |
645 "kvm_map": true, |
646 "clk_domain": "system.clk_domain", 647 "power_model": null, 648 "latency_var": 0, 649 "bandwidth": "0.000000", 650 "conf_table_reported": true, 651 "cxx_class": "SimpleMemory", 652 "p_state_clk_gate_max": 2000000000, 653 "path": "system.hypervisor_desc", --- 87 unchanged lines hidden (view full) --- 741 "default": { 742 "peer": "system.membus.badaddr_responder.pio", 743 "role": "MASTER" 744 }, 745 "p_state_clk_gate_bins": 20, 746 "use_default_range": false 747 }, 748 "nvram": { |
749 "range": "133429198848:133429207039:0:0:0:0", |
750 "latency": 60, 751 "name": "nvram", 752 "p_state_clk_gate_min": 2, 753 "eventq_index": 0, 754 "p_state_clk_gate_bins": 20, 755 "default_p_state": "UNDEFINED", |
756 "kvm_map": true, |
757 "clk_domain": "system.clk_domain", 758 "power_model": null, 759 "latency_var": 0, 760 "bandwidth": "0.000000", 761 "conf_table_reported": true, 762 "cxx_class": "SimpleMemory", 763 "p_state_clk_gate_max": 2000000000, 764 "path": "system.nvram", --- 35 unchanged lines hidden (view full) --- 800 "cache_line_size": 64, 801 "boot_osflags": "a", 802 "system_port": { 803 "peer": "system.membus.slave[0]", 804 "role": "MASTER" 805 }, 806 "physmem": [ 807 { |
808 "range": "1048576:68157439:0:0:0:0", |
809 "latency": 60, 810 "name": "physmem0", 811 "p_state_clk_gate_min": 2, 812 "eventq_index": 0, 813 "p_state_clk_gate_bins": 20, 814 "default_p_state": "UNDEFINED", |
815 "kvm_map": true, |
816 "clk_domain": "system.clk_domain", 817 "power_model": null, 818 "latency_var": 0, 819 "bandwidth": "0.000000", 820 "conf_table_reported": true, 821 "cxx_class": "SimpleMemory", 822 "p_state_clk_gate_max": 2000000000, 823 "path": "system.physmem0", 824 "null": false, 825 "type": "SimpleMemory", 826 "port": { 827 "peer": "system.membus.master[7]", 828 "role": "SLAVE" 829 }, 830 "in_addr_map": true 831 }, 832 { |
833 "range": "2147483648:2415919103:0:0:0:0", |
834 "latency": 60, 835 "name": "physmem1", 836 "p_state_clk_gate_min": 2, 837 "eventq_index": 0, 838 "p_state_clk_gate_bins": 20, 839 "default_p_state": "UNDEFINED", |
840 "kvm_map": true, |
841 "clk_domain": "system.clk_domain", 842 "power_model": null, 843 "latency_var": 0, 844 "bandwidth": "0.000000", 845 "conf_table_reported": true, 846 "cxx_class": "SimpleMemory", 847 "p_state_clk_gate_max": 2000000000, 848 "path": "system.physmem1", --- 184 unchanged lines hidden --- |