1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
| 1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
|
9 "range": "1099243192320:1099251580927",
| 9 "range": "1099243192320:1099251580927:0:0:0:0",
|
10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
| 10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
|
| 16 "kvm_map": true,
|
16 "clk_domain": "system.clk_domain",
17 "power_model": null,
18 "latency_var": 0,
19 "bandwidth": "0.000000",
20 "conf_table_reported": true,
21 "cxx_class": "SimpleMemory",
22 "p_state_clk_gate_max": 2000000000,
23 "path": "system.rom",
24 "null": false,
25 "type": "SimpleMemory",
26 "port": {
27 "peer": "system.membus.master[3]",
28 "role": "SLAVE"
29 },
30 "in_addr_map": true
31 },
32 "bridge": {
33 "ranges": [
| 17 "clk_domain": "system.clk_domain",
18 "power_model": null,
19 "latency_var": 0,
20 "bandwidth": "0.000000",
21 "conf_table_reported": true,
22 "cxx_class": "SimpleMemory",
23 "p_state_clk_gate_max": 2000000000,
24 "path": "system.rom",
25 "null": false,
26 "type": "SimpleMemory",
27 "port": {
28 "peer": "system.membus.master[3]",
29 "role": "SLAVE"
30 },
31 "in_addr_map": true
32 },
33 "bridge": {
34 "ranges": [
|
34 "133412421632:133412421639",
35 "134217728000:554050781183",
36 "644245094400:652835028991",
37 "725849473024:1095485095935",
38 "1099255955456:1099255955463"
| 35 "133412421632:133412421639:0:0:0:0",
36 "134217728000:554050781183:0:0:0:0",
37 "644245094400:652835028991:0:0:0:0",
38 "725849473024:1095485095935:0:0:0:0",
39 "1099255955456:1099255955463:0:0:0:0"
|
39 ],
40 "slave": {
41 "peer": "system.membus.master[2]",
42 "role": "SLAVE"
43 },
44 "name": "bridge",
45 "p_state_clk_gate_min": 2,
46 "p_state_clk_gate_bins": 20,
47 "cxx_class": "Bridge",
48 "req_size": 16,
49 "clk_domain": "system.clk_domain",
50 "power_model": null,
51 "delay": 100,
52 "eventq_index": 0,
53 "master": {
54 "peer": "system.iobus.slave[0]",
55 "role": "MASTER"
56 },
57 "default_p_state": "UNDEFINED",
58 "p_state_clk_gate_max": 2000000000,
59 "path": "system.bridge",
60 "resp_size": 16,
61 "type": "Bridge"
62 },
63 "iobus": {
64 "forward_latency": 1,
65 "slave": {
66 "peer": [
67 "system.bridge.master"
68 ],
69 "role": "SLAVE"
70 },
71 "name": "iobus",
72 "p_state_clk_gate_min": 2,
73 "p_state_clk_gate_bins": 20,
74 "cxx_class": "NoncoherentXBar",
75 "clk_domain": "system.clk_domain",
76 "power_model": null,
77 "width": 16,
78 "eventq_index": 0,
79 "master": {
80 "peer": [
81 "system.t1000.fake_clk.pio",
82 "system.t1000.fake_membnks.pio",
83 "system.t1000.fake_l2_1.pio",
84 "system.t1000.fake_l2_2.pio",
85 "system.t1000.fake_l2_3.pio",
86 "system.t1000.fake_l2_4.pio",
87 "system.t1000.fake_l2esr_1.pio",
88 "system.t1000.fake_l2esr_2.pio",
89 "system.t1000.fake_l2esr_3.pio",
90 "system.t1000.fake_l2esr_4.pio",
91 "system.t1000.fake_ssi.pio",
92 "system.t1000.fake_jbi.pio",
93 "system.t1000.puart0.pio",
94 "system.t1000.hvuart.pio",
95 "system.disk0.pio"
96 ],
97 "role": "MASTER"
98 },
99 "response_latency": 2,
100 "default_p_state": "UNDEFINED",
101 "p_state_clk_gate_max": 2000000000,
102 "path": "system.iobus",
103 "type": "NoncoherentXBar",
104 "use_default_range": false,
105 "frontend_latency": 2
106 },
107 "t1000": {
108 "htod": {
109 "name": "htod",
110 "p_state_clk_gate_min": 2,
111 "pio": {
112 "peer": "system.membus.master[1]",
113 "role": "SLAVE"
114 },
115 "p_state_clk_gate_bins": 20,
116 "cxx_class": "DumbTOD",
117 "pio_latency": 200,
118 "clk_domain": "system.clk_domain",
119 "power_model": null,
120 "system": "system",
121 "eventq_index": 0,
122 "time": "Thu Jan 1 00:00:00 2009",
123 "default_p_state": "UNDEFINED",
124 "p_state_clk_gate_max": 2000000000,
125 "path": "system.t1000.htod",
126 "pio_addr": 1099255906296,
127 "type": "DumbTOD"
128 },
129 "puart0": {
130 "name": "puart0",
131 "p_state_clk_gate_min": 2,
132 "pio": {
133 "peer": "system.iobus.master[12]",
134 "role": "SLAVE"
135 },
136 "p_state_clk_gate_bins": 20,
137 "cxx_class": "Uart8250",
138 "pio_latency": 200,
139 "clk_domain": "system.clk_domain",
140 "power_model": null,
141 "system": "system",
142 "terminal": "system.t1000.pterm",
143 "platform": "system.t1000",
144 "eventq_index": 0,
145 "default_p_state": "UNDEFINED",
146 "p_state_clk_gate_max": 2000000000,
147 "path": "system.t1000.puart0",
148 "pio_addr": 133412421632,
149 "type": "Uart8250"
150 },
151 "fake_membnks": {
152 "pio": {
153 "peer": "system.iobus.master[1]",
154 "role": "SLAVE"
155 },
156 "ret_data64": 0,
157 "fake_mem": false,
158 "clk_domain": "system.clk_domain",
159 "cxx_class": "IsaFake",
160 "pio_addr": 648540061696,
161 "update_data": false,
162 "warn_access": "",
163 "pio_latency": 200,
164 "system": "system",
165 "eventq_index": 0,
166 "default_p_state": "UNDEFINED",
167 "p_state_clk_gate_max": 2000000000,
168 "type": "IsaFake",
169 "p_state_clk_gate_min": 2,
170 "power_model": null,
171 "ret_data32": 4294967295,
172 "path": "system.t1000.fake_membnks",
173 "ret_data16": 65535,
174 "ret_data8": 255,
175 "name": "fake_membnks",
176 "ret_bad_addr": false,
177 "pio_size": 16384,
178 "p_state_clk_gate_bins": 20
179 },
180 "cxx_class": "T1000",
181 "fake_jbi": {
182 "pio": {
183 "peer": "system.iobus.master[11]",
184 "role": "SLAVE"
185 },
186 "ret_data64": 18446744073709551615,
187 "fake_mem": false,
188 "clk_domain": "system.clk_domain",
189 "cxx_class": "IsaFake",
190 "pio_addr": 549755813888,
191 "update_data": false,
192 "warn_access": "",
193 "pio_latency": 200,
194 "system": "system",
195 "eventq_index": 0,
196 "default_p_state": "UNDEFINED",
197 "p_state_clk_gate_max": 2000000000,
198 "type": "IsaFake",
199 "p_state_clk_gate_min": 2,
200 "power_model": null,
201 "ret_data32": 4294967295,
202 "path": "system.t1000.fake_jbi",
203 "ret_data16": 65535,
204 "ret_data8": 255,
205 "name": "fake_jbi",
206 "ret_bad_addr": false,
207 "pio_size": 4294967296,
208 "p_state_clk_gate_bins": 20
209 },
210 "intrctrl": "system.intrctrl",
211 "fake_l2esr_2": {
212 "pio": {
213 "peer": "system.iobus.master[7]",
214 "role": "SLAVE"
215 },
216 "ret_data64": 0,
217 "fake_mem": false,
218 "clk_domain": "system.clk_domain",
219 "cxx_class": "IsaFake",
220 "pio_addr": 734439407680,
221 "update_data": true,
222 "warn_access": "",
223 "pio_latency": 200,
224 "system": "system",
225 "eventq_index": 0,
226 "default_p_state": "UNDEFINED",
227 "p_state_clk_gate_max": 2000000000,
228 "type": "IsaFake",
229 "p_state_clk_gate_min": 2,
230 "power_model": null,
231 "ret_data32": 4294967295,
232 "path": "system.t1000.fake_l2esr_2",
233 "ret_data16": 65535,
234 "ret_data8": 255,
235 "name": "fake_l2esr_2",
236 "ret_bad_addr": false,
237 "pio_size": 8,
238 "p_state_clk_gate_bins": 20
239 },
240 "system": "system",
241 "eventq_index": 0,
242 "hterm": {
243 "name": "hterm",
244 "output": true,
245 "number": 0,
246 "intr_control": "system.intrctrl",
247 "eventq_index": 0,
248 "cxx_class": "Terminal",
249 "path": "system.t1000.hterm",
250 "type": "Terminal",
251 "port": 3456
252 },
253 "type": "T1000",
254 "fake_l2_4": {
255 "pio": {
256 "peer": "system.iobus.master[5]",
257 "role": "SLAVE"
258 },
259 "ret_data64": 1,
260 "fake_mem": false,
261 "clk_domain": "system.clk_domain",
262 "cxx_class": "IsaFake",
263 "pio_addr": 725849473216,
264 "update_data": true,
265 "warn_access": "",
266 "pio_latency": 200,
267 "system": "system",
268 "eventq_index": 0,
269 "default_p_state": "UNDEFINED",
270 "p_state_clk_gate_max": 2000000000,
271 "type": "IsaFake",
272 "p_state_clk_gate_min": 2,
273 "power_model": null,
274 "ret_data32": 4294967295,
275 "path": "system.t1000.fake_l2_4",
276 "ret_data16": 65535,
277 "ret_data8": 255,
278 "name": "fake_l2_4",
279 "ret_bad_addr": false,
280 "pio_size": 8,
281 "p_state_clk_gate_bins": 20
282 },
283 "fake_l2_1": {
284 "pio": {
285 "peer": "system.iobus.master[2]",
286 "role": "SLAVE"
287 },
288 "ret_data64": 1,
289 "fake_mem": false,
290 "clk_domain": "system.clk_domain",
291 "cxx_class": "IsaFake",
292 "pio_addr": 725849473024,
293 "update_data": true,
294 "warn_access": "",
295 "pio_latency": 200,
296 "system": "system",
297 "eventq_index": 0,
298 "default_p_state": "UNDEFINED",
299 "p_state_clk_gate_max": 2000000000,
300 "type": "IsaFake",
301 "p_state_clk_gate_min": 2,
302 "power_model": null,
303 "ret_data32": 4294967295,
304 "path": "system.t1000.fake_l2_1",
305 "ret_data16": 65535,
306 "ret_data8": 255,
307 "name": "fake_l2_1",
308 "ret_bad_addr": false,
309 "pio_size": 8,
310 "p_state_clk_gate_bins": 20
311 },
312 "fake_l2_2": {
313 "pio": {
314 "peer": "system.iobus.master[3]",
315 "role": "SLAVE"
316 },
317 "ret_data64": 1,
318 "fake_mem": false,
319 "clk_domain": "system.clk_domain",
320 "cxx_class": "IsaFake",
321 "pio_addr": 725849473088,
322 "update_data": true,
323 "warn_access": "",
324 "pio_latency": 200,
325 "system": "system",
326 "eventq_index": 0,
327 "default_p_state": "UNDEFINED",
328 "p_state_clk_gate_max": 2000000000,
329 "type": "IsaFake",
330 "p_state_clk_gate_min": 2,
331 "power_model": null,
332 "ret_data32": 4294967295,
333 "path": "system.t1000.fake_l2_2",
334 "ret_data16": 65535,
335 "ret_data8": 255,
336 "name": "fake_l2_2",
337 "ret_bad_addr": false,
338 "pio_size": 8,
339 "p_state_clk_gate_bins": 20
340 },
341 "fake_l2_3": {
342 "pio": {
343 "peer": "system.iobus.master[4]",
344 "role": "SLAVE"
345 },
346 "ret_data64": 1,
347 "fake_mem": false,
348 "clk_domain": "system.clk_domain",
349 "cxx_class": "IsaFake",
350 "pio_addr": 725849473152,
351 "update_data": true,
352 "warn_access": "",
353 "pio_latency": 200,
354 "system": "system",
355 "eventq_index": 0,
356 "default_p_state": "UNDEFINED",
357 "p_state_clk_gate_max": 2000000000,
358 "type": "IsaFake",
359 "p_state_clk_gate_min": 2,
360 "power_model": null,
361 "ret_data32": 4294967295,
362 "path": "system.t1000.fake_l2_3",
363 "ret_data16": 65535,
364 "ret_data8": 255,
365 "name": "fake_l2_3",
366 "ret_bad_addr": false,
367 "pio_size": 8,
368 "p_state_clk_gate_bins": 20
369 },
370 "pterm": {
371 "name": "pterm",
372 "output": true,
373 "number": 0,
374 "intr_control": "system.intrctrl",
375 "eventq_index": 0,
376 "cxx_class": "Terminal",
377 "path": "system.t1000.pterm",
378 "type": "Terminal",
379 "port": 3456
380 },
381 "path": "system.t1000",
382 "iob": {
383 "name": "iob",
384 "p_state_clk_gate_min": 2,
385 "pio": {
386 "peer": "system.membus.master[0]",
387 "role": "SLAVE"
388 },
389 "p_state_clk_gate_bins": 20,
390 "cxx_class": "Iob",
391 "pio_latency": 2,
392 "clk_domain": "system.clk_domain",
393 "power_model": null,
394 "system": "system",
395 "platform": "system.t1000",
396 "eventq_index": 0,
397 "default_p_state": "UNDEFINED",
398 "p_state_clk_gate_max": 2000000000,
399 "path": "system.t1000.iob",
400 "type": "Iob"
401 },
402 "hvuart": {
403 "name": "hvuart",
404 "p_state_clk_gate_min": 2,
405 "pio": {
406 "peer": "system.iobus.master[13]",
407 "role": "SLAVE"
408 },
409 "p_state_clk_gate_bins": 20,
410 "cxx_class": "Uart8250",
411 "pio_latency": 200,
412 "clk_domain": "system.clk_domain",
413 "power_model": null,
414 "system": "system",
415 "terminal": "system.t1000.hterm",
416 "platform": "system.t1000",
417 "eventq_index": 0,
418 "default_p_state": "UNDEFINED",
419 "p_state_clk_gate_max": 2000000000,
420 "path": "system.t1000.hvuart",
421 "pio_addr": 1099255955456,
422 "type": "Uart8250"
423 },
424 "name": "t1000",
425 "fake_l2esr_3": {
426 "pio": {
427 "peer": "system.iobus.master[8]",
428 "role": "SLAVE"
429 },
430 "ret_data64": 0,
431 "fake_mem": false,
432 "clk_domain": "system.clk_domain",
433 "cxx_class": "IsaFake",
434 "pio_addr": 734439407744,
435 "update_data": true,
436 "warn_access": "",
437 "pio_latency": 200,
438 "system": "system",
439 "eventq_index": 0,
440 "default_p_state": "UNDEFINED",
441 "p_state_clk_gate_max": 2000000000,
442 "type": "IsaFake",
443 "p_state_clk_gate_min": 2,
444 "power_model": null,
445 "ret_data32": 4294967295,
446 "path": "system.t1000.fake_l2esr_3",
447 "ret_data16": 65535,
448 "ret_data8": 255,
449 "name": "fake_l2esr_3",
450 "ret_bad_addr": false,
451 "pio_size": 8,
452 "p_state_clk_gate_bins": 20
453 },
454 "fake_ssi": {
455 "pio": {
456 "peer": "system.iobus.master[10]",
457 "role": "SLAVE"
458 },
459 "ret_data64": 18446744073709551615,
460 "fake_mem": false,
461 "clk_domain": "system.clk_domain",
462 "cxx_class": "IsaFake",
463 "pio_addr": 1095216660480,
464 "update_data": false,
465 "warn_access": "",
466 "pio_latency": 200,
467 "system": "system",
468 "eventq_index": 0,
469 "default_p_state": "UNDEFINED",
470 "p_state_clk_gate_max": 2000000000,
471 "type": "IsaFake",
472 "p_state_clk_gate_min": 2,
473 "power_model": null,
474 "ret_data32": 4294967295,
475 "path": "system.t1000.fake_ssi",
476 "ret_data16": 65535,
477 "ret_data8": 255,
478 "name": "fake_ssi",
479 "ret_bad_addr": false,
480 "pio_size": 268435456,
481 "p_state_clk_gate_bins": 20
482 },
483 "fake_l2esr_1": {
484 "pio": {
485 "peer": "system.iobus.master[6]",
486 "role": "SLAVE"
487 },
488 "ret_data64": 0,
489 "fake_mem": false,
490 "clk_domain": "system.clk_domain",
491 "cxx_class": "IsaFake",
492 "pio_addr": 734439407616,
493 "update_data": true,
494 "warn_access": "",
495 "pio_latency": 200,
496 "system": "system",
497 "eventq_index": 0,
498 "default_p_state": "UNDEFINED",
499 "p_state_clk_gate_max": 2000000000,
500 "type": "IsaFake",
501 "p_state_clk_gate_min": 2,
502 "power_model": null,
503 "ret_data32": 4294967295,
504 "path": "system.t1000.fake_l2esr_1",
505 "ret_data16": 65535,
506 "ret_data8": 255,
507 "name": "fake_l2esr_1",
508 "ret_bad_addr": false,
509 "pio_size": 8,
510 "p_state_clk_gate_bins": 20
511 },
512 "fake_l2esr_4": {
513 "pio": {
514 "peer": "system.iobus.master[9]",
515 "role": "SLAVE"
516 },
517 "ret_data64": 0,
518 "fake_mem": false,
519 "clk_domain": "system.clk_domain",
520 "cxx_class": "IsaFake",
521 "pio_addr": 734439407808,
522 "update_data": true,
523 "warn_access": "",
524 "pio_latency": 200,
525 "system": "system",
526 "eventq_index": 0,
527 "default_p_state": "UNDEFINED",
528 "p_state_clk_gate_max": 2000000000,
529 "type": "IsaFake",
530 "p_state_clk_gate_min": 2,
531 "power_model": null,
532 "ret_data32": 4294967295,
533 "path": "system.t1000.fake_l2esr_4",
534 "ret_data16": 65535,
535 "ret_data8": 255,
536 "name": "fake_l2esr_4",
537 "ret_bad_addr": false,
538 "pio_size": 8,
539 "p_state_clk_gate_bins": 20
540 },
541 "fake_clk": {
542 "pio": {
543 "peer": "system.iobus.master[0]",
544 "role": "SLAVE"
545 },
546 "ret_data64": 18446744073709551615,
547 "fake_mem": false,
548 "clk_domain": "system.clk_domain",
549 "cxx_class": "IsaFake",
550 "pio_addr": 644245094400,
551 "update_data": false,
552 "warn_access": "",
553 "pio_latency": 200,
554 "system": "system",
555 "eventq_index": 0,
556 "default_p_state": "UNDEFINED",
557 "p_state_clk_gate_max": 2000000000,
558 "type": "IsaFake",
559 "p_state_clk_gate_min": 2,
560 "power_model": null,
561 "ret_data32": 4294967295,
562 "path": "system.t1000.fake_clk",
563 "ret_data16": 65535,
564 "ret_data8": 255,
565 "name": "fake_clk",
566 "ret_bad_addr": false,
567 "pio_size": 4294967296,
568 "p_state_clk_gate_bins": 20
569 }
570 },
571 "partition_desc_addr": 133445976064,
572 "symbolfile": "",
573 "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh",
574 "thermal_model": null,
575 "hypervisor_addr": 1099243257856,
576 "mem_ranges": [
| 40 ],
41 "slave": {
42 "peer": "system.membus.master[2]",
43 "role": "SLAVE"
44 },
45 "name": "bridge",
46 "p_state_clk_gate_min": 2,
47 "p_state_clk_gate_bins": 20,
48 "cxx_class": "Bridge",
49 "req_size": 16,
50 "clk_domain": "system.clk_domain",
51 "power_model": null,
52 "delay": 100,
53 "eventq_index": 0,
54 "master": {
55 "peer": "system.iobus.slave[0]",
56 "role": "MASTER"
57 },
58 "default_p_state": "UNDEFINED",
59 "p_state_clk_gate_max": 2000000000,
60 "path": "system.bridge",
61 "resp_size": 16,
62 "type": "Bridge"
63 },
64 "iobus": {
65 "forward_latency": 1,
66 "slave": {
67 "peer": [
68 "system.bridge.master"
69 ],
70 "role": "SLAVE"
71 },
72 "name": "iobus",
73 "p_state_clk_gate_min": 2,
74 "p_state_clk_gate_bins": 20,
75 "cxx_class": "NoncoherentXBar",
76 "clk_domain": "system.clk_domain",
77 "power_model": null,
78 "width": 16,
79 "eventq_index": 0,
80 "master": {
81 "peer": [
82 "system.t1000.fake_clk.pio",
83 "system.t1000.fake_membnks.pio",
84 "system.t1000.fake_l2_1.pio",
85 "system.t1000.fake_l2_2.pio",
86 "system.t1000.fake_l2_3.pio",
87 "system.t1000.fake_l2_4.pio",
88 "system.t1000.fake_l2esr_1.pio",
89 "system.t1000.fake_l2esr_2.pio",
90 "system.t1000.fake_l2esr_3.pio",
91 "system.t1000.fake_l2esr_4.pio",
92 "system.t1000.fake_ssi.pio",
93 "system.t1000.fake_jbi.pio",
94 "system.t1000.puart0.pio",
95 "system.t1000.hvuart.pio",
96 "system.disk0.pio"
97 ],
98 "role": "MASTER"
99 },
100 "response_latency": 2,
101 "default_p_state": "UNDEFINED",
102 "p_state_clk_gate_max": 2000000000,
103 "path": "system.iobus",
104 "type": "NoncoherentXBar",
105 "use_default_range": false,
106 "frontend_latency": 2
107 },
108 "t1000": {
109 "htod": {
110 "name": "htod",
111 "p_state_clk_gate_min": 2,
112 "pio": {
113 "peer": "system.membus.master[1]",
114 "role": "SLAVE"
115 },
116 "p_state_clk_gate_bins": 20,
117 "cxx_class": "DumbTOD",
118 "pio_latency": 200,
119 "clk_domain": "system.clk_domain",
120 "power_model": null,
121 "system": "system",
122 "eventq_index": 0,
123 "time": "Thu Jan 1 00:00:00 2009",
124 "default_p_state": "UNDEFINED",
125 "p_state_clk_gate_max": 2000000000,
126 "path": "system.t1000.htod",
127 "pio_addr": 1099255906296,
128 "type": "DumbTOD"
129 },
130 "puart0": {
131 "name": "puart0",
132 "p_state_clk_gate_min": 2,
133 "pio": {
134 "peer": "system.iobus.master[12]",
135 "role": "SLAVE"
136 },
137 "p_state_clk_gate_bins": 20,
138 "cxx_class": "Uart8250",
139 "pio_latency": 200,
140 "clk_domain": "system.clk_domain",
141 "power_model": null,
142 "system": "system",
143 "terminal": "system.t1000.pterm",
144 "platform": "system.t1000",
145 "eventq_index": 0,
146 "default_p_state": "UNDEFINED",
147 "p_state_clk_gate_max": 2000000000,
148 "path": "system.t1000.puart0",
149 "pio_addr": 133412421632,
150 "type": "Uart8250"
151 },
152 "fake_membnks": {
153 "pio": {
154 "peer": "system.iobus.master[1]",
155 "role": "SLAVE"
156 },
157 "ret_data64": 0,
158 "fake_mem": false,
159 "clk_domain": "system.clk_domain",
160 "cxx_class": "IsaFake",
161 "pio_addr": 648540061696,
162 "update_data": false,
163 "warn_access": "",
164 "pio_latency": 200,
165 "system": "system",
166 "eventq_index": 0,
167 "default_p_state": "UNDEFINED",
168 "p_state_clk_gate_max": 2000000000,
169 "type": "IsaFake",
170 "p_state_clk_gate_min": 2,
171 "power_model": null,
172 "ret_data32": 4294967295,
173 "path": "system.t1000.fake_membnks",
174 "ret_data16": 65535,
175 "ret_data8": 255,
176 "name": "fake_membnks",
177 "ret_bad_addr": false,
178 "pio_size": 16384,
179 "p_state_clk_gate_bins": 20
180 },
181 "cxx_class": "T1000",
182 "fake_jbi": {
183 "pio": {
184 "peer": "system.iobus.master[11]",
185 "role": "SLAVE"
186 },
187 "ret_data64": 18446744073709551615,
188 "fake_mem": false,
189 "clk_domain": "system.clk_domain",
190 "cxx_class": "IsaFake",
191 "pio_addr": 549755813888,
192 "update_data": false,
193 "warn_access": "",
194 "pio_latency": 200,
195 "system": "system",
196 "eventq_index": 0,
197 "default_p_state": "UNDEFINED",
198 "p_state_clk_gate_max": 2000000000,
199 "type": "IsaFake",
200 "p_state_clk_gate_min": 2,
201 "power_model": null,
202 "ret_data32": 4294967295,
203 "path": "system.t1000.fake_jbi",
204 "ret_data16": 65535,
205 "ret_data8": 255,
206 "name": "fake_jbi",
207 "ret_bad_addr": false,
208 "pio_size": 4294967296,
209 "p_state_clk_gate_bins": 20
210 },
211 "intrctrl": "system.intrctrl",
212 "fake_l2esr_2": {
213 "pio": {
214 "peer": "system.iobus.master[7]",
215 "role": "SLAVE"
216 },
217 "ret_data64": 0,
218 "fake_mem": false,
219 "clk_domain": "system.clk_domain",
220 "cxx_class": "IsaFake",
221 "pio_addr": 734439407680,
222 "update_data": true,
223 "warn_access": "",
224 "pio_latency": 200,
225 "system": "system",
226 "eventq_index": 0,
227 "default_p_state": "UNDEFINED",
228 "p_state_clk_gate_max": 2000000000,
229 "type": "IsaFake",
230 "p_state_clk_gate_min": 2,
231 "power_model": null,
232 "ret_data32": 4294967295,
233 "path": "system.t1000.fake_l2esr_2",
234 "ret_data16": 65535,
235 "ret_data8": 255,
236 "name": "fake_l2esr_2",
237 "ret_bad_addr": false,
238 "pio_size": 8,
239 "p_state_clk_gate_bins": 20
240 },
241 "system": "system",
242 "eventq_index": 0,
243 "hterm": {
244 "name": "hterm",
245 "output": true,
246 "number": 0,
247 "intr_control": "system.intrctrl",
248 "eventq_index": 0,
249 "cxx_class": "Terminal",
250 "path": "system.t1000.hterm",
251 "type": "Terminal",
252 "port": 3456
253 },
254 "type": "T1000",
255 "fake_l2_4": {
256 "pio": {
257 "peer": "system.iobus.master[5]",
258 "role": "SLAVE"
259 },
260 "ret_data64": 1,
261 "fake_mem": false,
262 "clk_domain": "system.clk_domain",
263 "cxx_class": "IsaFake",
264 "pio_addr": 725849473216,
265 "update_data": true,
266 "warn_access": "",
267 "pio_latency": 200,
268 "system": "system",
269 "eventq_index": 0,
270 "default_p_state": "UNDEFINED",
271 "p_state_clk_gate_max": 2000000000,
272 "type": "IsaFake",
273 "p_state_clk_gate_min": 2,
274 "power_model": null,
275 "ret_data32": 4294967295,
276 "path": "system.t1000.fake_l2_4",
277 "ret_data16": 65535,
278 "ret_data8": 255,
279 "name": "fake_l2_4",
280 "ret_bad_addr": false,
281 "pio_size": 8,
282 "p_state_clk_gate_bins": 20
283 },
284 "fake_l2_1": {
285 "pio": {
286 "peer": "system.iobus.master[2]",
287 "role": "SLAVE"
288 },
289 "ret_data64": 1,
290 "fake_mem": false,
291 "clk_domain": "system.clk_domain",
292 "cxx_class": "IsaFake",
293 "pio_addr": 725849473024,
294 "update_data": true,
295 "warn_access": "",
296 "pio_latency": 200,
297 "system": "system",
298 "eventq_index": 0,
299 "default_p_state": "UNDEFINED",
300 "p_state_clk_gate_max": 2000000000,
301 "type": "IsaFake",
302 "p_state_clk_gate_min": 2,
303 "power_model": null,
304 "ret_data32": 4294967295,
305 "path": "system.t1000.fake_l2_1",
306 "ret_data16": 65535,
307 "ret_data8": 255,
308 "name": "fake_l2_1",
309 "ret_bad_addr": false,
310 "pio_size": 8,
311 "p_state_clk_gate_bins": 20
312 },
313 "fake_l2_2": {
314 "pio": {
315 "peer": "system.iobus.master[3]",
316 "role": "SLAVE"
317 },
318 "ret_data64": 1,
319 "fake_mem": false,
320 "clk_domain": "system.clk_domain",
321 "cxx_class": "IsaFake",
322 "pio_addr": 725849473088,
323 "update_data": true,
324 "warn_access": "",
325 "pio_latency": 200,
326 "system": "system",
327 "eventq_index": 0,
328 "default_p_state": "UNDEFINED",
329 "p_state_clk_gate_max": 2000000000,
330 "type": "IsaFake",
331 "p_state_clk_gate_min": 2,
332 "power_model": null,
333 "ret_data32": 4294967295,
334 "path": "system.t1000.fake_l2_2",
335 "ret_data16": 65535,
336 "ret_data8": 255,
337 "name": "fake_l2_2",
338 "ret_bad_addr": false,
339 "pio_size": 8,
340 "p_state_clk_gate_bins": 20
341 },
342 "fake_l2_3": {
343 "pio": {
344 "peer": "system.iobus.master[4]",
345 "role": "SLAVE"
346 },
347 "ret_data64": 1,
348 "fake_mem": false,
349 "clk_domain": "system.clk_domain",
350 "cxx_class": "IsaFake",
351 "pio_addr": 725849473152,
352 "update_data": true,
353 "warn_access": "",
354 "pio_latency": 200,
355 "system": "system",
356 "eventq_index": 0,
357 "default_p_state": "UNDEFINED",
358 "p_state_clk_gate_max": 2000000000,
359 "type": "IsaFake",
360 "p_state_clk_gate_min": 2,
361 "power_model": null,
362 "ret_data32": 4294967295,
363 "path": "system.t1000.fake_l2_3",
364 "ret_data16": 65535,
365 "ret_data8": 255,
366 "name": "fake_l2_3",
367 "ret_bad_addr": false,
368 "pio_size": 8,
369 "p_state_clk_gate_bins": 20
370 },
371 "pterm": {
372 "name": "pterm",
373 "output": true,
374 "number": 0,
375 "intr_control": "system.intrctrl",
376 "eventq_index": 0,
377 "cxx_class": "Terminal",
378 "path": "system.t1000.pterm",
379 "type": "Terminal",
380 "port": 3456
381 },
382 "path": "system.t1000",
383 "iob": {
384 "name": "iob",
385 "p_state_clk_gate_min": 2,
386 "pio": {
387 "peer": "system.membus.master[0]",
388 "role": "SLAVE"
389 },
390 "p_state_clk_gate_bins": 20,
391 "cxx_class": "Iob",
392 "pio_latency": 2,
393 "clk_domain": "system.clk_domain",
394 "power_model": null,
395 "system": "system",
396 "platform": "system.t1000",
397 "eventq_index": 0,
398 "default_p_state": "UNDEFINED",
399 "p_state_clk_gate_max": 2000000000,
400 "path": "system.t1000.iob",
401 "type": "Iob"
402 },
403 "hvuart": {
404 "name": "hvuart",
405 "p_state_clk_gate_min": 2,
406 "pio": {
407 "peer": "system.iobus.master[13]",
408 "role": "SLAVE"
409 },
410 "p_state_clk_gate_bins": 20,
411 "cxx_class": "Uart8250",
412 "pio_latency": 200,
413 "clk_domain": "system.clk_domain",
414 "power_model": null,
415 "system": "system",
416 "terminal": "system.t1000.hterm",
417 "platform": "system.t1000",
418 "eventq_index": 0,
419 "default_p_state": "UNDEFINED",
420 "p_state_clk_gate_max": 2000000000,
421 "path": "system.t1000.hvuart",
422 "pio_addr": 1099255955456,
423 "type": "Uart8250"
424 },
425 "name": "t1000",
426 "fake_l2esr_3": {
427 "pio": {
428 "peer": "system.iobus.master[8]",
429 "role": "SLAVE"
430 },
431 "ret_data64": 0,
432 "fake_mem": false,
433 "clk_domain": "system.clk_domain",
434 "cxx_class": "IsaFake",
435 "pio_addr": 734439407744,
436 "update_data": true,
437 "warn_access": "",
438 "pio_latency": 200,
439 "system": "system",
440 "eventq_index": 0,
441 "default_p_state": "UNDEFINED",
442 "p_state_clk_gate_max": 2000000000,
443 "type": "IsaFake",
444 "p_state_clk_gate_min": 2,
445 "power_model": null,
446 "ret_data32": 4294967295,
447 "path": "system.t1000.fake_l2esr_3",
448 "ret_data16": 65535,
449 "ret_data8": 255,
450 "name": "fake_l2esr_3",
451 "ret_bad_addr": false,
452 "pio_size": 8,
453 "p_state_clk_gate_bins": 20
454 },
455 "fake_ssi": {
456 "pio": {
457 "peer": "system.iobus.master[10]",
458 "role": "SLAVE"
459 },
460 "ret_data64": 18446744073709551615,
461 "fake_mem": false,
462 "clk_domain": "system.clk_domain",
463 "cxx_class": "IsaFake",
464 "pio_addr": 1095216660480,
465 "update_data": false,
466 "warn_access": "",
467 "pio_latency": 200,
468 "system": "system",
469 "eventq_index": 0,
470 "default_p_state": "UNDEFINED",
471 "p_state_clk_gate_max": 2000000000,
472 "type": "IsaFake",
473 "p_state_clk_gate_min": 2,
474 "power_model": null,
475 "ret_data32": 4294967295,
476 "path": "system.t1000.fake_ssi",
477 "ret_data16": 65535,
478 "ret_data8": 255,
479 "name": "fake_ssi",
480 "ret_bad_addr": false,
481 "pio_size": 268435456,
482 "p_state_clk_gate_bins": 20
483 },
484 "fake_l2esr_1": {
485 "pio": {
486 "peer": "system.iobus.master[6]",
487 "role": "SLAVE"
488 },
489 "ret_data64": 0,
490 "fake_mem": false,
491 "clk_domain": "system.clk_domain",
492 "cxx_class": "IsaFake",
493 "pio_addr": 734439407616,
494 "update_data": true,
495 "warn_access": "",
496 "pio_latency": 200,
497 "system": "system",
498 "eventq_index": 0,
499 "default_p_state": "UNDEFINED",
500 "p_state_clk_gate_max": 2000000000,
501 "type": "IsaFake",
502 "p_state_clk_gate_min": 2,
503 "power_model": null,
504 "ret_data32": 4294967295,
505 "path": "system.t1000.fake_l2esr_1",
506 "ret_data16": 65535,
507 "ret_data8": 255,
508 "name": "fake_l2esr_1",
509 "ret_bad_addr": false,
510 "pio_size": 8,
511 "p_state_clk_gate_bins": 20
512 },
513 "fake_l2esr_4": {
514 "pio": {
515 "peer": "system.iobus.master[9]",
516 "role": "SLAVE"
517 },
518 "ret_data64": 0,
519 "fake_mem": false,
520 "clk_domain": "system.clk_domain",
521 "cxx_class": "IsaFake",
522 "pio_addr": 734439407808,
523 "update_data": true,
524 "warn_access": "",
525 "pio_latency": 200,
526 "system": "system",
527 "eventq_index": 0,
528 "default_p_state": "UNDEFINED",
529 "p_state_clk_gate_max": 2000000000,
530 "type": "IsaFake",
531 "p_state_clk_gate_min": 2,
532 "power_model": null,
533 "ret_data32": 4294967295,
534 "path": "system.t1000.fake_l2esr_4",
535 "ret_data16": 65535,
536 "ret_data8": 255,
537 "name": "fake_l2esr_4",
538 "ret_bad_addr": false,
539 "pio_size": 8,
540 "p_state_clk_gate_bins": 20
541 },
542 "fake_clk": {
543 "pio": {
544 "peer": "system.iobus.master[0]",
545 "role": "SLAVE"
546 },
547 "ret_data64": 18446744073709551615,
548 "fake_mem": false,
549 "clk_domain": "system.clk_domain",
550 "cxx_class": "IsaFake",
551 "pio_addr": 644245094400,
552 "update_data": false,
553 "warn_access": "",
554 "pio_latency": 200,
555 "system": "system",
556 "eventq_index": 0,
557 "default_p_state": "UNDEFINED",
558 "p_state_clk_gate_max": 2000000000,
559 "type": "IsaFake",
560 "p_state_clk_gate_min": 2,
561 "power_model": null,
562 "ret_data32": 4294967295,
563 "path": "system.t1000.fake_clk",
564 "ret_data16": 65535,
565 "ret_data8": 255,
566 "name": "fake_clk",
567 "ret_bad_addr": false,
568 "pio_size": 4294967296,
569 "p_state_clk_gate_bins": 20
570 }
571 },
572 "partition_desc_addr": 133445976064,
573 "symbolfile": "",
574 "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh",
575 "thermal_model": null,
576 "hypervisor_addr": 1099243257856,
577 "mem_ranges": [
|
577 "1048576:68157439",
578 "2147483648:2415919103"
| 578 "1048576:68157439:0:0:0:0",
579 "2147483648:2415919103:0:0:0:0"
|
579 ],
580 "cxx_class": "SparcSystem",
581 "work_begin_cpu_id_exit": -1,
582 "load_offset": 0,
583 "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin",
584 "work_end_ckpt_count": 0,
585 "work_begin_exit_count": 0,
586 "openboot_addr": 1099243716608,
587 "p_state_clk_gate_min": 2,
588 "nvram_addr": 133429198848,
589 "memories": [
590 "system.hypervisor_desc",
591 "system.nvram",
592 "system.partition_desc",
593 "system.physmem0",
594 "system.physmem1",
595 "system.rom"
596 ],
597 "work_begin_ckpt_count": 0,
598 "partition_desc": {
| 580 ],
581 "cxx_class": "SparcSystem",
582 "work_begin_cpu_id_exit": -1,
583 "load_offset": 0,
584 "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin",
585 "work_end_ckpt_count": 0,
586 "work_begin_exit_count": 0,
587 "openboot_addr": 1099243716608,
588 "p_state_clk_gate_min": 2,
589 "nvram_addr": 133429198848,
590 "memories": [
591 "system.hypervisor_desc",
592 "system.nvram",
593 "system.partition_desc",
594 "system.physmem0",
595 "system.physmem1",
596 "system.rom"
597 ],
598 "work_begin_ckpt_count": 0,
599 "partition_desc": {
|
599 "range": "133445976064:133445984255",
| 600 "range": "133445976064:133445984255:0:0:0:0",
|
600 "latency": 60,
601 "name": "partition_desc",
602 "p_state_clk_gate_min": 2,
603 "eventq_index": 0,
604 "p_state_clk_gate_bins": 20,
605 "default_p_state": "UNDEFINED",
| 601 "latency": 60,
602 "name": "partition_desc",
603 "p_state_clk_gate_min": 2,
604 "eventq_index": 0,
605 "p_state_clk_gate_bins": 20,
606 "default_p_state": "UNDEFINED",
|
| 607 "kvm_map": true,
|
606 "clk_domain": "system.clk_domain",
607 "power_model": null,
608 "latency_var": 0,
609 "bandwidth": "0.000000",
610 "conf_table_reported": true,
611 "cxx_class": "SimpleMemory",
612 "p_state_clk_gate_max": 2000000000,
613 "path": "system.partition_desc",
614 "null": false,
615 "type": "SimpleMemory",
616 "port": {
617 "peer": "system.membus.master[6]",
618 "role": "SLAVE"
619 },
620 "in_addr_map": true
621 },
622 "clk_domain": {
623 "name": "clk_domain",
624 "clock": [
625 2
626 ],
627 "init_perf_level": 0,
628 "voltage_domain": "system.voltage_domain",
629 "eventq_index": 0,
630 "cxx_class": "SrcClockDomain",
631 "path": "system.clk_domain",
632 "type": "SrcClockDomain",
633 "domain_id": -1
634 },
635 "hypervisor_desc": {
| 608 "clk_domain": "system.clk_domain",
609 "power_model": null,
610 "latency_var": 0,
611 "bandwidth": "0.000000",
612 "conf_table_reported": true,
613 "cxx_class": "SimpleMemory",
614 "p_state_clk_gate_max": 2000000000,
615 "path": "system.partition_desc",
616 "null": false,
617 "type": "SimpleMemory",
618 "port": {
619 "peer": "system.membus.master[6]",
620 "role": "SLAVE"
621 },
622 "in_addr_map": true
623 },
624 "clk_domain": {
625 "name": "clk_domain",
626 "clock": [
627 2
628 ],
629 "init_perf_level": 0,
630 "voltage_domain": "system.voltage_domain",
631 "eventq_index": 0,
632 "cxx_class": "SrcClockDomain",
633 "path": "system.clk_domain",
634 "type": "SrcClockDomain",
635 "domain_id": -1
636 },
637 "hypervisor_desc": {
|
636 "range": "133446500352:133446508543",
| 638 "range": "133446500352:133446508543:0:0:0:0",
|
637 "latency": 60,
638 "name": "hypervisor_desc",
639 "p_state_clk_gate_min": 2,
640 "eventq_index": 0,
641 "p_state_clk_gate_bins": 20,
642 "default_p_state": "UNDEFINED",
| 639 "latency": 60,
640 "name": "hypervisor_desc",
641 "p_state_clk_gate_min": 2,
642 "eventq_index": 0,
643 "p_state_clk_gate_bins": 20,
644 "default_p_state": "UNDEFINED",
|
| 645 "kvm_map": true,
|
643 "clk_domain": "system.clk_domain",
644 "power_model": null,
645 "latency_var": 0,
646 "bandwidth": "0.000000",
647 "conf_table_reported": true,
648 "cxx_class": "SimpleMemory",
649 "p_state_clk_gate_max": 2000000000,
650 "path": "system.hypervisor_desc",
651 "null": false,
652 "type": "SimpleMemory",
653 "port": {
654 "peer": "system.membus.master[5]",
655 "role": "SLAVE"
656 },
657 "in_addr_map": true
658 },
659 "membus": {
660 "point_of_coherency": true,
661 "system": "system",
662 "response_latency": 2,
663 "cxx_class": "CoherentXBar",
664 "badaddr_responder": {
665 "pio": {
666 "peer": "system.membus.default",
667 "role": "SLAVE"
668 },
669 "ret_data64": 18446744073709551615,
670 "fake_mem": false,
671 "clk_domain": "system.clk_domain",
672 "cxx_class": "IsaFake",
673 "pio_addr": 0,
674 "update_data": false,
675 "warn_access": "",
676 "pio_latency": 200,
677 "system": "system",
678 "eventq_index": 0,
679 "default_p_state": "UNDEFINED",
680 "p_state_clk_gate_max": 2000000000,
681 "type": "IsaFake",
682 "p_state_clk_gate_min": 2,
683 "power_model": null,
684 "ret_data32": 4294967295,
685 "path": "system.membus.badaddr_responder",
686 "ret_data16": 65535,
687 "ret_data8": 255,
688 "name": "badaddr_responder",
689 "ret_bad_addr": true,
690 "pio_size": 8,
691 "p_state_clk_gate_bins": 20
692 },
693 "forward_latency": 4,
694 "clk_domain": "system.clk_domain",
695 "width": 16,
696 "eventq_index": 0,
697 "default_p_state": "UNDEFINED",
698 "p_state_clk_gate_max": 2000000000,
699 "master": {
700 "peer": [
701 "system.t1000.iob.pio",
702 "system.t1000.htod.pio",
703 "system.bridge.slave",
704 "system.rom.port",
705 "system.nvram.port",
706 "system.hypervisor_desc.port",
707 "system.partition_desc.port",
708 "system.physmem0.port",
709 "system.physmem1.port"
710 ],
711 "role": "MASTER"
712 },
713 "type": "CoherentXBar",
714 "frontend_latency": 3,
715 "slave": {
716 "peer": [
717 "system.system_port",
718 "system.cpu.icache_port",
719 "system.cpu.dcache_port"
720 ],
721 "role": "SLAVE"
722 },
723 "p_state_clk_gate_min": 2,
724 "snoop_filter": {
725 "name": "snoop_filter",
726 "system": "system",
727 "max_capacity": 8388608,
728 "eventq_index": 0,
729 "cxx_class": "SnoopFilter",
730 "path": "system.membus.snoop_filter",
731 "type": "SnoopFilter",
732 "lookup_latency": 1
733 },
734 "power_model": null,
735 "path": "system.membus",
736 "snoop_response_latency": 4,
737 "name": "membus",
738 "default": {
739 "peer": "system.membus.badaddr_responder.pio",
740 "role": "MASTER"
741 },
742 "p_state_clk_gate_bins": 20,
743 "use_default_range": false
744 },
745 "nvram": {
| 646 "clk_domain": "system.clk_domain",
647 "power_model": null,
648 "latency_var": 0,
649 "bandwidth": "0.000000",
650 "conf_table_reported": true,
651 "cxx_class": "SimpleMemory",
652 "p_state_clk_gate_max": 2000000000,
653 "path": "system.hypervisor_desc",
654 "null": false,
655 "type": "SimpleMemory",
656 "port": {
657 "peer": "system.membus.master[5]",
658 "role": "SLAVE"
659 },
660 "in_addr_map": true
661 },
662 "membus": {
663 "point_of_coherency": true,
664 "system": "system",
665 "response_latency": 2,
666 "cxx_class": "CoherentXBar",
667 "badaddr_responder": {
668 "pio": {
669 "peer": "system.membus.default",
670 "role": "SLAVE"
671 },
672 "ret_data64": 18446744073709551615,
673 "fake_mem": false,
674 "clk_domain": "system.clk_domain",
675 "cxx_class": "IsaFake",
676 "pio_addr": 0,
677 "update_data": false,
678 "warn_access": "",
679 "pio_latency": 200,
680 "system": "system",
681 "eventq_index": 0,
682 "default_p_state": "UNDEFINED",
683 "p_state_clk_gate_max": 2000000000,
684 "type": "IsaFake",
685 "p_state_clk_gate_min": 2,
686 "power_model": null,
687 "ret_data32": 4294967295,
688 "path": "system.membus.badaddr_responder",
689 "ret_data16": 65535,
690 "ret_data8": 255,
691 "name": "badaddr_responder",
692 "ret_bad_addr": true,
693 "pio_size": 8,
694 "p_state_clk_gate_bins": 20
695 },
696 "forward_latency": 4,
697 "clk_domain": "system.clk_domain",
698 "width": 16,
699 "eventq_index": 0,
700 "default_p_state": "UNDEFINED",
701 "p_state_clk_gate_max": 2000000000,
702 "master": {
703 "peer": [
704 "system.t1000.iob.pio",
705 "system.t1000.htod.pio",
706 "system.bridge.slave",
707 "system.rom.port",
708 "system.nvram.port",
709 "system.hypervisor_desc.port",
710 "system.partition_desc.port",
711 "system.physmem0.port",
712 "system.physmem1.port"
713 ],
714 "role": "MASTER"
715 },
716 "type": "CoherentXBar",
717 "frontend_latency": 3,
718 "slave": {
719 "peer": [
720 "system.system_port",
721 "system.cpu.icache_port",
722 "system.cpu.dcache_port"
723 ],
724 "role": "SLAVE"
725 },
726 "p_state_clk_gate_min": 2,
727 "snoop_filter": {
728 "name": "snoop_filter",
729 "system": "system",
730 "max_capacity": 8388608,
731 "eventq_index": 0,
732 "cxx_class": "SnoopFilter",
733 "path": "system.membus.snoop_filter",
734 "type": "SnoopFilter",
735 "lookup_latency": 1
736 },
737 "power_model": null,
738 "path": "system.membus",
739 "snoop_response_latency": 4,
740 "name": "membus",
741 "default": {
742 "peer": "system.membus.badaddr_responder.pio",
743 "role": "MASTER"
744 },
745 "p_state_clk_gate_bins": 20,
746 "use_default_range": false
747 },
748 "nvram": {
|
746 "range": "133429198848:133429207039",
| 749 "range": "133429198848:133429207039:0:0:0:0",
|
747 "latency": 60,
748 "name": "nvram",
749 "p_state_clk_gate_min": 2,
750 "eventq_index": 0,
751 "p_state_clk_gate_bins": 20,
752 "default_p_state": "UNDEFINED",
| 750 "latency": 60,
751 "name": "nvram",
752 "p_state_clk_gate_min": 2,
753 "eventq_index": 0,
754 "p_state_clk_gate_bins": 20,
755 "default_p_state": "UNDEFINED",
|
| 756 "kvm_map": true,
|
753 "clk_domain": "system.clk_domain",
754 "power_model": null,
755 "latency_var": 0,
756 "bandwidth": "0.000000",
757 "conf_table_reported": true,
758 "cxx_class": "SimpleMemory",
759 "p_state_clk_gate_max": 2000000000,
760 "path": "system.nvram",
761 "null": false,
762 "type": "SimpleMemory",
763 "port": {
764 "peer": "system.membus.master[4]",
765 "role": "SLAVE"
766 },
767 "in_addr_map": true
768 },
769 "eventq_index": 0,
770 "default_p_state": "UNDEFINED",
771 "p_state_clk_gate_max": 2000000000,
772 "dvfs_handler": {
773 "enable": false,
774 "name": "dvfs_handler",
775 "sys_clk_domain": "system.clk_domain",
776 "transition_latency": 200000,
777 "eventq_index": 0,
778 "cxx_class": "DVFSHandler",
779 "domains": [],
780 "path": "system.dvfs_handler",
781 "type": "DVFSHandler"
782 },
783 "work_end_exit_count": 0,
784 "hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin",
785 "openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin",
786 "voltage_domain": {
787 "name": "voltage_domain",
788 "eventq_index": 0,
789 "voltage": [
790 "1.0"
791 ],
792 "cxx_class": "VoltageDomain",
793 "path": "system.voltage_domain",
794 "type": "VoltageDomain"
795 },
796 "cache_line_size": 64,
797 "boot_osflags": "a",
798 "system_port": {
799 "peer": "system.membus.slave[0]",
800 "role": "MASTER"
801 },
802 "physmem": [
803 {
| 757 "clk_domain": "system.clk_domain",
758 "power_model": null,
759 "latency_var": 0,
760 "bandwidth": "0.000000",
761 "conf_table_reported": true,
762 "cxx_class": "SimpleMemory",
763 "p_state_clk_gate_max": 2000000000,
764 "path": "system.nvram",
765 "null": false,
766 "type": "SimpleMemory",
767 "port": {
768 "peer": "system.membus.master[4]",
769 "role": "SLAVE"
770 },
771 "in_addr_map": true
772 },
773 "eventq_index": 0,
774 "default_p_state": "UNDEFINED",
775 "p_state_clk_gate_max": 2000000000,
776 "dvfs_handler": {
777 "enable": false,
778 "name": "dvfs_handler",
779 "sys_clk_domain": "system.clk_domain",
780 "transition_latency": 200000,
781 "eventq_index": 0,
782 "cxx_class": "DVFSHandler",
783 "domains": [],
784 "path": "system.dvfs_handler",
785 "type": "DVFSHandler"
786 },
787 "work_end_exit_count": 0,
788 "hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin",
789 "openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin",
790 "voltage_domain": {
791 "name": "voltage_domain",
792 "eventq_index": 0,
793 "voltage": [
794 "1.0"
795 ],
796 "cxx_class": "VoltageDomain",
797 "path": "system.voltage_domain",
798 "type": "VoltageDomain"
799 },
800 "cache_line_size": 64,
801 "boot_osflags": "a",
802 "system_port": {
803 "peer": "system.membus.slave[0]",
804 "role": "MASTER"
805 },
806 "physmem": [
807 {
|
804 "range": "1048576:68157439",
| 808 "range": "1048576:68157439:0:0:0:0",
|
805 "latency": 60,
806 "name": "physmem0",
807 "p_state_clk_gate_min": 2,
808 "eventq_index": 0,
809 "p_state_clk_gate_bins": 20,
810 "default_p_state": "UNDEFINED",
| 809 "latency": 60,
810 "name": "physmem0",
811 "p_state_clk_gate_min": 2,
812 "eventq_index": 0,
813 "p_state_clk_gate_bins": 20,
814 "default_p_state": "UNDEFINED",
|
| 815 "kvm_map": true,
|
811 "clk_domain": "system.clk_domain",
812 "power_model": null,
813 "latency_var": 0,
814 "bandwidth": "0.000000",
815 "conf_table_reported": true,
816 "cxx_class": "SimpleMemory",
817 "p_state_clk_gate_max": 2000000000,
818 "path": "system.physmem0",
819 "null": false,
820 "type": "SimpleMemory",
821 "port": {
822 "peer": "system.membus.master[7]",
823 "role": "SLAVE"
824 },
825 "in_addr_map": true
826 },
827 {
| 816 "clk_domain": "system.clk_domain",
817 "power_model": null,
818 "latency_var": 0,
819 "bandwidth": "0.000000",
820 "conf_table_reported": true,
821 "cxx_class": "SimpleMemory",
822 "p_state_clk_gate_max": 2000000000,
823 "path": "system.physmem0",
824 "null": false,
825 "type": "SimpleMemory",
826 "port": {
827 "peer": "system.membus.master[7]",
828 "role": "SLAVE"
829 },
830 "in_addr_map": true
831 },
832 {
|
828 "range": "2147483648:2415919103",
| 833 "range": "2147483648:2415919103:0:0:0:0",
|
829 "latency": 60,
830 "name": "physmem1",
831 "p_state_clk_gate_min": 2,
832 "eventq_index": 0,
833 "p_state_clk_gate_bins": 20,
834 "default_p_state": "UNDEFINED",
| 834 "latency": 60,
835 "name": "physmem1",
836 "p_state_clk_gate_min": 2,
837 "eventq_index": 0,
838 "p_state_clk_gate_bins": 20,
839 "default_p_state": "UNDEFINED",
|
| 840 "kvm_map": true,
|
835 "clk_domain": "system.clk_domain",
836 "power_model": null,
837 "latency_var": 0,
838 "bandwidth": "0.000000",
839 "conf_table_reported": true,
840 "cxx_class": "SimpleMemory",
841 "p_state_clk_gate_max": 2000000000,
842 "path": "system.physmem1",
843 "null": false,
844 "type": "SimpleMemory",
845 "port": {
846 "peer": "system.membus.master[8]",
847 "role": "SLAVE"
848 },
849 "in_addr_map": true
850 }
851 ],
852 "power_model": null,
853 "work_cpus_ckpt_count": 0,
854 "thermal_components": [],
855 "path": "system",
856 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
857 "cpu_clk_domain": {
858 "name": "cpu_clk_domain",
859 "clock": [
860 2
861 ],
862 "init_perf_level": 0,
863 "voltage_domain": "system.voltage_domain",
864 "eventq_index": 0,
865 "cxx_class": "SrcClockDomain",
866 "path": "system.cpu_clk_domain",
867 "type": "SrcClockDomain",
868 "domain_id": -1
869 },
870 "nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1",
871 "mem_mode": "atomic",
872 "name": "system",
873 "init_param": 0,
874 "type": "SparcSystem",
875 "partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin",
876 "load_addr_mask": 1099511627775,
877 "cpu": {
878 "do_statistics_insts": true,
879 "numThreads": 1,
880 "itb": {
881 "name": "itb",
882 "eventq_index": 0,
883 "cxx_class": "SparcISA::TLB",
884 "path": "system.cpu.itb",
885 "type": "SparcTLB",
886 "size": 64
887 },
888 "simulate_data_stalls": false,
889 "function_trace": false,
890 "do_checkpoint_insts": true,
891 "cxx_class": "AtomicSimpleCPU",
892 "max_loads_all_threads": 0,
893 "system": "system",
894 "clk_domain": "system.cpu_clk_domain",
895 "function_trace_start": 0,
896 "cpu_id": 0,
897 "width": 1,
898 "checker": null,
899 "eventq_index": 0,
900 "default_p_state": "UNDEFINED",
901 "p_state_clk_gate_max": 2000000000,
902 "do_quiesce": true,
903 "type": "AtomicSimpleCPU",
904 "fastmem": false,
905 "profile": 0,
906 "icache_port": {
907 "peer": "system.membus.slave[1]",
908 "role": "MASTER"
909 },
910 "p_state_clk_gate_bins": 20,
911 "p_state_clk_gate_min": 2,
912 "interrupts": [
913 {
914 "eventq_index": 0,
915 "path": "system.cpu.interrupts",
916 "type": "SparcInterrupts",
917 "name": "interrupts",
918 "cxx_class": "SparcISA::Interrupts"
919 }
920 ],
921 "dcache_port": {
922 "peer": "system.membus.slave[2]",
923 "role": "MASTER"
924 },
925 "socket_id": 0,
926 "power_model": null,
927 "max_insts_all_threads": 0,
928 "path": "system.cpu",
929 "max_loads_any_thread": 0,
930 "switched_out": false,
931 "workload": [],
932 "name": "cpu",
933 "dtb": {
934 "name": "dtb",
935 "eventq_index": 0,
936 "cxx_class": "SparcISA::TLB",
937 "path": "system.cpu.dtb",
938 "type": "SparcTLB",
939 "size": 64
940 },
941 "simpoint_start_insts": [],
942 "max_insts_any_thread": 0,
943 "simulate_inst_stalls": false,
944 "progress_interval": 0,
945 "branchPred": null,
946 "isa": [
947 {
948 "eventq_index": 0,
949 "path": "system.cpu.isa",
950 "type": "SparcISA",
951 "name": "isa",
952 "cxx_class": "SparcISA::ISA"
953 }
954 ],
955 "tracer": {
956 "eventq_index": 0,
957 "path": "system.cpu.tracer",
958 "type": "ExeTracer",
959 "name": "tracer",
960 "cxx_class": "Trace::ExeTracer"
961 }
962 },
963 "intrctrl": {
964 "name": "intrctrl",
965 "sys": "system",
966 "eventq_index": 0,
967 "cxx_class": "IntrControl",
968 "path": "system.intrctrl",
969 "type": "IntrControl"
970 },
971 "disk0": {
972 "name": "disk0",
973 "p_state_clk_gate_min": 2,
974 "pio": {
975 "peer": "system.iobus.master[14]",
976 "role": "SLAVE"
977 },
978 "p_state_clk_gate_bins": 20,
979 "image": {
980 "read_only": false,
981 "name": "image",
982 "cxx_class": "CowDiskImage",
983 "eventq_index": 0,
984 "child": {
985 "read_only": true,
986 "name": "child",
987 "eventq_index": 0,
988 "cxx_class": "RawDiskImage",
989 "path": "system.disk0.image.child",
990 "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2",
991 "type": "RawDiskImage"
992 },
993 "path": "system.disk0.image",
994 "image_file": "",
995 "type": "CowDiskImage",
996 "table_size": 65536
997 },
998 "cxx_class": "MmDisk",
999 "pio_latency": 200,
1000 "clk_domain": "system.clk_domain",
1001 "power_model": null,
1002 "system": "system",
1003 "eventq_index": 0,
1004 "default_p_state": "UNDEFINED",
1005 "p_state_clk_gate_max": 2000000000,
1006 "path": "system.disk0",
1007 "pio_addr": 134217728000,
1008 "type": "MmDisk"
1009 },
1010 "multi_thread": false,
1011 "reset_addr": 1099243192320,
1012 "p_state_clk_gate_bins": 20,
1013 "hypervisor_desc_addr": 133446500352,
1014 "num_work_ids": 16,
1015 "work_item_id": -1,
1016 "exit_on_work_items": false
1017 },
1018 "time_sync_period": 200000000,
1019 "eventq_index": 0,
1020 "time_sync_spin_threshold": 200000,
1021 "cxx_class": "Root",
1022 "path": "root",
1023 "time_sync_enable": false,
1024 "type": "Root",
1025 "full_system": true
1026}
| 841 "clk_domain": "system.clk_domain",
842 "power_model": null,
843 "latency_var": 0,
844 "bandwidth": "0.000000",
845 "conf_table_reported": true,
846 "cxx_class": "SimpleMemory",
847 "p_state_clk_gate_max": 2000000000,
848 "path": "system.physmem1",
849 "null": false,
850 "type": "SimpleMemory",
851 "port": {
852 "peer": "system.membus.master[8]",
853 "role": "SLAVE"
854 },
855 "in_addr_map": true
856 }
857 ],
858 "power_model": null,
859 "work_cpus_ckpt_count": 0,
860 "thermal_components": [],
861 "path": "system",
862 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
863 "cpu_clk_domain": {
864 "name": "cpu_clk_domain",
865 "clock": [
866 2
867 ],
868 "init_perf_level": 0,
869 "voltage_domain": "system.voltage_domain",
870 "eventq_index": 0,
871 "cxx_class": "SrcClockDomain",
872 "path": "system.cpu_clk_domain",
873 "type": "SrcClockDomain",
874 "domain_id": -1
875 },
876 "nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1",
877 "mem_mode": "atomic",
878 "name": "system",
879 "init_param": 0,
880 "type": "SparcSystem",
881 "partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin",
882 "load_addr_mask": 1099511627775,
883 "cpu": {
884 "do_statistics_insts": true,
885 "numThreads": 1,
886 "itb": {
887 "name": "itb",
888 "eventq_index": 0,
889 "cxx_class": "SparcISA::TLB",
890 "path": "system.cpu.itb",
891 "type": "SparcTLB",
892 "size": 64
893 },
894 "simulate_data_stalls": false,
895 "function_trace": false,
896 "do_checkpoint_insts": true,
897 "cxx_class": "AtomicSimpleCPU",
898 "max_loads_all_threads": 0,
899 "system": "system",
900 "clk_domain": "system.cpu_clk_domain",
901 "function_trace_start": 0,
902 "cpu_id": 0,
903 "width": 1,
904 "checker": null,
905 "eventq_index": 0,
906 "default_p_state": "UNDEFINED",
907 "p_state_clk_gate_max": 2000000000,
908 "do_quiesce": true,
909 "type": "AtomicSimpleCPU",
910 "fastmem": false,
911 "profile": 0,
912 "icache_port": {
913 "peer": "system.membus.slave[1]",
914 "role": "MASTER"
915 },
916 "p_state_clk_gate_bins": 20,
917 "p_state_clk_gate_min": 2,
918 "interrupts": [
919 {
920 "eventq_index": 0,
921 "path": "system.cpu.interrupts",
922 "type": "SparcInterrupts",
923 "name": "interrupts",
924 "cxx_class": "SparcISA::Interrupts"
925 }
926 ],
927 "dcache_port": {
928 "peer": "system.membus.slave[2]",
929 "role": "MASTER"
930 },
931 "socket_id": 0,
932 "power_model": null,
933 "max_insts_all_threads": 0,
934 "path": "system.cpu",
935 "max_loads_any_thread": 0,
936 "switched_out": false,
937 "workload": [],
938 "name": "cpu",
939 "dtb": {
940 "name": "dtb",
941 "eventq_index": 0,
942 "cxx_class": "SparcISA::TLB",
943 "path": "system.cpu.dtb",
944 "type": "SparcTLB",
945 "size": 64
946 },
947 "simpoint_start_insts": [],
948 "max_insts_any_thread": 0,
949 "simulate_inst_stalls": false,
950 "progress_interval": 0,
951 "branchPred": null,
952 "isa": [
953 {
954 "eventq_index": 0,
955 "path": "system.cpu.isa",
956 "type": "SparcISA",
957 "name": "isa",
958 "cxx_class": "SparcISA::ISA"
959 }
960 ],
961 "tracer": {
962 "eventq_index": 0,
963 "path": "system.cpu.tracer",
964 "type": "ExeTracer",
965 "name": "tracer",
966 "cxx_class": "Trace::ExeTracer"
967 }
968 },
969 "intrctrl": {
970 "name": "intrctrl",
971 "sys": "system",
972 "eventq_index": 0,
973 "cxx_class": "IntrControl",
974 "path": "system.intrctrl",
975 "type": "IntrControl"
976 },
977 "disk0": {
978 "name": "disk0",
979 "p_state_clk_gate_min": 2,
980 "pio": {
981 "peer": "system.iobus.master[14]",
982 "role": "SLAVE"
983 },
984 "p_state_clk_gate_bins": 20,
985 "image": {
986 "read_only": false,
987 "name": "image",
988 "cxx_class": "CowDiskImage",
989 "eventq_index": 0,
990 "child": {
991 "read_only": true,
992 "name": "child",
993 "eventq_index": 0,
994 "cxx_class": "RawDiskImage",
995 "path": "system.disk0.image.child",
996 "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2",
997 "type": "RawDiskImage"
998 },
999 "path": "system.disk0.image",
1000 "image_file": "",
1001 "type": "CowDiskImage",
1002 "table_size": 65536
1003 },
1004 "cxx_class": "MmDisk",
1005 "pio_latency": 200,
1006 "clk_domain": "system.clk_domain",
1007 "power_model": null,
1008 "system": "system",
1009 "eventq_index": 0,
1010 "default_p_state": "UNDEFINED",
1011 "p_state_clk_gate_max": 2000000000,
1012 "path": "system.disk0",
1013 "pio_addr": 134217728000,
1014 "type": "MmDisk"
1015 },
1016 "multi_thread": false,
1017 "reset_addr": 1099243192320,
1018 "p_state_clk_gate_bins": 20,
1019 "hypervisor_desc_addr": 133446500352,
1020 "num_work_ids": 16,
1021 "work_item_id": -1,
1022 "exit_on_work_items": false
1023 },
1024 "time_sync_period": 200000000,
1025 "eventq_index": 0,
1026 "time_sync_spin_threshold": 200000,
1027 "cxx_class": "Root",
1028 "path": "root",
1029 "time_sync_enable": false,
1030 "type": "Root",
1031 "full_system": true
1032}
|