1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
16 "clk_domain": "system.clk_domain",
17 "power_model": null,
18 "latency_var": 0,
19 "bandwidth": "0.000000",
20 "conf_table_reported": true,
21 "cxx_class": "SimpleMemory",
22 "p_state_clk_gate_max": 2000000000,
23 "path": "system.rom",
24 "null": false,
25 "type": "SimpleMemory",
26 "port": {
27 "peer": "system.membus.master[3]",
28 "role": "SLAVE"
29 },
30 "in_addr_map": true
31 },
32 "bridge": {
33 "ranges": [
34 "133412421632:133412421639",
35 "134217728000:554050781183",
36 "644245094400:652835028991",
37 "725849473024:1095485095935",
38 "1099255955456:1099255955463"
39 ],
40 "slave": {
41 "peer": "system.membus.master[2]",
42 "role": "SLAVE"
43 },
44 "name": "bridge",
45 "p_state_clk_gate_min": 2,
46 "p_state_clk_gate_bins": 20,
47 "cxx_class": "Bridge",
48 "req_size": 16,
49 "clk_domain": "system.clk_domain",
50 "power_model": null,
51 "delay": 100,
52 "eventq_index": 0,
53 "master": {
54 "peer": "system.iobus.slave[0]",
55 "role": "MASTER"
56 },
57 "default_p_state": "UNDEFINED",
58 "p_state_clk_gate_max": 2000000000,
59 "path": "system.bridge",
60 "resp_size": 16,
61 "type": "Bridge"
62 },
63 "iobus": {
64 "forward_latency": 1,
65 "slave": {
66 "peer": [
67 "system.bridge.master"
68 ],
69 "role": "SLAVE"
70 },
71 "name": "iobus",
72 "p_state_clk_gate_min": 2,
73 "p_state_clk_gate_bins": 20,
74 "cxx_class": "NoncoherentXBar",
75 "clk_domain": "system.clk_domain",
76 "power_model": null,
77 "width": 16,
78 "eventq_index": 0,
79 "master": {
80 "peer": [
81 "system.t1000.fake_clk.pio",
82 "system.t1000.fake_membnks.pio",
83 "system.t1000.fake_l2_1.pio",
84 "system.t1000.fake_l2_2.pio",
85 "system.t1000.fake_l2_3.pio",
86 "system.t1000.fake_l2_4.pio",
87 "system.t1000.fake_l2esr_1.pio",
88 "system.t1000.fake_l2esr_2.pio",
89 "system.t1000.fake_l2esr_3.pio",
90 "system.t1000.fake_l2esr_4.pio",
91 "system.t1000.fake_ssi.pio",
92 "system.t1000.fake_jbi.pio",
93 "system.t1000.puart0.pio",
94 "system.t1000.hvuart.pio",
95 "system.disk0.pio"
96 ],
97 "role": "MASTER"
98 },
99 "response_latency": 2,
100 "default_p_state": "UNDEFINED",
101 "p_state_clk_gate_max": 2000000000,
102 "path": "system.iobus",
103 "type": "NoncoherentXBar",
104 "use_default_range": false,
105 "frontend_latency": 2
106 },
107 "t1000": {
108 "htod": {
109 "name": "htod",
110 "p_state_clk_gate_min": 2,
111 "pio": {
112 "peer": "system.membus.master[1]",
113 "role": "SLAVE"
114 },
115 "p_state_clk_gate_bins": 20,
116 "cxx_class": "DumbTOD",
117 "pio_latency": 200,
118 "clk_domain": "system.clk_domain",
119 "power_model": null,
120 "system": "system",
121 "eventq_index": 0,
122 "time": "Thu Jan 1 00:00:00 2009",
123 "default_p_state": "UNDEFINED",
124 "p_state_clk_gate_max": 2000000000,
125 "path": "system.t1000.htod",
126 "pio_addr": 1099255906296,
127 "type": "DumbTOD"
128 },
129 "puart0": {
130 "name": "puart0",
131 "p_state_clk_gate_min": 2,
132 "pio": {
133 "peer": "system.iobus.master[12]",
134 "role": "SLAVE"
135 },
136 "p_state_clk_gate_bins": 20,
137 "cxx_class": "Uart8250",
138 "pio_latency": 200,
139 "clk_domain": "system.clk_domain",
140 "power_model": null,
141 "system": "system",
142 "terminal": "system.t1000.pterm",
143 "platform": "system.t1000",
144 "eventq_index": 0,
145 "default_p_state": "UNDEFINED",
146 "p_state_clk_gate_max": 2000000000,
147 "path": "system.t1000.puart0",
148 "pio_addr": 133412421632,
149 "type": "Uart8250"
150 },
151 "fake_membnks": {
152 "pio": {
153 "peer": "system.iobus.master[1]",
154 "role": "SLAVE"
155 },
156 "ret_data64": 0,
157 "fake_mem": false,
158 "clk_domain": "system.clk_domain",
159 "cxx_class": "IsaFake",
160 "pio_addr": 648540061696,
161 "update_data": false,
162 "warn_access": "",
163 "pio_latency": 200,
164 "system": "system",
165 "eventq_index": 0,
166 "default_p_state": "UNDEFINED",
167 "p_state_clk_gate_max": 2000000000,
168 "type": "IsaFake",
169 "p_state_clk_gate_min": 2,
170 "power_model": null,
171 "ret_data32": 4294967295,
172 "path": "system.t1000.fake_membnks",
173 "ret_data16": 65535,
174 "ret_data8": 255,
175 "name": "fake_membnks",
176 "ret_bad_addr": false,
177 "pio_size": 16384,
178 "p_state_clk_gate_bins": 20
179 },
180 "cxx_class": "T1000",
181 "fake_jbi": {
182 "pio": {
183 "peer": "system.iobus.master[11]",
184 "role": "SLAVE"
185 },
186 "ret_data64": 18446744073709551615,
187 "fake_mem": false,
188 "clk_domain": "system.clk_domain",
189 "cxx_class": "IsaFake",
190 "pio_addr": 549755813888,
191 "update_data": false,
192 "warn_access": "",
193 "pio_latency": 200,
194 "system": "system",
195 "eventq_index": 0,
196 "default_p_state": "UNDEFINED",
197 "p_state_clk_gate_max": 2000000000,
198 "type": "IsaFake",
199 "p_state_clk_gate_min": 2,
200 "power_model": null,
201 "ret_data32": 4294967295,
202 "path": "system.t1000.fake_jbi",
203 "ret_data16": 65535,
204 "ret_data8": 255,
205 "name": "fake_jbi",
206 "ret_bad_addr": false,
207 "pio_size": 4294967296,
208 "p_state_clk_gate_bins": 20
209 },
210 "intrctrl": "system.intrctrl",
211 "fake_l2esr_2": {
212 "pio": {
213 "peer": "system.iobus.master[7]",
214 "role": "SLAVE"
215 },
216 "ret_data64": 0,
217 "fake_mem": false,
218 "clk_domain": "system.clk_domain",
219 "cxx_class": "IsaFake",
220 "pio_addr": 734439407680,
221 "update_data": true,
222 "warn_access": "",
223 "pio_latency": 200,
224 "system": "system",
225 "eventq_index": 0,
226 "default_p_state": "UNDEFINED",
227 "p_state_clk_gate_max": 2000000000,
228 "type": "IsaFake",
229 "p_state_clk_gate_min": 2,
230 "power_model": null,
231 "ret_data32": 4294967295,
232 "path": "system.t1000.fake_l2esr_2",
233 "ret_data16": 65535,
234 "ret_data8": 255,
235 "name": "fake_l2esr_2",
236 "ret_bad_addr": false,
237 "pio_size": 8,
238 "p_state_clk_gate_bins": 20
239 },
240 "system": "system",
241 "eventq_index": 0,
242 "hterm": {
243 "name": "hterm",
244 "output": true,
245 "number": 0,
246 "intr_control": "system.intrctrl",
247 "eventq_index": 0,
248 "cxx_class": "Terminal",
249 "path": "system.t1000.hterm",
250 "type": "Terminal",
251 "port": 3456
252 },
253 "type": "T1000",
254 "fake_l2_4": {
255 "pio": {
256 "peer": "system.iobus.master[5]",
257 "role": "SLAVE"
258 },
259 "ret_data64": 1,
260 "fake_mem": false,
261 "clk_domain": "system.clk_domain",
262 "cxx_class": "IsaFake",
263 "pio_addr": 725849473216,
264 "update_data": true,
265 "warn_access": "",
266 "pio_latency": 200,
267 "system": "system",
268 "eventq_index": 0,
269 "default_p_state": "UNDEFINED",
270 "p_state_clk_gate_max": 2000000000,
271 "type": "IsaFake",
272 "p_state_clk_gate_min": 2,
273 "power_model": null,
274 "ret_data32": 4294967295,
275 "path": "system.t1000.fake_l2_4",
276 "ret_data16": 65535,
277 "ret_data8": 255,
278 "name": "fake_l2_4",
279 "ret_bad_addr": false,
280 "pio_size": 8,
281 "p_state_clk_gate_bins": 20
282 },
283 "fake_l2_1": {
284 "pio": {
285 "peer": "system.iobus.master[2]",
286 "role": "SLAVE"
287 },
288 "ret_data64": 1,
289 "fake_mem": false,
290 "clk_domain": "system.clk_domain",
291 "cxx_class": "IsaFake",
292 "pio_addr": 725849473024,
293 "update_data": true,
294 "warn_access": "",
295 "pio_latency": 200,
296 "system": "system",
297 "eventq_index": 0,
298 "default_p_state": "UNDEFINED",
299 "p_state_clk_gate_max": 2000000000,
300 "type": "IsaFake",
301 "p_state_clk_gate_min": 2,
302 "power_model": null,
303 "ret_data32": 4294967295,
304 "path": "system.t1000.fake_l2_1",
305 "ret_data16": 65535,
306 "ret_data8": 255,
307 "name": "fake_l2_1",
308 "ret_bad_addr": false,
309 "pio_size": 8,
310 "p_state_clk_gate_bins": 20
311 },
312 "fake_l2_2": {
313 "pio": {
314 "peer": "system.iobus.master[3]",
315 "role": "SLAVE"
316 },
317 "ret_data64": 1,
318 "fake_mem": false,
319 "clk_domain": "system.clk_domain",
320 "cxx_class": "IsaFake",
321 "pio_addr": 725849473088,
322 "update_data": true,
323 "warn_access": "",
324 "pio_latency": 200,
325 "system": "system",
326 "eventq_index": 0,
327 "default_p_state": "UNDEFINED",
328 "p_state_clk_gate_max": 2000000000,
329 "type": "IsaFake",
330 "p_state_clk_gate_min": 2,
331 "power_model": null,
332 "ret_data32": 4294967295,
333 "path": "system.t1000.fake_l2_2",
334 "ret_data16": 65535,
335 "ret_data8": 255,
336 "name": "fake_l2_2",
337 "ret_bad_addr": false,
338 "pio_size": 8,
339 "p_state_clk_gate_bins": 20
340 },
341 "fake_l2_3": {
342 "pio": {
343 "peer": "system.iobus.master[4]",
344 "role": "SLAVE"
345 },
346 "ret_data64": 1,
347 "fake_mem": false,
348 "clk_domain": "system.clk_domain",
349 "cxx_class": "IsaFake",
350 "pio_addr": 725849473152,
351 "update_data": true,
352 "warn_access": "",
353 "pio_latency": 200,
354 "system": "system",
355 "eventq_index": 0,
356 "default_p_state": "UNDEFINED",
357 "p_state_clk_gate_max": 2000000000,
358 "type": "IsaFake",
359 "p_state_clk_gate_min": 2,
360 "power_model": null,
361 "ret_data32": 4294967295,
362 "path": "system.t1000.fake_l2_3",
363 "ret_data16": 65535,
364 "ret_data8": 255,
365 "name": "fake_l2_3",
366 "ret_bad_addr": false,
367 "pio_size": 8,
368 "p_state_clk_gate_bins": 20
369 },
370 "pterm": {
371 "name": "pterm",
372 "output": true,
373 "number": 0,
374 "intr_control": "system.intrctrl",
375 "eventq_index": 0,
376 "cxx_class": "Terminal",
377 "path": "system.t1000.pterm",
378 "type": "Terminal",
379 "port": 3456
380 },
381 "path": "system.t1000",
382 "iob": {
383 "name": "iob",
384 "p_state_clk_gate_min": 2,
385 "pio": {
386 "peer": "system.membus.master[0]",
387 "role": "SLAVE"
388 },
389 "p_state_clk_gate_bins": 20,
390 "cxx_class": "Iob",
391 "pio_latency": 2,
392 "clk_domain": "system.clk_domain",
393 "power_model": null,
394 "system": "system",
395 "platform": "system.t1000",
396 "eventq_index": 0,
397 "default_p_state": "UNDEFINED",
398 "p_state_clk_gate_max": 2000000000,
399 "path": "system.t1000.iob",
400 "type": "Iob"
401 },
402 "hvuart": {
403 "name": "hvuart",
404 "p_state_clk_gate_min": 2,
405 "pio": {
406 "peer": "system.iobus.master[13]",
407 "role": "SLAVE"
408 },
409 "p_state_clk_gate_bins": 20,
410 "cxx_class": "Uart8250",
411 "pio_latency": 200,
412 "clk_domain": "system.clk_domain",
413 "power_model": null,
414 "system": "system",
415 "terminal": "system.t1000.hterm",
416 "platform": "system.t1000",
417 "eventq_index": 0,
418 "default_p_state": "UNDEFINED",
419 "p_state_clk_gate_max": 2000000000,
420 "path": "system.t1000.hvuart",
421 "pio_addr": 1099255955456,
422 "type": "Uart8250"
423 },
424 "name": "t1000",
425 "fake_l2esr_3": {
426 "pio": {
427 "peer": "system.iobus.master[8]",
428 "role": "SLAVE"
429 },
430 "ret_data64": 0,
431 "fake_mem": false,
432 "clk_domain": "system.clk_domain",
433 "cxx_class": "IsaFake",
434 "pio_addr": 734439407744,
435 "update_data": true,
436 "warn_access": "",
437 "pio_latency": 200,
438 "system": "system",
439 "eventq_index": 0,
440 "default_p_state": "UNDEFINED",
441 "p_state_clk_gate_max": 2000000000,
442 "type": "IsaFake",
443 "p_state_clk_gate_min": 2,
444 "power_model": null,
445 "ret_data32": 4294967295,
446 "path": "system.t1000.fake_l2esr_3",
447 "ret_data16": 65535,
448 "ret_data8": 255,
449 "name": "fake_l2esr_3",
450 "ret_bad_addr": false,
451 "pio_size": 8,
452 "p_state_clk_gate_bins": 20
453 },
454 "fake_ssi": {
455 "pio": {
456 "peer": "system.iobus.master[10]",
457 "role": "SLAVE"
458 },
459 "ret_data64": 18446744073709551615,
460 "fake_mem": false,
461 "clk_domain": "system.clk_domain",
462 "cxx_class": "IsaFake",
463 "pio_addr": 1095216660480,
464 "update_data": false,
465 "warn_access": "",
466 "pio_latency": 200,
467 "system": "system",
468 "eventq_index": 0,
469 "default_p_state": "UNDEFINED",
470 "p_state_clk_gate_max": 2000000000,
471 "type": "IsaFake",
472 "p_state_clk_gate_min": 2,
473 "power_model": null,
474 "ret_data32": 4294967295,
475 "path": "system.t1000.fake_ssi",
476 "ret_data16": 65535,
477 "ret_data8": 255,
478 "name": "fake_ssi",
479 "ret_bad_addr": false,
480 "pio_size": 268435456,
481 "p_state_clk_gate_bins": 20
482 },
483 "fake_l2esr_1": {
484 "pio": {
485 "peer": "system.iobus.master[6]",
486 "role": "SLAVE"
487 },
488 "ret_data64": 0,
489 "fake_mem": false,
490 "clk_domain": "system.clk_domain",
491 "cxx_class": "IsaFake",
492 "pio_addr": 734439407616,
493 "update_data": true,
494 "warn_access": "",
495 "pio_latency": 200,
496 "system": "system",
497 "eventq_index": 0,
498 "default_p_state": "UNDEFINED",
499 "p_state_clk_gate_max": 2000000000,
500 "type": "IsaFake",
501 "p_state_clk_gate_min": 2,
502 "power_model": null,
503 "ret_data32": 4294967295,
504 "path": "system.t1000.fake_l2esr_1",
505 "ret_data16": 65535,
506 "ret_data8": 255,
507 "name": "fake_l2esr_1",
508 "ret_bad_addr": false,
509 "pio_size": 8,
510 "p_state_clk_gate_bins": 20
511 },
512 "fake_l2esr_4": {
513 "pio": {
514 "peer": "system.iobus.master[9]",
515 "role": "SLAVE"
516 },
517 "ret_data64": 0,
518 "fake_mem": false,
519 "clk_domain": "system.clk_domain",
520 "cxx_class": "IsaFake",
521 "pio_addr": 734439407808,
522 "update_data": true,
523 "warn_access": "",
524 "pio_latency": 200,
525 "system": "system",
526 "eventq_index": 0,
527 "default_p_state": "UNDEFINED",
528 "p_state_clk_gate_max": 2000000000,
529 "type": "IsaFake",
530 "p_state_clk_gate_min": 2,
531 "power_model": null,
532 "ret_data32": 4294967295,
533 "path": "system.t1000.fake_l2esr_4",
534 "ret_data16": 65535,
535 "ret_data8": 255,
536 "name": "fake_l2esr_4",
537 "ret_bad_addr": false,
538 "pio_size": 8,
539 "p_state_clk_gate_bins": 20
540 },
541 "fake_clk": {
542 "pio": {
543 "peer": "system.iobus.master[0]",
544 "role": "SLAVE"
545 },
546 "ret_data64": 18446744073709551615,
547 "fake_mem": false,
548 "clk_domain": "system.clk_domain",
549 "cxx_class": "IsaFake",
550 "pio_addr": 644245094400,
551 "update_data": false,
552 "warn_access": "",
553 "pio_latency": 200,
554 "system": "system",
555 "eventq_index": 0,
556 "default_p_state": "UNDEFINED",
557 "p_state_clk_gate_max": 2000000000,
558 "type": "IsaFake",
559 "p_state_clk_gate_min": 2,
560 "power_model": null,
561 "ret_data32": 4294967295,
562 "path": "system.t1000.fake_clk",
563 "ret_data16": 65535,
564 "ret_data8": 255,
565 "name": "fake_clk",
566 "ret_bad_addr": false,
567 "pio_size": 4294967296,
568 "p_state_clk_gate_bins": 20
569 }
570 },
571 "partition_desc_addr": 133445976064,
572 "symbolfile": "",
573 "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh",
574 "thermal_model": null,
575 "hypervisor_addr": 1099243257856,
576 "mem_ranges": [
577 "1048576:68157439",
578 "2147483648:2415919103"
579 ],
580 "cxx_class": "SparcSystem",
581 "work_begin_cpu_id_exit": -1,
582 "load_offset": 0,
583 "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin",
584 "work_end_ckpt_count": 0,
585 "work_begin_exit_count": 0,
586 "openboot_addr": 1099243716608,
587 "p_state_clk_gate_min": 2,
588 "nvram_addr": 133429198848,
589 "memories": [
590 "system.hypervisor_desc",
591 "system.nvram",
592 "system.partition_desc",
593 "system.physmem0",
594 "system.physmem1",
595 "system.rom"
596 ],
597 "work_begin_ckpt_count": 0,
598 "partition_desc": {
599 "range": "133445976064:133445984255",
600 "latency": 60,
601 "name": "partition_desc",
602 "p_state_clk_gate_min": 2,
603 "eventq_index": 0,
604 "p_state_clk_gate_bins": 20,
605 "default_p_state": "UNDEFINED",
606 "clk_domain": "system.clk_domain",
607 "power_model": null,
608 "latency_var": 0,
609 "bandwidth": "0.000000",
610 "conf_table_reported": true,
611 "cxx_class": "SimpleMemory",
612 "p_state_clk_gate_max": 2000000000,
613 "path": "system.partition_desc",
614 "null": false,
615 "type": "SimpleMemory",
616 "port": {
617 "peer": "system.membus.master[6]",
618 "role": "SLAVE"
619 },
620 "in_addr_map": true
621 },
622 "clk_domain": {
623 "name": "clk_domain",
624 "clock": [
625 2
626 ],
627 "init_perf_level": 0,
628 "voltage_domain": "system.voltage_domain",
629 "eventq_index": 0,
630 "cxx_class": "SrcClockDomain",
631 "path": "system.clk_domain",
632 "type": "SrcClockDomain",
633 "domain_id": -1
634 },
635 "hypervisor_desc": {
636 "range": "133446500352:133446508543",
637 "latency": 60,
638 "name": "hypervisor_desc",
639 "p_state_clk_gate_min": 2,
640 "eventq_index": 0,
641 "p_state_clk_gate_bins": 20,
642 "default_p_state": "UNDEFINED",
643 "clk_domain": "system.clk_domain",
644 "power_model": null,
645 "latency_var": 0,
646 "bandwidth": "0.000000",
647 "conf_table_reported": true,
648 "cxx_class": "SimpleMemory",
649 "p_state_clk_gate_max": 2000000000,
650 "path": "system.hypervisor_desc",
651 "null": false,
652 "type": "SimpleMemory",
653 "port": {
654 "peer": "system.membus.master[5]",
655 "role": "SLAVE"
656 },
657 "in_addr_map": true
658 },
659 "membus": {
660 "point_of_coherency": true,
661 "system": "system",
662 "response_latency": 2,
663 "cxx_class": "CoherentXBar",
664 "badaddr_responder": {
665 "pio": {
666 "peer": "system.membus.default",
667 "role": "SLAVE"
668 },
669 "ret_data64": 18446744073709551615,
670 "fake_mem": false,
671 "clk_domain": "system.clk_domain",
672 "cxx_class": "IsaFake",
673 "pio_addr": 0,
674 "update_data": false,
675 "warn_access": "",
676 "pio_latency": 200,
677 "system": "system",
678 "eventq_index": 0,
679 "default_p_state": "UNDEFINED",
680 "p_state_clk_gate_max": 2000000000,
681 "type": "IsaFake",
682 "p_state_clk_gate_min": 2,
683 "power_model": null,
684 "ret_data32": 4294967295,
685 "path": "system.membus.badaddr_responder",
686 "ret_data16": 65535,
687 "ret_data8": 255,
688 "name": "badaddr_responder",
689 "ret_bad_addr": true,
690 "pio_size": 8,
691 "p_state_clk_gate_bins": 20
692 },
693 "forward_latency": 4,
694 "clk_domain": "system.clk_domain",
695 "width": 16,
696 "eventq_index": 0,
697 "default_p_state": "UNDEFINED",
698 "p_state_clk_gate_max": 2000000000,
699 "master": {
700 "peer": [
701 "system.t1000.iob.pio",
702 "system.t1000.htod.pio",
703 "system.bridge.slave",
704 "system.rom.port",
705 "system.nvram.port",
706 "system.hypervisor_desc.port",
707 "system.partition_desc.port",
708 "system.physmem0.port",
709 "system.physmem1.port"
710 ],
711 "role": "MASTER"
712 },
713 "type": "CoherentXBar",
714 "frontend_latency": 3,
715 "slave": {
716 "peer": [
717 "system.system_port",
718 "system.cpu.icache_port",
719 "system.cpu.dcache_port"
720 ],
721 "role": "SLAVE"
722 },
723 "p_state_clk_gate_min": 2,
| 1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
16 "clk_domain": "system.clk_domain",
17 "power_model": null,
18 "latency_var": 0,
19 "bandwidth": "0.000000",
20 "conf_table_reported": true,
21 "cxx_class": "SimpleMemory",
22 "p_state_clk_gate_max": 2000000000,
23 "path": "system.rom",
24 "null": false,
25 "type": "SimpleMemory",
26 "port": {
27 "peer": "system.membus.master[3]",
28 "role": "SLAVE"
29 },
30 "in_addr_map": true
31 },
32 "bridge": {
33 "ranges": [
34 "133412421632:133412421639",
35 "134217728000:554050781183",
36 "644245094400:652835028991",
37 "725849473024:1095485095935",
38 "1099255955456:1099255955463"
39 ],
40 "slave": {
41 "peer": "system.membus.master[2]",
42 "role": "SLAVE"
43 },
44 "name": "bridge",
45 "p_state_clk_gate_min": 2,
46 "p_state_clk_gate_bins": 20,
47 "cxx_class": "Bridge",
48 "req_size": 16,
49 "clk_domain": "system.clk_domain",
50 "power_model": null,
51 "delay": 100,
52 "eventq_index": 0,
53 "master": {
54 "peer": "system.iobus.slave[0]",
55 "role": "MASTER"
56 },
57 "default_p_state": "UNDEFINED",
58 "p_state_clk_gate_max": 2000000000,
59 "path": "system.bridge",
60 "resp_size": 16,
61 "type": "Bridge"
62 },
63 "iobus": {
64 "forward_latency": 1,
65 "slave": {
66 "peer": [
67 "system.bridge.master"
68 ],
69 "role": "SLAVE"
70 },
71 "name": "iobus",
72 "p_state_clk_gate_min": 2,
73 "p_state_clk_gate_bins": 20,
74 "cxx_class": "NoncoherentXBar",
75 "clk_domain": "system.clk_domain",
76 "power_model": null,
77 "width": 16,
78 "eventq_index": 0,
79 "master": {
80 "peer": [
81 "system.t1000.fake_clk.pio",
82 "system.t1000.fake_membnks.pio",
83 "system.t1000.fake_l2_1.pio",
84 "system.t1000.fake_l2_2.pio",
85 "system.t1000.fake_l2_3.pio",
86 "system.t1000.fake_l2_4.pio",
87 "system.t1000.fake_l2esr_1.pio",
88 "system.t1000.fake_l2esr_2.pio",
89 "system.t1000.fake_l2esr_3.pio",
90 "system.t1000.fake_l2esr_4.pio",
91 "system.t1000.fake_ssi.pio",
92 "system.t1000.fake_jbi.pio",
93 "system.t1000.puart0.pio",
94 "system.t1000.hvuart.pio",
95 "system.disk0.pio"
96 ],
97 "role": "MASTER"
98 },
99 "response_latency": 2,
100 "default_p_state": "UNDEFINED",
101 "p_state_clk_gate_max": 2000000000,
102 "path": "system.iobus",
103 "type": "NoncoherentXBar",
104 "use_default_range": false,
105 "frontend_latency": 2
106 },
107 "t1000": {
108 "htod": {
109 "name": "htod",
110 "p_state_clk_gate_min": 2,
111 "pio": {
112 "peer": "system.membus.master[1]",
113 "role": "SLAVE"
114 },
115 "p_state_clk_gate_bins": 20,
116 "cxx_class": "DumbTOD",
117 "pio_latency": 200,
118 "clk_domain": "system.clk_domain",
119 "power_model": null,
120 "system": "system",
121 "eventq_index": 0,
122 "time": "Thu Jan 1 00:00:00 2009",
123 "default_p_state": "UNDEFINED",
124 "p_state_clk_gate_max": 2000000000,
125 "path": "system.t1000.htod",
126 "pio_addr": 1099255906296,
127 "type": "DumbTOD"
128 },
129 "puart0": {
130 "name": "puart0",
131 "p_state_clk_gate_min": 2,
132 "pio": {
133 "peer": "system.iobus.master[12]",
134 "role": "SLAVE"
135 },
136 "p_state_clk_gate_bins": 20,
137 "cxx_class": "Uart8250",
138 "pio_latency": 200,
139 "clk_domain": "system.clk_domain",
140 "power_model": null,
141 "system": "system",
142 "terminal": "system.t1000.pterm",
143 "platform": "system.t1000",
144 "eventq_index": 0,
145 "default_p_state": "UNDEFINED",
146 "p_state_clk_gate_max": 2000000000,
147 "path": "system.t1000.puart0",
148 "pio_addr": 133412421632,
149 "type": "Uart8250"
150 },
151 "fake_membnks": {
152 "pio": {
153 "peer": "system.iobus.master[1]",
154 "role": "SLAVE"
155 },
156 "ret_data64": 0,
157 "fake_mem": false,
158 "clk_domain": "system.clk_domain",
159 "cxx_class": "IsaFake",
160 "pio_addr": 648540061696,
161 "update_data": false,
162 "warn_access": "",
163 "pio_latency": 200,
164 "system": "system",
165 "eventq_index": 0,
166 "default_p_state": "UNDEFINED",
167 "p_state_clk_gate_max": 2000000000,
168 "type": "IsaFake",
169 "p_state_clk_gate_min": 2,
170 "power_model": null,
171 "ret_data32": 4294967295,
172 "path": "system.t1000.fake_membnks",
173 "ret_data16": 65535,
174 "ret_data8": 255,
175 "name": "fake_membnks",
176 "ret_bad_addr": false,
177 "pio_size": 16384,
178 "p_state_clk_gate_bins": 20
179 },
180 "cxx_class": "T1000",
181 "fake_jbi": {
182 "pio": {
183 "peer": "system.iobus.master[11]",
184 "role": "SLAVE"
185 },
186 "ret_data64": 18446744073709551615,
187 "fake_mem": false,
188 "clk_domain": "system.clk_domain",
189 "cxx_class": "IsaFake",
190 "pio_addr": 549755813888,
191 "update_data": false,
192 "warn_access": "",
193 "pio_latency": 200,
194 "system": "system",
195 "eventq_index": 0,
196 "default_p_state": "UNDEFINED",
197 "p_state_clk_gate_max": 2000000000,
198 "type": "IsaFake",
199 "p_state_clk_gate_min": 2,
200 "power_model": null,
201 "ret_data32": 4294967295,
202 "path": "system.t1000.fake_jbi",
203 "ret_data16": 65535,
204 "ret_data8": 255,
205 "name": "fake_jbi",
206 "ret_bad_addr": false,
207 "pio_size": 4294967296,
208 "p_state_clk_gate_bins": 20
209 },
210 "intrctrl": "system.intrctrl",
211 "fake_l2esr_2": {
212 "pio": {
213 "peer": "system.iobus.master[7]",
214 "role": "SLAVE"
215 },
216 "ret_data64": 0,
217 "fake_mem": false,
218 "clk_domain": "system.clk_domain",
219 "cxx_class": "IsaFake",
220 "pio_addr": 734439407680,
221 "update_data": true,
222 "warn_access": "",
223 "pio_latency": 200,
224 "system": "system",
225 "eventq_index": 0,
226 "default_p_state": "UNDEFINED",
227 "p_state_clk_gate_max": 2000000000,
228 "type": "IsaFake",
229 "p_state_clk_gate_min": 2,
230 "power_model": null,
231 "ret_data32": 4294967295,
232 "path": "system.t1000.fake_l2esr_2",
233 "ret_data16": 65535,
234 "ret_data8": 255,
235 "name": "fake_l2esr_2",
236 "ret_bad_addr": false,
237 "pio_size": 8,
238 "p_state_clk_gate_bins": 20
239 },
240 "system": "system",
241 "eventq_index": 0,
242 "hterm": {
243 "name": "hterm",
244 "output": true,
245 "number": 0,
246 "intr_control": "system.intrctrl",
247 "eventq_index": 0,
248 "cxx_class": "Terminal",
249 "path": "system.t1000.hterm",
250 "type": "Terminal",
251 "port": 3456
252 },
253 "type": "T1000",
254 "fake_l2_4": {
255 "pio": {
256 "peer": "system.iobus.master[5]",
257 "role": "SLAVE"
258 },
259 "ret_data64": 1,
260 "fake_mem": false,
261 "clk_domain": "system.clk_domain",
262 "cxx_class": "IsaFake",
263 "pio_addr": 725849473216,
264 "update_data": true,
265 "warn_access": "",
266 "pio_latency": 200,
267 "system": "system",
268 "eventq_index": 0,
269 "default_p_state": "UNDEFINED",
270 "p_state_clk_gate_max": 2000000000,
271 "type": "IsaFake",
272 "p_state_clk_gate_min": 2,
273 "power_model": null,
274 "ret_data32": 4294967295,
275 "path": "system.t1000.fake_l2_4",
276 "ret_data16": 65535,
277 "ret_data8": 255,
278 "name": "fake_l2_4",
279 "ret_bad_addr": false,
280 "pio_size": 8,
281 "p_state_clk_gate_bins": 20
282 },
283 "fake_l2_1": {
284 "pio": {
285 "peer": "system.iobus.master[2]",
286 "role": "SLAVE"
287 },
288 "ret_data64": 1,
289 "fake_mem": false,
290 "clk_domain": "system.clk_domain",
291 "cxx_class": "IsaFake",
292 "pio_addr": 725849473024,
293 "update_data": true,
294 "warn_access": "",
295 "pio_latency": 200,
296 "system": "system",
297 "eventq_index": 0,
298 "default_p_state": "UNDEFINED",
299 "p_state_clk_gate_max": 2000000000,
300 "type": "IsaFake",
301 "p_state_clk_gate_min": 2,
302 "power_model": null,
303 "ret_data32": 4294967295,
304 "path": "system.t1000.fake_l2_1",
305 "ret_data16": 65535,
306 "ret_data8": 255,
307 "name": "fake_l2_1",
308 "ret_bad_addr": false,
309 "pio_size": 8,
310 "p_state_clk_gate_bins": 20
311 },
312 "fake_l2_2": {
313 "pio": {
314 "peer": "system.iobus.master[3]",
315 "role": "SLAVE"
316 },
317 "ret_data64": 1,
318 "fake_mem": false,
319 "clk_domain": "system.clk_domain",
320 "cxx_class": "IsaFake",
321 "pio_addr": 725849473088,
322 "update_data": true,
323 "warn_access": "",
324 "pio_latency": 200,
325 "system": "system",
326 "eventq_index": 0,
327 "default_p_state": "UNDEFINED",
328 "p_state_clk_gate_max": 2000000000,
329 "type": "IsaFake",
330 "p_state_clk_gate_min": 2,
331 "power_model": null,
332 "ret_data32": 4294967295,
333 "path": "system.t1000.fake_l2_2",
334 "ret_data16": 65535,
335 "ret_data8": 255,
336 "name": "fake_l2_2",
337 "ret_bad_addr": false,
338 "pio_size": 8,
339 "p_state_clk_gate_bins": 20
340 },
341 "fake_l2_3": {
342 "pio": {
343 "peer": "system.iobus.master[4]",
344 "role": "SLAVE"
345 },
346 "ret_data64": 1,
347 "fake_mem": false,
348 "clk_domain": "system.clk_domain",
349 "cxx_class": "IsaFake",
350 "pio_addr": 725849473152,
351 "update_data": true,
352 "warn_access": "",
353 "pio_latency": 200,
354 "system": "system",
355 "eventq_index": 0,
356 "default_p_state": "UNDEFINED",
357 "p_state_clk_gate_max": 2000000000,
358 "type": "IsaFake",
359 "p_state_clk_gate_min": 2,
360 "power_model": null,
361 "ret_data32": 4294967295,
362 "path": "system.t1000.fake_l2_3",
363 "ret_data16": 65535,
364 "ret_data8": 255,
365 "name": "fake_l2_3",
366 "ret_bad_addr": false,
367 "pio_size": 8,
368 "p_state_clk_gate_bins": 20
369 },
370 "pterm": {
371 "name": "pterm",
372 "output": true,
373 "number": 0,
374 "intr_control": "system.intrctrl",
375 "eventq_index": 0,
376 "cxx_class": "Terminal",
377 "path": "system.t1000.pterm",
378 "type": "Terminal",
379 "port": 3456
380 },
381 "path": "system.t1000",
382 "iob": {
383 "name": "iob",
384 "p_state_clk_gate_min": 2,
385 "pio": {
386 "peer": "system.membus.master[0]",
387 "role": "SLAVE"
388 },
389 "p_state_clk_gate_bins": 20,
390 "cxx_class": "Iob",
391 "pio_latency": 2,
392 "clk_domain": "system.clk_domain",
393 "power_model": null,
394 "system": "system",
395 "platform": "system.t1000",
396 "eventq_index": 0,
397 "default_p_state": "UNDEFINED",
398 "p_state_clk_gate_max": 2000000000,
399 "path": "system.t1000.iob",
400 "type": "Iob"
401 },
402 "hvuart": {
403 "name": "hvuart",
404 "p_state_clk_gate_min": 2,
405 "pio": {
406 "peer": "system.iobus.master[13]",
407 "role": "SLAVE"
408 },
409 "p_state_clk_gate_bins": 20,
410 "cxx_class": "Uart8250",
411 "pio_latency": 200,
412 "clk_domain": "system.clk_domain",
413 "power_model": null,
414 "system": "system",
415 "terminal": "system.t1000.hterm",
416 "platform": "system.t1000",
417 "eventq_index": 0,
418 "default_p_state": "UNDEFINED",
419 "p_state_clk_gate_max": 2000000000,
420 "path": "system.t1000.hvuart",
421 "pio_addr": 1099255955456,
422 "type": "Uart8250"
423 },
424 "name": "t1000",
425 "fake_l2esr_3": {
426 "pio": {
427 "peer": "system.iobus.master[8]",
428 "role": "SLAVE"
429 },
430 "ret_data64": 0,
431 "fake_mem": false,
432 "clk_domain": "system.clk_domain",
433 "cxx_class": "IsaFake",
434 "pio_addr": 734439407744,
435 "update_data": true,
436 "warn_access": "",
437 "pio_latency": 200,
438 "system": "system",
439 "eventq_index": 0,
440 "default_p_state": "UNDEFINED",
441 "p_state_clk_gate_max": 2000000000,
442 "type": "IsaFake",
443 "p_state_clk_gate_min": 2,
444 "power_model": null,
445 "ret_data32": 4294967295,
446 "path": "system.t1000.fake_l2esr_3",
447 "ret_data16": 65535,
448 "ret_data8": 255,
449 "name": "fake_l2esr_3",
450 "ret_bad_addr": false,
451 "pio_size": 8,
452 "p_state_clk_gate_bins": 20
453 },
454 "fake_ssi": {
455 "pio": {
456 "peer": "system.iobus.master[10]",
457 "role": "SLAVE"
458 },
459 "ret_data64": 18446744073709551615,
460 "fake_mem": false,
461 "clk_domain": "system.clk_domain",
462 "cxx_class": "IsaFake",
463 "pio_addr": 1095216660480,
464 "update_data": false,
465 "warn_access": "",
466 "pio_latency": 200,
467 "system": "system",
468 "eventq_index": 0,
469 "default_p_state": "UNDEFINED",
470 "p_state_clk_gate_max": 2000000000,
471 "type": "IsaFake",
472 "p_state_clk_gate_min": 2,
473 "power_model": null,
474 "ret_data32": 4294967295,
475 "path": "system.t1000.fake_ssi",
476 "ret_data16": 65535,
477 "ret_data8": 255,
478 "name": "fake_ssi",
479 "ret_bad_addr": false,
480 "pio_size": 268435456,
481 "p_state_clk_gate_bins": 20
482 },
483 "fake_l2esr_1": {
484 "pio": {
485 "peer": "system.iobus.master[6]",
486 "role": "SLAVE"
487 },
488 "ret_data64": 0,
489 "fake_mem": false,
490 "clk_domain": "system.clk_domain",
491 "cxx_class": "IsaFake",
492 "pio_addr": 734439407616,
493 "update_data": true,
494 "warn_access": "",
495 "pio_latency": 200,
496 "system": "system",
497 "eventq_index": 0,
498 "default_p_state": "UNDEFINED",
499 "p_state_clk_gate_max": 2000000000,
500 "type": "IsaFake",
501 "p_state_clk_gate_min": 2,
502 "power_model": null,
503 "ret_data32": 4294967295,
504 "path": "system.t1000.fake_l2esr_1",
505 "ret_data16": 65535,
506 "ret_data8": 255,
507 "name": "fake_l2esr_1",
508 "ret_bad_addr": false,
509 "pio_size": 8,
510 "p_state_clk_gate_bins": 20
511 },
512 "fake_l2esr_4": {
513 "pio": {
514 "peer": "system.iobus.master[9]",
515 "role": "SLAVE"
516 },
517 "ret_data64": 0,
518 "fake_mem": false,
519 "clk_domain": "system.clk_domain",
520 "cxx_class": "IsaFake",
521 "pio_addr": 734439407808,
522 "update_data": true,
523 "warn_access": "",
524 "pio_latency": 200,
525 "system": "system",
526 "eventq_index": 0,
527 "default_p_state": "UNDEFINED",
528 "p_state_clk_gate_max": 2000000000,
529 "type": "IsaFake",
530 "p_state_clk_gate_min": 2,
531 "power_model": null,
532 "ret_data32": 4294967295,
533 "path": "system.t1000.fake_l2esr_4",
534 "ret_data16": 65535,
535 "ret_data8": 255,
536 "name": "fake_l2esr_4",
537 "ret_bad_addr": false,
538 "pio_size": 8,
539 "p_state_clk_gate_bins": 20
540 },
541 "fake_clk": {
542 "pio": {
543 "peer": "system.iobus.master[0]",
544 "role": "SLAVE"
545 },
546 "ret_data64": 18446744073709551615,
547 "fake_mem": false,
548 "clk_domain": "system.clk_domain",
549 "cxx_class": "IsaFake",
550 "pio_addr": 644245094400,
551 "update_data": false,
552 "warn_access": "",
553 "pio_latency": 200,
554 "system": "system",
555 "eventq_index": 0,
556 "default_p_state": "UNDEFINED",
557 "p_state_clk_gate_max": 2000000000,
558 "type": "IsaFake",
559 "p_state_clk_gate_min": 2,
560 "power_model": null,
561 "ret_data32": 4294967295,
562 "path": "system.t1000.fake_clk",
563 "ret_data16": 65535,
564 "ret_data8": 255,
565 "name": "fake_clk",
566 "ret_bad_addr": false,
567 "pio_size": 4294967296,
568 "p_state_clk_gate_bins": 20
569 }
570 },
571 "partition_desc_addr": 133445976064,
572 "symbolfile": "",
573 "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh",
574 "thermal_model": null,
575 "hypervisor_addr": 1099243257856,
576 "mem_ranges": [
577 "1048576:68157439",
578 "2147483648:2415919103"
579 ],
580 "cxx_class": "SparcSystem",
581 "work_begin_cpu_id_exit": -1,
582 "load_offset": 0,
583 "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin",
584 "work_end_ckpt_count": 0,
585 "work_begin_exit_count": 0,
586 "openboot_addr": 1099243716608,
587 "p_state_clk_gate_min": 2,
588 "nvram_addr": 133429198848,
589 "memories": [
590 "system.hypervisor_desc",
591 "system.nvram",
592 "system.partition_desc",
593 "system.physmem0",
594 "system.physmem1",
595 "system.rom"
596 ],
597 "work_begin_ckpt_count": 0,
598 "partition_desc": {
599 "range": "133445976064:133445984255",
600 "latency": 60,
601 "name": "partition_desc",
602 "p_state_clk_gate_min": 2,
603 "eventq_index": 0,
604 "p_state_clk_gate_bins": 20,
605 "default_p_state": "UNDEFINED",
606 "clk_domain": "system.clk_domain",
607 "power_model": null,
608 "latency_var": 0,
609 "bandwidth": "0.000000",
610 "conf_table_reported": true,
611 "cxx_class": "SimpleMemory",
612 "p_state_clk_gate_max": 2000000000,
613 "path": "system.partition_desc",
614 "null": false,
615 "type": "SimpleMemory",
616 "port": {
617 "peer": "system.membus.master[6]",
618 "role": "SLAVE"
619 },
620 "in_addr_map": true
621 },
622 "clk_domain": {
623 "name": "clk_domain",
624 "clock": [
625 2
626 ],
627 "init_perf_level": 0,
628 "voltage_domain": "system.voltage_domain",
629 "eventq_index": 0,
630 "cxx_class": "SrcClockDomain",
631 "path": "system.clk_domain",
632 "type": "SrcClockDomain",
633 "domain_id": -1
634 },
635 "hypervisor_desc": {
636 "range": "133446500352:133446508543",
637 "latency": 60,
638 "name": "hypervisor_desc",
639 "p_state_clk_gate_min": 2,
640 "eventq_index": 0,
641 "p_state_clk_gate_bins": 20,
642 "default_p_state": "UNDEFINED",
643 "clk_domain": "system.clk_domain",
644 "power_model": null,
645 "latency_var": 0,
646 "bandwidth": "0.000000",
647 "conf_table_reported": true,
648 "cxx_class": "SimpleMemory",
649 "p_state_clk_gate_max": 2000000000,
650 "path": "system.hypervisor_desc",
651 "null": false,
652 "type": "SimpleMemory",
653 "port": {
654 "peer": "system.membus.master[5]",
655 "role": "SLAVE"
656 },
657 "in_addr_map": true
658 },
659 "membus": {
660 "point_of_coherency": true,
661 "system": "system",
662 "response_latency": 2,
663 "cxx_class": "CoherentXBar",
664 "badaddr_responder": {
665 "pio": {
666 "peer": "system.membus.default",
667 "role": "SLAVE"
668 },
669 "ret_data64": 18446744073709551615,
670 "fake_mem": false,
671 "clk_domain": "system.clk_domain",
672 "cxx_class": "IsaFake",
673 "pio_addr": 0,
674 "update_data": false,
675 "warn_access": "",
676 "pio_latency": 200,
677 "system": "system",
678 "eventq_index": 0,
679 "default_p_state": "UNDEFINED",
680 "p_state_clk_gate_max": 2000000000,
681 "type": "IsaFake",
682 "p_state_clk_gate_min": 2,
683 "power_model": null,
684 "ret_data32": 4294967295,
685 "path": "system.membus.badaddr_responder",
686 "ret_data16": 65535,
687 "ret_data8": 255,
688 "name": "badaddr_responder",
689 "ret_bad_addr": true,
690 "pio_size": 8,
691 "p_state_clk_gate_bins": 20
692 },
693 "forward_latency": 4,
694 "clk_domain": "system.clk_domain",
695 "width": 16,
696 "eventq_index": 0,
697 "default_p_state": "UNDEFINED",
698 "p_state_clk_gate_max": 2000000000,
699 "master": {
700 "peer": [
701 "system.t1000.iob.pio",
702 "system.t1000.htod.pio",
703 "system.bridge.slave",
704 "system.rom.port",
705 "system.nvram.port",
706 "system.hypervisor_desc.port",
707 "system.partition_desc.port",
708 "system.physmem0.port",
709 "system.physmem1.port"
710 ],
711 "role": "MASTER"
712 },
713 "type": "CoherentXBar",
714 "frontend_latency": 3,
715 "slave": {
716 "peer": [
717 "system.system_port",
718 "system.cpu.icache_port",
719 "system.cpu.dcache_port"
720 ],
721 "role": "SLAVE"
722 },
723 "p_state_clk_gate_min": 2,
|
725 "power_model": null,
726 "path": "system.membus",
727 "snoop_response_latency": 4,
728 "name": "membus",
729 "default": {
730 "peer": "system.membus.badaddr_responder.pio",
731 "role": "MASTER"
732 },
733 "p_state_clk_gate_bins": 20,
734 "use_default_range": false
735 },
736 "nvram": {
737 "range": "133429198848:133429207039",
738 "latency": 60,
739 "name": "nvram",
740 "p_state_clk_gate_min": 2,
741 "eventq_index": 0,
742 "p_state_clk_gate_bins": 20,
743 "default_p_state": "UNDEFINED",
744 "clk_domain": "system.clk_domain",
745 "power_model": null,
746 "latency_var": 0,
747 "bandwidth": "0.000000",
748 "conf_table_reported": true,
749 "cxx_class": "SimpleMemory",
750 "p_state_clk_gate_max": 2000000000,
751 "path": "system.nvram",
752 "null": false,
753 "type": "SimpleMemory",
754 "port": {
755 "peer": "system.membus.master[4]",
756 "role": "SLAVE"
757 },
758 "in_addr_map": true
759 },
760 "eventq_index": 0,
761 "default_p_state": "UNDEFINED",
762 "p_state_clk_gate_max": 2000000000,
763 "dvfs_handler": {
764 "enable": false,
765 "name": "dvfs_handler",
766 "sys_clk_domain": "system.clk_domain",
767 "transition_latency": 200000,
768 "eventq_index": 0,
769 "cxx_class": "DVFSHandler",
770 "domains": [],
771 "path": "system.dvfs_handler",
772 "type": "DVFSHandler"
773 },
774 "work_end_exit_count": 0,
775 "hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin",
776 "openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin",
777 "voltage_domain": {
778 "name": "voltage_domain",
779 "eventq_index": 0,
780 "voltage": [
781 "1.0"
782 ],
783 "cxx_class": "VoltageDomain",
784 "path": "system.voltage_domain",
785 "type": "VoltageDomain"
786 },
787 "cache_line_size": 64,
788 "boot_osflags": "a",
789 "system_port": {
790 "peer": "system.membus.slave[0]",
791 "role": "MASTER"
792 },
793 "physmem": [
794 {
795 "range": "1048576:68157439",
796 "latency": 60,
797 "name": "physmem0",
798 "p_state_clk_gate_min": 2,
799 "eventq_index": 0,
800 "p_state_clk_gate_bins": 20,
801 "default_p_state": "UNDEFINED",
802 "clk_domain": "system.clk_domain",
803 "power_model": null,
804 "latency_var": 0,
805 "bandwidth": "0.000000",
806 "conf_table_reported": true,
807 "cxx_class": "SimpleMemory",
808 "p_state_clk_gate_max": 2000000000,
809 "path": "system.physmem0",
810 "null": false,
811 "type": "SimpleMemory",
812 "port": {
813 "peer": "system.membus.master[7]",
814 "role": "SLAVE"
815 },
816 "in_addr_map": true
817 },
818 {
819 "range": "2147483648:2415919103",
820 "latency": 60,
821 "name": "physmem1",
822 "p_state_clk_gate_min": 2,
823 "eventq_index": 0,
824 "p_state_clk_gate_bins": 20,
825 "default_p_state": "UNDEFINED",
826 "clk_domain": "system.clk_domain",
827 "power_model": null,
828 "latency_var": 0,
829 "bandwidth": "0.000000",
830 "conf_table_reported": true,
831 "cxx_class": "SimpleMemory",
832 "p_state_clk_gate_max": 2000000000,
833 "path": "system.physmem1",
834 "null": false,
835 "type": "SimpleMemory",
836 "port": {
837 "peer": "system.membus.master[8]",
838 "role": "SLAVE"
839 },
840 "in_addr_map": true
841 }
842 ],
843 "power_model": null,
844 "work_cpus_ckpt_count": 0,
845 "thermal_components": [],
846 "path": "system",
847 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
848 "cpu_clk_domain": {
849 "name": "cpu_clk_domain",
850 "clock": [
851 2
852 ],
853 "init_perf_level": 0,
854 "voltage_domain": "system.voltage_domain",
855 "eventq_index": 0,
856 "cxx_class": "SrcClockDomain",
857 "path": "system.cpu_clk_domain",
858 "type": "SrcClockDomain",
859 "domain_id": -1
860 },
861 "nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1",
862 "mem_mode": "atomic",
863 "name": "system",
864 "init_param": 0,
865 "type": "SparcSystem",
866 "partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin",
867 "load_addr_mask": 1099511627775,
868 "cpu": {
869 "do_statistics_insts": true,
870 "numThreads": 1,
871 "itb": {
872 "name": "itb",
873 "eventq_index": 0,
874 "cxx_class": "SparcISA::TLB",
875 "path": "system.cpu.itb",
876 "type": "SparcTLB",
877 "size": 64
878 },
879 "simulate_data_stalls": false,
880 "function_trace": false,
881 "do_checkpoint_insts": true,
882 "cxx_class": "AtomicSimpleCPU",
883 "max_loads_all_threads": 0,
884 "system": "system",
885 "clk_domain": "system.cpu_clk_domain",
886 "function_trace_start": 0,
887 "cpu_id": 0,
888 "width": 1,
889 "checker": null,
890 "eventq_index": 0,
891 "default_p_state": "UNDEFINED",
892 "p_state_clk_gate_max": 2000000000,
893 "do_quiesce": true,
894 "type": "AtomicSimpleCPU",
895 "fastmem": false,
896 "profile": 0,
897 "icache_port": {
898 "peer": "system.membus.slave[1]",
899 "role": "MASTER"
900 },
901 "p_state_clk_gate_bins": 20,
902 "p_state_clk_gate_min": 2,
903 "interrupts": [
904 {
905 "eventq_index": 0,
906 "path": "system.cpu.interrupts",
907 "type": "SparcInterrupts",
908 "name": "interrupts",
909 "cxx_class": "SparcISA::Interrupts"
910 }
911 ],
912 "dcache_port": {
913 "peer": "system.membus.slave[2]",
914 "role": "MASTER"
915 },
916 "socket_id": 0,
917 "power_model": null,
918 "max_insts_all_threads": 0,
919 "path": "system.cpu",
920 "max_loads_any_thread": 0,
921 "switched_out": false,
922 "workload": [],
923 "name": "cpu",
924 "dtb": {
925 "name": "dtb",
926 "eventq_index": 0,
927 "cxx_class": "SparcISA::TLB",
928 "path": "system.cpu.dtb",
929 "type": "SparcTLB",
930 "size": 64
931 },
932 "simpoint_start_insts": [],
933 "max_insts_any_thread": 0,
934 "simulate_inst_stalls": false,
935 "progress_interval": 0,
936 "branchPred": null,
937 "isa": [
938 {
939 "eventq_index": 0,
940 "path": "system.cpu.isa",
941 "type": "SparcISA",
942 "name": "isa",
943 "cxx_class": "SparcISA::ISA"
944 }
945 ],
946 "tracer": {
947 "eventq_index": 0,
948 "path": "system.cpu.tracer",
949 "type": "ExeTracer",
950 "name": "tracer",
951 "cxx_class": "Trace::ExeTracer"
952 }
953 },
954 "intrctrl": {
955 "name": "intrctrl",
956 "sys": "system",
957 "eventq_index": 0,
958 "cxx_class": "IntrControl",
959 "path": "system.intrctrl",
960 "type": "IntrControl"
961 },
962 "disk0": {
963 "name": "disk0",
964 "p_state_clk_gate_min": 2,
965 "pio": {
966 "peer": "system.iobus.master[14]",
967 "role": "SLAVE"
968 },
969 "p_state_clk_gate_bins": 20,
970 "image": {
971 "read_only": false,
972 "name": "image",
973 "cxx_class": "CowDiskImage",
974 "eventq_index": 0,
975 "child": {
976 "read_only": true,
977 "name": "child",
978 "eventq_index": 0,
979 "cxx_class": "RawDiskImage",
980 "path": "system.disk0.image.child",
981 "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2",
982 "type": "RawDiskImage"
983 },
984 "path": "system.disk0.image",
985 "image_file": "",
986 "type": "CowDiskImage",
987 "table_size": 65536
988 },
989 "cxx_class": "MmDisk",
990 "pio_latency": 200,
991 "clk_domain": "system.clk_domain",
992 "power_model": null,
993 "system": "system",
994 "eventq_index": 0,
995 "default_p_state": "UNDEFINED",
996 "p_state_clk_gate_max": 2000000000,
997 "path": "system.disk0",
998 "pio_addr": 134217728000,
999 "type": "MmDisk"
1000 },
1001 "multi_thread": false,
1002 "reset_addr": 1099243192320,
1003 "p_state_clk_gate_bins": 20,
1004 "hypervisor_desc_addr": 133446500352,
1005 "num_work_ids": 16,
1006 "work_item_id": -1,
1007 "exit_on_work_items": false
1008 },
1009 "time_sync_period": 200000000,
1010 "eventq_index": 0,
1011 "time_sync_spin_threshold": 200000,
1012 "cxx_class": "Root",
1013 "path": "root",
1014 "time_sync_enable": false,
1015 "type": "Root",
1016 "full_system": true
1017}
| 734 "power_model": null,
735 "path": "system.membus",
736 "snoop_response_latency": 4,
737 "name": "membus",
738 "default": {
739 "peer": "system.membus.badaddr_responder.pio",
740 "role": "MASTER"
741 },
742 "p_state_clk_gate_bins": 20,
743 "use_default_range": false
744 },
745 "nvram": {
746 "range": "133429198848:133429207039",
747 "latency": 60,
748 "name": "nvram",
749 "p_state_clk_gate_min": 2,
750 "eventq_index": 0,
751 "p_state_clk_gate_bins": 20,
752 "default_p_state": "UNDEFINED",
753 "clk_domain": "system.clk_domain",
754 "power_model": null,
755 "latency_var": 0,
756 "bandwidth": "0.000000",
757 "conf_table_reported": true,
758 "cxx_class": "SimpleMemory",
759 "p_state_clk_gate_max": 2000000000,
760 "path": "system.nvram",
761 "null": false,
762 "type": "SimpleMemory",
763 "port": {
764 "peer": "system.membus.master[4]",
765 "role": "SLAVE"
766 },
767 "in_addr_map": true
768 },
769 "eventq_index": 0,
770 "default_p_state": "UNDEFINED",
771 "p_state_clk_gate_max": 2000000000,
772 "dvfs_handler": {
773 "enable": false,
774 "name": "dvfs_handler",
775 "sys_clk_domain": "system.clk_domain",
776 "transition_latency": 200000,
777 "eventq_index": 0,
778 "cxx_class": "DVFSHandler",
779 "domains": [],
780 "path": "system.dvfs_handler",
781 "type": "DVFSHandler"
782 },
783 "work_end_exit_count": 0,
784 "hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin",
785 "openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin",
786 "voltage_domain": {
787 "name": "voltage_domain",
788 "eventq_index": 0,
789 "voltage": [
790 "1.0"
791 ],
792 "cxx_class": "VoltageDomain",
793 "path": "system.voltage_domain",
794 "type": "VoltageDomain"
795 },
796 "cache_line_size": 64,
797 "boot_osflags": "a",
798 "system_port": {
799 "peer": "system.membus.slave[0]",
800 "role": "MASTER"
801 },
802 "physmem": [
803 {
804 "range": "1048576:68157439",
805 "latency": 60,
806 "name": "physmem0",
807 "p_state_clk_gate_min": 2,
808 "eventq_index": 0,
809 "p_state_clk_gate_bins": 20,
810 "default_p_state": "UNDEFINED",
811 "clk_domain": "system.clk_domain",
812 "power_model": null,
813 "latency_var": 0,
814 "bandwidth": "0.000000",
815 "conf_table_reported": true,
816 "cxx_class": "SimpleMemory",
817 "p_state_clk_gate_max": 2000000000,
818 "path": "system.physmem0",
819 "null": false,
820 "type": "SimpleMemory",
821 "port": {
822 "peer": "system.membus.master[7]",
823 "role": "SLAVE"
824 },
825 "in_addr_map": true
826 },
827 {
828 "range": "2147483648:2415919103",
829 "latency": 60,
830 "name": "physmem1",
831 "p_state_clk_gate_min": 2,
832 "eventq_index": 0,
833 "p_state_clk_gate_bins": 20,
834 "default_p_state": "UNDEFINED",
835 "clk_domain": "system.clk_domain",
836 "power_model": null,
837 "latency_var": 0,
838 "bandwidth": "0.000000",
839 "conf_table_reported": true,
840 "cxx_class": "SimpleMemory",
841 "p_state_clk_gate_max": 2000000000,
842 "path": "system.physmem1",
843 "null": false,
844 "type": "SimpleMemory",
845 "port": {
846 "peer": "system.membus.master[8]",
847 "role": "SLAVE"
848 },
849 "in_addr_map": true
850 }
851 ],
852 "power_model": null,
853 "work_cpus_ckpt_count": 0,
854 "thermal_components": [],
855 "path": "system",
856 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
857 "cpu_clk_domain": {
858 "name": "cpu_clk_domain",
859 "clock": [
860 2
861 ],
862 "init_perf_level": 0,
863 "voltage_domain": "system.voltage_domain",
864 "eventq_index": 0,
865 "cxx_class": "SrcClockDomain",
866 "path": "system.cpu_clk_domain",
867 "type": "SrcClockDomain",
868 "domain_id": -1
869 },
870 "nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1",
871 "mem_mode": "atomic",
872 "name": "system",
873 "init_param": 0,
874 "type": "SparcSystem",
875 "partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin",
876 "load_addr_mask": 1099511627775,
877 "cpu": {
878 "do_statistics_insts": true,
879 "numThreads": 1,
880 "itb": {
881 "name": "itb",
882 "eventq_index": 0,
883 "cxx_class": "SparcISA::TLB",
884 "path": "system.cpu.itb",
885 "type": "SparcTLB",
886 "size": 64
887 },
888 "simulate_data_stalls": false,
889 "function_trace": false,
890 "do_checkpoint_insts": true,
891 "cxx_class": "AtomicSimpleCPU",
892 "max_loads_all_threads": 0,
893 "system": "system",
894 "clk_domain": "system.cpu_clk_domain",
895 "function_trace_start": 0,
896 "cpu_id": 0,
897 "width": 1,
898 "checker": null,
899 "eventq_index": 0,
900 "default_p_state": "UNDEFINED",
901 "p_state_clk_gate_max": 2000000000,
902 "do_quiesce": true,
903 "type": "AtomicSimpleCPU",
904 "fastmem": false,
905 "profile": 0,
906 "icache_port": {
907 "peer": "system.membus.slave[1]",
908 "role": "MASTER"
909 },
910 "p_state_clk_gate_bins": 20,
911 "p_state_clk_gate_min": 2,
912 "interrupts": [
913 {
914 "eventq_index": 0,
915 "path": "system.cpu.interrupts",
916 "type": "SparcInterrupts",
917 "name": "interrupts",
918 "cxx_class": "SparcISA::Interrupts"
919 }
920 ],
921 "dcache_port": {
922 "peer": "system.membus.slave[2]",
923 "role": "MASTER"
924 },
925 "socket_id": 0,
926 "power_model": null,
927 "max_insts_all_threads": 0,
928 "path": "system.cpu",
929 "max_loads_any_thread": 0,
930 "switched_out": false,
931 "workload": [],
932 "name": "cpu",
933 "dtb": {
934 "name": "dtb",
935 "eventq_index": 0,
936 "cxx_class": "SparcISA::TLB",
937 "path": "system.cpu.dtb",
938 "type": "SparcTLB",
939 "size": 64
940 },
941 "simpoint_start_insts": [],
942 "max_insts_any_thread": 0,
943 "simulate_inst_stalls": false,
944 "progress_interval": 0,
945 "branchPred": null,
946 "isa": [
947 {
948 "eventq_index": 0,
949 "path": "system.cpu.isa",
950 "type": "SparcISA",
951 "name": "isa",
952 "cxx_class": "SparcISA::ISA"
953 }
954 ],
955 "tracer": {
956 "eventq_index": 0,
957 "path": "system.cpu.tracer",
958 "type": "ExeTracer",
959 "name": "tracer",
960 "cxx_class": "Trace::ExeTracer"
961 }
962 },
963 "intrctrl": {
964 "name": "intrctrl",
965 "sys": "system",
966 "eventq_index": 0,
967 "cxx_class": "IntrControl",
968 "path": "system.intrctrl",
969 "type": "IntrControl"
970 },
971 "disk0": {
972 "name": "disk0",
973 "p_state_clk_gate_min": 2,
974 "pio": {
975 "peer": "system.iobus.master[14]",
976 "role": "SLAVE"
977 },
978 "p_state_clk_gate_bins": 20,
979 "image": {
980 "read_only": false,
981 "name": "image",
982 "cxx_class": "CowDiskImage",
983 "eventq_index": 0,
984 "child": {
985 "read_only": true,
986 "name": "child",
987 "eventq_index": 0,
988 "cxx_class": "RawDiskImage",
989 "path": "system.disk0.image.child",
990 "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2",
991 "type": "RawDiskImage"
992 },
993 "path": "system.disk0.image",
994 "image_file": "",
995 "type": "CowDiskImage",
996 "table_size": 65536
997 },
998 "cxx_class": "MmDisk",
999 "pio_latency": 200,
1000 "clk_domain": "system.clk_domain",
1001 "power_model": null,
1002 "system": "system",
1003 "eventq_index": 0,
1004 "default_p_state": "UNDEFINED",
1005 "p_state_clk_gate_max": 2000000000,
1006 "path": "system.disk0",
1007 "pio_addr": 134217728000,
1008 "type": "MmDisk"
1009 },
1010 "multi_thread": false,
1011 "reset_addr": 1099243192320,
1012 "p_state_clk_gate_bins": 20,
1013 "hypervisor_desc_addr": 133446500352,
1014 "num_work_ids": 16,
1015 "work_item_id": -1,
1016 "exit_on_work_items": false
1017 },
1018 "time_sync_period": 200000000,
1019 "eventq_index": 0,
1020 "time_sync_spin_threshold": 200000,
1021 "cxx_class": "Root",
1022 "path": "root",
1023 "time_sync_enable": false,
1024 "type": "Root",
1025 "full_system": true
1026}
|