config.json (11946:8eb1f2595a92) config.json (11950:8011fd8ce05c)
1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
16 "clk_domain": "system.clk_domain",
1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
16 "clk_domain": "system.clk_domain",
17 "power_model": null,
17 "latency_var": 0,
18 "bandwidth": "0.000000",
19 "conf_table_reported": true,
20 "cxx_class": "SimpleMemory",
21 "p_state_clk_gate_max": 2000000000,
22 "path": "system.rom",
23 "null": false,
24 "type": "SimpleMemory",
25 "port": {
26 "peer": "system.membus.master[3]",
27 "role": "SLAVE"
28 },
29 "in_addr_map": true
30 },
31 "bridge": {
32 "ranges": [
33 "133412421632:133412421639",
34 "134217728000:554050781183",
35 "644245094400:652835028991",
36 "725849473024:1095485095935",
37 "1099255955456:1099255955463"
38 ],
39 "slave": {
40 "peer": "system.membus.master[2]",
41 "role": "SLAVE"
42 },
43 "name": "bridge",
44 "p_state_clk_gate_min": 2,
45 "p_state_clk_gate_bins": 20,
46 "cxx_class": "Bridge",
47 "req_size": 16,
48 "clk_domain": "system.clk_domain",
18 "latency_var": 0,
19 "bandwidth": "0.000000",
20 "conf_table_reported": true,
21 "cxx_class": "SimpleMemory",
22 "p_state_clk_gate_max": 2000000000,
23 "path": "system.rom",
24 "null": false,
25 "type": "SimpleMemory",
26 "port": {
27 "peer": "system.membus.master[3]",
28 "role": "SLAVE"
29 },
30 "in_addr_map": true
31 },
32 "bridge": {
33 "ranges": [
34 "133412421632:133412421639",
35 "134217728000:554050781183",
36 "644245094400:652835028991",
37 "725849473024:1095485095935",
38 "1099255955456:1099255955463"
39 ],
40 "slave": {
41 "peer": "system.membus.master[2]",
42 "role": "SLAVE"
43 },
44 "name": "bridge",
45 "p_state_clk_gate_min": 2,
46 "p_state_clk_gate_bins": 20,
47 "cxx_class": "Bridge",
48 "req_size": 16,
49 "clk_domain": "system.clk_domain",
50 "power_model": null,
49 "delay": 100,
50 "eventq_index": 0,
51 "master": {
52 "peer": "system.iobus.slave[0]",
53 "role": "MASTER"
54 },
55 "default_p_state": "UNDEFINED",
56 "p_state_clk_gate_max": 2000000000,
57 "path": "system.bridge",
58 "resp_size": 16,
59 "type": "Bridge"
60 },
61 "iobus": {
62 "forward_latency": 1,
63 "slave": {
64 "peer": [
65 "system.bridge.master"
66 ],
67 "role": "SLAVE"
68 },
69 "name": "iobus",
70 "p_state_clk_gate_min": 2,
71 "p_state_clk_gate_bins": 20,
72 "cxx_class": "NoncoherentXBar",
73 "clk_domain": "system.clk_domain",
51 "delay": 100,
52 "eventq_index": 0,
53 "master": {
54 "peer": "system.iobus.slave[0]",
55 "role": "MASTER"
56 },
57 "default_p_state": "UNDEFINED",
58 "p_state_clk_gate_max": 2000000000,
59 "path": "system.bridge",
60 "resp_size": 16,
61 "type": "Bridge"
62 },
63 "iobus": {
64 "forward_latency": 1,
65 "slave": {
66 "peer": [
67 "system.bridge.master"
68 ],
69 "role": "SLAVE"
70 },
71 "name": "iobus",
72 "p_state_clk_gate_min": 2,
73 "p_state_clk_gate_bins": 20,
74 "cxx_class": "NoncoherentXBar",
75 "clk_domain": "system.clk_domain",
76 "power_model": null,
74 "width": 16,
75 "eventq_index": 0,
76 "master": {
77 "peer": [
78 "system.t1000.fake_clk.pio",
79 "system.t1000.fake_membnks.pio",
80 "system.t1000.fake_l2_1.pio",
81 "system.t1000.fake_l2_2.pio",
82 "system.t1000.fake_l2_3.pio",
83 "system.t1000.fake_l2_4.pio",
84 "system.t1000.fake_l2esr_1.pio",
85 "system.t1000.fake_l2esr_2.pio",
86 "system.t1000.fake_l2esr_3.pio",
87 "system.t1000.fake_l2esr_4.pio",
88 "system.t1000.fake_ssi.pio",
89 "system.t1000.fake_jbi.pio",
90 "system.t1000.puart0.pio",
91 "system.t1000.hvuart.pio",
92 "system.disk0.pio"
93 ],
94 "role": "MASTER"
95 },
96 "response_latency": 2,
97 "default_p_state": "UNDEFINED",
98 "p_state_clk_gate_max": 2000000000,
99 "path": "system.iobus",
100 "type": "NoncoherentXBar",
101 "use_default_range": false,
102 "frontend_latency": 2
103 },
104 "t1000": {
105 "htod": {
106 "name": "htod",
107 "p_state_clk_gate_min": 2,
108 "pio": {
109 "peer": "system.membus.master[1]",
110 "role": "SLAVE"
111 },
112 "p_state_clk_gate_bins": 20,
113 "cxx_class": "DumbTOD",
114 "pio_latency": 200,
115 "clk_domain": "system.clk_domain",
77 "width": 16,
78 "eventq_index": 0,
79 "master": {
80 "peer": [
81 "system.t1000.fake_clk.pio",
82 "system.t1000.fake_membnks.pio",
83 "system.t1000.fake_l2_1.pio",
84 "system.t1000.fake_l2_2.pio",
85 "system.t1000.fake_l2_3.pio",
86 "system.t1000.fake_l2_4.pio",
87 "system.t1000.fake_l2esr_1.pio",
88 "system.t1000.fake_l2esr_2.pio",
89 "system.t1000.fake_l2esr_3.pio",
90 "system.t1000.fake_l2esr_4.pio",
91 "system.t1000.fake_ssi.pio",
92 "system.t1000.fake_jbi.pio",
93 "system.t1000.puart0.pio",
94 "system.t1000.hvuart.pio",
95 "system.disk0.pio"
96 ],
97 "role": "MASTER"
98 },
99 "response_latency": 2,
100 "default_p_state": "UNDEFINED",
101 "p_state_clk_gate_max": 2000000000,
102 "path": "system.iobus",
103 "type": "NoncoherentXBar",
104 "use_default_range": false,
105 "frontend_latency": 2
106 },
107 "t1000": {
108 "htod": {
109 "name": "htod",
110 "p_state_clk_gate_min": 2,
111 "pio": {
112 "peer": "system.membus.master[1]",
113 "role": "SLAVE"
114 },
115 "p_state_clk_gate_bins": 20,
116 "cxx_class": "DumbTOD",
117 "pio_latency": 200,
118 "clk_domain": "system.clk_domain",
119 "power_model": null,
116 "system": "system",
117 "eventq_index": 0,
118 "time": "Thu Jan 1 00:00:00 2009",
119 "default_p_state": "UNDEFINED",
120 "p_state_clk_gate_max": 2000000000,
121 "path": "system.t1000.htod",
122 "pio_addr": 1099255906296,
123 "type": "DumbTOD"
124 },
125 "puart0": {
126 "name": "puart0",
127 "p_state_clk_gate_min": 2,
128 "pio": {
129 "peer": "system.iobus.master[12]",
130 "role": "SLAVE"
131 },
132 "p_state_clk_gate_bins": 20,
133 "cxx_class": "Uart8250",
134 "pio_latency": 200,
135 "clk_domain": "system.clk_domain",
120 "system": "system",
121 "eventq_index": 0,
122 "time": "Thu Jan 1 00:00:00 2009",
123 "default_p_state": "UNDEFINED",
124 "p_state_clk_gate_max": 2000000000,
125 "path": "system.t1000.htod",
126 "pio_addr": 1099255906296,
127 "type": "DumbTOD"
128 },
129 "puart0": {
130 "name": "puart0",
131 "p_state_clk_gate_min": 2,
132 "pio": {
133 "peer": "system.iobus.master[12]",
134 "role": "SLAVE"
135 },
136 "p_state_clk_gate_bins": 20,
137 "cxx_class": "Uart8250",
138 "pio_latency": 200,
139 "clk_domain": "system.clk_domain",
140 "power_model": null,
136 "system": "system",
137 "terminal": "system.t1000.pterm",
138 "platform": "system.t1000",
139 "eventq_index": 0,
140 "default_p_state": "UNDEFINED",
141 "p_state_clk_gate_max": 2000000000,
142 "path": "system.t1000.puart0",
143 "pio_addr": 133412421632,
144 "type": "Uart8250"
145 },
146 "fake_membnks": {
147 "pio": {
148 "peer": "system.iobus.master[1]",
149 "role": "SLAVE"
150 },
151 "ret_data64": 0,
152 "fake_mem": false,
153 "clk_domain": "system.clk_domain",
154 "cxx_class": "IsaFake",
155 "pio_addr": 648540061696,
156 "update_data": false,
157 "warn_access": "",
158 "pio_latency": 200,
159 "system": "system",
160 "eventq_index": 0,
161 "default_p_state": "UNDEFINED",
162 "p_state_clk_gate_max": 2000000000,
163 "type": "IsaFake",
164 "p_state_clk_gate_min": 2,
141 "system": "system",
142 "terminal": "system.t1000.pterm",
143 "platform": "system.t1000",
144 "eventq_index": 0,
145 "default_p_state": "UNDEFINED",
146 "p_state_clk_gate_max": 2000000000,
147 "path": "system.t1000.puart0",
148 "pio_addr": 133412421632,
149 "type": "Uart8250"
150 },
151 "fake_membnks": {
152 "pio": {
153 "peer": "system.iobus.master[1]",
154 "role": "SLAVE"
155 },
156 "ret_data64": 0,
157 "fake_mem": false,
158 "clk_domain": "system.clk_domain",
159 "cxx_class": "IsaFake",
160 "pio_addr": 648540061696,
161 "update_data": false,
162 "warn_access": "",
163 "pio_latency": 200,
164 "system": "system",
165 "eventq_index": 0,
166 "default_p_state": "UNDEFINED",
167 "p_state_clk_gate_max": 2000000000,
168 "type": "IsaFake",
169 "p_state_clk_gate_min": 2,
170 "power_model": null,
165 "ret_data32": 4294967295,
166 "path": "system.t1000.fake_membnks",
167 "ret_data16": 65535,
168 "ret_data8": 255,
169 "name": "fake_membnks",
170 "ret_bad_addr": false,
171 "pio_size": 16384,
172 "p_state_clk_gate_bins": 20
173 },
174 "cxx_class": "T1000",
175 "fake_jbi": {
176 "pio": {
177 "peer": "system.iobus.master[11]",
178 "role": "SLAVE"
179 },
180 "ret_data64": 18446744073709551615,
181 "fake_mem": false,
182 "clk_domain": "system.clk_domain",
183 "cxx_class": "IsaFake",
184 "pio_addr": 549755813888,
185 "update_data": false,
186 "warn_access": "",
187 "pio_latency": 200,
188 "system": "system",
189 "eventq_index": 0,
190 "default_p_state": "UNDEFINED",
191 "p_state_clk_gate_max": 2000000000,
192 "type": "IsaFake",
193 "p_state_clk_gate_min": 2,
171 "ret_data32": 4294967295,
172 "path": "system.t1000.fake_membnks",
173 "ret_data16": 65535,
174 "ret_data8": 255,
175 "name": "fake_membnks",
176 "ret_bad_addr": false,
177 "pio_size": 16384,
178 "p_state_clk_gate_bins": 20
179 },
180 "cxx_class": "T1000",
181 "fake_jbi": {
182 "pio": {
183 "peer": "system.iobus.master[11]",
184 "role": "SLAVE"
185 },
186 "ret_data64": 18446744073709551615,
187 "fake_mem": false,
188 "clk_domain": "system.clk_domain",
189 "cxx_class": "IsaFake",
190 "pio_addr": 549755813888,
191 "update_data": false,
192 "warn_access": "",
193 "pio_latency": 200,
194 "system": "system",
195 "eventq_index": 0,
196 "default_p_state": "UNDEFINED",
197 "p_state_clk_gate_max": 2000000000,
198 "type": "IsaFake",
199 "p_state_clk_gate_min": 2,
200 "power_model": null,
194 "ret_data32": 4294967295,
195 "path": "system.t1000.fake_jbi",
196 "ret_data16": 65535,
197 "ret_data8": 255,
198 "name": "fake_jbi",
199 "ret_bad_addr": false,
200 "pio_size": 4294967296,
201 "p_state_clk_gate_bins": 20
202 },
203 "intrctrl": "system.intrctrl",
204 "fake_l2esr_2": {
205 "pio": {
206 "peer": "system.iobus.master[7]",
207 "role": "SLAVE"
208 },
209 "ret_data64": 0,
210 "fake_mem": false,
211 "clk_domain": "system.clk_domain",
212 "cxx_class": "IsaFake",
213 "pio_addr": 734439407680,
214 "update_data": true,
215 "warn_access": "",
216 "pio_latency": 200,
217 "system": "system",
218 "eventq_index": 0,
219 "default_p_state": "UNDEFINED",
220 "p_state_clk_gate_max": 2000000000,
221 "type": "IsaFake",
222 "p_state_clk_gate_min": 2,
201 "ret_data32": 4294967295,
202 "path": "system.t1000.fake_jbi",
203 "ret_data16": 65535,
204 "ret_data8": 255,
205 "name": "fake_jbi",
206 "ret_bad_addr": false,
207 "pio_size": 4294967296,
208 "p_state_clk_gate_bins": 20
209 },
210 "intrctrl": "system.intrctrl",
211 "fake_l2esr_2": {
212 "pio": {
213 "peer": "system.iobus.master[7]",
214 "role": "SLAVE"
215 },
216 "ret_data64": 0,
217 "fake_mem": false,
218 "clk_domain": "system.clk_domain",
219 "cxx_class": "IsaFake",
220 "pio_addr": 734439407680,
221 "update_data": true,
222 "warn_access": "",
223 "pio_latency": 200,
224 "system": "system",
225 "eventq_index": 0,
226 "default_p_state": "UNDEFINED",
227 "p_state_clk_gate_max": 2000000000,
228 "type": "IsaFake",
229 "p_state_clk_gate_min": 2,
230 "power_model": null,
223 "ret_data32": 4294967295,
224 "path": "system.t1000.fake_l2esr_2",
225 "ret_data16": 65535,
226 "ret_data8": 255,
227 "name": "fake_l2esr_2",
228 "ret_bad_addr": false,
229 "pio_size": 8,
230 "p_state_clk_gate_bins": 20
231 },
232 "system": "system",
233 "eventq_index": 0,
234 "hterm": {
235 "name": "hterm",
236 "output": true,
237 "number": 0,
238 "intr_control": "system.intrctrl",
239 "eventq_index": 0,
240 "cxx_class": "Terminal",
241 "path": "system.t1000.hterm",
242 "type": "Terminal",
243 "port": 3456
244 },
245 "type": "T1000",
246 "fake_l2_4": {
247 "pio": {
248 "peer": "system.iobus.master[5]",
249 "role": "SLAVE"
250 },
251 "ret_data64": 1,
252 "fake_mem": false,
253 "clk_domain": "system.clk_domain",
254 "cxx_class": "IsaFake",
255 "pio_addr": 725849473216,
256 "update_data": true,
257 "warn_access": "",
258 "pio_latency": 200,
259 "system": "system",
260 "eventq_index": 0,
261 "default_p_state": "UNDEFINED",
262 "p_state_clk_gate_max": 2000000000,
263 "type": "IsaFake",
264 "p_state_clk_gate_min": 2,
231 "ret_data32": 4294967295,
232 "path": "system.t1000.fake_l2esr_2",
233 "ret_data16": 65535,
234 "ret_data8": 255,
235 "name": "fake_l2esr_2",
236 "ret_bad_addr": false,
237 "pio_size": 8,
238 "p_state_clk_gate_bins": 20
239 },
240 "system": "system",
241 "eventq_index": 0,
242 "hterm": {
243 "name": "hterm",
244 "output": true,
245 "number": 0,
246 "intr_control": "system.intrctrl",
247 "eventq_index": 0,
248 "cxx_class": "Terminal",
249 "path": "system.t1000.hterm",
250 "type": "Terminal",
251 "port": 3456
252 },
253 "type": "T1000",
254 "fake_l2_4": {
255 "pio": {
256 "peer": "system.iobus.master[5]",
257 "role": "SLAVE"
258 },
259 "ret_data64": 1,
260 "fake_mem": false,
261 "clk_domain": "system.clk_domain",
262 "cxx_class": "IsaFake",
263 "pio_addr": 725849473216,
264 "update_data": true,
265 "warn_access": "",
266 "pio_latency": 200,
267 "system": "system",
268 "eventq_index": 0,
269 "default_p_state": "UNDEFINED",
270 "p_state_clk_gate_max": 2000000000,
271 "type": "IsaFake",
272 "p_state_clk_gate_min": 2,
273 "power_model": null,
265 "ret_data32": 4294967295,
266 "path": "system.t1000.fake_l2_4",
267 "ret_data16": 65535,
268 "ret_data8": 255,
269 "name": "fake_l2_4",
270 "ret_bad_addr": false,
271 "pio_size": 8,
272 "p_state_clk_gate_bins": 20
273 },
274 "fake_l2_1": {
275 "pio": {
276 "peer": "system.iobus.master[2]",
277 "role": "SLAVE"
278 },
279 "ret_data64": 1,
280 "fake_mem": false,
281 "clk_domain": "system.clk_domain",
282 "cxx_class": "IsaFake",
283 "pio_addr": 725849473024,
284 "update_data": true,
285 "warn_access": "",
286 "pio_latency": 200,
287 "system": "system",
288 "eventq_index": 0,
289 "default_p_state": "UNDEFINED",
290 "p_state_clk_gate_max": 2000000000,
291 "type": "IsaFake",
292 "p_state_clk_gate_min": 2,
274 "ret_data32": 4294967295,
275 "path": "system.t1000.fake_l2_4",
276 "ret_data16": 65535,
277 "ret_data8": 255,
278 "name": "fake_l2_4",
279 "ret_bad_addr": false,
280 "pio_size": 8,
281 "p_state_clk_gate_bins": 20
282 },
283 "fake_l2_1": {
284 "pio": {
285 "peer": "system.iobus.master[2]",
286 "role": "SLAVE"
287 },
288 "ret_data64": 1,
289 "fake_mem": false,
290 "clk_domain": "system.clk_domain",
291 "cxx_class": "IsaFake",
292 "pio_addr": 725849473024,
293 "update_data": true,
294 "warn_access": "",
295 "pio_latency": 200,
296 "system": "system",
297 "eventq_index": 0,
298 "default_p_state": "UNDEFINED",
299 "p_state_clk_gate_max": 2000000000,
300 "type": "IsaFake",
301 "p_state_clk_gate_min": 2,
302 "power_model": null,
293 "ret_data32": 4294967295,
294 "path": "system.t1000.fake_l2_1",
295 "ret_data16": 65535,
296 "ret_data8": 255,
297 "name": "fake_l2_1",
298 "ret_bad_addr": false,
299 "pio_size": 8,
300 "p_state_clk_gate_bins": 20
301 },
302 "fake_l2_2": {
303 "pio": {
304 "peer": "system.iobus.master[3]",
305 "role": "SLAVE"
306 },
307 "ret_data64": 1,
308 "fake_mem": false,
309 "clk_domain": "system.clk_domain",
310 "cxx_class": "IsaFake",
311 "pio_addr": 725849473088,
312 "update_data": true,
313 "warn_access": "",
314 "pio_latency": 200,
315 "system": "system",
316 "eventq_index": 0,
317 "default_p_state": "UNDEFINED",
318 "p_state_clk_gate_max": 2000000000,
319 "type": "IsaFake",
320 "p_state_clk_gate_min": 2,
303 "ret_data32": 4294967295,
304 "path": "system.t1000.fake_l2_1",
305 "ret_data16": 65535,
306 "ret_data8": 255,
307 "name": "fake_l2_1",
308 "ret_bad_addr": false,
309 "pio_size": 8,
310 "p_state_clk_gate_bins": 20
311 },
312 "fake_l2_2": {
313 "pio": {
314 "peer": "system.iobus.master[3]",
315 "role": "SLAVE"
316 },
317 "ret_data64": 1,
318 "fake_mem": false,
319 "clk_domain": "system.clk_domain",
320 "cxx_class": "IsaFake",
321 "pio_addr": 725849473088,
322 "update_data": true,
323 "warn_access": "",
324 "pio_latency": 200,
325 "system": "system",
326 "eventq_index": 0,
327 "default_p_state": "UNDEFINED",
328 "p_state_clk_gate_max": 2000000000,
329 "type": "IsaFake",
330 "p_state_clk_gate_min": 2,
331 "power_model": null,
321 "ret_data32": 4294967295,
322 "path": "system.t1000.fake_l2_2",
323 "ret_data16": 65535,
324 "ret_data8": 255,
325 "name": "fake_l2_2",
326 "ret_bad_addr": false,
327 "pio_size": 8,
328 "p_state_clk_gate_bins": 20
329 },
330 "fake_l2_3": {
331 "pio": {
332 "peer": "system.iobus.master[4]",
333 "role": "SLAVE"
334 },
335 "ret_data64": 1,
336 "fake_mem": false,
337 "clk_domain": "system.clk_domain",
338 "cxx_class": "IsaFake",
339 "pio_addr": 725849473152,
340 "update_data": true,
341 "warn_access": "",
342 "pio_latency": 200,
343 "system": "system",
344 "eventq_index": 0,
345 "default_p_state": "UNDEFINED",
346 "p_state_clk_gate_max": 2000000000,
347 "type": "IsaFake",
348 "p_state_clk_gate_min": 2,
332 "ret_data32": 4294967295,
333 "path": "system.t1000.fake_l2_2",
334 "ret_data16": 65535,
335 "ret_data8": 255,
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551 },
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680 "system.t1000.htod.pio",
681 "system.bridge.slave",
682 "system.rom.port",
683 "system.nvram.port",
684 "system.hypervisor_desc.port",
685 "system.partition_desc.port",
686 "system.physmem0.port",
687 "system.physmem1.port"
688 ],
689 "role": "MASTER"
690 },
691 "type": "CoherentXBar",
692 "frontend_latency": 3,
693 "slave": {
694 "peer": [
695 "system.system_port",
696 "system.cpu.icache_port",
697 "system.cpu.dcache_port"
698 ],
699 "role": "SLAVE"
700 },
701 "p_state_clk_gate_min": 2,
702 "snoop_filter": null,
684 "ret_data32": 4294967295,
685 "path": "system.membus.badaddr_responder",
686 "ret_data16": 65535,
687 "ret_data8": 255,
688 "name": "badaddr_responder",
689 "ret_bad_addr": true,
690 "pio_size": 8,
691 "p_state_clk_gate_bins": 20
692 },
693 "forward_latency": 4,
694 "clk_domain": "system.clk_domain",
695 "width": 16,
696 "eventq_index": 0,
697 "default_p_state": "UNDEFINED",
698 "p_state_clk_gate_max": 2000000000,
699 "master": {
700 "peer": [
701 "system.t1000.iob.pio",
702 "system.t1000.htod.pio",
703 "system.bridge.slave",
704 "system.rom.port",
705 "system.nvram.port",
706 "system.hypervisor_desc.port",
707 "system.partition_desc.port",
708 "system.physmem0.port",
709 "system.physmem1.port"
710 ],
711 "role": "MASTER"
712 },
713 "type": "CoherentXBar",
714 "frontend_latency": 3,
715 "slave": {
716 "peer": [
717 "system.system_port",
718 "system.cpu.icache_port",
719 "system.cpu.dcache_port"
720 ],
721 "role": "SLAVE"
722 },
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724 "snoop_filter": null,
725 "power_model": null,
703 "path": "system.membus",
704 "snoop_response_latency": 4,
705 "name": "membus",
706 "default": {
707 "peer": "system.membus.badaddr_responder.pio",
708 "role": "MASTER"
709 },
710 "p_state_clk_gate_bins": 20,
711 "use_default_range": false
712 },
713 "nvram": {
714 "range": "133429198848:133429207039",
715 "latency": 60,
716 "name": "nvram",
717 "p_state_clk_gate_min": 2,
718 "eventq_index": 0,
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720 "default_p_state": "UNDEFINED",
721 "clk_domain": "system.clk_domain",
726 "path": "system.membus",
727 "snoop_response_latency": 4,
728 "name": "membus",
729 "default": {
730 "peer": "system.membus.badaddr_responder.pio",
731 "role": "MASTER"
732 },
733 "p_state_clk_gate_bins": 20,
734 "use_default_range": false
735 },
736 "nvram": {
737 "range": "133429198848:133429207039",
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739 "name": "nvram",
740 "p_state_clk_gate_min": 2,
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742 "p_state_clk_gate_bins": 20,
743 "default_p_state": "UNDEFINED",
744 "clk_domain": "system.clk_domain",
745 "power_model": null,
722 "latency_var": 0,
723 "bandwidth": "0.000000",
724 "conf_table_reported": true,
725 "cxx_class": "SimpleMemory",
726 "p_state_clk_gate_max": 2000000000,
727 "path": "system.nvram",
728 "null": false,
729 "type": "SimpleMemory",
730 "port": {
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732 "role": "SLAVE"
733 },
734 "in_addr_map": true
735 },
736 "eventq_index": 0,
737 "default_p_state": "UNDEFINED",
738 "p_state_clk_gate_max": 2000000000,
739 "dvfs_handler": {
740 "enable": false,
741 "name": "dvfs_handler",
742 "sys_clk_domain": "system.clk_domain",
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744 "eventq_index": 0,
745 "cxx_class": "DVFSHandler",
746 "domains": [],
747 "path": "system.dvfs_handler",
748 "type": "DVFSHandler"
749 },
750 "work_end_exit_count": 0,
751 "hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin",
752 "openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin",
753 "voltage_domain": {
754 "name": "voltage_domain",
755 "eventq_index": 0,
756 "voltage": [
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758 ],
759 "cxx_class": "VoltageDomain",
760 "path": "system.voltage_domain",
761 "type": "VoltageDomain"
762 },
763 "cache_line_size": 64,
764 "boot_osflags": "a",
765 "system_port": {
766 "peer": "system.membus.slave[0]",
767 "role": "MASTER"
768 },
769 "physmem": [
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771 "range": "1048576:68157439",
772 "latency": 60,
773 "name": "physmem0",
774 "p_state_clk_gate_min": 2,
775 "eventq_index": 0,
776 "p_state_clk_gate_bins": 20,
777 "default_p_state": "UNDEFINED",
778 "clk_domain": "system.clk_domain",
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747 "bandwidth": "0.000000",
748 "conf_table_reported": true,
749 "cxx_class": "SimpleMemory",
750 "p_state_clk_gate_max": 2000000000,
751 "path": "system.nvram",
752 "null": false,
753 "type": "SimpleMemory",
754 "port": {
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756 "role": "SLAVE"
757 },
758 "in_addr_map": true
759 },
760 "eventq_index": 0,
761 "default_p_state": "UNDEFINED",
762 "p_state_clk_gate_max": 2000000000,
763 "dvfs_handler": {
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765 "name": "dvfs_handler",
766 "sys_clk_domain": "system.clk_domain",
767 "transition_latency": 200000,
768 "eventq_index": 0,
769 "cxx_class": "DVFSHandler",
770 "domains": [],
771 "path": "system.dvfs_handler",
772 "type": "DVFSHandler"
773 },
774 "work_end_exit_count": 0,
775 "hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin",
776 "openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin",
777 "voltage_domain": {
778 "name": "voltage_domain",
779 "eventq_index": 0,
780 "voltage": [
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782 ],
783 "cxx_class": "VoltageDomain",
784 "path": "system.voltage_domain",
785 "type": "VoltageDomain"
786 },
787 "cache_line_size": 64,
788 "boot_osflags": "a",
789 "system_port": {
790 "peer": "system.membus.slave[0]",
791 "role": "MASTER"
792 },
793 "physmem": [
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796 "latency": 60,
797 "name": "physmem0",
798 "p_state_clk_gate_min": 2,
799 "eventq_index": 0,
800 "p_state_clk_gate_bins": 20,
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802 "clk_domain": "system.clk_domain",
803 "power_model": null,
779 "latency_var": 0,
780 "bandwidth": "0.000000",
781 "conf_table_reported": true,
782 "cxx_class": "SimpleMemory",
783 "p_state_clk_gate_max": 2000000000,
784 "path": "system.physmem0",
785 "null": false,
786 "type": "SimpleMemory",
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790 },
791 "in_addr_map": true
792 },
793 {
794 "range": "2147483648:2415919103",
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796 "name": "physmem1",
797 "p_state_clk_gate_min": 2,
798 "eventq_index": 0,
799 "p_state_clk_gate_bins": 20,
800 "default_p_state": "UNDEFINED",
801 "clk_domain": "system.clk_domain",
804 "latency_var": 0,
805 "bandwidth": "0.000000",
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807 "cxx_class": "SimpleMemory",
808 "p_state_clk_gate_max": 2000000000,
809 "path": "system.physmem0",
810 "null": false,
811 "type": "SimpleMemory",
812 "port": {
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814 "role": "SLAVE"
815 },
816 "in_addr_map": true
817 },
818 {
819 "range": "2147483648:2415919103",
820 "latency": 60,
821 "name": "physmem1",
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825 "default_p_state": "UNDEFINED",
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802 "latency_var": 0,
803 "bandwidth": "0.000000",
804 "conf_table_reported": true,
805 "cxx_class": "SimpleMemory",
806 "p_state_clk_gate_max": 2000000000,
807 "path": "system.physmem1",
808 "null": false,
809 "type": "SimpleMemory",
810 "port": {
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812 "role": "SLAVE"
813 },
814 "in_addr_map": true
815 }
816 ],
828 "latency_var": 0,
829 "bandwidth": "0.000000",
830 "conf_table_reported": true,
831 "cxx_class": "SimpleMemory",
832 "p_state_clk_gate_max": 2000000000,
833 "path": "system.physmem1",
834 "null": false,
835 "type": "SimpleMemory",
836 "port": {
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838 "role": "SLAVE"
839 },
840 "in_addr_map": true
841 }
842 ],
843 "power_model": null,
817 "work_cpus_ckpt_count": 0,
818 "thermal_components": [],
819 "path": "system",
820 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
821 "cpu_clk_domain": {
822 "name": "cpu_clk_domain",
823 "clock": [
824 2
825 ],
826 "init_perf_level": 0,
827 "voltage_domain": "system.voltage_domain",
828 "eventq_index": 0,
829 "cxx_class": "SrcClockDomain",
830 "path": "system.cpu_clk_domain",
831 "type": "SrcClockDomain",
832 "domain_id": -1
833 },
834 "nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1",
835 "mem_mode": "atomic",
836 "name": "system",
837 "init_param": 0,
838 "type": "SparcSystem",
839 "partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin",
840 "load_addr_mask": 1099511627775,
841 "cpu": {
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843 "numThreads": 1,
844 "itb": {
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846 "eventq_index": 0,
847 "cxx_class": "SparcISA::TLB",
848 "path": "system.cpu.itb",
849 "type": "SparcTLB",
850 "size": 64
851 },
852 "simulate_data_stalls": false,
853 "function_trace": false,
854 "do_checkpoint_insts": true,
855 "cxx_class": "AtomicSimpleCPU",
856 "max_loads_all_threads": 0,
857 "system": "system",
858 "clk_domain": "system.cpu_clk_domain",
859 "function_trace_start": 0,
860 "cpu_id": 0,
861 "width": 1,
862 "checker": null,
863 "eventq_index": 0,
864 "default_p_state": "UNDEFINED",
865 "p_state_clk_gate_max": 2000000000,
866 "do_quiesce": true,
867 "type": "AtomicSimpleCPU",
868 "fastmem": false,
869 "profile": 0,
870 "icache_port": {
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872 "role": "MASTER"
873 },
874 "p_state_clk_gate_bins": 20,
875 "p_state_clk_gate_min": 2,
876 "interrupts": [
877 {
878 "eventq_index": 0,
879 "path": "system.cpu.interrupts",
880 "type": "SparcInterrupts",
881 "name": "interrupts",
882 "cxx_class": "SparcISA::Interrupts"
883 }
884 ],
885 "dcache_port": {
886 "peer": "system.membus.slave[2]",
887 "role": "MASTER"
888 },
889 "socket_id": 0,
844 "work_cpus_ckpt_count": 0,
845 "thermal_components": [],
846 "path": "system",
847 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
848 "cpu_clk_domain": {
849 "name": "cpu_clk_domain",
850 "clock": [
851 2
852 ],
853 "init_perf_level": 0,
854 "voltage_domain": "system.voltage_domain",
855 "eventq_index": 0,
856 "cxx_class": "SrcClockDomain",
857 "path": "system.cpu_clk_domain",
858 "type": "SrcClockDomain",
859 "domain_id": -1
860 },
861 "nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1",
862 "mem_mode": "atomic",
863 "name": "system",
864 "init_param": 0,
865 "type": "SparcSystem",
866 "partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin",
867 "load_addr_mask": 1099511627775,
868 "cpu": {
869 "do_statistics_insts": true,
870 "numThreads": 1,
871 "itb": {
872 "name": "itb",
873 "eventq_index": 0,
874 "cxx_class": "SparcISA::TLB",
875 "path": "system.cpu.itb",
876 "type": "SparcTLB",
877 "size": 64
878 },
879 "simulate_data_stalls": false,
880 "function_trace": false,
881 "do_checkpoint_insts": true,
882 "cxx_class": "AtomicSimpleCPU",
883 "max_loads_all_threads": 0,
884 "system": "system",
885 "clk_domain": "system.cpu_clk_domain",
886 "function_trace_start": 0,
887 "cpu_id": 0,
888 "width": 1,
889 "checker": null,
890 "eventq_index": 0,
891 "default_p_state": "UNDEFINED",
892 "p_state_clk_gate_max": 2000000000,
893 "do_quiesce": true,
894 "type": "AtomicSimpleCPU",
895 "fastmem": false,
896 "profile": 0,
897 "icache_port": {
898 "peer": "system.membus.slave[1]",
899 "role": "MASTER"
900 },
901 "p_state_clk_gate_bins": 20,
902 "p_state_clk_gate_min": 2,
903 "interrupts": [
904 {
905 "eventq_index": 0,
906 "path": "system.cpu.interrupts",
907 "type": "SparcInterrupts",
908 "name": "interrupts",
909 "cxx_class": "SparcISA::Interrupts"
910 }
911 ],
912 "dcache_port": {
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914 "role": "MASTER"
915 },
916 "socket_id": 0,
917 "power_model": null,
890 "max_insts_all_threads": 0,
891 "path": "system.cpu",
892 "max_loads_any_thread": 0,
893 "switched_out": false,
894 "workload": [],
895 "name": "cpu",
896 "dtb": {
897 "name": "dtb",
898 "eventq_index": 0,
899 "cxx_class": "SparcISA::TLB",
900 "path": "system.cpu.dtb",
901 "type": "SparcTLB",
902 "size": 64
903 },
904 "simpoint_start_insts": [],
905 "max_insts_any_thread": 0,
906 "simulate_inst_stalls": false,
907 "progress_interval": 0,
908 "branchPred": null,
909 "isa": [
910 {
911 "eventq_index": 0,
912 "path": "system.cpu.isa",
913 "type": "SparcISA",
914 "name": "isa",
915 "cxx_class": "SparcISA::ISA"
916 }
917 ],
918 "tracer": {
919 "eventq_index": 0,
920 "path": "system.cpu.tracer",
921 "type": "ExeTracer",
922 "name": "tracer",
923 "cxx_class": "Trace::ExeTracer"
924 }
925 },
926 "intrctrl": {
927 "name": "intrctrl",
928 "sys": "system",
929 "eventq_index": 0,
930 "cxx_class": "IntrControl",
931 "path": "system.intrctrl",
932 "type": "IntrControl"
933 },
934 "disk0": {
935 "name": "disk0",
936 "p_state_clk_gate_min": 2,
937 "pio": {
938 "peer": "system.iobus.master[14]",
939 "role": "SLAVE"
940 },
941 "p_state_clk_gate_bins": 20,
942 "image": {
943 "read_only": false,
944 "name": "image",
945 "cxx_class": "CowDiskImage",
946 "eventq_index": 0,
947 "child": {
948 "read_only": true,
949 "name": "child",
950 "eventq_index": 0,
951 "cxx_class": "RawDiskImage",
952 "path": "system.disk0.image.child",
953 "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2",
954 "type": "RawDiskImage"
955 },
956 "path": "system.disk0.image",
957 "image_file": "",
958 "type": "CowDiskImage",
959 "table_size": 65536
960 },
961 "cxx_class": "MmDisk",
962 "pio_latency": 200,
963 "clk_domain": "system.clk_domain",
918 "max_insts_all_threads": 0,
919 "path": "system.cpu",
920 "max_loads_any_thread": 0,
921 "switched_out": false,
922 "workload": [],
923 "name": "cpu",
924 "dtb": {
925 "name": "dtb",
926 "eventq_index": 0,
927 "cxx_class": "SparcISA::TLB",
928 "path": "system.cpu.dtb",
929 "type": "SparcTLB",
930 "size": 64
931 },
932 "simpoint_start_insts": [],
933 "max_insts_any_thread": 0,
934 "simulate_inst_stalls": false,
935 "progress_interval": 0,
936 "branchPred": null,
937 "isa": [
938 {
939 "eventq_index": 0,
940 "path": "system.cpu.isa",
941 "type": "SparcISA",
942 "name": "isa",
943 "cxx_class": "SparcISA::ISA"
944 }
945 ],
946 "tracer": {
947 "eventq_index": 0,
948 "path": "system.cpu.tracer",
949 "type": "ExeTracer",
950 "name": "tracer",
951 "cxx_class": "Trace::ExeTracer"
952 }
953 },
954 "intrctrl": {
955 "name": "intrctrl",
956 "sys": "system",
957 "eventq_index": 0,
958 "cxx_class": "IntrControl",
959 "path": "system.intrctrl",
960 "type": "IntrControl"
961 },
962 "disk0": {
963 "name": "disk0",
964 "p_state_clk_gate_min": 2,
965 "pio": {
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967 "role": "SLAVE"
968 },
969 "p_state_clk_gate_bins": 20,
970 "image": {
971 "read_only": false,
972 "name": "image",
973 "cxx_class": "CowDiskImage",
974 "eventq_index": 0,
975 "child": {
976 "read_only": true,
977 "name": "child",
978 "eventq_index": 0,
979 "cxx_class": "RawDiskImage",
980 "path": "system.disk0.image.child",
981 "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2",
982 "type": "RawDiskImage"
983 },
984 "path": "system.disk0.image",
985 "image_file": "",
986 "type": "CowDiskImage",
987 "table_size": 65536
988 },
989 "cxx_class": "MmDisk",
990 "pio_latency": 200,
991 "clk_domain": "system.clk_domain",
992 "power_model": null,
964 "system": "system",
965 "eventq_index": 0,
966 "default_p_state": "UNDEFINED",
967 "p_state_clk_gate_max": 2000000000,
968 "path": "system.disk0",
969 "pio_addr": 134217728000,
970 "type": "MmDisk"
971 },
972 "multi_thread": false,
973 "reset_addr": 1099243192320,
974 "p_state_clk_gate_bins": 20,
975 "hypervisor_desc_addr": 133446500352,
976 "num_work_ids": 16,
977 "work_item_id": -1,
978 "exit_on_work_items": false
979 },
980 "time_sync_period": 200000000,
981 "eventq_index": 0,
982 "time_sync_spin_threshold": 200000,
983 "cxx_class": "Root",
984 "path": "root",
985 "time_sync_enable": false,
986 "type": "Root",
987 "full_system": true
988}
993 "system": "system",
994 "eventq_index": 0,
995 "default_p_state": "UNDEFINED",
996 "p_state_clk_gate_max": 2000000000,
997 "path": "system.disk0",
998 "pio_addr": 134217728000,
999 "type": "MmDisk"
1000 },
1001 "multi_thread": false,
1002 "reset_addr": 1099243192320,
1003 "p_state_clk_gate_bins": 20,
1004 "hypervisor_desc_addr": 133446500352,
1005 "num_work_ids": 16,
1006 "work_item_id": -1,
1007 "exit_on_work_items": false
1008 },
1009 "time_sync_period": 200000000,
1010 "eventq_index": 0,
1011 "time_sync_spin_threshold": 200000,
1012 "cxx_class": "Root",
1013 "path": "root",
1014 "time_sync_enable": false,
1015 "type": "Root",
1016 "full_system": true
1017}