config.json (11103:38f6188421e0) config.json (11298:e535b95573c0)
1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "eventq_index": 0,
13 "clk_domain": "system.clk_domain",
14 "latency_var": 0,
15 "bandwidth": "0.000000",
16 "conf_table_reported": true,
17 "cxx_class": "SimpleMemory",
18 "path": "system.rom",
19 "null": false,
20 "type": "SimpleMemory",
21 "port": {
22 "peer": "system.membus.master[3]",
23 "role": "SLAVE"
24 },
25 "in_addr_map": true
26 },
27 "bridge": {
28 "ranges": [
29 "133412421632:133412421639",
30 "134217728000:554050781183",
31 "644245094400:652835028991",
32 "725849473024:1095485095935",
33 "1099255955456:1099255955463"
34 ],
35 "slave": {
36 "peer": "system.membus.master[2]",
37 "role": "SLAVE"
38 },
39 "name": "bridge",
40 "req_size": 16,
41 "clk_domain": "system.clk_domain",
42 "delay": 100,
43 "eventq_index": 0,
44 "master": {
45 "peer": "system.iobus.slave[0]",
46 "role": "MASTER"
47 },
48 "cxx_class": "Bridge",
49 "path": "system.bridge",
50 "resp_size": 16,
51 "type": "Bridge"
52 },
53 "iobus": {
54 "slave": {
55 "peer": [
56 "system.bridge.master"
57 ],
58 "role": "SLAVE"
59 },
60 "name": "iobus",
61 "forward_latency": 1,
62 "clk_domain": "system.clk_domain",
63 "width": 16,
64 "eventq_index": 0,
65 "master": {
66 "peer": [
67 "system.t1000.fake_clk.pio",
68 "system.t1000.fake_membnks.pio",
69 "system.t1000.fake_l2_1.pio",
70 "system.t1000.fake_l2_2.pio",
71 "system.t1000.fake_l2_3.pio",
72 "system.t1000.fake_l2_4.pio",
73 "system.t1000.fake_l2esr_1.pio",
74 "system.t1000.fake_l2esr_2.pio",
75 "system.t1000.fake_l2esr_3.pio",
76 "system.t1000.fake_l2esr_4.pio",
77 "system.t1000.fake_ssi.pio",
78 "system.t1000.fake_jbi.pio",
79 "system.t1000.puart0.pio",
80 "system.t1000.hvuart.pio",
81 "system.disk0.pio"
82 ],
83 "role": "MASTER"
84 },
85 "response_latency": 2,
86 "cxx_class": "NoncoherentXBar",
87 "path": "system.iobus",
88 "type": "NoncoherentXBar",
89 "use_default_range": false,
90 "frontend_latency": 2
91 },
92 "t1000": {
93 "htod": {
94 "name": "htod",
95 "pio": {
96 "peer": "system.membus.master[1]",
97 "role": "SLAVE"
98 },
99 "time": "Thu Jan 1 00:00:00 2009",
100 "pio_latency": 200,
101 "clk_domain": "system.clk_domain",
102 "system": "system",
103 "eventq_index": 0,
104 "cxx_class": "DumbTOD",
105 "path": "system.t1000.htod",
106 "pio_addr": 1099255906296,
107 "type": "DumbTOD"
108 },
109 "puart0": {
110 "name": "puart0",
111 "pio": {
112 "peer": "system.iobus.master[12]",
113 "role": "SLAVE"
114 },
115 "pio_latency": 200,
116 "clk_domain": "system.clk_domain",
117 "system": "system",
118 "terminal": "system.t1000.pterm",
119 "platform": "system.t1000",
120 "eventq_index": 0,
121 "cxx_class": "Uart8250",
122 "path": "system.t1000.puart0",
123 "pio_addr": 133412421632,
124 "type": "Uart8250"
125 },
126 "fake_membnks": {
127 "system": "system",
128 "ret_data8": 255,
129 "name": "fake_membnks",
130 "warn_access": "",
131 "pio": {
132 "peer": "system.iobus.master[1]",
133 "role": "SLAVE"
134 },
135 "ret_bad_addr": false,
136 "pio_latency": 200,
137 "clk_domain": "system.clk_domain",
138 "fake_mem": false,
139 "pio_size": 16384,
140 "ret_data32": 4294967295,
141 "eventq_index": 0,
142 "update_data": false,
143 "ret_data64": 0,
144 "cxx_class": "IsaFake",
145 "path": "system.t1000.fake_membnks",
146 "pio_addr": 648540061696,
147 "type": "IsaFake",
148 "ret_data16": 65535
149 },
150 "cxx_class": "T1000",
151 "fake_jbi": {
152 "system": "system",
153 "ret_data8": 255,
154 "name": "fake_jbi",
155 "warn_access": "",
156 "pio": {
157 "peer": "system.iobus.master[11]",
158 "role": "SLAVE"
159 },
160 "ret_bad_addr": false,
161 "pio_latency": 200,
162 "clk_domain": "system.clk_domain",
163 "fake_mem": false,
164 "pio_size": 4294967296,
165 "ret_data32": 4294967295,
166 "eventq_index": 0,
167 "update_data": false,
168 "ret_data64": 18446744073709551615,
169 "cxx_class": "IsaFake",
170 "path": "system.t1000.fake_jbi",
171 "pio_addr": 549755813888,
172 "type": "IsaFake",
173 "ret_data16": 65535
174 },
175 "intrctrl": "system.intrctrl",
176 "fake_l2esr_2": {
177 "system": "system",
178 "ret_data8": 255,
179 "name": "fake_l2esr_2",
180 "warn_access": "",
181 "pio": {
182 "peer": "system.iobus.master[7]",
183 "role": "SLAVE"
184 },
185 "ret_bad_addr": false,
186 "pio_latency": 200,
187 "clk_domain": "system.clk_domain",
188 "fake_mem": false,
189 "pio_size": 8,
190 "ret_data32": 4294967295,
191 "eventq_index": 0,
192 "update_data": true,
193 "ret_data64": 0,
194 "cxx_class": "IsaFake",
195 "path": "system.t1000.fake_l2esr_2",
196 "pio_addr": 734439407680,
197 "type": "IsaFake",
198 "ret_data16": 65535
199 },
200 "system": "system",
201 "eventq_index": 0,
202 "hterm": {
203 "name": "hterm",
204 "output": true,
205 "number": 0,
206 "intr_control": "system.intrctrl",
207 "eventq_index": 0,
208 "cxx_class": "Terminal",
209 "path": "system.t1000.hterm",
210 "type": "Terminal",
211 "port": 3456
212 },
213 "type": "T1000",
214 "fake_l2_4": {
215 "system": "system",
216 "ret_data8": 255,
217 "name": "fake_l2_4",
218 "warn_access": "",
219 "pio": {
220 "peer": "system.iobus.master[5]",
221 "role": "SLAVE"
222 },
223 "ret_bad_addr": false,
224 "pio_latency": 200,
225 "clk_domain": "system.clk_domain",
226 "fake_mem": false,
227 "pio_size": 8,
228 "ret_data32": 4294967295,
229 "eventq_index": 0,
230 "update_data": true,
231 "ret_data64": 1,
232 "cxx_class": "IsaFake",
233 "path": "system.t1000.fake_l2_4",
234 "pio_addr": 725849473216,
235 "type": "IsaFake",
236 "ret_data16": 65535
237 },
238 "fake_l2_1": {
239 "system": "system",
240 "ret_data8": 255,
241 "name": "fake_l2_1",
242 "warn_access": "",
243 "pio": {
244 "peer": "system.iobus.master[2]",
245 "role": "SLAVE"
246 },
247 "ret_bad_addr": false,
248 "pio_latency": 200,
249 "clk_domain": "system.clk_domain",
250 "fake_mem": false,
251 "pio_size": 8,
252 "ret_data32": 4294967295,
253 "eventq_index": 0,
254 "update_data": true,
255 "ret_data64": 1,
256 "cxx_class": "IsaFake",
257 "path": "system.t1000.fake_l2_1",
258 "pio_addr": 725849473024,
259 "type": "IsaFake",
260 "ret_data16": 65535
261 },
262 "fake_l2_2": {
263 "system": "system",
264 "ret_data8": 255,
265 "name": "fake_l2_2",
266 "warn_access": "",
267 "pio": {
268 "peer": "system.iobus.master[3]",
269 "role": "SLAVE"
270 },
271 "ret_bad_addr": false,
272 "pio_latency": 200,
273 "clk_domain": "system.clk_domain",
274 "fake_mem": false,
275 "pio_size": 8,
276 "ret_data32": 4294967295,
277 "eventq_index": 0,
278 "update_data": true,
279 "ret_data64": 1,
280 "cxx_class": "IsaFake",
281 "path": "system.t1000.fake_l2_2",
282 "pio_addr": 725849473088,
283 "type": "IsaFake",
284 "ret_data16": 65535
285 },
286 "fake_l2_3": {
287 "system": "system",
288 "ret_data8": 255,
289 "name": "fake_l2_3",
290 "warn_access": "",
291 "pio": {
292 "peer": "system.iobus.master[4]",
293 "role": "SLAVE"
294 },
295 "ret_bad_addr": false,
296 "pio_latency": 200,
297 "clk_domain": "system.clk_domain",
298 "fake_mem": false,
299 "pio_size": 8,
300 "ret_data32": 4294967295,
301 "eventq_index": 0,
302 "update_data": true,
303 "ret_data64": 1,
304 "cxx_class": "IsaFake",
305 "path": "system.t1000.fake_l2_3",
306 "pio_addr": 725849473152,
307 "type": "IsaFake",
308 "ret_data16": 65535
309 },
310 "pterm": {
311 "name": "pterm",
312 "output": true,
313 "number": 0,
314 "intr_control": "system.intrctrl",
315 "eventq_index": 0,
316 "cxx_class": "Terminal",
317 "path": "system.t1000.pterm",
318 "type": "Terminal",
319 "port": 3456
320 },
321 "path": "system.t1000",
322 "iob": {
323 "name": "iob",
324 "pio": {
325 "peer": "system.membus.master[0]",
326 "role": "SLAVE"
327 },
328 "pio_latency": 2,
329 "clk_domain": "system.clk_domain",
330 "system": "system",
331 "platform": "system.t1000",
332 "eventq_index": 0,
333 "cxx_class": "Iob",
334 "path": "system.t1000.iob",
335 "type": "Iob"
336 },
337 "hvuart": {
338 "name": "hvuart",
339 "pio": {
340 "peer": "system.iobus.master[13]",
341 "role": "SLAVE"
342 },
343 "pio_latency": 200,
344 "clk_domain": "system.clk_domain",
345 "system": "system",
346 "terminal": "system.t1000.hterm",
347 "platform": "system.t1000",
348 "eventq_index": 0,
349 "cxx_class": "Uart8250",
350 "path": "system.t1000.hvuart",
351 "pio_addr": 1099255955456,
352 "type": "Uart8250"
353 },
354 "name": "t1000",
355 "fake_l2esr_3": {
356 "system": "system",
357 "ret_data8": 255,
358 "name": "fake_l2esr_3",
359 "warn_access": "",
360 "pio": {
361 "peer": "system.iobus.master[8]",
362 "role": "SLAVE"
363 },
364 "ret_bad_addr": false,
365 "pio_latency": 200,
366 "clk_domain": "system.clk_domain",
367 "fake_mem": false,
368 "pio_size": 8,
369 "ret_data32": 4294967295,
370 "eventq_index": 0,
371 "update_data": true,
372 "ret_data64": 0,
373 "cxx_class": "IsaFake",
374 "path": "system.t1000.fake_l2esr_3",
375 "pio_addr": 734439407744,
376 "type": "IsaFake",
377 "ret_data16": 65535
378 },
379 "fake_ssi": {
380 "system": "system",
381 "ret_data8": 255,
382 "name": "fake_ssi",
383 "warn_access": "",
384 "pio": {
385 "peer": "system.iobus.master[10]",
386 "role": "SLAVE"
387 },
388 "ret_bad_addr": false,
389 "pio_latency": 200,
390 "clk_domain": "system.clk_domain",
391 "fake_mem": false,
392 "pio_size": 268435456,
393 "ret_data32": 4294967295,
394 "eventq_index": 0,
395 "update_data": false,
396 "ret_data64": 18446744073709551615,
397 "cxx_class": "IsaFake",
398 "path": "system.t1000.fake_ssi",
399 "pio_addr": 1095216660480,
400 "type": "IsaFake",
401 "ret_data16": 65535
402 },
403 "fake_l2esr_1": {
404 "system": "system",
405 "ret_data8": 255,
406 "name": "fake_l2esr_1",
407 "warn_access": "",
408 "pio": {
409 "peer": "system.iobus.master[6]",
410 "role": "SLAVE"
411 },
412 "ret_bad_addr": false,
413 "pio_latency": 200,
414 "clk_domain": "system.clk_domain",
415 "fake_mem": false,
416 "pio_size": 8,
417 "ret_data32": 4294967295,
418 "eventq_index": 0,
419 "update_data": true,
420 "ret_data64": 0,
421 "cxx_class": "IsaFake",
422 "path": "system.t1000.fake_l2esr_1",
423 "pio_addr": 734439407616,
424 "type": "IsaFake",
425 "ret_data16": 65535
426 },
427 "fake_l2esr_4": {
428 "system": "system",
429 "ret_data8": 255,
430 "name": "fake_l2esr_4",
431 "warn_access": "",
432 "pio": {
433 "peer": "system.iobus.master[9]",
434 "role": "SLAVE"
435 },
436 "ret_bad_addr": false,
437 "pio_latency": 200,
438 "clk_domain": "system.clk_domain",
439 "fake_mem": false,
440 "pio_size": 8,
441 "ret_data32": 4294967295,
442 "eventq_index": 0,
443 "update_data": true,
444 "ret_data64": 0,
445 "cxx_class": "IsaFake",
446 "path": "system.t1000.fake_l2esr_4",
447 "pio_addr": 734439407808,
448 "type": "IsaFake",
449 "ret_data16": 65535
450 },
451 "fake_clk": {
452 "system": "system",
453 "ret_data8": 255,
454 "name": "fake_clk",
455 "warn_access": "",
456 "pio": {
457 "peer": "system.iobus.master[0]",
458 "role": "SLAVE"
459 },
460 "ret_bad_addr": false,
461 "pio_latency": 200,
462 "clk_domain": "system.clk_domain",
463 "fake_mem": false,
464 "pio_size": 4294967296,
465 "ret_data32": 4294967295,
466 "eventq_index": 0,
467 "update_data": false,
468 "ret_data64": 18446744073709551615,
469 "cxx_class": "IsaFake",
470 "path": "system.t1000.fake_clk",
471 "pio_addr": 644245094400,
472 "type": "IsaFake",
473 "ret_data16": 65535
474 }
475 },
1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "eventq_index": 0,
13 "clk_domain": "system.clk_domain",
14 "latency_var": 0,
15 "bandwidth": "0.000000",
16 "conf_table_reported": true,
17 "cxx_class": "SimpleMemory",
18 "path": "system.rom",
19 "null": false,
20 "type": "SimpleMemory",
21 "port": {
22 "peer": "system.membus.master[3]",
23 "role": "SLAVE"
24 },
25 "in_addr_map": true
26 },
27 "bridge": {
28 "ranges": [
29 "133412421632:133412421639",
30 "134217728000:554050781183",
31 "644245094400:652835028991",
32 "725849473024:1095485095935",
33 "1099255955456:1099255955463"
34 ],
35 "slave": {
36 "peer": "system.membus.master[2]",
37 "role": "SLAVE"
38 },
39 "name": "bridge",
40 "req_size": 16,
41 "clk_domain": "system.clk_domain",
42 "delay": 100,
43 "eventq_index": 0,
44 "master": {
45 "peer": "system.iobus.slave[0]",
46 "role": "MASTER"
47 },
48 "cxx_class": "Bridge",
49 "path": "system.bridge",
50 "resp_size": 16,
51 "type": "Bridge"
52 },
53 "iobus": {
54 "slave": {
55 "peer": [
56 "system.bridge.master"
57 ],
58 "role": "SLAVE"
59 },
60 "name": "iobus",
61 "forward_latency": 1,
62 "clk_domain": "system.clk_domain",
63 "width": 16,
64 "eventq_index": 0,
65 "master": {
66 "peer": [
67 "system.t1000.fake_clk.pio",
68 "system.t1000.fake_membnks.pio",
69 "system.t1000.fake_l2_1.pio",
70 "system.t1000.fake_l2_2.pio",
71 "system.t1000.fake_l2_3.pio",
72 "system.t1000.fake_l2_4.pio",
73 "system.t1000.fake_l2esr_1.pio",
74 "system.t1000.fake_l2esr_2.pio",
75 "system.t1000.fake_l2esr_3.pio",
76 "system.t1000.fake_l2esr_4.pio",
77 "system.t1000.fake_ssi.pio",
78 "system.t1000.fake_jbi.pio",
79 "system.t1000.puart0.pio",
80 "system.t1000.hvuart.pio",
81 "system.disk0.pio"
82 ],
83 "role": "MASTER"
84 },
85 "response_latency": 2,
86 "cxx_class": "NoncoherentXBar",
87 "path": "system.iobus",
88 "type": "NoncoherentXBar",
89 "use_default_range": false,
90 "frontend_latency": 2
91 },
92 "t1000": {
93 "htod": {
94 "name": "htod",
95 "pio": {
96 "peer": "system.membus.master[1]",
97 "role": "SLAVE"
98 },
99 "time": "Thu Jan 1 00:00:00 2009",
100 "pio_latency": 200,
101 "clk_domain": "system.clk_domain",
102 "system": "system",
103 "eventq_index": 0,
104 "cxx_class": "DumbTOD",
105 "path": "system.t1000.htod",
106 "pio_addr": 1099255906296,
107 "type": "DumbTOD"
108 },
109 "puart0": {
110 "name": "puart0",
111 "pio": {
112 "peer": "system.iobus.master[12]",
113 "role": "SLAVE"
114 },
115 "pio_latency": 200,
116 "clk_domain": "system.clk_domain",
117 "system": "system",
118 "terminal": "system.t1000.pterm",
119 "platform": "system.t1000",
120 "eventq_index": 0,
121 "cxx_class": "Uart8250",
122 "path": "system.t1000.puart0",
123 "pio_addr": 133412421632,
124 "type": "Uart8250"
125 },
126 "fake_membnks": {
127 "system": "system",
128 "ret_data8": 255,
129 "name": "fake_membnks",
130 "warn_access": "",
131 "pio": {
132 "peer": "system.iobus.master[1]",
133 "role": "SLAVE"
134 },
135 "ret_bad_addr": false,
136 "pio_latency": 200,
137 "clk_domain": "system.clk_domain",
138 "fake_mem": false,
139 "pio_size": 16384,
140 "ret_data32": 4294967295,
141 "eventq_index": 0,
142 "update_data": false,
143 "ret_data64": 0,
144 "cxx_class": "IsaFake",
145 "path": "system.t1000.fake_membnks",
146 "pio_addr": 648540061696,
147 "type": "IsaFake",
148 "ret_data16": 65535
149 },
150 "cxx_class": "T1000",
151 "fake_jbi": {
152 "system": "system",
153 "ret_data8": 255,
154 "name": "fake_jbi",
155 "warn_access": "",
156 "pio": {
157 "peer": "system.iobus.master[11]",
158 "role": "SLAVE"
159 },
160 "ret_bad_addr": false,
161 "pio_latency": 200,
162 "clk_domain": "system.clk_domain",
163 "fake_mem": false,
164 "pio_size": 4294967296,
165 "ret_data32": 4294967295,
166 "eventq_index": 0,
167 "update_data": false,
168 "ret_data64": 18446744073709551615,
169 "cxx_class": "IsaFake",
170 "path": "system.t1000.fake_jbi",
171 "pio_addr": 549755813888,
172 "type": "IsaFake",
173 "ret_data16": 65535
174 },
175 "intrctrl": "system.intrctrl",
176 "fake_l2esr_2": {
177 "system": "system",
178 "ret_data8": 255,
179 "name": "fake_l2esr_2",
180 "warn_access": "",
181 "pio": {
182 "peer": "system.iobus.master[7]",
183 "role": "SLAVE"
184 },
185 "ret_bad_addr": false,
186 "pio_latency": 200,
187 "clk_domain": "system.clk_domain",
188 "fake_mem": false,
189 "pio_size": 8,
190 "ret_data32": 4294967295,
191 "eventq_index": 0,
192 "update_data": true,
193 "ret_data64": 0,
194 "cxx_class": "IsaFake",
195 "path": "system.t1000.fake_l2esr_2",
196 "pio_addr": 734439407680,
197 "type": "IsaFake",
198 "ret_data16": 65535
199 },
200 "system": "system",
201 "eventq_index": 0,
202 "hterm": {
203 "name": "hterm",
204 "output": true,
205 "number": 0,
206 "intr_control": "system.intrctrl",
207 "eventq_index": 0,
208 "cxx_class": "Terminal",
209 "path": "system.t1000.hterm",
210 "type": "Terminal",
211 "port": 3456
212 },
213 "type": "T1000",
214 "fake_l2_4": {
215 "system": "system",
216 "ret_data8": 255,
217 "name": "fake_l2_4",
218 "warn_access": "",
219 "pio": {
220 "peer": "system.iobus.master[5]",
221 "role": "SLAVE"
222 },
223 "ret_bad_addr": false,
224 "pio_latency": 200,
225 "clk_domain": "system.clk_domain",
226 "fake_mem": false,
227 "pio_size": 8,
228 "ret_data32": 4294967295,
229 "eventq_index": 0,
230 "update_data": true,
231 "ret_data64": 1,
232 "cxx_class": "IsaFake",
233 "path": "system.t1000.fake_l2_4",
234 "pio_addr": 725849473216,
235 "type": "IsaFake",
236 "ret_data16": 65535
237 },
238 "fake_l2_1": {
239 "system": "system",
240 "ret_data8": 255,
241 "name": "fake_l2_1",
242 "warn_access": "",
243 "pio": {
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740 },
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760 },
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761 },
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770 ],
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807 }
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825 },
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833 "name": "child",
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835 "type": "RawDiskImage"
836 },
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840 "table_size": 65536
841 },
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843 "clk_domain": "system.clk_domain",
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846 "cxx_class": "MmDisk",
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850 },
838 "type": "RawDiskImage"
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840 "path": "system.disk0.image",
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852 "type": "MmDisk"
853 },
854 "multi_thread": false,
851 "reset_addr": 1099243192320,
852 "hypervisor_desc_addr": 133446500352,
855 "reset_addr": 1099243192320,
856 "hypervisor_desc_addr": 133446500352,
853 "partition_desc_addr": 133445976064,
857 "num_work_ids": 16,
854 "work_item_id": -1,
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855 "num_work_ids": 16
859 "exit_on_work_items": false
856 },
857 "time_sync_period": 200000000,
858 "eventq_index": 0,
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860 "cxx_class": "Root",
861 "path": "root",
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863 "type": "Root",
864 "full_system": true
865}
860 },
861 "time_sync_period": 200000000,
862 "eventq_index": 0,
863 "time_sync_spin_threshold": 200000,
864 "cxx_class": "Root",
865 "path": "root",
866 "time_sync_enable": false,
867 "type": "Root",
868 "full_system": true
869}