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"fake_ssi": { 380 "system": "system", 381 "ret_data8": 255, 382 "name": "fake_ssi", 383 "warn_access": "", 384 "pio": { 385 "peer": "system.iobus.master[10]", 386 "role": "SLAVE" 387 }, 388 "ret_bad_addr": false, 389 "pio_latency": 200, 390 "clk_domain": "system.clk_domain", 391 "fake_mem": false, 392 "pio_size": 268435456, 393 "ret_data32": 4294967295, 394 "eventq_index": 0, 395 "update_data": false, 396 "ret_data64": 18446744073709551615, 397 "cxx_class": "IsaFake", 398 "path": "system.t1000.fake_ssi", 399 "pio_addr": 1095216660480, 400 "type": "IsaFake", 401 "ret_data16": 65535 402 }, 403 "fake_l2esr_1": { 404 "system": "system", 405 "ret_data8": 255, 406 "name": "fake_l2esr_1", 407 "warn_access": "", 408 "pio": { 409 "peer": "system.iobus.master[6]", 410 "role": "SLAVE" 411 }, 412 "ret_bad_addr": false, 413 "pio_latency": 200, 414 "clk_domain": "system.clk_domain", 415 "fake_mem": false, 416 "pio_size": 8, 417 "ret_data32": 4294967295, 418 "eventq_index": 0, 419 "update_data": true, 420 "ret_data64": 0, 421 "cxx_class": "IsaFake", 422 "path": "system.t1000.fake_l2esr_1", 423 "pio_addr": 734439407616, 424 "type": "IsaFake", 425 "ret_data16": 65535 426 }, 427 "fake_l2esr_4": { 428 "system": "system", 429 "ret_data8": 255, 430 "name": "fake_l2esr_4", 431 "warn_access": "", 432 "pio": { 433 "peer": "system.iobus.master[9]", 434 "role": "SLAVE" 435 }, 436 "ret_bad_addr": false, 437 "pio_latency": 200, 438 "clk_domain": "system.clk_domain", 439 "fake_mem": false, 440 "pio_size": 8, 441 "ret_data32": 4294967295, 442 "eventq_index": 0, 443 "update_data": true, 444 "ret_data64": 0, 445 "cxx_class": "IsaFake", 446 "path": "system.t1000.fake_l2esr_4", 447 "pio_addr": 734439407808, 448 "type": "IsaFake", 449 "ret_data16": 65535 450 }, 451 "fake_clk": { 452 "system": "system", 453 "ret_data8": 255, 454 "name": "fake_clk", 455 "warn_access": "", 456 "pio": { 457 "peer": "system.iobus.master[0]", 458 "role": "SLAVE" 459 }, 460 "ret_bad_addr": false, 461 "pio_latency": 200, 462 "clk_domain": "system.clk_domain", 463 "fake_mem": false, 464 "pio_size": 4294967296, 465 "ret_data32": 4294967295, 466 "eventq_index": 0, 467 "update_data": false, 468 "ret_data64": 18446744073709551615, 469 "cxx_class": "IsaFake", 470 "path": "system.t1000.fake_clk", 471 "pio_addr": 644245094400, 472 "type": "IsaFake", 473 "ret_data16": 65535 474 } 475 },
|
486 "openboot_addr": 1099243716608, 487 "work_end_ckpt_count": 0, 488 "nvram_addr": 133429198848, 489 "memories": [ 490 "system.hypervisor_desc", 491 "system.nvram", 492 "system.partition_desc", 493 "system.physmem0", 494 "system.physmem1", 495 "system.rom" 496 ], 497 "work_begin_ckpt_count": 0, 498 "partition_desc": { 499 "range": "133445976064:133445984255", 500 "latency": 60, 501 "name": "partition_desc", 502 "eventq_index": 0, 503 "clk_domain": "system.clk_domain", 504 "latency_var": 0, 505 "bandwidth": "0.000000", 506 "conf_table_reported": true, 507 "cxx_class": "SimpleMemory", 508 "path": "system.partition_desc", 509 "null": false, 510 "type": "SimpleMemory", 511 "port": { 512 "peer": "system.membus.master[6]", 513 "role": "SLAVE" 514 }, 515 "in_addr_map": true 516 }, 517 "clk_domain": { 518 "name": "clk_domain", 519 "clock": [ 520 2 521 ], 522 "init_perf_level": 0, 523 "voltage_domain": "system.voltage_domain", 524 "eventq_index": 0, 525 "cxx_class": "SrcClockDomain", 526 "path": "system.clk_domain", 527 "type": "SrcClockDomain", 528 "domain_id": -1 529 }, 530 "hypervisor_desc": { 531 "range": "133446500352:133446508543", 532 "latency": 60, 533 "name": "hypervisor_desc", 534 "eventq_index": 0, 535 "clk_domain": "system.clk_domain", 536 "latency_var": 0, 537 "bandwidth": "0.000000", 538 "conf_table_reported": true, 539 "cxx_class": "SimpleMemory", 540 "path": "system.hypervisor_desc", 541 "null": false, 542 "type": "SimpleMemory", 543 "port": { 544 "peer": "system.membus.master[5]", 545 "role": "SLAVE" 546 }, 547 "in_addr_map": true 548 }, 549 "membus": { 550 "default": { 551 "peer": "system.membus.badaddr_responder.pio", 552 "role": "MASTER" 553 }, 554 "slave": { 555 "peer": [ 556 "system.system_port", 557 "system.cpu.icache_port", 558 "system.cpu.dcache_port" 559 ], 560 "role": "SLAVE" 561 }, 562 "name": "membus", 563 "badaddr_responder": { 564 "system": "system", 565 "ret_data8": 255, 566 "name": "badaddr_responder", 567 "warn_access": "", 568 "pio": { 569 "peer": "system.membus.default", 570 "role": "SLAVE" 571 }, 572 "ret_bad_addr": true, 573 "pio_latency": 200, 574 "clk_domain": "system.clk_domain", 575 "fake_mem": false, 576 "pio_size": 8, 577 "ret_data32": 4294967295, 578 "eventq_index": 0, 579 "update_data": false, 580 "ret_data64": 18446744073709551615, 581 "cxx_class": "IsaFake", 582 "path": "system.membus.badaddr_responder", 583 "pio_addr": 0, 584 "type": "IsaFake", 585 "ret_data16": 65535 586 }, 587 "snoop_filter": null, 588 "forward_latency": 4, 589 "clk_domain": "system.clk_domain", 590 "system": "system", 591 "width": 16, 592 "eventq_index": 0, 593 "master": { 594 "peer": [ 595 "system.t1000.iob.pio", 596 "system.t1000.htod.pio", 597 "system.bridge.slave", 598 "system.rom.port", 599 "system.nvram.port", 600 "system.hypervisor_desc.port", 601 "system.partition_desc.port", 602 "system.physmem0.port", 603 "system.physmem1.port" 604 ], 605 "role": "MASTER" 606 }, 607 "response_latency": 2, 608 "cxx_class": "CoherentXBar", 609 "path": "system.membus", 610 "snoop_response_latency": 4, 611 "type": "CoherentXBar", 612 "use_default_range": false, 613 "frontend_latency": 3 614 }, 615 "nvram": { 616 "range": "133429198848:133429207039", 617 "latency": 60, 618 "name": "nvram", 619 "eventq_index": 0, 620 "clk_domain": "system.clk_domain", 621 "latency_var": 0, 622 "bandwidth": "0.000000", 623 "conf_table_reported": true, 624 "cxx_class": "SimpleMemory", 625 "path": "system.nvram", 626 "null": false, 627 "type": "SimpleMemory", 628 "port": { 629 "peer": "system.membus.master[4]", 630 "role": "SLAVE" 631 }, 632 "in_addr_map": true 633 }, 634 "eventq_index": 0, 635 "work_begin_cpu_id_exit": -1, 636 "dvfs_handler": { 637 "enable": false, 638 "name": "dvfs_handler", 639 "sys_clk_domain": "system.clk_domain", 640 "transition_latency": 200000, 641 "eventq_index": 0, 642 "cxx_class": "DVFSHandler", 643 "domains": [], 644 "path": "system.dvfs_handler", 645 "type": "DVFSHandler" 646 }, 647 "work_end_exit_count": 0,
| 487 "openboot_addr": 1099243716608, 488 "work_end_ckpt_count": 0, 489 "nvram_addr": 133429198848, 490 "memories": [ 491 "system.hypervisor_desc", 492 "system.nvram", 493 "system.partition_desc", 494 "system.physmem0", 495 "system.physmem1", 496 "system.rom" 497 ], 498 "work_begin_ckpt_count": 0, 499 "partition_desc": { 500 "range": "133445976064:133445984255", 501 "latency": 60, 502 "name": "partition_desc", 503 "eventq_index": 0, 504 "clk_domain": "system.clk_domain", 505 "latency_var": 0, 506 "bandwidth": "0.000000", 507 "conf_table_reported": true, 508 "cxx_class": "SimpleMemory", 509 "path": "system.partition_desc", 510 "null": false, 511 "type": "SimpleMemory", 512 "port": { 513 "peer": "system.membus.master[6]", 514 "role": "SLAVE" 515 }, 516 "in_addr_map": true 517 }, 518 "clk_domain": { 519 "name": "clk_domain", 520 "clock": [ 521 2 522 ], 523 "init_perf_level": 0, 524 "voltage_domain": "system.voltage_domain", 525 "eventq_index": 0, 526 "cxx_class": "SrcClockDomain", 527 "path": "system.clk_domain", 528 "type": "SrcClockDomain", 529 "domain_id": -1 530 }, 531 "hypervisor_desc": { 532 "range": "133446500352:133446508543", 533 "latency": 60, 534 "name": "hypervisor_desc", 535 "eventq_index": 0, 536 "clk_domain": "system.clk_domain", 537 "latency_var": 0, 538 "bandwidth": "0.000000", 539 "conf_table_reported": true, 540 "cxx_class": "SimpleMemory", 541 "path": "system.hypervisor_desc", 542 "null": false, 543 "type": "SimpleMemory", 544 "port": { 545 "peer": "system.membus.master[5]", 546 "role": "SLAVE" 547 }, 548 "in_addr_map": true 549 }, 550 "membus": { 551 "default": { 552 "peer": "system.membus.badaddr_responder.pio", 553 "role": "MASTER" 554 }, 555 "slave": { 556 "peer": [ 557 "system.system_port", 558 "system.cpu.icache_port", 559 "system.cpu.dcache_port" 560 ], 561 "role": "SLAVE" 562 }, 563 "name": "membus", 564 "badaddr_responder": { 565 "system": "system", 566 "ret_data8": 255, 567 "name": "badaddr_responder", 568 "warn_access": "", 569 "pio": { 570 "peer": "system.membus.default", 571 "role": "SLAVE" 572 }, 573 "ret_bad_addr": true, 574 "pio_latency": 200, 575 "clk_domain": "system.clk_domain", 576 "fake_mem": false, 577 "pio_size": 8, 578 "ret_data32": 4294967295, 579 "eventq_index": 0, 580 "update_data": false, 581 "ret_data64": 18446744073709551615, 582 "cxx_class": "IsaFake", 583 "path": "system.membus.badaddr_responder", 584 "pio_addr": 0, 585 "type": "IsaFake", 586 "ret_data16": 65535 587 }, 588 "snoop_filter": null, 589 "forward_latency": 4, 590 "clk_domain": "system.clk_domain", 591 "system": "system", 592 "width": 16, 593 "eventq_index": 0, 594 "master": { 595 "peer": [ 596 "system.t1000.iob.pio", 597 "system.t1000.htod.pio", 598 "system.bridge.slave", 599 "system.rom.port", 600 "system.nvram.port", 601 "system.hypervisor_desc.port", 602 "system.partition_desc.port", 603 "system.physmem0.port", 604 "system.physmem1.port" 605 ], 606 "role": "MASTER" 607 }, 608 "response_latency": 2, 609 "cxx_class": "CoherentXBar", 610 "path": "system.membus", 611 "snoop_response_latency": 4, 612 "type": "CoherentXBar", 613 "use_default_range": false, 614 "frontend_latency": 3 615 }, 616 "nvram": { 617 "range": "133429198848:133429207039", 618 "latency": 60, 619 "name": "nvram", 620 "eventq_index": 0, 621 "clk_domain": "system.clk_domain", 622 "latency_var": 0, 623 "bandwidth": "0.000000", 624 "conf_table_reported": true, 625 "cxx_class": "SimpleMemory", 626 "path": "system.nvram", 627 "null": false, 628 "type": "SimpleMemory", 629 "port": { 630 "peer": "system.membus.master[4]", 631 "role": "SLAVE" 632 }, 633 "in_addr_map": true 634 }, 635 "eventq_index": 0, 636 "work_begin_cpu_id_exit": -1, 637 "dvfs_handler": { 638 "enable": false, 639 "name": "dvfs_handler", 640 "sys_clk_domain": "system.clk_domain", 641 "transition_latency": 200000, 642 "eventq_index": 0, 643 "cxx_class": "DVFSHandler", 644 "domains": [], 645 "path": "system.dvfs_handler", 646 "type": "DVFSHandler" 647 }, 648 "work_end_exit_count": 0,
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