config.json (10411:d96740732a61) config.json (10451:3a87241adfb8)
1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "kernel_addr_check": true,
7 "rom": {
8 "range": "1099243192320:1099251580927",
9 "latency": 60,
10 "name": "rom",
11 "eventq_index": 0,
12 "clk_domain": "system.clk_domain",
13 "latency_var": 0,
14 "bandwidth": "0.000000",
15 "conf_table_reported": true,
16 "cxx_class": "SimpleMemory",
17 "path": "system.rom",
18 "null": false,
19 "type": "SimpleMemory",
20 "port": {
21 "peer": "system.membus.master[3]",
22 "role": "SLAVE"
23 },
24 "in_addr_map": true
25 },
26 "bridge": {
27 "ranges": [
28 "133412421632:133412421639",
29 "134217728000:554050781183",
30 "644245094400:652835028991",
31 "725849473024:1095485095935",
32 "1099255955456:1099255955463"
33 ],
34 "slave": {
35 "peer": "system.membus.master[2]",
36 "role": "SLAVE"
37 },
38 "name": "bridge",
39 "req_size": 16,
40 "clk_domain": "system.clk_domain",
41 "delay": 100,
42 "eventq_index": 0,
43 "master": {
44 "peer": "system.iobus.slave[0]",
45 "role": "MASTER"
46 },
47 "cxx_class": "Bridge",
48 "path": "system.bridge",
49 "resp_size": 16,
50 "type": "Bridge"
51 },
52 "iobus": {
53 "slave": {
54 "peer": [
55 "system.bridge.master"
56 ],
57 "role": "SLAVE"
58 },
59 "name": "iobus",
60 "clk_domain": "system.clk_domain",
61 "header_cycles": 1,
62 "width": 8,
63 "eventq_index": 0,
64 "master": {
65 "peer": [
66 "system.t1000.fake_clk.pio",
67 "system.t1000.fake_membnks.pio",
68 "system.t1000.fake_l2_1.pio",
69 "system.t1000.fake_l2_2.pio",
70 "system.t1000.fake_l2_3.pio",
71 "system.t1000.fake_l2_4.pio",
72 "system.t1000.fake_l2esr_1.pio",
73 "system.t1000.fake_l2esr_2.pio",
74 "system.t1000.fake_l2esr_3.pio",
75 "system.t1000.fake_l2esr_4.pio",
76 "system.t1000.fake_ssi.pio",
77 "system.t1000.fake_jbi.pio",
78 "system.t1000.puart0.pio",
79 "system.t1000.hvuart.pio",
80 "system.disk0.pio"
81 ],
82 "role": "MASTER"
83 },
84 "cxx_class": "NoncoherentXBar",
85 "path": "system.iobus",
86 "type": "NoncoherentXBar",
87 "use_default_range": false
88 },
89 "t1000": {
90 "htod": {
91 "name": "htod",
92 "pio": {
93 "peer": "system.membus.master[1]",
94 "role": "SLAVE"
95 },
96 "time": "Thu Jan 1 00:00:00 2009",
97 "pio_latency": 200,
98 "clk_domain": "system.clk_domain",
99 "system": "system",
100 "eventq_index": 0,
101 "cxx_class": "DumbTOD",
102 "path": "system.t1000.htod",
103 "pio_addr": 1099255906296,
104 "type": "DumbTOD"
105 },
106 "puart0": {
107 "name": "puart0",
108 "pio": {
109 "peer": "system.iobus.master[12]",
110 "role": "SLAVE"
111 },
112 "pio_latency": 200,
113 "clk_domain": "system.clk_domain",
114 "system": "system",
115 "terminal": "system.t1000.pterm",
116 "platform": "system.t1000",
117 "eventq_index": 0,
118 "cxx_class": "Uart8250",
119 "path": "system.t1000.puart0",
120 "pio_addr": 133412421632,
121 "type": "Uart8250"
122 },
123 "fake_membnks": {
124 "system": "system",
125 "ret_data8": 255,
126 "name": "fake_membnks",
127 "warn_access": "",
128 "pio": {
129 "peer": "system.iobus.master[1]",
130 "role": "SLAVE"
131 },
132 "ret_bad_addr": false,
133 "pio_latency": 200,
134 "clk_domain": "system.clk_domain",
135 "fake_mem": false,
136 "pio_size": 16384,
137 "ret_data32": 4294967295,
138 "eventq_index": 0,
139 "update_data": false,
140 "ret_data64": 0,
141 "cxx_class": "IsaFake",
142 "path": "system.t1000.fake_membnks",
143 "pio_addr": 648540061696,
144 "type": "IsaFake",
145 "ret_data16": 65535
146 },
147 "cxx_class": "T1000",
148 "fake_jbi": {
149 "system": "system",
150 "ret_data8": 255,
151 "name": "fake_jbi",
152 "warn_access": "",
153 "pio": {
154 "peer": "system.iobus.master[11]",
155 "role": "SLAVE"
156 },
157 "ret_bad_addr": false,
158 "pio_latency": 200,
159 "clk_domain": "system.clk_domain",
160 "fake_mem": false,
161 "pio_size": 4294967296,
162 "ret_data32": 4294967295,
163 "eventq_index": 0,
164 "update_data": false,
165 "ret_data64": 18446744073709551615,
166 "cxx_class": "IsaFake",
167 "path": "system.t1000.fake_jbi",
168 "pio_addr": 549755813888,
169 "type": "IsaFake",
170 "ret_data16": 65535
171 },
172 "intrctrl": "system.intrctrl",
173 "fake_l2esr_2": {
174 "system": "system",
175 "ret_data8": 255,
176 "name": "fake_l2esr_2",
177 "warn_access": "",
178 "pio": {
179 "peer": "system.iobus.master[7]",
180 "role": "SLAVE"
181 },
182 "ret_bad_addr": false,
183 "pio_latency": 200,
184 "clk_domain": "system.clk_domain",
185 "fake_mem": false,
186 "pio_size": 8,
187 "ret_data32": 4294967295,
188 "eventq_index": 0,
189 "update_data": true,
190 "ret_data64": 0,
191 "cxx_class": "IsaFake",
192 "path": "system.t1000.fake_l2esr_2",
193 "pio_addr": 734439407680,
194 "type": "IsaFake",
195 "ret_data16": 65535
196 },
197 "system": "system",
198 "eventq_index": 0,
199 "hterm": {
200 "name": "hterm",
201 "output": true,
202 "number": 0,
203 "intr_control": "system.intrctrl",
204 "eventq_index": 0,
205 "cxx_class": "Terminal",
206 "path": "system.t1000.hterm",
207 "type": "Terminal",
208 "port": 3456
209 },
210 "type": "T1000",
211 "fake_l2_4": {
212 "system": "system",
213 "ret_data8": 255,
214 "name": "fake_l2_4",
215 "warn_access": "",
216 "pio": {
217 "peer": "system.iobus.master[5]",
218 "role": "SLAVE"
219 },
220 "ret_bad_addr": false,
221 "pio_latency": 200,
222 "clk_domain": "system.clk_domain",
223 "fake_mem": false,
224 "pio_size": 8,
225 "ret_data32": 4294967295,
226 "eventq_index": 0,
227 "update_data": true,
228 "ret_data64": 1,
229 "cxx_class": "IsaFake",
230 "path": "system.t1000.fake_l2_4",
231 "pio_addr": 725849473216,
232 "type": "IsaFake",
233 "ret_data16": 65535
234 },
235 "fake_l2_1": {
236 "system": "system",
237 "ret_data8": 255,
238 "name": "fake_l2_1",
239 "warn_access": "",
240 "pio": {
241 "peer": "system.iobus.master[2]",
242 "role": "SLAVE"
243 },
244 "ret_bad_addr": false,
245 "pio_latency": 200,
246 "clk_domain": "system.clk_domain",
247 "fake_mem": false,
248 "pio_size": 8,
249 "ret_data32": 4294967295,
250 "eventq_index": 0,
251 "update_data": true,
252 "ret_data64": 1,
253 "cxx_class": "IsaFake",
254 "path": "system.t1000.fake_l2_1",
255 "pio_addr": 725849473024,
256 "type": "IsaFake",
257 "ret_data16": 65535
258 },
259 "fake_l2_2": {
260 "system": "system",
261 "ret_data8": 255,
262 "name": "fake_l2_2",
263 "warn_access": "",
264 "pio": {
265 "peer": "system.iobus.master[3]",
266 "role": "SLAVE"
267 },
268 "ret_bad_addr": false,
269 "pio_latency": 200,
270 "clk_domain": "system.clk_domain",
271 "fake_mem": false,
272 "pio_size": 8,
273 "ret_data32": 4294967295,
274 "eventq_index": 0,
275 "update_data": true,
276 "ret_data64": 1,
277 "cxx_class": "IsaFake",
278 "path": "system.t1000.fake_l2_2",
279 "pio_addr": 725849473088,
280 "type": "IsaFake",
281 "ret_data16": 65535
282 },
283 "fake_l2_3": {
284 "system": "system",
285 "ret_data8": 255,
286 "name": "fake_l2_3",
287 "warn_access": "",
288 "pio": {
289 "peer": "system.iobus.master[4]",
290 "role": "SLAVE"
291 },
292 "ret_bad_addr": false,
293 "pio_latency": 200,
294 "clk_domain": "system.clk_domain",
295 "fake_mem": false,
296 "pio_size": 8,
297 "ret_data32": 4294967295,
298 "eventq_index": 0,
299 "update_data": true,
300 "ret_data64": 1,
301 "cxx_class": "IsaFake",
302 "path": "system.t1000.fake_l2_3",
303 "pio_addr": 725849473152,
304 "type": "IsaFake",
305 "ret_data16": 65535
306 },
307 "pterm": {
308 "name": "pterm",
309 "output": true,
310 "number": 0,
311 "intr_control": "system.intrctrl",
312 "eventq_index": 0,
313 "cxx_class": "Terminal",
314 "path": "system.t1000.pterm",
315 "type": "Terminal",
316 "port": 3456
317 },
318 "path": "system.t1000",
319 "iob": {
320 "name": "iob",
321 "pio": {
322 "peer": "system.membus.master[0]",
323 "role": "SLAVE"
324 },
325 "pio_latency": 2,
326 "clk_domain": "system.clk_domain",
327 "system": "system",
328 "platform": "system.t1000",
329 "eventq_index": 0,
330 "cxx_class": "Iob",
331 "path": "system.t1000.iob",
332 "type": "Iob"
333 },
334 "hvuart": {
335 "name": "hvuart",
336 "pio": {
337 "peer": "system.iobus.master[13]",
338 "role": "SLAVE"
339 },
340 "pio_latency": 200,
341 "clk_domain": "system.clk_domain",
342 "system": "system",
343 "terminal": "system.t1000.hterm",
344 "platform": "system.t1000",
345 "eventq_index": 0,
346 "cxx_class": "Uart8250",
347 "path": "system.t1000.hvuart",
348 "pio_addr": 1099255955456,
349 "type": "Uart8250"
350 },
351 "name": "t1000",
352 "fake_l2esr_3": {
353 "system": "system",
354 "ret_data8": 255,
355 "name": "fake_l2esr_3",
356 "warn_access": "",
357 "pio": {
358 "peer": "system.iobus.master[8]",
359 "role": "SLAVE"
360 },
361 "ret_bad_addr": false,
362 "pio_latency": 200,
363 "clk_domain": "system.clk_domain",
364 "fake_mem": false,
365 "pio_size": 8,
366 "ret_data32": 4294967295,
367 "eventq_index": 0,
368 "update_data": true,
369 "ret_data64": 0,
370 "cxx_class": "IsaFake",
371 "path": "system.t1000.fake_l2esr_3",
372 "pio_addr": 734439407744,
373 "type": "IsaFake",
374 "ret_data16": 65535
375 },
376 "fake_ssi": {
377 "system": "system",
378 "ret_data8": 255,
379 "name": "fake_ssi",
380 "warn_access": "",
381 "pio": {
382 "peer": "system.iobus.master[10]",
383 "role": "SLAVE"
384 },
385 "ret_bad_addr": false,
386 "pio_latency": 200,
387 "clk_domain": "system.clk_domain",
388 "fake_mem": false,
389 "pio_size": 268435456,
390 "ret_data32": 4294967295,
391 "eventq_index": 0,
392 "update_data": false,
393 "ret_data64": 18446744073709551615,
394 "cxx_class": "IsaFake",
395 "path": "system.t1000.fake_ssi",
396 "pio_addr": 1095216660480,
397 "type": "IsaFake",
398 "ret_data16": 65535
399 },
400 "fake_l2esr_1": {
401 "system": "system",
402 "ret_data8": 255,
403 "name": "fake_l2esr_1",
404 "warn_access": "",
405 "pio": {
406 "peer": "system.iobus.master[6]",
407 "role": "SLAVE"
408 },
409 "ret_bad_addr": false,
410 "pio_latency": 200,
411 "clk_domain": "system.clk_domain",
412 "fake_mem": false,
413 "pio_size": 8,
414 "ret_data32": 4294967295,
415 "eventq_index": 0,
416 "update_data": true,
417 "ret_data64": 0,
418 "cxx_class": "IsaFake",
419 "path": "system.t1000.fake_l2esr_1",
420 "pio_addr": 734439407616,
421 "type": "IsaFake",
422 "ret_data16": 65535
423 },
424 "fake_l2esr_4": {
425 "system": "system",
426 "ret_data8": 255,
427 "name": "fake_l2esr_4",
428 "warn_access": "",
429 "pio": {
430 "peer": "system.iobus.master[9]",
431 "role": "SLAVE"
432 },
433 "ret_bad_addr": false,
434 "pio_latency": 200,
435 "clk_domain": "system.clk_domain",
436 "fake_mem": false,
437 "pio_size": 8,
438 "ret_data32": 4294967295,
439 "eventq_index": 0,
440 "update_data": true,
441 "ret_data64": 0,
442 "cxx_class": "IsaFake",
443 "path": "system.t1000.fake_l2esr_4",
444 "pio_addr": 734439407808,
445 "type": "IsaFake",
446 "ret_data16": 65535
447 },
448 "fake_clk": {
449 "system": "system",
450 "ret_data8": 255,
451 "name": "fake_clk",
452 "warn_access": "",
453 "pio": {
454 "peer": "system.iobus.master[0]",
455 "role": "SLAVE"
456 },
457 "ret_bad_addr": false,
458 "pio_latency": 200,
459 "clk_domain": "system.clk_domain",
460 "fake_mem": false,
461 "pio_size": 4294967296,
462 "ret_data32": 4294967295,
463 "eventq_index": 0,
464 "update_data": false,
465 "ret_data64": 18446744073709551615,
466 "cxx_class": "IsaFake",
467 "path": "system.t1000.fake_clk",
468 "pio_addr": 644245094400,
469 "type": "IsaFake",
470 "ret_data16": 65535
471 }
472 },
473 "symbolfile": "",
1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "kernel_addr_check": true,
7 "rom": {
8 "range": "1099243192320:1099251580927",
9 "latency": 60,
10 "name": "rom",
11 "eventq_index": 0,
12 "clk_domain": "system.clk_domain",
13 "latency_var": 0,
14 "bandwidth": "0.000000",
15 "conf_table_reported": true,
16 "cxx_class": "SimpleMemory",
17 "path": "system.rom",
18 "null": false,
19 "type": "SimpleMemory",
20 "port": {
21 "peer": "system.membus.master[3]",
22 "role": "SLAVE"
23 },
24 "in_addr_map": true
25 },
26 "bridge": {
27 "ranges": [
28 "133412421632:133412421639",
29 "134217728000:554050781183",
30 "644245094400:652835028991",
31 "725849473024:1095485095935",
32 "1099255955456:1099255955463"
33 ],
34 "slave": {
35 "peer": "system.membus.master[2]",
36 "role": "SLAVE"
37 },
38 "name": "bridge",
39 "req_size": 16,
40 "clk_domain": "system.clk_domain",
41 "delay": 100,
42 "eventq_index": 0,
43 "master": {
44 "peer": "system.iobus.slave[0]",
45 "role": "MASTER"
46 },
47 "cxx_class": "Bridge",
48 "path": "system.bridge",
49 "resp_size": 16,
50 "type": "Bridge"
51 },
52 "iobus": {
53 "slave": {
54 "peer": [
55 "system.bridge.master"
56 ],
57 "role": "SLAVE"
58 },
59 "name": "iobus",
60 "clk_domain": "system.clk_domain",
61 "header_cycles": 1,
62 "width": 8,
63 "eventq_index": 0,
64 "master": {
65 "peer": [
66 "system.t1000.fake_clk.pio",
67 "system.t1000.fake_membnks.pio",
68 "system.t1000.fake_l2_1.pio",
69 "system.t1000.fake_l2_2.pio",
70 "system.t1000.fake_l2_3.pio",
71 "system.t1000.fake_l2_4.pio",
72 "system.t1000.fake_l2esr_1.pio",
73 "system.t1000.fake_l2esr_2.pio",
74 "system.t1000.fake_l2esr_3.pio",
75 "system.t1000.fake_l2esr_4.pio",
76 "system.t1000.fake_ssi.pio",
77 "system.t1000.fake_jbi.pio",
78 "system.t1000.puart0.pio",
79 "system.t1000.hvuart.pio",
80 "system.disk0.pio"
81 ],
82 "role": "MASTER"
83 },
84 "cxx_class": "NoncoherentXBar",
85 "path": "system.iobus",
86 "type": "NoncoherentXBar",
87 "use_default_range": false
88 },
89 "t1000": {
90 "htod": {
91 "name": "htod",
92 "pio": {
93 "peer": "system.membus.master[1]",
94 "role": "SLAVE"
95 },
96 "time": "Thu Jan 1 00:00:00 2009",
97 "pio_latency": 200,
98 "clk_domain": "system.clk_domain",
99 "system": "system",
100 "eventq_index": 0,
101 "cxx_class": "DumbTOD",
102 "path": "system.t1000.htod",
103 "pio_addr": 1099255906296,
104 "type": "DumbTOD"
105 },
106 "puart0": {
107 "name": "puart0",
108 "pio": {
109 "peer": "system.iobus.master[12]",
110 "role": "SLAVE"
111 },
112 "pio_latency": 200,
113 "clk_domain": "system.clk_domain",
114 "system": "system",
115 "terminal": "system.t1000.pterm",
116 "platform": "system.t1000",
117 "eventq_index": 0,
118 "cxx_class": "Uart8250",
119 "path": "system.t1000.puart0",
120 "pio_addr": 133412421632,
121 "type": "Uart8250"
122 },
123 "fake_membnks": {
124 "system": "system",
125 "ret_data8": 255,
126 "name": "fake_membnks",
127 "warn_access": "",
128 "pio": {
129 "peer": "system.iobus.master[1]",
130 "role": "SLAVE"
131 },
132 "ret_bad_addr": false,
133 "pio_latency": 200,
134 "clk_domain": "system.clk_domain",
135 "fake_mem": false,
136 "pio_size": 16384,
137 "ret_data32": 4294967295,
138 "eventq_index": 0,
139 "update_data": false,
140 "ret_data64": 0,
141 "cxx_class": "IsaFake",
142 "path": "system.t1000.fake_membnks",
143 "pio_addr": 648540061696,
144 "type": "IsaFake",
145 "ret_data16": 65535
146 },
147 "cxx_class": "T1000",
148 "fake_jbi": {
149 "system": "system",
150 "ret_data8": 255,
151 "name": "fake_jbi",
152 "warn_access": "",
153 "pio": {
154 "peer": "system.iobus.master[11]",
155 "role": "SLAVE"
156 },
157 "ret_bad_addr": false,
158 "pio_latency": 200,
159 "clk_domain": "system.clk_domain",
160 "fake_mem": false,
161 "pio_size": 4294967296,
162 "ret_data32": 4294967295,
163 "eventq_index": 0,
164 "update_data": false,
165 "ret_data64": 18446744073709551615,
166 "cxx_class": "IsaFake",
167 "path": "system.t1000.fake_jbi",
168 "pio_addr": 549755813888,
169 "type": "IsaFake",
170 "ret_data16": 65535
171 },
172 "intrctrl": "system.intrctrl",
173 "fake_l2esr_2": {
174 "system": "system",
175 "ret_data8": 255,
176 "name": "fake_l2esr_2",
177 "warn_access": "",
178 "pio": {
179 "peer": "system.iobus.master[7]",
180 "role": "SLAVE"
181 },
182 "ret_bad_addr": false,
183 "pio_latency": 200,
184 "clk_domain": "system.clk_domain",
185 "fake_mem": false,
186 "pio_size": 8,
187 "ret_data32": 4294967295,
188 "eventq_index": 0,
189 "update_data": true,
190 "ret_data64": 0,
191 "cxx_class": "IsaFake",
192 "path": "system.t1000.fake_l2esr_2",
193 "pio_addr": 734439407680,
194 "type": "IsaFake",
195 "ret_data16": 65535
196 },
197 "system": "system",
198 "eventq_index": 0,
199 "hterm": {
200 "name": "hterm",
201 "output": true,
202 "number": 0,
203 "intr_control": "system.intrctrl",
204 "eventq_index": 0,
205 "cxx_class": "Terminal",
206 "path": "system.t1000.hterm",
207 "type": "Terminal",
208 "port": 3456
209 },
210 "type": "T1000",
211 "fake_l2_4": {
212 "system": "system",
213 "ret_data8": 255,
214 "name": "fake_l2_4",
215 "warn_access": "",
216 "pio": {
217 "peer": "system.iobus.master[5]",
218 "role": "SLAVE"
219 },
220 "ret_bad_addr": false,
221 "pio_latency": 200,
222 "clk_domain": "system.clk_domain",
223 "fake_mem": false,
224 "pio_size": 8,
225 "ret_data32": 4294967295,
226 "eventq_index": 0,
227 "update_data": true,
228 "ret_data64": 1,
229 "cxx_class": "IsaFake",
230 "path": "system.t1000.fake_l2_4",
231 "pio_addr": 725849473216,
232 "type": "IsaFake",
233 "ret_data16": 65535
234 },
235 "fake_l2_1": {
236 "system": "system",
237 "ret_data8": 255,
238 "name": "fake_l2_1",
239 "warn_access": "",
240 "pio": {
241 "peer": "system.iobus.master[2]",
242 "role": "SLAVE"
243 },
244 "ret_bad_addr": false,
245 "pio_latency": 200,
246 "clk_domain": "system.clk_domain",
247 "fake_mem": false,
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857 "type": "Root",
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859}