1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
16 "clk_domain": "system.clk_domain",
17 "power_model": null,
18 "latency_var": 0,
19 "bandwidth": "0.000000",
20 "conf_table_reported": true,
21 "cxx_class": "SimpleMemory",
22 "p_state_clk_gate_max": 2000000000,
23 "path": "system.rom",
24 "null": false,
25 "type": "SimpleMemory",
26 "port": {
27 "peer": "system.membus.master[3]",
28 "role": "SLAVE"
29 },
30 "in_addr_map": true
31 },
32 "bridge": {
33 "ranges": [
34 "133412421632:133412421639",
35 "134217728000:554050781183",
36 "644245094400:652835028991",
37 "725849473024:1095485095935",
38 "1099255955456:1099255955463"
39 ],
40 "slave": {
41 "peer": "system.membus.master[2]",
42 "role": "SLAVE"
43 },
44 "name": "bridge",
45 "p_state_clk_gate_min": 2,
46 "p_state_clk_gate_bins": 20,

--- 522 unchanged lines hidden (view full) ---

569 }
570 },
571 "partition_desc_addr": 133445976064,
572 "symbolfile": "",
573 "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh",
574 "thermal_model": null,
575 "hypervisor_addr": 1099243257856,
576 "mem_ranges": [
577 "1048576:68157439",
578 "2147483648:2415919103"
579 ],
580 "cxx_class": "SparcSystem",
581 "work_begin_cpu_id_exit": -1,
582 "load_offset": 0,
583 "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin",
584 "work_end_ckpt_count": 0,
585 "work_begin_exit_count": 0,
586 "openboot_addr": 1099243716608,

--- 4 unchanged lines hidden (view full) ---

591 "system.nvram",
592 "system.partition_desc",
593 "system.physmem0",
594 "system.physmem1",
595 "system.rom"
596 ],
597 "work_begin_ckpt_count": 0,
598 "partition_desc": {
599 "range": "133445976064:133445984255",
600 "latency": 60,
601 "name": "partition_desc",
602 "p_state_clk_gate_min": 2,
603 "eventq_index": 0,
604 "p_state_clk_gate_bins": 20,
605 "default_p_state": "UNDEFINED",
606 "clk_domain": "system.clk_domain",
607 "power_model": null,
608 "latency_var": 0,
609 "bandwidth": "0.000000",
610 "conf_table_reported": true,
611 "cxx_class": "SimpleMemory",
612 "p_state_clk_gate_max": 2000000000,
613 "path": "system.partition_desc",

--- 14 unchanged lines hidden (view full) ---

628 "voltage_domain": "system.voltage_domain",
629 "eventq_index": 0,
630 "cxx_class": "SrcClockDomain",
631 "path": "system.clk_domain",
632 "type": "SrcClockDomain",
633 "domain_id": -1
634 },
635 "hypervisor_desc": {
636 "range": "133446500352:133446508543",
637 "latency": 60,
638 "name": "hypervisor_desc",
639 "p_state_clk_gate_min": 2,
640 "eventq_index": 0,
641 "p_state_clk_gate_bins": 20,
642 "default_p_state": "UNDEFINED",
643 "clk_domain": "system.clk_domain",
644 "power_model": null,
645 "latency_var": 0,
646 "bandwidth": "0.000000",
647 "conf_table_reported": true,
648 "cxx_class": "SimpleMemory",
649 "p_state_clk_gate_max": 2000000000,
650 "path": "system.hypervisor_desc",

--- 87 unchanged lines hidden (view full) ---

738 "default": {
739 "peer": "system.membus.badaddr_responder.pio",
740 "role": "MASTER"
741 },
742 "p_state_clk_gate_bins": 20,
743 "use_default_range": false
744 },
745 "nvram": {
746 "range": "133429198848:133429207039",
747 "latency": 60,
748 "name": "nvram",
749 "p_state_clk_gate_min": 2,
750 "eventq_index": 0,
751 "p_state_clk_gate_bins": 20,
752 "default_p_state": "UNDEFINED",
753 "clk_domain": "system.clk_domain",
754 "power_model": null,
755 "latency_var": 0,
756 "bandwidth": "0.000000",
757 "conf_table_reported": true,
758 "cxx_class": "SimpleMemory",
759 "p_state_clk_gate_max": 2000000000,
760 "path": "system.nvram",

--- 35 unchanged lines hidden (view full) ---

796 "cache_line_size": 64,
797 "boot_osflags": "a",
798 "system_port": {
799 "peer": "system.membus.slave[0]",
800 "role": "MASTER"
801 },
802 "physmem": [
803 {
804 "range": "1048576:68157439",
805 "latency": 60,
806 "name": "physmem0",
807 "p_state_clk_gate_min": 2,
808 "eventq_index": 0,
809 "p_state_clk_gate_bins": 20,
810 "default_p_state": "UNDEFINED",
811 "clk_domain": "system.clk_domain",
812 "power_model": null,
813 "latency_var": 0,
814 "bandwidth": "0.000000",
815 "conf_table_reported": true,
816 "cxx_class": "SimpleMemory",
817 "p_state_clk_gate_max": 2000000000,
818 "path": "system.physmem0",
819 "null": false,
820 "type": "SimpleMemory",
821 "port": {
822 "peer": "system.membus.master[7]",
823 "role": "SLAVE"
824 },
825 "in_addr_map": true
826 },
827 {
828 "range": "2147483648:2415919103",
829 "latency": 60,
830 "name": "physmem1",
831 "p_state_clk_gate_min": 2,
832 "eventq_index": 0,
833 "p_state_clk_gate_bins": 20,
834 "default_p_state": "UNDEFINED",
835 "clk_domain": "system.clk_domain",
836 "power_model": null,
837 "latency_var": 0,
838 "bandwidth": "0.000000",
839 "conf_table_reported": true,
840 "cxx_class": "SimpleMemory",
841 "p_state_clk_gate_max": 2000000000,
842 "path": "system.physmem1",

--- 184 unchanged lines hidden ---