1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
16 "clk_domain": "system.clk_domain",
17 "latency_var": 0,
18 "bandwidth": "0.000000",
19 "conf_table_reported": true,
20 "cxx_class": "SimpleMemory",
21 "p_state_clk_gate_max": 2000000000,
22 "path": "system.rom",
23 "null": false,
24 "type": "SimpleMemory",
--- 16 unchanged lines hidden (view full) ---
41 "role": "SLAVE"
42 },
43 "name": "bridge",
44 "p_state_clk_gate_min": 2,
45 "p_state_clk_gate_bins": 20,
46 "cxx_class": "Bridge",
47 "req_size": 16,
48 "clk_domain": "system.clk_domain",
49 "delay": 100,
50 "eventq_index": 0,
51 "master": {
52 "peer": "system.iobus.slave[0]",
53 "role": "MASTER"
54 },
55 "default_p_state": "UNDEFINED",
56 "p_state_clk_gate_max": 2000000000,
--- 9 unchanged lines hidden (view full) ---
66 ],
67 "role": "SLAVE"
68 },
69 "name": "iobus",
70 "p_state_clk_gate_min": 2,
71 "p_state_clk_gate_bins": 20,
72 "cxx_class": "NoncoherentXBar",
73 "clk_domain": "system.clk_domain",
74 "width": 16,
75 "eventq_index": 0,
76 "master": {
77 "peer": [
78 "system.t1000.fake_clk.pio",
79 "system.t1000.fake_membnks.pio",
80 "system.t1000.fake_l2_1.pio",
81 "system.t1000.fake_l2_2.pio",
--- 26 unchanged lines hidden (view full) ---
108 "pio": {
109 "peer": "system.membus.master[1]",
110 "role": "SLAVE"
111 },
112 "p_state_clk_gate_bins": 20,
113 "cxx_class": "DumbTOD",
114 "pio_latency": 200,
115 "clk_domain": "system.clk_domain",
116 "system": "system",
117 "eventq_index": 0,
118 "time": "Thu Jan 1 00:00:00 2009",
119 "default_p_state": "UNDEFINED",
120 "p_state_clk_gate_max": 2000000000,
121 "path": "system.t1000.htod",
122 "pio_addr": 1099255906296,
123 "type": "DumbTOD"
--- 4 unchanged lines hidden (view full) ---
128 "pio": {
129 "peer": "system.iobus.master[12]",
130 "role": "SLAVE"
131 },
132 "p_state_clk_gate_bins": 20,
133 "cxx_class": "Uart8250",
134 "pio_latency": 200,
135 "clk_domain": "system.clk_domain",
136 "system": "system",
137 "terminal": "system.t1000.pterm",
138 "platform": "system.t1000",
139 "eventq_index": 0,
140 "default_p_state": "UNDEFINED",
141 "p_state_clk_gate_max": 2000000000,
142 "path": "system.t1000.puart0",
143 "pio_addr": 133412421632,
--- 13 unchanged lines hidden (view full) ---
157 "warn_access": "",
158 "pio_latency": 200,
159 "system": "system",
160 "eventq_index": 0,
161 "default_p_state": "UNDEFINED",
162 "p_state_clk_gate_max": 2000000000,
163 "type": "IsaFake",
164 "p_state_clk_gate_min": 2,
165 "ret_data32": 4294967295,
166 "path": "system.t1000.fake_membnks",
167 "ret_data16": 65535,
168 "ret_data8": 255,
169 "name": "fake_membnks",
170 "ret_bad_addr": false,
171 "pio_size": 16384,
172 "p_state_clk_gate_bins": 20
--- 13 unchanged lines hidden (view full) ---
186 "warn_access": "",
187 "pio_latency": 200,
188 "system": "system",
189 "eventq_index": 0,
190 "default_p_state": "UNDEFINED",
191 "p_state_clk_gate_max": 2000000000,
192 "type": "IsaFake",
193 "p_state_clk_gate_min": 2,
194 "ret_data32": 4294967295,
195 "path": "system.t1000.fake_jbi",
196 "ret_data16": 65535,
197 "ret_data8": 255,
198 "name": "fake_jbi",
199 "ret_bad_addr": false,
200 "pio_size": 4294967296,
201 "p_state_clk_gate_bins": 20
--- 13 unchanged lines hidden (view full) ---
215 "warn_access": "",
216 "pio_latency": 200,
217 "system": "system",
218 "eventq_index": 0,
219 "default_p_state": "UNDEFINED",
220 "p_state_clk_gate_max": 2000000000,
221 "type": "IsaFake",
222 "p_state_clk_gate_min": 2,
223 "ret_data32": 4294967295,
224 "path": "system.t1000.fake_l2esr_2",
225 "ret_data16": 65535,
226 "ret_data8": 255,
227 "name": "fake_l2esr_2",
228 "ret_bad_addr": false,
229 "pio_size": 8,
230 "p_state_clk_gate_bins": 20
--- 26 unchanged lines hidden (view full) ---
257 "warn_access": "",
258 "pio_latency": 200,
259 "system": "system",
260 "eventq_index": 0,
261 "default_p_state": "UNDEFINED",
262 "p_state_clk_gate_max": 2000000000,
263 "type": "IsaFake",
264 "p_state_clk_gate_min": 2,
265 "ret_data32": 4294967295,
266 "path": "system.t1000.fake_l2_4",
267 "ret_data16": 65535,
268 "ret_data8": 255,
269 "name": "fake_l2_4",
270 "ret_bad_addr": false,
271 "pio_size": 8,
272 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
285 "warn_access": "",
286 "pio_latency": 200,
287 "system": "system",
288 "eventq_index": 0,
289 "default_p_state": "UNDEFINED",
290 "p_state_clk_gate_max": 2000000000,
291 "type": "IsaFake",
292 "p_state_clk_gate_min": 2,
293 "ret_data32": 4294967295,
294 "path": "system.t1000.fake_l2_1",
295 "ret_data16": 65535,
296 "ret_data8": 255,
297 "name": "fake_l2_1",
298 "ret_bad_addr": false,
299 "pio_size": 8,
300 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
313 "warn_access": "",
314 "pio_latency": 200,
315 "system": "system",
316 "eventq_index": 0,
317 "default_p_state": "UNDEFINED",
318 "p_state_clk_gate_max": 2000000000,
319 "type": "IsaFake",
320 "p_state_clk_gate_min": 2,
321 "ret_data32": 4294967295,
322 "path": "system.t1000.fake_l2_2",
323 "ret_data16": 65535,
324 "ret_data8": 255,
325 "name": "fake_l2_2",
326 "ret_bad_addr": false,
327 "pio_size": 8,
328 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
341 "warn_access": "",
342 "pio_latency": 200,
343 "system": "system",
344 "eventq_index": 0,
345 "default_p_state": "UNDEFINED",
346 "p_state_clk_gate_max": 2000000000,
347 "type": "IsaFake",
348 "p_state_clk_gate_min": 2,
349 "ret_data32": 4294967295,
350 "path": "system.t1000.fake_l2_3",
351 "ret_data16": 65535,
352 "ret_data8": 255,
353 "name": "fake_l2_3",
354 "ret_bad_addr": false,
355 "pio_size": 8,
356 "p_state_clk_gate_bins": 20
--- 16 unchanged lines hidden (view full) ---
373 "pio": {
374 "peer": "system.membus.master[0]",
375 "role": "SLAVE"
376 },
377 "p_state_clk_gate_bins": 20,
378 "cxx_class": "Iob",
379 "pio_latency": 2,
380 "clk_domain": "system.clk_domain",
381 "system": "system",
382 "platform": "system.t1000",
383 "eventq_index": 0,
384 "default_p_state": "UNDEFINED",
385 "p_state_clk_gate_max": 2000000000,
386 "path": "system.t1000.iob",
387 "type": "Iob"
388 },
389 "hvuart": {
390 "name": "hvuart",
391 "p_state_clk_gate_min": 2,
392 "pio": {
393 "peer": "system.iobus.master[13]",
394 "role": "SLAVE"
395 },
396 "p_state_clk_gate_bins": 20,
397 "cxx_class": "Uart8250",
398 "pio_latency": 200,
399 "clk_domain": "system.clk_domain",
400 "system": "system",
401 "terminal": "system.t1000.hterm",
402 "platform": "system.t1000",
403 "eventq_index": 0,
404 "default_p_state": "UNDEFINED",
405 "p_state_clk_gate_max": 2000000000,
406 "path": "system.t1000.hvuart",
407 "pio_addr": 1099255955456,
--- 14 unchanged lines hidden (view full) ---
422 "warn_access": "",
423 "pio_latency": 200,
424 "system": "system",
425 "eventq_index": 0,
426 "default_p_state": "UNDEFINED",
427 "p_state_clk_gate_max": 2000000000,
428 "type": "IsaFake",
429 "p_state_clk_gate_min": 2,
430 "ret_data32": 4294967295,
431 "path": "system.t1000.fake_l2esr_3",
432 "ret_data16": 65535,
433 "ret_data8": 255,
434 "name": "fake_l2esr_3",
435 "ret_bad_addr": false,
436 "pio_size": 8,
437 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
450 "warn_access": "",
451 "pio_latency": 200,
452 "system": "system",
453 "eventq_index": 0,
454 "default_p_state": "UNDEFINED",
455 "p_state_clk_gate_max": 2000000000,
456 "type": "IsaFake",
457 "p_state_clk_gate_min": 2,
458 "ret_data32": 4294967295,
459 "path": "system.t1000.fake_ssi",
460 "ret_data16": 65535,
461 "ret_data8": 255,
462 "name": "fake_ssi",
463 "ret_bad_addr": false,
464 "pio_size": 268435456,
465 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
478 "warn_access": "",
479 "pio_latency": 200,
480 "system": "system",
481 "eventq_index": 0,
482 "default_p_state": "UNDEFINED",
483 "p_state_clk_gate_max": 2000000000,
484 "type": "IsaFake",
485 "p_state_clk_gate_min": 2,
486 "ret_data32": 4294967295,
487 "path": "system.t1000.fake_l2esr_1",
488 "ret_data16": 65535,
489 "ret_data8": 255,
490 "name": "fake_l2esr_1",
491 "ret_bad_addr": false,
492 "pio_size": 8,
493 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
506 "warn_access": "",
507 "pio_latency": 200,
508 "system": "system",
509 "eventq_index": 0,
510 "default_p_state": "UNDEFINED",
511 "p_state_clk_gate_max": 2000000000,
512 "type": "IsaFake",
513 "p_state_clk_gate_min": 2,
514 "ret_data32": 4294967295,
515 "path": "system.t1000.fake_l2esr_4",
516 "ret_data16": 65535,
517 "ret_data8": 255,
518 "name": "fake_l2esr_4",
519 "ret_bad_addr": false,
520 "pio_size": 8,
521 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
534 "warn_access": "",
535 "pio_latency": 200,
536 "system": "system",
537 "eventq_index": 0,
538 "default_p_state": "UNDEFINED",
539 "p_state_clk_gate_max": 2000000000,
540 "type": "IsaFake",
541 "p_state_clk_gate_min": 2,
542 "ret_data32": 4294967295,
543 "path": "system.t1000.fake_clk",
544 "ret_data16": 65535,
545 "ret_data8": 255,
546 "name": "fake_clk",
547 "ret_bad_addr": false,
548 "pio_size": 4294967296,
549 "p_state_clk_gate_bins": 20
--- 30 unchanged lines hidden (view full) ---
580 "range": "133445976064:133445984255",
581 "latency": 60,
582 "name": "partition_desc",
583 "p_state_clk_gate_min": 2,
584 "eventq_index": 0,
585 "p_state_clk_gate_bins": 20,
586 "default_p_state": "UNDEFINED",
587 "clk_domain": "system.clk_domain",
588 "latency_var": 0,
589 "bandwidth": "0.000000",
590 "conf_table_reported": true,
591 "cxx_class": "SimpleMemory",
592 "p_state_clk_gate_max": 2000000000,
593 "path": "system.partition_desc",
594 "null": false,
595 "type": "SimpleMemory",
--- 20 unchanged lines hidden (view full) ---
616 "range": "133446500352:133446508543",
617 "latency": 60,
618 "name": "hypervisor_desc",
619 "p_state_clk_gate_min": 2,
620 "eventq_index": 0,
621 "p_state_clk_gate_bins": 20,
622 "default_p_state": "UNDEFINED",
623 "clk_domain": "system.clk_domain",
624 "latency_var": 0,
625 "bandwidth": "0.000000",
626 "conf_table_reported": true,
627 "cxx_class": "SimpleMemory",
628 "p_state_clk_gate_max": 2000000000,
629 "path": "system.hypervisor_desc",
630 "null": false,
631 "type": "SimpleMemory",
--- 22 unchanged lines hidden (view full) ---
654 "warn_access": "",
655 "pio_latency": 200,
656 "system": "system",
657 "eventq_index": 0,
658 "default_p_state": "UNDEFINED",
659 "p_state_clk_gate_max": 2000000000,
660 "type": "IsaFake",
661 "p_state_clk_gate_min": 2,
662 "ret_data32": 4294967295,
663 "path": "system.membus.badaddr_responder",
664 "ret_data16": 65535,
665 "ret_data8": 255,
666 "name": "badaddr_responder",
667 "ret_bad_addr": true,
668 "pio_size": 8,
669 "p_state_clk_gate_bins": 20
--- 25 unchanged lines hidden (view full) ---
695 "system.system_port",
696 "system.cpu.icache_port",
697 "system.cpu.dcache_port"
698 ],
699 "role": "SLAVE"
700 },
701 "p_state_clk_gate_min": 2,
702 "snoop_filter": null,
703 "path": "system.membus",
704 "snoop_response_latency": 4,
705 "name": "membus",
706 "default": {
707 "peer": "system.membus.badaddr_responder.pio",
708 "role": "MASTER"
709 },
710 "p_state_clk_gate_bins": 20,
711 "use_default_range": false
712 },
713 "nvram": {
714 "range": "133429198848:133429207039",
715 "latency": 60,
716 "name": "nvram",
717 "p_state_clk_gate_min": 2,
718 "eventq_index": 0,
719 "p_state_clk_gate_bins": 20,
720 "default_p_state": "UNDEFINED",
721 "clk_domain": "system.clk_domain",
722 "latency_var": 0,
723 "bandwidth": "0.000000",
724 "conf_table_reported": true,
725 "cxx_class": "SimpleMemory",
726 "p_state_clk_gate_max": 2000000000,
727 "path": "system.nvram",
728 "null": false,
729 "type": "SimpleMemory",
--- 41 unchanged lines hidden (view full) ---
771 "range": "1048576:68157439",
772 "latency": 60,
773 "name": "physmem0",
774 "p_state_clk_gate_min": 2,
775 "eventq_index": 0,
776 "p_state_clk_gate_bins": 20,
777 "default_p_state": "UNDEFINED",
778 "clk_domain": "system.clk_domain",
779 "latency_var": 0,
780 "bandwidth": "0.000000",
781 "conf_table_reported": true,
782 "cxx_class": "SimpleMemory",
783 "p_state_clk_gate_max": 2000000000,
784 "path": "system.physmem0",
785 "null": false,
786 "type": "SimpleMemory",
--- 7 unchanged lines hidden (view full) ---
794 "range": "2147483648:2415919103",
795 "latency": 60,
796 "name": "physmem1",
797 "p_state_clk_gate_min": 2,
798 "eventq_index": 0,
799 "p_state_clk_gate_bins": 20,
800 "default_p_state": "UNDEFINED",
801 "clk_domain": "system.clk_domain",
802 "latency_var": 0,
803 "bandwidth": "0.000000",
804 "conf_table_reported": true,
805 "cxx_class": "SimpleMemory",
806 "p_state_clk_gate_max": 2000000000,
807 "path": "system.physmem1",
808 "null": false,
809 "type": "SimpleMemory",
810 "port": {
811 "peer": "system.membus.master[8]",
812 "role": "SLAVE"
813 },
814 "in_addr_map": true
815 }
816 ],
817 "work_cpus_ckpt_count": 0,
818 "thermal_components": [],
819 "path": "system",
820 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
821 "cpu_clk_domain": {
822 "name": "cpu_clk_domain",
823 "clock": [
824 2
--- 57 unchanged lines hidden (view full) ---
882 "cxx_class": "SparcISA::Interrupts"
883 }
884 ],
885 "dcache_port": {
886 "peer": "system.membus.slave[2]",
887 "role": "MASTER"
888 },
889 "socket_id": 0,
890 "max_insts_all_threads": 0,
891 "path": "system.cpu",
892 "max_loads_any_thread": 0,
893 "switched_out": false,
894 "workload": [],
895 "name": "cpu",
896 "dtb": {
897 "name": "dtb",
--- 58 unchanged lines hidden (view full) ---
956 "path": "system.disk0.image",
957 "image_file": "",
958 "type": "CowDiskImage",
959 "table_size": 65536
960 },
961 "cxx_class": "MmDisk",
962 "pio_latency": 200,
963 "clk_domain": "system.clk_domain",
964 "system": "system",
965 "eventq_index": 0,
966 "default_p_state": "UNDEFINED",
967 "p_state_clk_gate_max": 2000000000,
968 "path": "system.disk0",
969 "pio_addr": 134217728000,
970 "type": "MmDisk"
971 },
--- 17 unchanged lines hidden ---
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
9 "range": "1099243192320:1099251580927",
10 "latency": 60,
11 "name": "rom",
12 "p_state_clk_gate_min": 2,
13 "eventq_index": 0,
14 "p_state_clk_gate_bins": 20,
15 "default_p_state": "UNDEFINED",
16 "clk_domain": "system.clk_domain",
17 "latency_var": 0,
18 "bandwidth": "0.000000",
19 "conf_table_reported": true,
20 "cxx_class": "SimpleMemory",
21 "p_state_clk_gate_max": 2000000000,
22 "path": "system.rom",
23 "null": false,
24 "type": "SimpleMemory",
--- 16 unchanged lines hidden (view full) ---
41 "role": "SLAVE"
42 },
43 "name": "bridge",
44 "p_state_clk_gate_min": 2,
45 "p_state_clk_gate_bins": 20,
46 "cxx_class": "Bridge",
47 "req_size": 16,
48 "clk_domain": "system.clk_domain",
49 "delay": 100,
50 "eventq_index": 0,
51 "master": {
52 "peer": "system.iobus.slave[0]",
53 "role": "MASTER"
54 },
55 "default_p_state": "UNDEFINED",
56 "p_state_clk_gate_max": 2000000000,
--- 9 unchanged lines hidden (view full) ---
66 ],
67 "role": "SLAVE"
68 },
69 "name": "iobus",
70 "p_state_clk_gate_min": 2,
71 "p_state_clk_gate_bins": 20,
72 "cxx_class": "NoncoherentXBar",
73 "clk_domain": "system.clk_domain",
74 "width": 16,
75 "eventq_index": 0,
76 "master": {
77 "peer": [
78 "system.t1000.fake_clk.pio",
79 "system.t1000.fake_membnks.pio",
80 "system.t1000.fake_l2_1.pio",
81 "system.t1000.fake_l2_2.pio",
--- 26 unchanged lines hidden (view full) ---
108 "pio": {
109 "peer": "system.membus.master[1]",
110 "role": "SLAVE"
111 },
112 "p_state_clk_gate_bins": 20,
113 "cxx_class": "DumbTOD",
114 "pio_latency": 200,
115 "clk_domain": "system.clk_domain",
116 "system": "system",
117 "eventq_index": 0,
118 "time": "Thu Jan 1 00:00:00 2009",
119 "default_p_state": "UNDEFINED",
120 "p_state_clk_gate_max": 2000000000,
121 "path": "system.t1000.htod",
122 "pio_addr": 1099255906296,
123 "type": "DumbTOD"
--- 4 unchanged lines hidden (view full) ---
128 "pio": {
129 "peer": "system.iobus.master[12]",
130 "role": "SLAVE"
131 },
132 "p_state_clk_gate_bins": 20,
133 "cxx_class": "Uart8250",
134 "pio_latency": 200,
135 "clk_domain": "system.clk_domain",
136 "system": "system",
137 "terminal": "system.t1000.pterm",
138 "platform": "system.t1000",
139 "eventq_index": 0,
140 "default_p_state": "UNDEFINED",
141 "p_state_clk_gate_max": 2000000000,
142 "path": "system.t1000.puart0",
143 "pio_addr": 133412421632,
--- 13 unchanged lines hidden (view full) ---
157 "warn_access": "",
158 "pio_latency": 200,
159 "system": "system",
160 "eventq_index": 0,
161 "default_p_state": "UNDEFINED",
162 "p_state_clk_gate_max": 2000000000,
163 "type": "IsaFake",
164 "p_state_clk_gate_min": 2,
165 "ret_data32": 4294967295,
166 "path": "system.t1000.fake_membnks",
167 "ret_data16": 65535,
168 "ret_data8": 255,
169 "name": "fake_membnks",
170 "ret_bad_addr": false,
171 "pio_size": 16384,
172 "p_state_clk_gate_bins": 20
--- 13 unchanged lines hidden (view full) ---
186 "warn_access": "",
187 "pio_latency": 200,
188 "system": "system",
189 "eventq_index": 0,
190 "default_p_state": "UNDEFINED",
191 "p_state_clk_gate_max": 2000000000,
192 "type": "IsaFake",
193 "p_state_clk_gate_min": 2,
194 "ret_data32": 4294967295,
195 "path": "system.t1000.fake_jbi",
196 "ret_data16": 65535,
197 "ret_data8": 255,
198 "name": "fake_jbi",
199 "ret_bad_addr": false,
200 "pio_size": 4294967296,
201 "p_state_clk_gate_bins": 20
--- 13 unchanged lines hidden (view full) ---
215 "warn_access": "",
216 "pio_latency": 200,
217 "system": "system",
218 "eventq_index": 0,
219 "default_p_state": "UNDEFINED",
220 "p_state_clk_gate_max": 2000000000,
221 "type": "IsaFake",
222 "p_state_clk_gate_min": 2,
223 "ret_data32": 4294967295,
224 "path": "system.t1000.fake_l2esr_2",
225 "ret_data16": 65535,
226 "ret_data8": 255,
227 "name": "fake_l2esr_2",
228 "ret_bad_addr": false,
229 "pio_size": 8,
230 "p_state_clk_gate_bins": 20
--- 26 unchanged lines hidden (view full) ---
257 "warn_access": "",
258 "pio_latency": 200,
259 "system": "system",
260 "eventq_index": 0,
261 "default_p_state": "UNDEFINED",
262 "p_state_clk_gate_max": 2000000000,
263 "type": "IsaFake",
264 "p_state_clk_gate_min": 2,
265 "ret_data32": 4294967295,
266 "path": "system.t1000.fake_l2_4",
267 "ret_data16": 65535,
268 "ret_data8": 255,
269 "name": "fake_l2_4",
270 "ret_bad_addr": false,
271 "pio_size": 8,
272 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
285 "warn_access": "",
286 "pio_latency": 200,
287 "system": "system",
288 "eventq_index": 0,
289 "default_p_state": "UNDEFINED",
290 "p_state_clk_gate_max": 2000000000,
291 "type": "IsaFake",
292 "p_state_clk_gate_min": 2,
293 "ret_data32": 4294967295,
294 "path": "system.t1000.fake_l2_1",
295 "ret_data16": 65535,
296 "ret_data8": 255,
297 "name": "fake_l2_1",
298 "ret_bad_addr": false,
299 "pio_size": 8,
300 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
313 "warn_access": "",
314 "pio_latency": 200,
315 "system": "system",
316 "eventq_index": 0,
317 "default_p_state": "UNDEFINED",
318 "p_state_clk_gate_max": 2000000000,
319 "type": "IsaFake",
320 "p_state_clk_gate_min": 2,
321 "ret_data32": 4294967295,
322 "path": "system.t1000.fake_l2_2",
323 "ret_data16": 65535,
324 "ret_data8": 255,
325 "name": "fake_l2_2",
326 "ret_bad_addr": false,
327 "pio_size": 8,
328 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
341 "warn_access": "",
342 "pio_latency": 200,
343 "system": "system",
344 "eventq_index": 0,
345 "default_p_state": "UNDEFINED",
346 "p_state_clk_gate_max": 2000000000,
347 "type": "IsaFake",
348 "p_state_clk_gate_min": 2,
349 "ret_data32": 4294967295,
350 "path": "system.t1000.fake_l2_3",
351 "ret_data16": 65535,
352 "ret_data8": 255,
353 "name": "fake_l2_3",
354 "ret_bad_addr": false,
355 "pio_size": 8,
356 "p_state_clk_gate_bins": 20
--- 16 unchanged lines hidden (view full) ---
373 "pio": {
374 "peer": "system.membus.master[0]",
375 "role": "SLAVE"
376 },
377 "p_state_clk_gate_bins": 20,
378 "cxx_class": "Iob",
379 "pio_latency": 2,
380 "clk_domain": "system.clk_domain",
381 "system": "system",
382 "platform": "system.t1000",
383 "eventq_index": 0,
384 "default_p_state": "UNDEFINED",
385 "p_state_clk_gate_max": 2000000000,
386 "path": "system.t1000.iob",
387 "type": "Iob"
388 },
389 "hvuart": {
390 "name": "hvuart",
391 "p_state_clk_gate_min": 2,
392 "pio": {
393 "peer": "system.iobus.master[13]",
394 "role": "SLAVE"
395 },
396 "p_state_clk_gate_bins": 20,
397 "cxx_class": "Uart8250",
398 "pio_latency": 200,
399 "clk_domain": "system.clk_domain",
400 "system": "system",
401 "terminal": "system.t1000.hterm",
402 "platform": "system.t1000",
403 "eventq_index": 0,
404 "default_p_state": "UNDEFINED",
405 "p_state_clk_gate_max": 2000000000,
406 "path": "system.t1000.hvuart",
407 "pio_addr": 1099255955456,
--- 14 unchanged lines hidden (view full) ---
422 "warn_access": "",
423 "pio_latency": 200,
424 "system": "system",
425 "eventq_index": 0,
426 "default_p_state": "UNDEFINED",
427 "p_state_clk_gate_max": 2000000000,
428 "type": "IsaFake",
429 "p_state_clk_gate_min": 2,
430 "ret_data32": 4294967295,
431 "path": "system.t1000.fake_l2esr_3",
432 "ret_data16": 65535,
433 "ret_data8": 255,
434 "name": "fake_l2esr_3",
435 "ret_bad_addr": false,
436 "pio_size": 8,
437 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
450 "warn_access": "",
451 "pio_latency": 200,
452 "system": "system",
453 "eventq_index": 0,
454 "default_p_state": "UNDEFINED",
455 "p_state_clk_gate_max": 2000000000,
456 "type": "IsaFake",
457 "p_state_clk_gate_min": 2,
458 "ret_data32": 4294967295,
459 "path": "system.t1000.fake_ssi",
460 "ret_data16": 65535,
461 "ret_data8": 255,
462 "name": "fake_ssi",
463 "ret_bad_addr": false,
464 "pio_size": 268435456,
465 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
478 "warn_access": "",
479 "pio_latency": 200,
480 "system": "system",
481 "eventq_index": 0,
482 "default_p_state": "UNDEFINED",
483 "p_state_clk_gate_max": 2000000000,
484 "type": "IsaFake",
485 "p_state_clk_gate_min": 2,
486 "ret_data32": 4294967295,
487 "path": "system.t1000.fake_l2esr_1",
488 "ret_data16": 65535,
489 "ret_data8": 255,
490 "name": "fake_l2esr_1",
491 "ret_bad_addr": false,
492 "pio_size": 8,
493 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
506 "warn_access": "",
507 "pio_latency": 200,
508 "system": "system",
509 "eventq_index": 0,
510 "default_p_state": "UNDEFINED",
511 "p_state_clk_gate_max": 2000000000,
512 "type": "IsaFake",
513 "p_state_clk_gate_min": 2,
514 "ret_data32": 4294967295,
515 "path": "system.t1000.fake_l2esr_4",
516 "ret_data16": 65535,
517 "ret_data8": 255,
518 "name": "fake_l2esr_4",
519 "ret_bad_addr": false,
520 "pio_size": 8,
521 "p_state_clk_gate_bins": 20
--- 12 unchanged lines hidden (view full) ---
534 "warn_access": "",
535 "pio_latency": 200,
536 "system": "system",
537 "eventq_index": 0,
538 "default_p_state": "UNDEFINED",
539 "p_state_clk_gate_max": 2000000000,
540 "type": "IsaFake",
541 "p_state_clk_gate_min": 2,
542 "ret_data32": 4294967295,
543 "path": "system.t1000.fake_clk",
544 "ret_data16": 65535,
545 "ret_data8": 255,
546 "name": "fake_clk",
547 "ret_bad_addr": false,
548 "pio_size": 4294967296,
549 "p_state_clk_gate_bins": 20
--- 30 unchanged lines hidden (view full) ---
580 "range": "133445976064:133445984255",
581 "latency": 60,
582 "name": "partition_desc",
583 "p_state_clk_gate_min": 2,
584 "eventq_index": 0,
585 "p_state_clk_gate_bins": 20,
586 "default_p_state": "UNDEFINED",
587 "clk_domain": "system.clk_domain",
588 "latency_var": 0,
589 "bandwidth": "0.000000",
590 "conf_table_reported": true,
591 "cxx_class": "SimpleMemory",
592 "p_state_clk_gate_max": 2000000000,
593 "path": "system.partition_desc",
594 "null": false,
595 "type": "SimpleMemory",
--- 20 unchanged lines hidden (view full) ---
616 "range": "133446500352:133446508543",
617 "latency": 60,
618 "name": "hypervisor_desc",
619 "p_state_clk_gate_min": 2,
620 "eventq_index": 0,
621 "p_state_clk_gate_bins": 20,
622 "default_p_state": "UNDEFINED",
623 "clk_domain": "system.clk_domain",
624 "latency_var": 0,
625 "bandwidth": "0.000000",
626 "conf_table_reported": true,
627 "cxx_class": "SimpleMemory",
628 "p_state_clk_gate_max": 2000000000,
629 "path": "system.hypervisor_desc",
630 "null": false,
631 "type": "SimpleMemory",
--- 22 unchanged lines hidden (view full) ---
654 "warn_access": "",
655 "pio_latency": 200,
656 "system": "system",
657 "eventq_index": 0,
658 "default_p_state": "UNDEFINED",
659 "p_state_clk_gate_max": 2000000000,
660 "type": "IsaFake",
661 "p_state_clk_gate_min": 2,
662 "ret_data32": 4294967295,
663 "path": "system.membus.badaddr_responder",
664 "ret_data16": 65535,
665 "ret_data8": 255,
666 "name": "badaddr_responder",
667 "ret_bad_addr": true,
668 "pio_size": 8,
669 "p_state_clk_gate_bins": 20
--- 25 unchanged lines hidden (view full) ---
695 "system.system_port",
696 "system.cpu.icache_port",
697 "system.cpu.dcache_port"
698 ],
699 "role": "SLAVE"
700 },
701 "p_state_clk_gate_min": 2,
702 "snoop_filter": null,
703 "path": "system.membus",
704 "snoop_response_latency": 4,
705 "name": "membus",
706 "default": {
707 "peer": "system.membus.badaddr_responder.pio",
708 "role": "MASTER"
709 },
710 "p_state_clk_gate_bins": 20,
711 "use_default_range": false
712 },
713 "nvram": {
714 "range": "133429198848:133429207039",
715 "latency": 60,
716 "name": "nvram",
717 "p_state_clk_gate_min": 2,
718 "eventq_index": 0,
719 "p_state_clk_gate_bins": 20,
720 "default_p_state": "UNDEFINED",
721 "clk_domain": "system.clk_domain",
722 "latency_var": 0,
723 "bandwidth": "0.000000",
724 "conf_table_reported": true,
725 "cxx_class": "SimpleMemory",
726 "p_state_clk_gate_max": 2000000000,
727 "path": "system.nvram",
728 "null": false,
729 "type": "SimpleMemory",
--- 41 unchanged lines hidden (view full) ---
771 "range": "1048576:68157439",
772 "latency": 60,
773 "name": "physmem0",
774 "p_state_clk_gate_min": 2,
775 "eventq_index": 0,
776 "p_state_clk_gate_bins": 20,
777 "default_p_state": "UNDEFINED",
778 "clk_domain": "system.clk_domain",
779 "latency_var": 0,
780 "bandwidth": "0.000000",
781 "conf_table_reported": true,
782 "cxx_class": "SimpleMemory",
783 "p_state_clk_gate_max": 2000000000,
784 "path": "system.physmem0",
785 "null": false,
786 "type": "SimpleMemory",
--- 7 unchanged lines hidden (view full) ---
794 "range": "2147483648:2415919103",
795 "latency": 60,
796 "name": "physmem1",
797 "p_state_clk_gate_min": 2,
798 "eventq_index": 0,
799 "p_state_clk_gate_bins": 20,
800 "default_p_state": "UNDEFINED",
801 "clk_domain": "system.clk_domain",
802 "latency_var": 0,
803 "bandwidth": "0.000000",
804 "conf_table_reported": true,
805 "cxx_class": "SimpleMemory",
806 "p_state_clk_gate_max": 2000000000,
807 "path": "system.physmem1",
808 "null": false,
809 "type": "SimpleMemory",
810 "port": {
811 "peer": "system.membus.master[8]",
812 "role": "SLAVE"
813 },
814 "in_addr_map": true
815 }
816 ],
817 "work_cpus_ckpt_count": 0,
818 "thermal_components": [],
819 "path": "system",
820 "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
821 "cpu_clk_domain": {
822 "name": "cpu_clk_domain",
823 "clock": [
824 2
--- 57 unchanged lines hidden (view full) ---
882 "cxx_class": "SparcISA::Interrupts"
883 }
884 ],
885 "dcache_port": {
886 "peer": "system.membus.slave[2]",
887 "role": "MASTER"
888 },
889 "socket_id": 0,
890 "max_insts_all_threads": 0,
891 "path": "system.cpu",
892 "max_loads_any_thread": 0,
893 "switched_out": false,
894 "workload": [],
895 "name": "cpu",
896 "dtb": {
897 "name": "dtb",
--- 58 unchanged lines hidden (view full) ---
956 "path": "system.disk0.image",
957 "image_file": "",
958 "type": "CowDiskImage",
959 "table_size": 65536
960 },
961 "cxx_class": "MmDisk",
962 "pio_latency": 200,
963 "clk_domain": "system.clk_domain",
964 "system": "system",
965 "eventq_index": 0,
966 "default_p_state": "UNDEFINED",
967 "p_state_clk_gate_max": 2000000000,
968 "path": "system.disk0",
969 "pio_addr": 134217728000,
970 "type": "MmDisk"
971 },
--- 17 unchanged lines hidden ---