1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
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--- 6 unchanged lines hidden (view full) ---
32 "725849473024:1095485095935",
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67 "system.t1000.fake_clk.pio",
68 "system.t1000.fake_membnks.pio",
69 "system.t1000.fake_l2_1.pio",
--- 8 unchanged lines hidden (view full) ---
78 "system.t1000.fake_jbi.pio",
79 "system.t1000.puart0.pio",
80 "system.t1000.hvuart.pio",
81 "system.disk0.pio"
82 ],
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84 },
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90 "frontend_latency": 2
91 },
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97 "role": "SLAVE"
98 },
99 "time": "Thu Jan 1 00:00:00 2009",
100 "pio_latency": 200,
101 "clk_domain": "system.clk_domain",
102 "system": "system",
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117 "system": "system",
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125 },
126 "fake_membnks": {
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149 },
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156 "pio": {
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176 "fake_l2esr_2": {
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212 },
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318 "type": "Terminal",
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320 },
321 "path": "system.t1000",
322 "iob": {
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327 },
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330 "system": "system",
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333 "cxx_class": "Iob",
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336 },
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342 },
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344 "clk_domain": "system.clk_domain",
345 "system": "system",
346 "terminal": "system.t1000.hterm",
347 "platform": "system.t1000",
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352 "type": "Uart8250"
353 },
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355 "fake_l2esr_3": {
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379 "fake_ssi": {
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384 "pio": {
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386 "role": "SLAVE"
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450 },
451 "fake_clk": {
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456 "pio": {
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472 "type": "IsaFake",
473 "ret_data16": 65535
474 }
475 },
476 "partition_desc_addr": 133445976064,
477 "symbolfile": "",
478 "readfile": "/z/stever/hg/gem5/tests/halt.sh",
479 "hypervisor_addr": 1099243257856,
480 "mem_ranges": [
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482 "2147483648:2415919103"
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486 "reset_bin": "/dist/m5/system/binaries/reset_new.bin",
487 "openboot_addr": 1099243716608,
488 "work_end_ckpt_count": 0,
489 "nvram_addr": 133429198848,
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492 "system.nvram",
493 "system.partition_desc",
494 "system.physmem0",
495 "system.physmem1",
496 "system.rom"
497 ],
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508 "cxx_class": "SimpleMemory",
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516 "in_addr_map": true
--- 10 unchanged lines hidden (view full) ---
527 "path": "system.clk_domain",
528 "type": "SrcClockDomain",
529 "domain_id": -1
530 },
531 "hypervisor_desc": {
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540 "cxx_class": "SimpleMemory",
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544 "port": {
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547 },
548 "in_addr_map": true
549 },
550 "membus": {
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553 "role": "MASTER"
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555 "slave": {
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558 "system.cpu.icache_port",
559 "system.cpu.dcache_port"
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561 "role": "SLAVE"
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567 "name": "badaddr_responder",
568 "warn_access": "",
569 "pio": {
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571 "role": "SLAVE"
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597 "system.t1000.htod.pio",
598 "system.bridge.slave",
599 "system.rom.port",
600 "system.nvram.port",
601 "system.hypervisor_desc.port",
602 "system.partition_desc.port",
603 "system.physmem0.port",
604 "system.physmem1.port"
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606 "role": "MASTER"
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608 "response_latency": 2,
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610 "path": "system.membus",
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614 "frontend_latency": 3
615 },
616 "nvram": {
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623 "bandwidth": "0.000000",
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625 "cxx_class": "SimpleMemory",
626 "path": "system.nvram",
627 "null": false,
628 "type": "SimpleMemory",
629 "port": {
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632 },
633 "in_addr_map": true
634 },
635 "eventq_index": 0,
636 "work_begin_cpu_id_exit": -1,
637 "dvfs_handler": {
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639 "name": "dvfs_handler",
640 "sys_clk_domain": "system.clk_domain",
641 "transition_latency": 200000,
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644 "domains": [],
645 "path": "system.dvfs_handler",
646 "type": "DVFSHandler"
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648 "work_end_exit_count": 0,
649 "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin",
650 "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin",
651 "voltage_domain": {
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653 "eventq_index": 0,
654 "voltage": [
655 "1.0"
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657 "cxx_class": "VoltageDomain",
658 "path": "system.voltage_domain",
--- 5 unchanged lines hidden (view full) ---
664 "peer": "system.membus.slave[0]",
665 "role": "MASTER"
666 },
667 "physmem": [
668 {
669 "range": "1048576:68157439",
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671 "name": "physmem0",
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673 "clk_domain": "system.clk_domain",
674 "latency_var": 0,
675 "bandwidth": "0.000000",
676 "conf_table_reported": true,
677 "cxx_class": "SimpleMemory",
678 "path": "system.physmem0",
679 "null": false,
680 "type": "SimpleMemory",
681 "port": {
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683 "role": "SLAVE"
684 },
685 "in_addr_map": true
686 },
687 {
688 "range": "2147483648:2415919103",
689 "latency": 60,
690 "name": "physmem1",
691 "eventq_index": 0,
692 "clk_domain": "system.clk_domain",
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694 "bandwidth": "0.000000",
695 "conf_table_reported": true,
696 "cxx_class": "SimpleMemory",
697 "path": "system.physmem1",
698 "null": false,
699 "type": "SimpleMemory",
700 "port": {
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702 "role": "SLAVE"
703 },
704 "in_addr_map": true
705 }
706 ],
707 "work_cpus_ckpt_count": 0,
708 "work_begin_exit_count": 0,
709 "path": "system",
710 "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin",
711 "cpu_clk_domain": {
712 "name": "cpu_clk_domain",
713 "clock": [
714 2
715 ],
716 "init_perf_level": 0,
717 "voltage_domain": "system.voltage_domain",
718 "eventq_index": 0,
719 "cxx_class": "SrcClockDomain",
720 "path": "system.cpu_clk_domain",
721 "type": "SrcClockDomain",
722 "domain_id": -1
723 },
724 "nvram_bin": "/dist/m5/system/binaries/nvram1",
725 "mem_mode": "atomic",
726 "name": "system",
727 "init_param": 0,
728 "type": "SparcSystem",
729 "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin",
730 "load_addr_mask": 1099511627775,
731 "cpu": {
732 "do_statistics_insts": true,
733 "numThreads": 1,
734 "itb": {
735 "name": "itb",
736 "eventq_index": 0,
737 "cxx_class": "SparcISA::TLB",
--- 8 unchanged lines hidden (view full) ---
746 "max_loads_all_threads": 0,
747 "system": "system",
748 "clk_domain": "system.cpu_clk_domain",
749 "function_trace_start": 0,
750 "cpu_id": 0,
751 "width": 1,
752 "checker": null,
753 "eventq_index": 0,
754 "do_quiesce": true,
755 "type": "AtomicSimpleCPU",
756 "fastmem": false,
757 "profile": 0,
758 "icache_port": {
759 "peer": "system.membus.slave[1]",
760 "role": "MASTER"
761 },
762 "interrupts": [
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766 "type": "SparcInterrupts",
767 "name": "interrupts",
768 "cxx_class": "SparcISA::Interrupts"
769 }
--- 44 unchanged lines hidden (view full) ---
814 "sys": "system",
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819 },
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833 "name": "child",
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837 "image_file": "/dist/m5/system/disks/disk.s10hw2",
838 "type": "RawDiskImage"
839 },
840 "path": "system.disk0.image",
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844 },
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846 "clk_domain": "system.clk_domain",
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849 "cxx_class": "MmDisk",
850 "path": "system.disk0",
851 "pio_addr": 134217728000,
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853 },
854 "multi_thread": false,
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858 "work_item_id": -1,
859 "exit_on_work_items": false
860 },
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862 "eventq_index": 0,
863 "time_sync_spin_threshold": 200000,
864 "cxx_class": "Root",
865 "path": "root",
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867 "type": "Root",
868 "full_system": true
869}
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "rom": {
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24 },
25 "in_addr_map": true
--- 6 unchanged lines hidden (view full) ---
32 "725849473024:1095485095935",
33 "1099255955456:1099255955463"
34 ],
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38 },
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47 },
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52 },
53 "iobus": {
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57 ],
58 "role": "SLAVE"
59 },
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62 "clk_domain": "system.clk_domain",
63 "width": 16,
64 "eventq_index": 0,
65 "master": {
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67 "system.t1000.fake_clk.pio",
68 "system.t1000.fake_membnks.pio",
69 "system.t1000.fake_l2_1.pio",
--- 8 unchanged lines hidden (view full) ---
78 "system.t1000.fake_jbi.pio",
79 "system.t1000.puart0.pio",
80 "system.t1000.hvuart.pio",
81 "system.disk0.pio"
82 ],
83 "role": "MASTER"
84 },
85 "response_latency": 2,
86 "cxx_class": "NoncoherentXBar",
87 "path": "system.iobus",
88 "type": "NoncoherentXBar",
89 "use_default_range": false,
90 "frontend_latency": 2
91 },
92 "t1000": {
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95 "pio": {
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97 "role": "SLAVE"
98 },
99 "time": "Thu Jan 1 00:00:00 2009",
100 "pio_latency": 200,
101 "clk_domain": "system.clk_domain",
102 "system": "system",
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107 "type": "DumbTOD"
108 },
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114 },
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117 "system": "system",
118 "terminal": "system.t1000.pterm",
119 "platform": "system.t1000",
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124 "type": "Uart8250"
125 },
126 "fake_membnks": {
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128 "ret_data8": 255,
129 "name": "fake_membnks",
130 "warn_access": "",
131 "pio": {
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149 },
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154 "name": "fake_jbi",
155 "warn_access": "",
156 "pio": {
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158 "role": "SLAVE"
159 },
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176 "fake_l2esr_2": {
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212 },
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285 },
286 "fake_l2_3": {
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290 "warn_access": "",
291 "pio": {
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309 },
310 "pterm": {
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312 "output": true,
313 "number": 0,
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317 "path": "system.t1000.pterm",
318 "type": "Terminal",
319 "port": 3456
320 },
321 "path": "system.t1000",
322 "iob": {
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324 "pio": {
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326 "role": "SLAVE"
327 },
328 "pio_latency": 2,
329 "clk_domain": "system.clk_domain",
330 "system": "system",
331 "platform": "system.t1000",
332 "eventq_index": 0,
333 "cxx_class": "Iob",
334 "path": "system.t1000.iob",
335 "type": "Iob"
336 },
337 "hvuart": {
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340 "peer": "system.iobus.master[13]",
341 "role": "SLAVE"
342 },
343 "pio_latency": 200,
344 "clk_domain": "system.clk_domain",
345 "system": "system",
346 "terminal": "system.t1000.hterm",
347 "platform": "system.t1000",
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349 "cxx_class": "Uart8250",
350 "path": "system.t1000.hvuart",
351 "pio_addr": 1099255955456,
352 "type": "Uart8250"
353 },
354 "name": "t1000",
355 "fake_l2esr_3": {
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358 "name": "fake_l2esr_3",
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360 "pio": {
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378 },
379 "fake_ssi": {
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382 "name": "fake_ssi",
383 "warn_access": "",
384 "pio": {
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386 "role": "SLAVE"
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403 "fake_l2esr_1": {
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427 "fake_l2esr_4": {
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430 "name": "fake_l2esr_4",
431 "warn_access": "",
432 "pio": {
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446 "path": "system.t1000.fake_l2esr_4",
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450 },
451 "fake_clk": {
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453 "ret_data8": 255,
454 "name": "fake_clk",
455 "warn_access": "",
456 "pio": {
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458 "role": "SLAVE"
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471 "pio_addr": 644245094400,
472 "type": "IsaFake",
473 "ret_data16": 65535
474 }
475 },
476 "partition_desc_addr": 133445976064,
477 "symbolfile": "",
478 "readfile": "/z/stever/hg/gem5/tests/halt.sh",
479 "hypervisor_addr": 1099243257856,
480 "mem_ranges": [
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482 "2147483648:2415919103"
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484 "cxx_class": "SparcSystem",
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486 "reset_bin": "/dist/m5/system/binaries/reset_new.bin",
487 "openboot_addr": 1099243716608,
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489 "nvram_addr": 133429198848,
490 "memories": [
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492 "system.nvram",
493 "system.partition_desc",
494 "system.physmem0",
495 "system.physmem1",
496 "system.rom"
497 ],
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508 "cxx_class": "SimpleMemory",
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510 "null": false,
511 "type": "SimpleMemory",
512 "port": {
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514 "role": "SLAVE"
515 },
516 "in_addr_map": true
--- 10 unchanged lines hidden (view full) ---
527 "path": "system.clk_domain",
528 "type": "SrcClockDomain",
529 "domain_id": -1
530 },
531 "hypervisor_desc": {
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534 "name": "hypervisor_desc",
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538 "bandwidth": "0.000000",
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540 "cxx_class": "SimpleMemory",
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543 "type": "SimpleMemory",
544 "port": {
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546 "role": "SLAVE"
547 },
548 "in_addr_map": true
549 },
550 "membus": {
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553 "role": "MASTER"
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555 "slave": {
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558 "system.cpu.icache_port",
559 "system.cpu.dcache_port"
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561 "role": "SLAVE"
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563 "name": "membus",
564 "badaddr_responder": {
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566 "ret_data8": 255,
567 "name": "badaddr_responder",
568 "warn_access": "",
569 "pio": {
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571 "role": "SLAVE"
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582 "cxx_class": "IsaFake",
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594 "master": {
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596 "system.t1000.iob.pio",
597 "system.t1000.htod.pio",
598 "system.bridge.slave",
599 "system.rom.port",
600 "system.nvram.port",
601 "system.hypervisor_desc.port",
602 "system.partition_desc.port",
603 "system.physmem0.port",
604 "system.physmem1.port"
605 ],
606 "role": "MASTER"
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608 "response_latency": 2,
609 "cxx_class": "CoherentXBar",
610 "path": "system.membus",
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614 "frontend_latency": 3
615 },
616 "nvram": {
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618 "latency": 60,
619 "name": "nvram",
620 "eventq_index": 0,
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622 "latency_var": 0,
623 "bandwidth": "0.000000",
624 "conf_table_reported": true,
625 "cxx_class": "SimpleMemory",
626 "path": "system.nvram",
627 "null": false,
628 "type": "SimpleMemory",
629 "port": {
630 "peer": "system.membus.master[4]",
631 "role": "SLAVE"
632 },
633 "in_addr_map": true
634 },
635 "eventq_index": 0,
636 "work_begin_cpu_id_exit": -1,
637 "dvfs_handler": {
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639 "name": "dvfs_handler",
640 "sys_clk_domain": "system.clk_domain",
641 "transition_latency": 200000,
642 "eventq_index": 0,
643 "cxx_class": "DVFSHandler",
644 "domains": [],
645 "path": "system.dvfs_handler",
646 "type": "DVFSHandler"
647 },
648 "work_end_exit_count": 0,
649 "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin",
650 "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin",
651 "voltage_domain": {
652 "name": "voltage_domain",
653 "eventq_index": 0,
654 "voltage": [
655 "1.0"
656 ],
657 "cxx_class": "VoltageDomain",
658 "path": "system.voltage_domain",
--- 5 unchanged lines hidden (view full) ---
664 "peer": "system.membus.slave[0]",
665 "role": "MASTER"
666 },
667 "physmem": [
668 {
669 "range": "1048576:68157439",
670 "latency": 60,
671 "name": "physmem0",
672 "eventq_index": 0,
673 "clk_domain": "system.clk_domain",
674 "latency_var": 0,
675 "bandwidth": "0.000000",
676 "conf_table_reported": true,
677 "cxx_class": "SimpleMemory",
678 "path": "system.physmem0",
679 "null": false,
680 "type": "SimpleMemory",
681 "port": {
682 "peer": "system.membus.master[7]",
683 "role": "SLAVE"
684 },
685 "in_addr_map": true
686 },
687 {
688 "range": "2147483648:2415919103",
689 "latency": 60,
690 "name": "physmem1",
691 "eventq_index": 0,
692 "clk_domain": "system.clk_domain",
693 "latency_var": 0,
694 "bandwidth": "0.000000",
695 "conf_table_reported": true,
696 "cxx_class": "SimpleMemory",
697 "path": "system.physmem1",
698 "null": false,
699 "type": "SimpleMemory",
700 "port": {
701 "peer": "system.membus.master[8]",
702 "role": "SLAVE"
703 },
704 "in_addr_map": true
705 }
706 ],
707 "work_cpus_ckpt_count": 0,
708 "work_begin_exit_count": 0,
709 "path": "system",
710 "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin",
711 "cpu_clk_domain": {
712 "name": "cpu_clk_domain",
713 "clock": [
714 2
715 ],
716 "init_perf_level": 0,
717 "voltage_domain": "system.voltage_domain",
718 "eventq_index": 0,
719 "cxx_class": "SrcClockDomain",
720 "path": "system.cpu_clk_domain",
721 "type": "SrcClockDomain",
722 "domain_id": -1
723 },
724 "nvram_bin": "/dist/m5/system/binaries/nvram1",
725 "mem_mode": "atomic",
726 "name": "system",
727 "init_param": 0,
728 "type": "SparcSystem",
729 "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin",
730 "load_addr_mask": 1099511627775,
731 "cpu": {
732 "do_statistics_insts": true,
733 "numThreads": 1,
734 "itb": {
735 "name": "itb",
736 "eventq_index": 0,
737 "cxx_class": "SparcISA::TLB",
--- 8 unchanged lines hidden (view full) ---
746 "max_loads_all_threads": 0,
747 "system": "system",
748 "clk_domain": "system.cpu_clk_domain",
749 "function_trace_start": 0,
750 "cpu_id": 0,
751 "width": 1,
752 "checker": null,
753 "eventq_index": 0,
754 "do_quiesce": true,
755 "type": "AtomicSimpleCPU",
756 "fastmem": false,
757 "profile": 0,
758 "icache_port": {
759 "peer": "system.membus.slave[1]",
760 "role": "MASTER"
761 },
762 "interrupts": [
763 {
764 "eventq_index": 0,
765 "path": "system.cpu.interrupts",
766 "type": "SparcInterrupts",
767 "name": "interrupts",
768 "cxx_class": "SparcISA::Interrupts"
769 }
--- 44 unchanged lines hidden (view full) ---
814 "sys": "system",
815 "eventq_index": 0,
816 "cxx_class": "IntrControl",
817 "path": "system.intrctrl",
818 "type": "IntrControl"
819 },
820 "disk0": {
821 "name": "disk0",
822 "pio": {
823 "peer": "system.iobus.master[14]",
824 "role": "SLAVE"
825 },
826 "image": {
827 "read_only": false,
828 "name": "image",
829 "cxx_class": "CowDiskImage",
830 "eventq_index": 0,
831 "child": {
832 "read_only": true,
833 "name": "child",
834 "eventq_index": 0,
835 "cxx_class": "RawDiskImage",
836 "path": "system.disk0.image.child",
837 "image_file": "/dist/m5/system/disks/disk.s10hw2",
838 "type": "RawDiskImage"
839 },
840 "path": "system.disk0.image",
841 "image_file": "",
842 "type": "CowDiskImage",
843 "table_size": 65536
844 },
845 "pio_latency": 200,
846 "clk_domain": "system.clk_domain",
847 "system": "system",
848 "eventq_index": 0,
849 "cxx_class": "MmDisk",
850 "path": "system.disk0",
851 "pio_addr": 134217728000,
852 "type": "MmDisk"
853 },
854 "multi_thread": false,
855 "reset_addr": 1099243192320,
856 "hypervisor_desc_addr": 133446500352,
857 "num_work_ids": 16,
858 "work_item_id": -1,
859 "exit_on_work_items": false
860 },
861 "time_sync_period": 200000000,
862 "eventq_index": 0,
863 "time_sync_spin_threshold": 200000,
864 "cxx_class": "Root",
865 "path": "root",
866 "time_sync_enable": false,
867 "type": "Root",
868 "full_system": true
869}