| stats.txt (9978:81d7551dd3be) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.133932 # Number of seconds simulated 4sim_ticks 5133932129000 # Number of ticks simulated 5final_tick 5133932129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.133933 # Number of seconds simulated 4sim_ticks 5133933067000 # Number of ticks simulated 5final_tick 5133933067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 157497 # Simulator instruction rate (inst/s) 8host_op_rate 311329 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1982921852 # Simulator tick rate (ticks/s) 10host_mem_usage 759792 # Number of bytes of host memory used 11host_seconds 2589.07 # Real time elapsed on the host 12sim_insts 407772261 # Number of instructions simulated 13sim_ops 806052921 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2442496 # Number of bytes read from this memory | 7host_inst_rate 121984 # Simulator instruction rate (inst/s) 8host_op_rate 241126 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1535878817 # Simulator tick rate (ticks/s) 10host_mem_usage 781700 # Number of bytes of host memory used 11host_seconds 3342.67 # Real time elapsed on the host 12sim_insts 407751929 # Number of instructions simulated 13sim_ops 806002693 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2437184 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 1029568 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10759232 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14235520 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1029568 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1029568 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9509568 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9509568 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38164 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 1029376 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10746496 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14217280 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1029376 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1029376 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9492672 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9492672 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38081 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 25system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.inst 16087 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 168113 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 222430 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 148587 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 148587 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 475755 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::cpu.inst 16084 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 167914 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 222145 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 148323 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 148323 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 474721 # Total read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.inst 200542 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2095710 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2772830 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 200542 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 200542 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1852297 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1852297 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1852297 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 475755 # Total bandwidth to/from this memory (bytes/s) | 35system.physmem.bw_read::cpu.inst 200504 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2093229 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2769276 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 200504 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 200504 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1849006 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1849006 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1849006 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 474721 # Total bandwidth to/from this memory (bytes/s) |
| 44system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) | 44system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.inst 200542 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2095710 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4625127 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 222430 # Number of read requests accepted 50system.physmem.writeReqs 148587 # Number of write requests accepted 51system.physmem.readBursts 222430 # Number of DRAM read bursts, including those serviced by the write queue 52system.physmem.writeBursts 148587 # Number of DRAM write bursts, including those merged in the write queue 53system.physmem.bytesReadDRAM 14231616 # Total number of bytes read from DRAM 54system.physmem.bytesReadWrQ 3904 # Total number of bytes read from write queue 55system.physmem.bytesWritten 9508480 # Total number of bytes written to DRAM 56system.physmem.bytesReadSys 14235520 # Total read bytes from the system interface side 57system.physmem.bytesWrittenSys 9509568 # Total written bytes from the system interface side 58system.physmem.servicedByWrQ 61 # Number of DRAM read bursts serviced by the write queue | 46system.physmem.bw_total::cpu.inst 200504 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2093229 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4618282 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 222145 # Number of read requests accepted 50system.physmem.writeReqs 148323 # Number of write requests accepted 51system.physmem.readBursts 222145 # Number of DRAM read bursts, including those serviced by the write queue 52system.physmem.writeBursts 148323 # Number of DRAM write bursts, including those merged in the write queue 53system.physmem.bytesReadDRAM 14211648 # Total number of bytes read from DRAM 54system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue 55system.physmem.bytesWritten 9492416 # Total number of bytes written to DRAM 56system.physmem.bytesReadSys 14217280 # Total read bytes from the system interface side 57system.physmem.bytesWrittenSys 9492672 # Total written bytes from the system interface side 58system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue |
| 59system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 59system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 60system.physmem.neitherReadNorWriteReqs 1723 # Number of requests that are neither read nor write 61system.physmem.perBankRdBursts::0 14853 # Per bank write bursts 62system.physmem.perBankRdBursts::1 13635 # Per bank write bursts 63system.physmem.perBankRdBursts::2 14415 # Per bank write bursts 64system.physmem.perBankRdBursts::3 13770 # Per bank write bursts 65system.physmem.perBankRdBursts::4 14136 # Per bank write bursts 66system.physmem.perBankRdBursts::5 13341 # Per bank write bursts 67system.physmem.perBankRdBursts::6 13755 # Per bank write bursts 68system.physmem.perBankRdBursts::7 13953 # Per bank write bursts 69system.physmem.perBankRdBursts::8 13590 # Per bank write bursts 70system.physmem.perBankRdBursts::9 13369 # Per bank write bursts 71system.physmem.perBankRdBursts::10 13469 # Per bank write bursts 72system.physmem.perBankRdBursts::11 13962 # Per bank write bursts 73system.physmem.perBankRdBursts::12 14252 # Per bank write bursts 74system.physmem.perBankRdBursts::13 14454 # Per bank write bursts 75system.physmem.perBankRdBursts::14 13844 # Per bank write bursts 76system.physmem.perBankRdBursts::15 13571 # Per bank write bursts 77system.physmem.perBankWrBursts::0 10225 # Per bank write bursts 78system.physmem.perBankWrBursts::1 9089 # Per bank write bursts 79system.physmem.perBankWrBursts::2 9605 # Per bank write bursts | 60system.physmem.neitherReadNorWriteReqs 1715 # Number of requests that are neither read nor write 61system.physmem.perBankRdBursts::0 14970 # Per bank write bursts 62system.physmem.perBankRdBursts::1 13960 # Per bank write bursts 63system.physmem.perBankRdBursts::2 14769 # Per bank write bursts 64system.physmem.perBankRdBursts::3 13764 # Per bank write bursts 65system.physmem.perBankRdBursts::4 13644 # Per bank write bursts 66system.physmem.perBankRdBursts::5 13392 # Per bank write bursts 67system.physmem.perBankRdBursts::6 13407 # Per bank write bursts 68system.physmem.perBankRdBursts::7 13589 # Per bank write bursts 69system.physmem.perBankRdBursts::8 13408 # Per bank write bursts 70system.physmem.perBankRdBursts::9 13258 # Per bank write bursts 71system.physmem.perBankRdBursts::10 13821 # Per bank write bursts 72system.physmem.perBankRdBursts::11 13878 # Per bank write bursts 73system.physmem.perBankRdBursts::12 14332 # Per bank write bursts 74system.physmem.perBankRdBursts::13 14527 # Per bank write bursts 75system.physmem.perBankRdBursts::14 13749 # Per bank write bursts 76system.physmem.perBankRdBursts::15 13589 # Per bank write bursts 77system.physmem.perBankWrBursts::0 10370 # Per bank write bursts 78system.physmem.perBankWrBursts::1 9405 # Per bank write bursts 79system.physmem.perBankWrBursts::2 9871 # Per bank write bursts |
| 80system.physmem.perBankWrBursts::3 9165 # Per bank write bursts | 80system.physmem.perBankWrBursts::3 9165 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::4 9475 # Per bank write bursts 82system.physmem.perBankWrBursts::5 8866 # Per bank write bursts 83system.physmem.perBankWrBursts::6 9032 # Per bank write bursts 84system.physmem.perBankWrBursts::7 9363 # Per bank write bursts 85system.physmem.perBankWrBursts::8 8843 # Per bank write bursts 86system.physmem.perBankWrBursts::9 8764 # Per bank write bursts 87system.physmem.perBankWrBursts::10 9099 # Per bank write bursts 88system.physmem.perBankWrBursts::11 9352 # Per bank write bursts 89system.physmem.perBankWrBursts::12 9596 # Per bank write bursts 90system.physmem.perBankWrBursts::13 9639 # Per bank write bursts 91system.physmem.perBankWrBursts::14 9447 # Per bank write bursts 92system.physmem.perBankWrBursts::15 9010 # Per bank write bursts | 81system.physmem.perBankWrBursts::4 9017 # Per bank write bursts 82system.physmem.perBankWrBursts::5 8953 # Per bank write bursts 83system.physmem.perBankWrBursts::6 8740 # Per bank write bursts 84system.physmem.perBankWrBursts::7 8992 # Per bank write bursts 85system.physmem.perBankWrBursts::8 8721 # Per bank write bursts 86system.physmem.perBankWrBursts::9 8568 # Per bank write bursts 87system.physmem.perBankWrBursts::10 9309 # Per bank write bursts 88system.physmem.perBankWrBursts::11 9216 # Per bank write bursts 89system.physmem.perBankWrBursts::12 9686 # Per bank write bursts 90system.physmem.perBankWrBursts::13 9800 # Per bank write bursts 91system.physmem.perBankWrBursts::14 9415 # Per bank write bursts 92system.physmem.perBankWrBursts::15 9091 # Per bank write bursts |
| 93system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 93system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 94system.physmem.numWrRetry 11 # Number of times write queue was full causing retry 95system.physmem.totGap 5133932076000 # Total gap between requests | 94system.physmem.numWrRetry 8 # Number of times write queue was full causing retry 95system.physmem.totGap 5133933013500 # Total gap between requests |
| 96system.physmem.readPktSize::0 0 # Read request sizes (log2) 97system.physmem.readPktSize::1 0 # Read request sizes (log2) 98system.physmem.readPktSize::2 0 # Read request sizes (log2) 99system.physmem.readPktSize::3 0 # Read request sizes (log2) 100system.physmem.readPktSize::4 0 # Read request sizes (log2) 101system.physmem.readPktSize::5 0 # Read request sizes (log2) | 96system.physmem.readPktSize::0 0 # Read request sizes (log2) 97system.physmem.readPktSize::1 0 # Read request sizes (log2) 98system.physmem.readPktSize::2 0 # Read request sizes (log2) 99system.physmem.readPktSize::3 0 # Read request sizes (log2) 100system.physmem.readPktSize::4 0 # Read request sizes (log2) 101system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 102system.physmem.readPktSize::6 222430 # Read request sizes (log2) | 102system.physmem.readPktSize::6 222145 # Read request sizes (log2) |
| 103system.physmem.writePktSize::0 0 # Write request sizes (log2) 104system.physmem.writePktSize::1 0 # Write request sizes (log2) 105system.physmem.writePktSize::2 0 # Write request sizes (log2) 106system.physmem.writePktSize::3 0 # Write request sizes (log2) 107system.physmem.writePktSize::4 0 # Write request sizes (log2) 108system.physmem.writePktSize::5 0 # Write request sizes (log2) | 103system.physmem.writePktSize::0 0 # Write request sizes (log2) 104system.physmem.writePktSize::1 0 # Write request sizes (log2) 105system.physmem.writePktSize::2 0 # Write request sizes (log2) 106system.physmem.writePktSize::3 0 # Write request sizes (log2) 107system.physmem.writePktSize::4 0 # Write request sizes (log2) 108system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 109system.physmem.writePktSize::6 148587 # Write request sizes (log2) 110system.physmem.rdQLenPdf::0 174915 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 21440 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 6913 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 2946 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2118 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2079 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 1523 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 1580 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 1438 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 1083 # What read queue length does an incoming req see | 109system.physmem.writePktSize::6 148323 # Write request sizes (log2) 110system.physmem.rdQLenPdf::0 174666 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 21456 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 6950 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 2913 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2112 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2066 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 1506 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 1430 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 1072 # What read queue length does an incoming req see |
| 120system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see | 120system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see |
| 121system.physmem.rdQLenPdf::11 749 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 638 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 608 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 585 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 567 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 550 # What read queue length does an incoming req see | 121system.physmem.rdQLenPdf::11 755 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 678 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 656 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 606 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 583 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 571 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 555 # What read queue length does an incoming req see |
| 128system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see | 128system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see |
| 129system.physmem.rdQLenPdf::19 516 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see | 129system.physmem.rdQLenPdf::19 523 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see |
| 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 142system.physmem.wrQLenPdf::0 6034 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 6271 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 6300 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 6343 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 6454 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 6600 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 6598 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 6691 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 7044 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 7025 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 7044 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 7124 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 7641 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 7124 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 7239 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 7407 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 7483 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 6336 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 6266 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 6185 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 6164 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 6231 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 369 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 293 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 75 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 31 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 26 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see 174system.physmem.bytesPerActivate::samples 69161 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::mean 343.214933 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::gmean 150.395098 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::stdev 1078.627974 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::64-67 31181 45.08% 45.08% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::128-131 10634 15.38% 60.46% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::192-195 6892 9.97% 70.43% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::256-259 4363 6.31% 76.73% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::320-323 2774 4.01% 80.74% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::384-387 2145 3.10% 83.85% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::448-451 1632 2.36% 86.21% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::512-515 1184 1.71% 87.92% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::576-579 1083 1.57% 89.48% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::640-643 997 1.44% 90.93% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::704-707 641 0.93% 91.85% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::768-771 593 0.86% 92.71% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::832-835 458 0.66% 93.37% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::896-899 430 0.62% 93.99% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::960-963 348 0.50% 94.50% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1024-1027 543 0.79% 95.28% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1088-1091 251 0.36% 95.64% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1152-1155 231 0.33% 95.98% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1216-1219 148 0.21% 96.19% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1280-1283 131 0.19% 96.38% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1344-1347 159 0.23% 96.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1408-1411 414 0.60% 97.21% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1472-1475 146 0.21% 97.42% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1536-1539 132 0.19% 97.61% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1600-1603 102 0.15% 97.76% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1664-1667 88 0.13% 97.89% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.97% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1792-1795 56 0.08% 98.05% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1856-1859 31 0.04% 98.10% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1920-1923 34 0.05% 98.15% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1984-1987 24 0.03% 98.18% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2048-2051 33 0.05% 98.23% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.26% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2176-2179 49 0.07% 98.33% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2240-2243 19 0.03% 98.36% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.38% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2368-2371 10 0.01% 98.39% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2432-2435 32 0.05% 98.44% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.45% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2560-2563 7 0.01% 98.46% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.47% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2688-2691 29 0.04% 98.52% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.53% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2816-2819 12 0.02% 98.55% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2944-2947 32 0.05% 98.60% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3008-3011 7 0.01% 98.61% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3072-3075 13 0.02% 98.63% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3136-3139 8 0.01% 98.64% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3200-3203 25 0.04% 98.68% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3264-3267 5 0.01% 98.69% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.69% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3392-3395 4 0.01% 98.70% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3456-3459 26 0.04% 98.74% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3520-3523 2 0.00% 98.74% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3584-3587 7 0.01% 98.75% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.76% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3712-3715 31 0.04% 98.80% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3776-3779 9 0.01% 98.82% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.82% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3904-3907 7 0.01% 98.83% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.87% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.88% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4096-4099 17 0.02% 98.90% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4160-4163 2 0.00% 98.91% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4224-4227 24 0.03% 98.94% # Bytes accessed per row activation | 142system.physmem.wrQLenPdf::0 6022 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 6256 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 6299 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 6341 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 6448 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 6596 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 6608 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 6666 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 6998 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 7022 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 7020 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 7083 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 7644 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 7121 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 7236 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 7399 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 7458 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 6317 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 6247 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 6188 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 6157 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 6233 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 386 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 282 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 69 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 36 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see 174system.physmem.bytesPerActivate::samples 68754 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::mean 344.735608 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::gmean 150.882581 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::stdev 1084.800437 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::64-67 30893 44.93% 44.93% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::128-131 10573 15.38% 60.31% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::192-195 6859 9.98% 70.29% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::256-259 4406 6.41% 76.70% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::320-323 2663 3.87% 80.57% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::384-387 2166 3.15% 83.72% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::448-451 1652 2.40% 86.12% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::512-515 1226 1.78% 87.90% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::576-579 1018 1.48% 89.39% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::640-643 978 1.42% 90.81% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::704-707 656 0.95% 91.76% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::768-771 637 0.93% 92.69% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::832-835 446 0.65% 93.34% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::896-899 438 0.64% 93.97% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::960-963 344 0.50% 94.47% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1024-1027 542 0.79% 95.26% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1088-1091 252 0.37% 95.63% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1152-1155 218 0.32% 95.95% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1216-1219 163 0.24% 96.18% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1280-1283 136 0.20% 96.38% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1344-1347 158 0.23% 96.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1408-1411 420 0.61% 97.22% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1472-1475 150 0.22% 97.44% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1536-1539 127 0.18% 97.62% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1600-1603 107 0.16% 97.78% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1664-1667 87 0.13% 97.91% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.99% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1792-1795 64 0.09% 98.09% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1856-1859 17 0.02% 98.11% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1920-1923 43 0.06% 98.17% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1984-1987 19 0.03% 98.20% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2048-2051 31 0.05% 98.25% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.28% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2176-2179 40 0.06% 98.33% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2240-2243 10 0.01% 98.35% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.37% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2368-2371 16 0.02% 98.39% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2432-2435 31 0.05% 98.44% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2496-2499 10 0.01% 98.45% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2560-2563 6 0.01% 98.46% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2624-2627 13 0.02% 98.48% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2688-2691 31 0.05% 98.52% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.54% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2816-2819 4 0.01% 98.55% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2880-2883 6 0.01% 98.55% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2944-2947 27 0.04% 98.59% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3008-3011 9 0.01% 98.61% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3072-3075 12 0.02% 98.62% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.63% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3200-3203 28 0.04% 98.67% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.68% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3328-3331 7 0.01% 98.69% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.70% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3456-3459 25 0.04% 98.73% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.74% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.74% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.75% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3712-3715 26 0.04% 98.79% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3776-3779 10 0.01% 98.80% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3840-3843 5 0.01% 98.81% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3904-3907 9 0.01% 98.82% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.86% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4032-4035 4 0.01% 98.87% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4096-4099 15 0.02% 98.89% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4160-4163 3 0.00% 98.90% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4224-4227 27 0.04% 98.94% # Bytes accessed per row activation |
| 244system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation | 244system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation |
| 245system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.95% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4416-4419 1 0.00% 98.95% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4480-4483 22 0.03% 98.98% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.98% # Bytes accessed per row activation | 245system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.94% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.95% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4480-4483 23 0.03% 98.98% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.98% # Bytes accessed per row activation |
| 249system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation | 249system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation |
| 250system.physmem.bytesPerActivate::4672-4675 3 0.00% 98.99% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4736-4739 28 0.04% 99.03% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4800-4803 2 0.00% 99.03% # Bytes accessed per row activation | 250system.physmem.bytesPerActivate::4672-4675 5 0.01% 98.99% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4736-4739 25 0.04% 99.03% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4800-4803 4 0.01% 99.04% # Bytes accessed per row activation |
| 253system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation | 253system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation |
| 254system.physmem.bytesPerActivate::4928-4931 2 0.00% 99.04% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4992-4995 23 0.03% 99.07% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5056-5059 3 0.00% 99.08% # Bytes accessed per row activation | 254system.physmem.bytesPerActivate::4992-4995 22 0.03% 99.07% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5056-5059 2 0.00% 99.07% # Bytes accessed per row activation |
| 257system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation | 256system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation |
| 258system.physmem.bytesPerActivate::5184-5187 3 0.00% 99.08% # Bytes accessed per row activation | 257system.physmem.bytesPerActivate::5184-5187 4 0.01% 99.08% # Bytes accessed per row activation |
| 259system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation | 258system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation |
| 261system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.13% # Bytes accessed per row activation | 260system.physmem.bytesPerActivate::5440-5443 2 0.00% 99.12% # Bytes accessed per row activation |
| 262system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation | 261system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation |
| 263system.physmem.bytesPerActivate::5568-5571 5 0.01% 99.16% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5632-5635 4 0.01% 99.17% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5696-5699 2 0.00% 99.17% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5760-5763 26 0.04% 99.21% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5824-5827 3 0.00% 99.21% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.22% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.22% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6016-6019 25 0.04% 99.25% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6080-6083 6 0.01% 99.26% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6144-6147 3 0.00% 99.27% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6208-6211 5 0.01% 99.27% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6272-6275 25 0.04% 99.31% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6336-6339 2 0.00% 99.31% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6400-6403 3 0.00% 99.32% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.32% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6528-6531 26 0.04% 99.36% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6592-6595 3 0.00% 99.36% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::6656-6659 76 0.11% 99.47% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.48% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.48% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::6848-6851 6 0.01% 99.49% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.49% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.49% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7040-7043 6 0.01% 99.50% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7104-7107 6 0.01% 99.51% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.52% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7232-7235 3 0.00% 99.53% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.53% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7424-7427 2 0.00% 99.53% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.53% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.54% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::7744-7747 3 0.00% 99.54% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.54% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.55% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.55% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::8000-8003 2 0.00% 99.56% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.56% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.56% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::8192-8195 14 0.02% 99.58% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.58% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.58% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.59% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.59% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.59% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8576-8579 3 0.00% 99.59% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.59% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.60% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.60% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::9152-9155 3 0.00% 99.60% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.61% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.61% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.62% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.62% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.62% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::9792-9795 3 0.00% 99.63% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::9856-9859 4 0.01% 99.63% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.63% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::10112-10115 2 0.00% 99.64% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.64% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.64% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.64% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.64% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.65% # Bytes accessed per row activation | 262system.physmem.bytesPerActivate::5568-5571 4 0.01% 99.16% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5696-5699 3 0.00% 99.17% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5760-5763 24 0.03% 99.20% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5824-5827 4 0.01% 99.21% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.21% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.21% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6016-6019 24 0.03% 99.25% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.25% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.25% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6208-6211 3 0.00% 99.25% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6272-6275 24 0.03% 99.29% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6336-6339 3 0.00% 99.29% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6400-6403 4 0.01% 99.30% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.30% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6528-6531 23 0.03% 99.33% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.34% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6656-6659 75 0.11% 99.45% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6720-6723 3 0.00% 99.45% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::6784-6787 2 0.00% 99.45% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.46% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::6912-6915 5 0.01% 99.47% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::6976-6979 3 0.00% 99.47% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7040-7043 9 0.01% 99.49% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7104-7107 2 0.00% 99.49% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.51% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7232-7235 2 0.00% 99.51% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.51% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7488-7491 2 0.00% 99.51% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7552-7555 2 0.00% 99.52% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.52% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7680-7683 1 0.00% 99.52% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7744-7747 2 0.00% 99.52% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::7808-7811 3 0.00% 99.53% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.53% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7936-7939 3 0.00% 99.54% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.54% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::8064-8067 5 0.01% 99.55% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::8128-8131 3 0.00% 99.55% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::8192-8195 15 0.02% 99.57% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.57% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.58% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.58% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8512-8515 5 0.01% 99.58% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8640-8643 2 0.00% 99.59% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.59% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.59% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.59% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.60% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.60% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::9152-9155 4 0.01% 99.60% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.61% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.61% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.61% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::9536-9539 4 0.01% 99.62% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::9600-9603 4 0.01% 99.62% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.63% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.63% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.63% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.64% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.64% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::10112-10115 3 0.00% 99.65% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.65% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.65% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.65% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.65% # Bytes accessed per row activation |
| 326system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation | 328system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation |
| 327system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.65% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.65% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.65% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.66% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.66% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.66% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.66% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.67% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.67% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::11968-11971 3 0.00% 99.67% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.68% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::12096-12099 4 0.01% 99.68% # Bytes accessed per row activation | 329system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.66% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.66% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::11136-11139 1 0.00% 99.66% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.66% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.66% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.66% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::11392-11395 3 0.00% 99.67% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::11520-11523 3 0.00% 99.67% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.68% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.68% # Bytes accessed per row activation |
| 339system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation | 339system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation |
| 340system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.69% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.69% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.69% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.69% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::12608-12611 2 0.00% 99.69% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.70% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.70% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.70% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.71% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.71% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.71% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.71% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.71% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.72% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.72% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::13440-13443 2 0.00% 99.72% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.72% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.72% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.73% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::13952-13955 2 0.00% 99.74% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.74% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::14272-14275 5 0.01% 99.75% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.75% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::14592-14595 5 0.01% 99.76% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.76% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.77% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.77% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::14912-14915 20 0.03% 99.80% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.81% # Bytes accessed per row activation | 340system.physmem.bytesPerActivate::12224-12227 2 0.00% 99.68% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.69% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.69% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::12672-12675 3 0.00% 99.69% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.69% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.70% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.70% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.70% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.70% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.70% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.71% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::13696-13699 3 0.00% 99.71% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.71% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.72% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::13952-13955 5 0.01% 99.73% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.73% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.73% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.74% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::14272-14275 4 0.01% 99.74% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.74% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.75% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.75% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.75% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.76% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.76% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.76% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::14912-14915 25 0.04% 99.79% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::14976-14979 6 0.01% 99.80% # Bytes accessed per row activation |
| 371system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation | 369system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation |
| 372system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.83% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.84% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.84% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::15296-15299 4 0.01% 99.85% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.87% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.87% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.87% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.88% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.88% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.89% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.89% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::15808-15811 5 0.01% 99.90% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.90% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.90% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.91% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.91% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::16128-16131 2 0.00% 99.91% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::16192-16195 4 0.01% 99.92% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::16256-16259 9 0.01% 99.93% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::16320-16323 5 0.01% 99.94% # Bytes accessed per row activation | 370system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.82% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::15168-15171 3 0.00% 99.83% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::15232-15235 8 0.01% 99.84% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::15296-15299 3 0.00% 99.84% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.86% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.86% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.86% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.87% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.87% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.88% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.88% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::15808-15811 4 0.01% 99.89% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.89% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.90% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.90% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::16064-16067 3 0.00% 99.90% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::16128-16131 4 0.01% 99.91% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::16192-16195 2 0.00% 99.91% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::16256-16259 10 0.01% 99.93% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::16320-16323 9 0.01% 99.94% # Bytes accessed per row activation |
| 392system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation | 390system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation |
| 393system.physmem.bytesPerActivate::total 69161 # Bytes accessed per row activation 394system.physmem.totQLat 5163279754 # Total ticks spent queuing 395system.physmem.totMemAccLat 9388468504 # Total ticks spent from burst creation until serviced by the DRAM 396system.physmem.totBusLat 1111845000 # Total ticks spent in databus transfers 397system.physmem.totBankLat 3113343750 # Total ticks spent accessing banks 398system.physmem.avgQLat 23219.42 # Average queueing delay per DRAM burst 399system.physmem.avgBankLat 14000.80 # Average bank access latency per DRAM burst | 391system.physmem.bytesPerActivate::total 68754 # Bytes accessed per row activation 392system.physmem.totQLat 5103462500 # Total ticks spent queuing 393system.physmem.totMemAccLat 9310522500 # Total ticks spent from burst creation until serviced by the DRAM 394system.physmem.totBusLat 1110285000 # Total ticks spent in databus transfers 395system.physmem.totBankLat 3096775000 # Total ticks spent accessing banks 396system.physmem.avgQLat 22982.67 # Average queueing delay per DRAM burst 397system.physmem.avgBankLat 13945.86 # Average bank access latency per DRAM burst |
| 400system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 398system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 401system.physmem.avgMemAccLat 42220.22 # Average memory access latency per DRAM burst | 399system.physmem.avgMemAccLat 41928.53 # Average memory access latency per DRAM burst |
| 402system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s 403system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s 404system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s 405system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s 406system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 407system.physmem.busUtil 0.04 # Data bus utilization in percentage 408system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 409system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 410system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing | 400system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s 401system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s 402system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s 403system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s 404system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 405system.physmem.busUtil 0.04 # Data bus utilization in percentage 406system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 407system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 408system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing |
| 411system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing 412system.physmem.readRowHits 193089 # Number of row buffer hits during reads 413system.physmem.writeRowHits 108689 # Number of row buffer hits during writes 414system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads 415system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes 416system.physmem.avgGap 13837457.79 # Average gap between requests 417system.physmem.pageHitRate 81.35 # Row buffer hit rate, read and write combined | 409system.physmem.avgWrQLen 8.57 # Average write queue length when enqueuing 410system.physmem.readRowHits 193293 # Number of row buffer hits during reads 411system.physmem.writeRowHits 108329 # Number of row buffer hits during writes 412system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads 413system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes 414system.physmem.avgGap 13857966.18 # Average gap between requests 415system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined |
| 418system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state | 416system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state |
| 419system.membus.throughput 5101771 # Throughput (bytes/s) 420system.membus.trans_dist::ReadReq 662370 # Transaction distribution 421system.membus.trans_dist::ReadResp 662362 # Transaction distribution 422system.membus.trans_dist::WriteReq 13778 # Transaction distribution 423system.membus.trans_dist::WriteResp 13778 # Transaction distribution 424system.membus.trans_dist::Writeback 148587 # Transaction distribution 425system.membus.trans_dist::UpgradeReq 2227 # Transaction distribution 426system.membus.trans_dist::UpgradeResp 1742 # Transaction distribution 427system.membus.trans_dist::ReadExReq 179504 # Transaction distribution 428system.membus.trans_dist::ReadExResp 179502 # Transaction distribution 429system.membus.trans_dist::MessageReq 1643 # Transaction distribution 430system.membus.trans_dist::MessageResp 1643 # Transaction distribution 431system.membus.trans_dist::BadAddressError 8 # Transaction distribution 432system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) 433system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) 434system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) 435system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes) 436system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475070 # Packet count per connected master and slave (bytes) 437system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) 438system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721244 # Packet count per connected master and slave (bytes) 439system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132462 # Packet count per connected master and slave (bytes) 440system.membus.pkt_count_system.iocache.mem_side::total 132462 # Packet count per connected master and slave (bytes) 441system.membus.pkt_count::total 1856992 # Packet count per connected master and slave (bytes) 442system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) 443system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) 444system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) 445system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes) 446system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18315904 # Cumulative packet size per connected master and slave (bytes) 447system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20107877 # Cumulative packet size per connected master and slave (bytes) 448system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5429184 # Cumulative packet size per connected master and slave (bytes) 449system.membus.tot_pkt_size_system.iocache.mem_side::total 5429184 # Cumulative packet size per connected master and slave (bytes) 450system.membus.tot_pkt_size::total 25543633 # Cumulative packet size per connected master and slave (bytes) 451system.membus.data_through_bus 25543633 # Total data (bytes) 452system.membus.snoop_data_through_bus 648512 # Total snoop data (bytes) 453system.membus.reqLayer0.occupancy 250559500 # Layer occupancy (ticks) | 417system.membus.throughput 5095991 # Throughput (bytes/s) 418system.membus.trans_dist::ReadReq 662317 # Transaction distribution 419system.membus.trans_dist::ReadResp 662311 # Transaction distribution 420system.membus.trans_dist::WriteReq 13762 # Transaction distribution 421system.membus.trans_dist::WriteResp 13762 # Transaction distribution 422system.membus.trans_dist::Writeback 148323 # Transaction distribution 423system.membus.trans_dist::UpgradeReq 2201 # Transaction distribution 424system.membus.trans_dist::UpgradeResp 1734 # Transaction distribution 425system.membus.trans_dist::ReadExReq 179351 # Transaction distribution 426system.membus.trans_dist::ReadExResp 179346 # Transaction distribution 427system.membus.trans_dist::MessageReq 1642 # Transaction distribution 428system.membus.trans_dist::MessageResp 1642 # Transaction distribution 429system.membus.trans_dist::BadAddressError 6 # Transaction distribution 430system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) 431system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) 432system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) 433system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) 434system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 474374 # Packet count per connected master and slave (bytes) 435system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) 436system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720496 # Packet count per connected master and slave (bytes) 437system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132379 # Packet count per connected master and slave (bytes) 438system.membus.pkt_count_system.iocache.mem_side::total 132379 # Packet count per connected master and slave (bytes) 439system.membus.pkt_count::total 1856159 # Packet count per connected master and slave (bytes) 440system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) 441system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) 442system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) 443system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) 444system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18286080 # Cumulative packet size per connected master and slave (bytes) 445system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20078023 # Cumulative packet size per connected master and slave (bytes) 446system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5423872 # Cumulative packet size per connected master and slave (bytes) 447system.membus.tot_pkt_size_system.iocache.mem_side::total 5423872 # Cumulative packet size per connected master and slave (bytes) 448system.membus.tot_pkt_size::total 25508463 # Cumulative packet size per connected master and slave (bytes) 449system.membus.data_through_bus 25508463 # Total data (bytes) 450system.membus.snoop_data_through_bus 654016 # Total snoop data (bytes) 451system.membus.reqLayer0.occupancy 250556000 # Layer occupancy (ticks) |
| 454system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 452system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 455system.membus.reqLayer1.occupancy 583301000 # Layer occupancy (ticks) | 453system.membus.reqLayer1.occupancy 583258500 # Layer occupancy (ticks) |
| 456system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 454system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 457system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) | 455system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks) |
| 458system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 456system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 459system.membus.reqLayer3.occupancy 1608447497 # Layer occupancy (ticks) | 457system.membus.reqLayer3.occupancy 1605908499 # Layer occupancy (ticks) |
| 460system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) | 458system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 461system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) | 459system.membus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) |
| 462system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 460system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 463system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) | 461system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) |
| 464system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 462system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 465system.membus.respLayer2.occupancy 3153020380 # Layer occupancy (ticks) | 463system.membus.respLayer2.occupancy 3150989153 # Layer occupancy (ticks) |
| 466system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 464system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 467system.membus.respLayer4.occupancy 429468745 # Layer occupancy (ticks) | 465system.membus.respLayer4.occupancy 429464748 # Layer occupancy (ticks) |
| 468system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 469system.iocache.tags.replacements 47576 # number of replacements | 466system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 467system.iocache.tags.replacements 47576 # number of replacements |
| 470system.iocache.tags.tagsinuse 0.103982 # Cycle average of tags in use | 468system.iocache.tags.tagsinuse 0.103980 # Cycle average of tags in use |
| 471system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 472system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. 473system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 469system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 470system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. 471system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 474system.iocache.tags.warmup_cycle 4992954297000 # Cycle when the warmup percentage was hit. 475system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103982 # Average occupied blocks per requestor | 472system.iocache.tags.warmup_cycle 4992951939000 # Cycle when the warmup percentage was hit. 473system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103980 # Average occupied blocks per requestor |
| 476system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy 477system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy 478system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses 479system.iocache.ReadReq_misses::total 911 # number of ReadReq misses 480system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 481system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 482system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses 483system.iocache.demand_misses::total 47631 # number of demand (read+write) misses 484system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses 485system.iocache.overall_misses::total 47631 # number of overall misses | 474system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy 475system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy 476system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses 477system.iocache.ReadReq_misses::total 911 # number of ReadReq misses 478system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 479system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 480system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses 481system.iocache.demand_misses::total 47631 # number of demand (read+write) misses 482system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses 483system.iocache.overall_misses::total 47631 # number of overall misses |
| 486system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149420946 # number of ReadReq miss cycles 487system.iocache.ReadReq_miss_latency::total 149420946 # number of ReadReq miss cycles 488system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11534885027 # number of WriteReq miss cycles 489system.iocache.WriteReq_miss_latency::total 11534885027 # number of WriteReq miss cycles 490system.iocache.demand_miss_latency::pc.south_bridge.ide 11684305973 # number of demand (read+write) miss cycles 491system.iocache.demand_miss_latency::total 11684305973 # number of demand (read+write) miss cycles 492system.iocache.overall_miss_latency::pc.south_bridge.ide 11684305973 # number of overall miss cycles 493system.iocache.overall_miss_latency::total 11684305973 # number of overall miss cycles | 484system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151022435 # number of ReadReq miss cycles 485system.iocache.ReadReq_miss_latency::total 151022435 # number of ReadReq miss cycles 486system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11480088301 # number of WriteReq miss cycles 487system.iocache.WriteReq_miss_latency::total 11480088301 # number of WriteReq miss cycles 488system.iocache.demand_miss_latency::pc.south_bridge.ide 11631110736 # number of demand (read+write) miss cycles 489system.iocache.demand_miss_latency::total 11631110736 # number of demand (read+write) miss cycles 490system.iocache.overall_miss_latency::pc.south_bridge.ide 11631110736 # number of overall miss cycles 491system.iocache.overall_miss_latency::total 11631110736 # number of overall miss cycles |
| 494system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) 495system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) 496system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 497system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 498system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses 499system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses 500system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses 501system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses 502system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 503system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 504system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 505system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 506system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 507system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 508system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 509system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 492system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) 493system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) 494system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 495system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 496system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses 497system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses 498system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses 499system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses 500system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 501system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 502system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 503system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 504system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 505system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 506system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 507system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 510system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164018.601537 # average ReadReq miss latency 511system.iocache.ReadReq_avg_miss_latency::total 164018.601537 # average ReadReq miss latency 512system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 246893.943215 # average WriteReq miss latency 513system.iocache.WriteReq_avg_miss_latency::total 246893.943215 # average WriteReq miss latency 514system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency 515system.iocache.demand_avg_miss_latency::total 245308.852911 # average overall miss latency 516system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency 517system.iocache.overall_avg_miss_latency::total 245308.852911 # average overall miss latency 518system.iocache.blocked_cycles::no_mshrs 173314 # number of cycles access was blocked | 508system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165776.547750 # average ReadReq miss latency 509system.iocache.ReadReq_avg_miss_latency::total 165776.547750 # average ReadReq miss latency 510system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245721.068086 # average WriteReq miss latency 511system.iocache.WriteReq_avg_miss_latency::total 245721.068086 # average WriteReq miss latency 512system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency 513system.iocache.demand_avg_miss_latency::total 244192.033256 # average overall miss latency 514system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency 515system.iocache.overall_avg_miss_latency::total 244192.033256 # average overall miss latency 516system.iocache.blocked_cycles::no_mshrs 172788 # number of cycles access was blocked |
| 519system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 517system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 520system.iocache.blocked::no_mshrs 10321 # number of cycles access was blocked | 518system.iocache.blocked::no_mshrs 10383 # number of cycles access was blocked |
| 521system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 519system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 522system.iocache.avg_blocked_cycles::no_mshrs 16.792365 # average number of cycles each access was blocked | 520system.iocache.avg_blocked_cycles::no_mshrs 16.641433 # average number of cycles each access was blocked |
| 523system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 524system.iocache.fast_writes 0 # number of fast writes performed 525system.iocache.cache_copies 0 # number of cache copies performed 526system.iocache.writebacks::writebacks 46667 # number of writebacks 527system.iocache.writebacks::total 46667 # number of writebacks 528system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 529system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses 530system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 531system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 532system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses 533system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses 534system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses 535system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses | 521system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 522system.iocache.fast_writes 0 # number of fast writes performed 523system.iocache.cache_copies 0 # number of cache copies performed 524system.iocache.writebacks::writebacks 46667 # number of writebacks 525system.iocache.writebacks::total 46667 # number of writebacks 526system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 527system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses 528system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 529system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 530system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses 531system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses 532system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses 533system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses |
| 536system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102021946 # number of ReadReq MSHR miss cycles 537system.iocache.ReadReq_mshr_miss_latency::total 102021946 # number of ReadReq MSHR miss cycles 538system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9103892537 # number of WriteReq MSHR miss cycles 539system.iocache.WriteReq_mshr_miss_latency::total 9103892537 # number of WriteReq MSHR miss cycles 540system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of demand (read+write) MSHR miss cycles 541system.iocache.demand_mshr_miss_latency::total 9205914483 # number of demand (read+write) MSHR miss cycles 542system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of overall MSHR miss cycles 543system.iocache.overall_mshr_miss_latency::total 9205914483 # number of overall MSHR miss cycles | 534system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 103624935 # number of ReadReq MSHR miss cycles 535system.iocache.ReadReq_mshr_miss_latency::total 103624935 # number of ReadReq MSHR miss cycles 536system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9049102305 # number of WriteReq MSHR miss cycles 537system.iocache.WriteReq_mshr_miss_latency::total 9049102305 # number of WriteReq MSHR miss cycles 538system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of demand (read+write) MSHR miss cycles 539system.iocache.demand_mshr_miss_latency::total 9152727240 # number of demand (read+write) MSHR miss cycles 540system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of overall MSHR miss cycles 541system.iocache.overall_mshr_miss_latency::total 9152727240 # number of overall MSHR miss cycles |
| 544system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 545system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 546system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 547system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 548system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 549system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 550system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 551system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 542system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 543system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 544system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 545system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 546system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 547system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 548system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 549system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 552system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111988.963776 # average ReadReq mshr miss latency 553system.iocache.ReadReq_avg_mshr_miss_latency::total 111988.963776 # average ReadReq mshr miss latency 554system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 194860.713549 # average WriteReq mshr miss latency 555system.iocache.WriteReq_avg_mshr_miss_latency::total 194860.713549 # average WriteReq mshr miss latency 556system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency 557system.iocache.demand_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency 558system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency 559system.iocache.overall_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency | 550system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113748.556531 # average ReadReq mshr miss latency 551system.iocache.ReadReq_avg_mshr_miss_latency::total 113748.556531 # average ReadReq mshr miss latency 552system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193687.977419 # average WriteReq mshr miss latency 553system.iocache.WriteReq_avg_mshr_miss_latency::total 193687.977419 # average WriteReq mshr miss latency 554system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency 555system.iocache.demand_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency 556system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency 557system.iocache.overall_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency |
| 560system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 561system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 562system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). | 558system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 559system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 560system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |
| 563system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). | 561system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). |
| 564system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 565system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 566system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 567system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 568system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 569system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 570system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 571system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 572system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 562system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 563system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 564system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 565system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 566system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 567system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 568system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 569system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 570system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 573system.iobus.throughput 638153 # Throughput (bytes/s) 574system.iobus.trans_dist::ReadReq 225567 # Transaction distribution 575system.iobus.trans_dist::ReadResp 225567 # Transaction distribution 576system.iobus.trans_dist::WriteReq 57606 # Transaction distribution 577system.iobus.trans_dist::WriteResp 57606 # Transaction distribution 578system.iobus.trans_dist::MessageReq 1643 # Transaction distribution 579system.iobus.trans_dist::MessageResp 1643 # Transaction distribution | 571system.iobus.throughput 638147 # Throughput (bytes/s) 572system.iobus.trans_dist::ReadReq 225559 # Transaction distribution 573system.iobus.trans_dist::ReadResp 225559 # Transaction distribution 574system.iobus.trans_dist::WriteReq 57591 # Transaction distribution 575system.iobus.trans_dist::WriteResp 57591 # Transaction distribution 576system.iobus.trans_dist::MessageReq 1642 # Transaction distribution 577system.iobus.trans_dist::MessageResp 1642 # Transaction distribution |
| 580system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 581system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) | 578system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 579system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) |
| 582system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) | 580system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) |
| 583system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 584system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 585system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 586system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 587system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 588system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 589system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 590system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 591system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 592system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 593system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 594system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 595system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 596system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 597system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) | 581system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 582system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 583system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 584system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 585system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 586system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) 587system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 588system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 589system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 590system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 591system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 592system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 593system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 594system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 595system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) |
| 598system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) | 596system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) |
| 599system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) 600system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) | 597system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) 598system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) |
| 601system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) 602system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) 603system.iobus.pkt_count::total 569632 # Packet count per connected master and slave (bytes) | 599system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) 600system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) 601system.iobus.pkt_count::total 569584 # Packet count per connected master and slave (bytes) |
| 604system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 605system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) | 602system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 603system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) |
| 606system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) | 604system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) |
| 607system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 608system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 609system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 610system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 611system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 612system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 613system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 614system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 615system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 616system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 617system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 618system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 619system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 620system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 621system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) | 605system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 606system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 607system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 608system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 609system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 610system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) 611system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 612system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 613system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 614system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 615system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 616system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 617system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 618system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 619system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) |
| 622system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) | 620system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) |
| 623system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) | 621system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) 622system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) |
| 625system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.tot_pkt_size::total 3276232 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.data_through_bus 3276232 # Total data (bytes) 629system.iobus.reqLayer0.occupancy 3917850 # Layer occupancy (ticks) | 623system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.tot_pkt_size::total 3276202 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.data_through_bus 3276202 # Total data (bytes) 627system.iobus.reqLayer0.occupancy 3916600 # Layer occupancy (ticks) |
| 630system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 631system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 632system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 633system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 634system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 628system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 629system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 630system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 631system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 632system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 635system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) | 633system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) |
| 636system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 637system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 638system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 639system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 640system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 641system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 642system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 643system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) --- 13 unchanged lines hidden (view full) --- 657system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 658system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 659system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 660system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 662system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 664system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 634system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 635system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 636system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 637system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 638system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 639system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 640system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 641system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) --- 13 unchanged lines hidden (view full) --- 655system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 656system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 657system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 658system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 659system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 660system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 662system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 665system.iobus.reqLayer18.occupancy 424362228 # Layer occupancy (ticks) | 663system.iobus.reqLayer18.occupancy 424364988 # Layer occupancy (ticks) |
| 666system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 667system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 668system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) | 664system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 665system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 666system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) |
| 669system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) | 667system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) |
| 670system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 668system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 671system.iobus.respLayer1.occupancy 53078255 # Layer occupancy (ticks) | 669system.iobus.respLayer1.occupancy 53080252 # Layer occupancy (ticks) |
| 672system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 670system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 673system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) | 671system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) |
| 674system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) | 672system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 675system.cpu.branchPred.lookups 85592238 # Number of BP lookups 676system.cpu.branchPred.condPredicted 85592238 # Number of conditional branches predicted 677system.cpu.branchPred.condIncorrect 882873 # Number of conditional branches incorrect 678system.cpu.branchPred.BTBLookups 79245732 # Number of BTB lookups 679system.cpu.branchPred.BTBHits 77532748 # Number of BTB hits | 673system.cpu.branchPred.lookups 85602749 # Number of BP lookups 674system.cpu.branchPred.condPredicted 85602749 # Number of conditional branches predicted 675system.cpu.branchPred.condIncorrect 882967 # Number of conditional branches incorrect 676system.cpu.branchPred.BTBLookups 79146839 # Number of BTB lookups 677system.cpu.branchPred.BTBHits 77528417 # Number of BTB hits |
| 680system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 678system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 681system.cpu.branchPred.BTBHitPct 97.838390 # BTB Hit Percentage 682system.cpu.branchPred.usedRAS 1439092 # Number of times the RAS was used to get a target. 683system.cpu.branchPred.RASInCorrect 180819 # Number of incorrect RAS predictions. 684system.cpu.numCycles 453841851 # number of cpu cycles simulated | 679system.cpu.branchPred.BTBHitPct 97.955165 # BTB Hit Percentage 680system.cpu.branchPred.usedRAS 1444593 # Number of times the RAS was used to get a target. 681system.cpu.branchPred.RASInCorrect 180696 # Number of incorrect RAS predictions. 682system.cpu.numCycles 453810576 # number of cpu cycles simulated |
| 685system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 686system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 683system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 684system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 687system.cpu.fetch.icacheStallCycles 25587982 # Number of cycles fetch is stalled on an Icache miss 688system.cpu.fetch.Insts 422693278 # Number of instructions fetch has processed 689system.cpu.fetch.Branches 85592238 # Number of branches that fetch encountered 690system.cpu.fetch.predictedBranches 78971840 # Number of branches that fetch has predicted taken 691system.cpu.fetch.Cycles 162652701 # Number of cycles fetch has run and was not squashing or blocked 692system.cpu.fetch.SquashCycles 3982002 # Number of cycles fetch has spent squashing 693system.cpu.fetch.TlbCycles 104057 # Number of cycles fetch has spent waiting for tlb 694system.cpu.fetch.BlockedCycles 71419426 # Number of cycles fetch has spent blocked 695system.cpu.fetch.MiscStallCycles 42857 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 696system.cpu.fetch.PendingTrapStallCycles 89331 # Number of stall cycles due to pending traps 697system.cpu.fetch.IcacheWaitRetryStallCycles 200 # Number of stall cycles due to full MSHR 698system.cpu.fetch.CacheLines 8481476 # Number of cache lines fetched 699system.cpu.fetch.IcacheSquashes 385696 # Number of outstanding Icache misses that were squashed 700system.cpu.fetch.ItlbSquashes 2322 # Number of outstanding ITLB misses that were squashed 701system.cpu.fetch.rateDist::samples 262951613 # Number of instructions fetched each cycle (Total) 702system.cpu.fetch.rateDist::mean 3.174902 # Number of instructions fetched each cycle (Total) 703system.cpu.fetch.rateDist::stdev 3.411090 # Number of instructions fetched each cycle (Total) | 685system.cpu.fetch.icacheStallCycles 25587128 # Number of cycles fetch is stalled on an Icache miss 686system.cpu.fetch.Insts 422793434 # Number of instructions fetch has processed 687system.cpu.fetch.Branches 85602749 # Number of branches that fetch encountered 688system.cpu.fetch.predictedBranches 78973010 # Number of branches that fetch has predicted taken 689system.cpu.fetch.Cycles 162653475 # Number of cycles fetch has run and was not squashing or blocked 690system.cpu.fetch.SquashCycles 3995125 # Number of cycles fetch has spent squashing 691system.cpu.fetch.TlbCycles 108453 # Number of cycles fetch has spent waiting for tlb 692system.cpu.fetch.BlockedCycles 71359520 # Number of cycles fetch has spent blocked 693system.cpu.fetch.MiscStallCycles 43835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 694system.cpu.fetch.PendingTrapStallCycles 87857 # Number of stall cycles due to pending traps 695system.cpu.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR 696system.cpu.fetch.CacheLines 8489508 # Number of cache lines fetched 697system.cpu.fetch.IcacheSquashes 384110 # Number of outstanding Icache misses that were squashed 698system.cpu.fetch.ItlbSquashes 2391 # Number of outstanding ITLB misses that were squashed 699system.cpu.fetch.rateDist::samples 262908725 # Number of instructions fetched each cycle (Total) 700system.cpu.fetch.rateDist::mean 3.175877 # Number of instructions fetched each cycle (Total) 701system.cpu.fetch.rateDist::stdev 3.411274 # Number of instructions fetched each cycle (Total) |
| 704system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 702system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 705system.cpu.fetch.rateDist::0 100714901 38.30% 38.30% # Number of instructions fetched each cycle (Total) 706system.cpu.fetch.rateDist::1 1542522 0.59% 38.89% # Number of instructions fetched each cycle (Total) 707system.cpu.fetch.rateDist::2 71823019 27.31% 66.20% # Number of instructions fetched each cycle (Total) 708system.cpu.fetch.rateDist::3 902488 0.34% 66.55% # Number of instructions fetched each cycle (Total) 709system.cpu.fetch.rateDist::4 1566536 0.60% 67.14% # Number of instructions fetched each cycle (Total) 710system.cpu.fetch.rateDist::5 2391041 0.91% 68.05% # Number of instructions fetched each cycle (Total) 711system.cpu.fetch.rateDist::6 1017988 0.39% 68.44% # Number of instructions fetched each cycle (Total) 712system.cpu.fetch.rateDist::7 1324647 0.50% 68.94% # Number of instructions fetched each cycle (Total) 713system.cpu.fetch.rateDist::8 81668471 31.06% 100.00% # Number of instructions fetched each cycle (Total) | 703system.cpu.fetch.rateDist::0 100670178 38.29% 38.29% # Number of instructions fetched each cycle (Total) 704system.cpu.fetch.rateDist::1 1530444 0.58% 38.87% # Number of instructions fetched each cycle (Total) 705system.cpu.fetch.rateDist::2 71820335 27.32% 66.19% # Number of instructions fetched each cycle (Total) 706system.cpu.fetch.rateDist::3 896426 0.34% 66.53% # Number of instructions fetched each cycle (Total) 707system.cpu.fetch.rateDist::4 1566584 0.60% 67.13% # Number of instructions fetched each cycle (Total) 708system.cpu.fetch.rateDist::5 2396730 0.91% 68.04% # Number of instructions fetched each cycle (Total) 709system.cpu.fetch.rateDist::6 1019321 0.39% 68.43% # Number of instructions fetched each cycle (Total) 710system.cpu.fetch.rateDist::7 1330214 0.51% 68.93% # Number of instructions fetched each cycle (Total) 711system.cpu.fetch.rateDist::8 81678493 31.07% 100.00% # Number of instructions fetched each cycle (Total) |
| 714system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 715system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 716system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 712system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 713system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 714system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 717system.cpu.fetch.rateDist::total 262951613 # Number of instructions fetched each cycle (Total) 718system.cpu.fetch.branchRate 0.188595 # Number of branch fetches per cycle 719system.cpu.fetch.rate 0.931367 # Number of inst fetches per cycle 720system.cpu.decode.IdleCycles 29471400 # Number of cycles decode is idle 721system.cpu.decode.BlockedCycles 68588335 # Number of cycles decode is blocked 722system.cpu.decode.RunCycles 158500700 # Number of cycles decode is running 723system.cpu.decode.UnblockCycles 3336119 # Number of cycles decode is unblocking 724system.cpu.decode.SquashCycles 3055059 # Number of cycles decode is squashing 725system.cpu.decode.DecodedInsts 832519072 # Number of instructions handled by decode 726system.cpu.decode.SquashedInsts 997 # Number of squashed instructions handled by decode 727system.cpu.rename.SquashCycles 3055059 # Number of cycles rename is squashing 728system.cpu.rename.IdleCycles 32166739 # Number of cycles rename is idle 729system.cpu.rename.BlockCycles 43365867 # Number of cycles rename is blocking 730system.cpu.rename.serializeStallCycles 12492763 # count of cycles rename stalled for serializing inst 731system.cpu.rename.RunCycles 158788078 # Number of cycles rename is running 732system.cpu.rename.UnblockCycles 13083107 # Number of cycles rename is unblocking 733system.cpu.rename.RenamedInsts 829619005 # Number of instructions processed by rename 734system.cpu.rename.ROBFullEvents 21424 # Number of times rename has blocked due to ROB full 735system.cpu.rename.IQFullEvents 6060149 # Number of times rename has blocked due to IQ full 736system.cpu.rename.LSQFullEvents 5145730 # Number of times rename has blocked due to LSQ full 737system.cpu.rename.RenamedOperands 991238350 # Number of destination operands rename has renamed 738system.cpu.rename.RenameLookups 1800229618 # Number of register rename lookups that rename has made 739system.cpu.rename.int_rename_lookups 1106821161 # Number of integer rename lookups 740system.cpu.rename.fp_rename_lookups 116 # Number of floating rename lookups 741system.cpu.rename.CommittedMaps 963974807 # Number of HB maps that are committed 742system.cpu.rename.UndoneMaps 27263541 # Number of HB maps that are undone due to squashing 743system.cpu.rename.serializingInsts 455448 # count of serializing insts renamed 744system.cpu.rename.tempSerializingInsts 461036 # count of temporary serializing insts renamed 745system.cpu.rename.skidInsts 29565034 # count of insts added to the skid buffer 746system.cpu.memDep0.insertedLoads 16718678 # Number of loads inserted to the mem dependence unit. 747system.cpu.memDep0.insertedStores 9823839 # Number of stores inserted to the mem dependence unit. 748system.cpu.memDep0.conflictingLoads 1099301 # Number of conflicting loads. 749system.cpu.memDep0.conflictingStores 921701 # Number of conflicting stores. 750system.cpu.iq.iqInstsAdded 824848453 # Number of instructions added to the IQ (excludes non-spec) 751system.cpu.iq.iqNonSpecInstsAdded 1187045 # Number of non-speculative instructions added to the IQ 752system.cpu.iq.iqInstsIssued 820941370 # Number of instructions issued 753system.cpu.iq.iqSquashedInstsIssued 145995 # Number of squashed instructions issued 754system.cpu.iq.iqSquashedInstsExamined 19149103 # Number of squashed instructions iterated over during squash; mainly for profiling 755system.cpu.iq.iqSquashedOperandsExamined 29112205 # Number of squashed operands that are examined and possibly removed from graph 756system.cpu.iq.iqSquashedNonSpecRemoved 132366 # Number of squashed non-spec instructions that were removed 757system.cpu.iq.issued_per_cycle::samples 262951613 # Number of insts issued each cycle 758system.cpu.iq.issued_per_cycle::mean 3.122024 # Number of insts issued each cycle 759system.cpu.iq.issued_per_cycle::stdev 2.401319 # Number of insts issued each cycle | 715system.cpu.fetch.rateDist::total 262908725 # Number of instructions fetched each cycle (Total) 716system.cpu.fetch.branchRate 0.188631 # Number of branch fetches per cycle 717system.cpu.fetch.rate 0.931652 # Number of inst fetches per cycle 718system.cpu.decode.IdleCycles 29469022 # Number of cycles decode is idle 719system.cpu.decode.BlockedCycles 68533895 # Number of cycles decode is blocked 720system.cpu.decode.RunCycles 158500921 # Number of cycles decode is running 721system.cpu.decode.UnblockCycles 3336716 # Number of cycles decode is unblocking 722system.cpu.decode.SquashCycles 3068171 # Number of cycles decode is squashing 723system.cpu.decode.DecodedInsts 832628882 # Number of instructions handled by decode 724system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode 725system.cpu.rename.SquashCycles 3068171 # Number of cycles rename is squashing 726system.cpu.rename.IdleCycles 32166033 # Number of cycles rename is idle 727system.cpu.rename.BlockCycles 43333689 # Number of cycles rename is blocking 728system.cpu.rename.serializeStallCycles 12473461 # count of cycles rename stalled for serializing inst 729system.cpu.rename.RunCycles 158788115 # Number of cycles rename is running 730system.cpu.rename.UnblockCycles 13079256 # Number of cycles rename is unblocking 731system.cpu.rename.RenamedInsts 829706187 # Number of instructions processed by rename 732system.cpu.rename.ROBFullEvents 21464 # Number of times rename has blocked due to ROB full 733system.cpu.rename.IQFullEvents 6056720 # Number of times rename has blocked due to IQ full 734system.cpu.rename.LSQFullEvents 5143219 # Number of times rename has blocked due to LSQ full 735system.cpu.rename.RenamedOperands 991368832 # Number of destination operands rename has renamed 736system.cpu.rename.RenameLookups 1800529447 # Number of register rename lookups that rename has made 737system.cpu.rename.int_rename_lookups 1106981108 # Number of integer rename lookups 738system.cpu.rename.fp_rename_lookups 114 # Number of floating rename lookups 739system.cpu.rename.CommittedMaps 963921381 # Number of HB maps that are committed 740system.cpu.rename.UndoneMaps 27447449 # Number of HB maps that are undone due to squashing 741system.cpu.rename.serializingInsts 454679 # count of serializing insts renamed 742system.cpu.rename.tempSerializingInsts 459073 # count of temporary serializing insts renamed 743system.cpu.rename.skidInsts 29562257 # count of insts added to the skid buffer 744system.cpu.memDep0.insertedLoads 16738170 # Number of loads inserted to the mem dependence unit. 745system.cpu.memDep0.insertedStores 9831898 # Number of stores inserted to the mem dependence unit. 746system.cpu.memDep0.conflictingLoads 1099509 # Number of conflicting loads. 747system.cpu.memDep0.conflictingStores 931888 # Number of conflicting stores. 748system.cpu.iq.iqInstsAdded 824922108 # Number of instructions added to the IQ (excludes non-spec) 749system.cpu.iq.iqNonSpecInstsAdded 1185282 # Number of non-speculative instructions added to the IQ 750system.cpu.iq.iqInstsIssued 820965230 # Number of instructions issued 751system.cpu.iq.iqSquashedInstsIssued 150616 # Number of squashed instructions issued 752system.cpu.iq.iqSquashedInstsExamined 19266581 # Number of squashed instructions iterated over during squash; mainly for profiling 753system.cpu.iq.iqSquashedOperandsExamined 29327510 # Number of squashed operands that are examined and possibly removed from graph 754system.cpu.iq.iqSquashedNonSpecRemoved 130776 # Number of squashed non-spec instructions that were removed 755system.cpu.iq.issued_per_cycle::samples 262908725 # Number of insts issued each cycle 756system.cpu.iq.issued_per_cycle::mean 3.122625 # Number of insts issued each cycle 757system.cpu.iq.issued_per_cycle::stdev 2.401229 # Number of insts issued each cycle |
| 760system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 758system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 761system.cpu.iq.issued_per_cycle::0 76573555 29.12% 29.12% # Number of insts issued each cycle 762system.cpu.iq.issued_per_cycle::1 15783174 6.00% 35.12% # Number of insts issued each cycle 763system.cpu.iq.issued_per_cycle::2 10543493 4.01% 39.13% # Number of insts issued each cycle 764system.cpu.iq.issued_per_cycle::3 7363188 2.80% 41.93% # Number of insts issued each cycle 765system.cpu.iq.issued_per_cycle::4 75733020 28.80% 70.73% # Number of insts issued each cycle 766system.cpu.iq.issued_per_cycle::5 3745069 1.42% 72.16% # Number of insts issued each cycle 767system.cpu.iq.issued_per_cycle::6 72294186 27.49% 99.65% # Number of insts issued each cycle 768system.cpu.iq.issued_per_cycle::7 768319 0.29% 99.94% # Number of insts issued each cycle 769system.cpu.iq.issued_per_cycle::8 147609 0.06% 100.00% # Number of insts issued each cycle | 759system.cpu.iq.issued_per_cycle::0 76541753 29.11% 29.11% # Number of insts issued each cycle 760system.cpu.iq.issued_per_cycle::1 15760378 5.99% 35.11% # Number of insts issued each cycle 761system.cpu.iq.issued_per_cycle::2 10546081 4.01% 39.12% # Number of insts issued each cycle 762system.cpu.iq.issued_per_cycle::3 7369618 2.80% 41.92% # Number of insts issued each cycle 763system.cpu.iq.issued_per_cycle::4 75729447 28.80% 70.73% # Number of insts issued each cycle 764system.cpu.iq.issued_per_cycle::5 3748882 1.43% 72.15% # Number of insts issued each cycle 765system.cpu.iq.issued_per_cycle::6 72293205 27.50% 99.65% # Number of insts issued each cycle 766system.cpu.iq.issued_per_cycle::7 772480 0.29% 99.94% # Number of insts issued each cycle 767system.cpu.iq.issued_per_cycle::8 146881 0.06% 100.00% # Number of insts issued each cycle |
| 770system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 771system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 772system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 768system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 769system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 770system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 773system.cpu.iq.issued_per_cycle::total 262951613 # Number of insts issued each cycle | 771system.cpu.iq.issued_per_cycle::total 262908725 # Number of insts issued each cycle |
| 774system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 772system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 775system.cpu.iq.fu_full::IntAlu 346888 33.04% 33.04% # attempts to use FU when none available 776system.cpu.iq.fu_full::IntMult 241 0.02% 33.06% # attempts to use FU when none available 777system.cpu.iq.fu_full::IntDiv 2034 0.19% 33.25% # attempts to use FU when none available 778system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.25% # attempts to use FU when none available 779system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.25% # attempts to use FU when none available 780system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.25% # attempts to use FU when none available 781system.cpu.iq.fu_full::FloatMult 0 0.00% 33.25% # attempts to use FU when none available 782system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.25% # attempts to use FU when none available 783system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.25% # attempts to use FU when none available 784system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.25% # attempts to use FU when none available 785system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.25% # attempts to use FU when none available 786system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.25% # attempts to use FU when none available 787system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.25% # attempts to use FU when none available 788system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.25% # attempts to use FU when none available 789system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.25% # attempts to use FU when none available 790system.cpu.iq.fu_full::SimdMult 0 0.00% 33.25% # attempts to use FU when none available 791system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.25% # attempts to use FU when none available 792system.cpu.iq.fu_full::SimdShift 0 0.00% 33.25% # attempts to use FU when none available 793system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.25% # attempts to use FU when none available 794system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.25% # attempts to use FU when none available 795system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.25% # attempts to use FU when none available 796system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.25% # attempts to use FU when none available 797system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.25% # attempts to use FU when none available 798system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.25% # attempts to use FU when none available 799system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.25% # attempts to use FU when none available 800system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.25% # attempts to use FU when none available 801system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.25% # attempts to use FU when none available 802system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.25% # attempts to use FU when none available 803system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.25% # attempts to use FU when none available 804system.cpu.iq.fu_full::MemRead 547279 52.12% 85.37% # attempts to use FU when none available 805system.cpu.iq.fu_full::MemWrite 153573 14.63% 100.00% # attempts to use FU when none available | 773system.cpu.iq.fu_full::IntAlu 349560 33.18% 33.18% # attempts to use FU when none available 774system.cpu.iq.fu_full::IntMult 241 0.02% 33.20% # attempts to use FU when none available 775system.cpu.iq.fu_full::IntDiv 1967 0.19% 33.39% # attempts to use FU when none available 776system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.39% # attempts to use FU when none available 777system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.39% # attempts to use FU when none available 778system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.39% # attempts to use FU when none available 779system.cpu.iq.fu_full::FloatMult 0 0.00% 33.39% # attempts to use FU when none available 780system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.39% # attempts to use FU when none available 781system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.39% # attempts to use FU when none available 782system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.39% # attempts to use FU when none available 783system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.39% # attempts to use FU when none available 784system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.39% # attempts to use FU when none available 785system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.39% # attempts to use FU when none available 786system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.39% # attempts to use FU when none available 787system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.39% # attempts to use FU when none available 788system.cpu.iq.fu_full::SimdMult 0 0.00% 33.39% # attempts to use FU when none available 789system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.39% # attempts to use FU when none available 790system.cpu.iq.fu_full::SimdShift 0 0.00% 33.39% # attempts to use FU when none available 791system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.39% # attempts to use FU when none available 792system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.39% # attempts to use FU when none available 793system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.39% # attempts to use FU when none available 794system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.39% # attempts to use FU when none available 795system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.39% # attempts to use FU when none available 796system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.39% # attempts to use FU when none available 797system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.39% # attempts to use FU when none available 798system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.39% # attempts to use FU when none available 799system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.39% # attempts to use FU when none available 800system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.39% # attempts to use FU when none available 801system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.39% # attempts to use FU when none available 802system.cpu.iq.fu_full::MemRead 548780 52.08% 85.47% # attempts to use FU when none available 803system.cpu.iq.fu_full::MemWrite 153094 14.53% 100.00% # attempts to use FU when none available |
| 806system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 807system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 804system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 805system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 808system.cpu.iq.FU_type_0::No_OpClass 309747 0.04% 0.04% # Type of FU issued 809system.cpu.iq.FU_type_0::IntAlu 793469361 96.65% 96.69% # Type of FU issued 810system.cpu.iq.FU_type_0::IntMult 149710 0.02% 96.71% # Type of FU issued 811system.cpu.iq.FU_type_0::IntDiv 124599 0.02% 96.72% # Type of FU issued | 806system.cpu.iq.FU_type_0::No_OpClass 307236 0.04% 0.04% # Type of FU issued 807system.cpu.iq.FU_type_0::IntAlu 793474466 96.65% 96.69% # Type of FU issued 808system.cpu.iq.FU_type_0::IntMult 149866 0.02% 96.71% # Type of FU issued 809system.cpu.iq.FU_type_0::IntDiv 124488 0.02% 96.72% # Type of FU issued |
| 812system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued 813system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued 814system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued 815system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued 816system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued 817system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued 818system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued 819system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 830system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued 831system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued 832system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued 833system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued 834system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued 835system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued 836system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued 837system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued | 810system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued 811system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued 812system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued 813system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued 814system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued 815system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued 816system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued 817system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 828system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued 829system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued 830system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued 831system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued 832system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued 833system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued 834system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued 835system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued |
| 838system.cpu.iq.FU_type_0::MemRead 17668051 2.15% 98.88% # Type of FU issued 839system.cpu.iq.FU_type_0::MemWrite 9219902 1.12% 100.00% # Type of FU issued | 836system.cpu.iq.FU_type_0::MemRead 17682042 2.15% 98.88% # Type of FU issued 837system.cpu.iq.FU_type_0::MemWrite 9227132 1.12% 100.00% # Type of FU issued |
| 840system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 841system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 838system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 839system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 842system.cpu.iq.FU_type_0::total 820941370 # Type of FU issued 843system.cpu.iq.rate 1.808871 # Inst issue rate 844system.cpu.iq.fu_busy_cnt 1050015 # FU busy when requested 845system.cpu.iq.fu_busy_rate 0.001279 # FU busy rate (busy events/executed inst) 846system.cpu.iq.int_inst_queue_reads 1906138377 # Number of integer instruction queue reads 847system.cpu.iq.int_inst_queue_writes 845194990 # Number of integer instruction queue writes 848system.cpu.iq.int_inst_queue_wakeup_accesses 817033315 # Number of integer instruction queue wakeup accesses 849system.cpu.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads 850system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes 851system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses 852system.cpu.iq.int_alu_accesses 821681548 # Number of integer alu accesses 853system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses 854system.cpu.iew.lsq.thread0.forwLoads 1692176 # Number of loads that had data forwarded from stores | 840system.cpu.iq.FU_type_0::total 820965230 # Type of FU issued 841system.cpu.iq.rate 1.809048 # Inst issue rate 842system.cpu.iq.fu_busy_cnt 1053642 # FU busy when requested 843system.cpu.iq.fu_busy_rate 0.001283 # FU busy rate (busy events/executed inst) 844system.cpu.iq.int_inst_queue_reads 1906151693 # Number of integer instruction queue reads 845system.cpu.iq.int_inst_queue_writes 845384400 # Number of integer instruction queue writes 846system.cpu.iq.int_inst_queue_wakeup_accesses 817050943 # Number of integer instruction queue wakeup accesses 847system.cpu.iq.fp_inst_queue_reads 198 # Number of floating instruction queue reads 848system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes 849system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses 850system.cpu.iq.int_alu_accesses 821711543 # Number of integer alu accesses 851system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses 852system.cpu.iew.lsq.thread0.forwLoads 1694469 # Number of loads that had data forwarded from stores |
| 855system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 853system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 856system.cpu.iew.lsq.thread0.squashedLoads 2727781 # Number of loads squashed 857system.cpu.iew.lsq.thread0.ignoredResponses 18489 # Number of memory responses ignored because the instruction is squashed 858system.cpu.iew.lsq.thread0.memOrderViolation 12047 # Number of memory ordering violations 859system.cpu.iew.lsq.thread0.squashedStores 1402321 # Number of stores squashed | 854system.cpu.iew.lsq.thread0.squashedLoads 2748093 # Number of loads squashed 855system.cpu.iew.lsq.thread0.ignoredResponses 19141 # Number of memory responses ignored because the instruction is squashed 856system.cpu.iew.lsq.thread0.memOrderViolation 11819 # Number of memory ordering violations 857system.cpu.iew.lsq.thread0.squashedStores 1409863 # Number of stores squashed |
| 860system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 861system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 858system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 859system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 862system.cpu.iew.lsq.thread0.rescheduledLoads 1931655 # Number of loads that were rescheduled 863system.cpu.iew.lsq.thread0.cacheBlocked 11924 # Number of times an access to memory failed due to the cache being blocked | 860system.cpu.iew.lsq.thread0.rescheduledLoads 1931395 # Number of loads that were rescheduled 861system.cpu.iew.lsq.thread0.cacheBlocked 11998 # Number of times an access to memory failed due to the cache being blocked |
| 864system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 862system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 865system.cpu.iew.iewSquashCycles 3055059 # Number of cycles IEW is squashing 866system.cpu.iew.iewBlockCycles 31495600 # Number of cycles IEW is blocking 867system.cpu.iew.iewUnblockCycles 2151607 # Number of cycles IEW is unblocking 868system.cpu.iew.iewDispatchedInsts 826035498 # Number of instructions dispatched to IQ 869system.cpu.iew.iewDispSquashedInsts 247681 # Number of squashed instructions skipped by dispatch 870system.cpu.iew.iewDispLoadInsts 16718678 # Number of dispatched load instructions 871system.cpu.iew.iewDispStoreInsts 9823839 # Number of dispatched store instructions 872system.cpu.iew.iewDispNonSpecInsts 691406 # Number of dispatched non-speculative instructions 873system.cpu.iew.iewIQFullEvents 1620111 # Number of times the IQ has become full, causing a stall 874system.cpu.iew.iewLSQFullEvents 12282 # Number of times the LSQ has become full, causing a stall 875system.cpu.iew.memOrderViolationEvents 12047 # Number of memory order violations 876system.cpu.iew.predictedTakenIncorrect 498908 # Number of branches that were predicted taken incorrectly 877system.cpu.iew.predictedNotTakenIncorrect 509123 # Number of branches that were predicted not taken incorrectly 878system.cpu.iew.branchMispredicts 1008031 # Number of branch mispredicts detected at execute 879system.cpu.iew.iewExecutedInsts 819536653 # Number of executed instructions 880system.cpu.iew.iewExecLoadInsts 17366589 # Number of load instructions executed 881system.cpu.iew.iewExecSquashedInsts 1404716 # Number of squashed instructions skipped in execute | 863system.cpu.iew.iewSquashCycles 3068171 # Number of cycles IEW is squashing 864system.cpu.iew.iewBlockCycles 31463417 # Number of cycles IEW is blocking 865system.cpu.iew.iewUnblockCycles 2151711 # Number of cycles IEW is unblocking 866system.cpu.iew.iewDispatchedInsts 826107390 # Number of instructions dispatched to IQ 867system.cpu.iew.iewDispSquashedInsts 248376 # Number of squashed instructions skipped by dispatch 868system.cpu.iew.iewDispLoadInsts 16738170 # Number of dispatched load instructions 869system.cpu.iew.iewDispStoreInsts 9831898 # Number of dispatched store instructions 870system.cpu.iew.iewDispNonSpecInsts 690155 # Number of dispatched non-speculative instructions 871system.cpu.iew.iewIQFullEvents 1620159 # Number of times the IQ has become full, causing a stall 872system.cpu.iew.iewLSQFullEvents 12279 # Number of times the LSQ has become full, causing a stall 873system.cpu.iew.memOrderViolationEvents 11819 # Number of memory order violations 874system.cpu.iew.predictedTakenIncorrect 498534 # Number of branches that were predicted taken incorrectly 875system.cpu.iew.predictedNotTakenIncorrect 508074 # Number of branches that were predicted not taken incorrectly 876system.cpu.iew.branchMispredicts 1006608 # Number of branch mispredicts detected at execute 877system.cpu.iew.iewExecutedInsts 819554351 # Number of executed instructions 878system.cpu.iew.iewExecLoadInsts 17378079 # Number of load instructions executed 879system.cpu.iew.iewExecSquashedInsts 1410878 # Number of squashed instructions skipped in execute |
| 882system.cpu.iew.exec_swp 0 # number of swp insts executed 883system.cpu.iew.exec_nop 0 # number of nop insts executed | 880system.cpu.iew.exec_swp 0 # number of swp insts executed 881system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 884system.cpu.iew.exec_refs 26403509 # number of memory reference insts executed 885system.cpu.iew.exec_branches 83090404 # Number of branches executed 886system.cpu.iew.exec_stores 9036920 # Number of stores executed 887system.cpu.iew.exec_rate 1.805776 # Inst execution rate 888system.cpu.iew.wb_sent 819134916 # cumulative count of insts sent to commit 889system.cpu.iew.wb_count 817033367 # cumulative count of insts written-back 890system.cpu.iew.wb_producers 638560375 # num instructions producing a value 891system.cpu.iew.wb_consumers 1043850178 # num instructions consuming a value | 882system.cpu.iew.exec_refs 26421028 # number of memory reference insts executed 883system.cpu.iew.exec_branches 83090233 # Number of branches executed 884system.cpu.iew.exec_stores 9042949 # Number of stores executed 885system.cpu.iew.exec_rate 1.805939 # Inst execution rate 886system.cpu.iew.wb_sent 819150966 # cumulative count of insts sent to commit 887system.cpu.iew.wb_count 817050997 # cumulative count of insts written-back 888system.cpu.iew.wb_producers 638575855 # num instructions producing a value 889system.cpu.iew.wb_consumers 1043882621 # num instructions consuming a value |
| 892system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 890system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 893system.cpu.iew.wb_rate 1.800260 # insts written-back per cycle 894system.cpu.iew.wb_fanout 0.611736 # average fanout of values written-back | 891system.cpu.iew.wb_rate 1.800423 # insts written-back per cycle 892system.cpu.iew.wb_fanout 0.611731 # average fanout of values written-back |
| 895system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 893system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 896system.cpu.commit.commitSquashedInsts 19875138 # The number of squashed insts skipped by commit 897system.cpu.commit.commitNonSpecStalls 1054679 # The number of times commit has been forced to stall to communicate backwards 898system.cpu.commit.branchMispredicts 892733 # The number of times a branch was mispredicted 899system.cpu.commit.committed_per_cycle::samples 259896554 # Number of insts commited each cycle 900system.cpu.commit.committed_per_cycle::mean 3.101438 # Number of insts commited each cycle 901system.cpu.commit.committed_per_cycle::stdev 2.863911 # Number of insts commited each cycle | 894system.cpu.commit.commitSquashedInsts 19994665 # The number of squashed insts skipped by commit 895system.cpu.commit.commitNonSpecStalls 1054506 # The number of times commit has been forced to stall to communicate backwards 896system.cpu.commit.branchMispredicts 892807 # The number of times a branch was mispredicted 897system.cpu.commit.committed_per_cycle::samples 259840554 # Number of insts commited each cycle 898system.cpu.commit.committed_per_cycle::mean 3.101913 # Number of insts commited each cycle 899system.cpu.commit.committed_per_cycle::stdev 2.863847 # Number of insts commited each cycle |
| 902system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 900system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 903system.cpu.commit.committed_per_cycle::0 88349043 33.99% 33.99% # Number of insts commited each cycle 904system.cpu.commit.committed_per_cycle::1 11862829 4.56% 38.56% # Number of insts commited each cycle 905system.cpu.commit.committed_per_cycle::2 3832305 1.47% 40.03% # Number of insts commited each cycle 906system.cpu.commit.committed_per_cycle::3 74754047 28.76% 68.80% # Number of insts commited each cycle 907system.cpu.commit.committed_per_cycle::4 2383630 0.92% 69.71% # Number of insts commited each cycle 908system.cpu.commit.committed_per_cycle::5 1474941 0.57% 70.28% # Number of insts commited each cycle 909system.cpu.commit.committed_per_cycle::6 857586 0.33% 70.61% # Number of insts commited each cycle 910system.cpu.commit.committed_per_cycle::7 70848784 27.26% 97.87% # Number of insts commited each cycle 911system.cpu.commit.committed_per_cycle::8 5533389 2.13% 100.00% # Number of insts commited each cycle | 901system.cpu.commit.committed_per_cycle::0 88304488 33.98% 33.98% # Number of insts commited each cycle 902system.cpu.commit.committed_per_cycle::1 11858711 4.56% 38.55% # Number of insts commited each cycle 903system.cpu.commit.committed_per_cycle::2 3833949 1.48% 40.02% # Number of insts commited each cycle 904system.cpu.commit.committed_per_cycle::3 74748511 28.77% 68.79% # Number of insts commited each cycle 905system.cpu.commit.committed_per_cycle::4 2384583 0.92% 69.71% # Number of insts commited each cycle 906system.cpu.commit.committed_per_cycle::5 1475819 0.57% 70.28% # Number of insts commited each cycle 907system.cpu.commit.committed_per_cycle::6 859128 0.33% 70.61% # Number of insts commited each cycle 908system.cpu.commit.committed_per_cycle::7 70844564 27.26% 97.87% # Number of insts commited each cycle 909system.cpu.commit.committed_per_cycle::8 5530801 2.13% 100.00% # Number of insts commited each cycle |
| 912system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 913system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 914system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 910system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 911system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 912system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 915system.cpu.commit.committed_per_cycle::total 259896554 # Number of insts commited each cycle 916system.cpu.commit.committedInsts 407772261 # Number of instructions committed 917system.cpu.commit.committedOps 806052921 # Number of ops (including micro ops) committed | 913system.cpu.commit.committed_per_cycle::total 259840554 # Number of insts commited each cycle 914system.cpu.commit.committedInsts 407751929 # Number of instructions committed 915system.cpu.commit.committedOps 806002693 # Number of ops (including micro ops) committed |
| 918system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 916system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 919system.cpu.commit.refs 22412414 # Number of memory references committed 920system.cpu.commit.loads 13990896 # Number of loads committed 921system.cpu.commit.membars 474709 # Number of memory barriers committed 922system.cpu.commit.branches 82160310 # Number of branches committed | 917system.cpu.commit.refs 22412111 # Number of memory references committed 918system.cpu.commit.loads 13990076 # Number of loads committed 919system.cpu.commit.membars 474663 # Number of memory barriers committed 920system.cpu.commit.branches 82157264 # Number of branches committed |
| 923system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. | 921system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. |
| 924system.cpu.commit.int_insts 734896243 # Number of committed integer instructions. 925system.cpu.commit.function_calls 1155289 # Number of function calls committed. 926system.cpu.commit.bw_lim_events 5533389 # number cycles where commit BW limit reached | 922system.cpu.commit.int_insts 734852381 # Number of committed integer instructions. 923system.cpu.commit.function_calls 1155163 # Number of function calls committed. 924system.cpu.commit.bw_lim_events 5530801 # number cycles where commit BW limit reached |
| 927system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 925system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 928system.cpu.rob.rob_reads 1080212949 # The number of ROB reads 929system.cpu.rob.rob_writes 1654925831 # The number of ROB writes 930system.cpu.timesIdled 1261862 # Number of times that the entire CPU went into an idle state and unscheduled itself 931system.cpu.idleCycles 190890238 # Total number of cycles that the CPU has spent unscheduled due to idling 932system.cpu.quiesceCycles 9814027971 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 933system.cpu.committedInsts 407772261 # Number of Instructions Simulated 934system.cpu.committedOps 806052921 # Number of Ops (including micro ops) Simulated 935system.cpu.committedInsts_total 407772261 # Number of Instructions Simulated 936system.cpu.cpi 1.112979 # CPI: Cycles Per Instruction 937system.cpu.cpi_total 1.112979 # CPI: Total CPI of All Threads 938system.cpu.ipc 0.898490 # IPC: Instructions Per Cycle 939system.cpu.ipc_total 0.898490 # IPC: Total IPC of All Threads 940system.cpu.int_regfile_reads 1088746320 # number of integer regfile reads 941system.cpu.int_regfile_writes 653799671 # number of integer regfile writes 942system.cpu.fp_regfile_reads 52 # number of floating regfile reads 943system.cpu.cc_regfile_reads 415603862 # number of cc regfile reads 944system.cpu.cc_regfile_writes 321491324 # number of cc regfile writes 945system.cpu.misc_regfile_reads 264059604 # number of misc regfile reads 946system.cpu.misc_regfile_writes 402440 # number of misc regfile writes 947system.cpu.toL2Bus.throughput 53738291 # Throughput (bytes/s) 948system.cpu.toL2Bus.trans_dist::ReadReq 3018879 # Transaction distribution 949system.cpu.toL2Bus.trans_dist::ReadResp 3018337 # Transaction distribution 950system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::Writeback 1585586 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::UpgradeReq 2261 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::UpgradeResp 2261 # Transaction distribution 955system.cpu.toL2Bus.trans_dist::ReadExReq 334835 # Transaction distribution 956system.cpu.toL2Bus.trans_dist::ReadExResp 288140 # Transaction distribution 957system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution 958system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919324 # Packet count per connected master and slave (bytes) 959system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6124632 # Packet count per connected master and slave (bytes) 960system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18318 # Packet count per connected master and slave (bytes) 961system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159709 # Packet count per connected master and slave (bytes) 962system.cpu.toL2Bus.pkt_count::total 8221983 # Packet count per connected master and slave (bytes) 963system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61414400 # Cumulative packet size per connected master and slave (bytes) 964system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207642981 # Cumulative packet size per connected master and slave (bytes) 965system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 603136 # Cumulative packet size per connected master and slave (bytes) 966system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5731328 # Cumulative packet size per connected master and slave (bytes) 967system.cpu.toL2Bus.tot_pkt_size::total 275391845 # Cumulative packet size per connected master and slave (bytes) 968system.cpu.toL2Bus.data_through_bus 275366117 # Total data (bytes) 969system.cpu.toL2Bus.snoop_data_through_bus 522624 # Total snoop data (bytes) 970system.cpu.toL2Bus.reqLayer0.occupancy 4046374411 # Layer occupancy (ticks) | 926system.cpu.rob.rob_reads 1080228878 # The number of ROB reads 927system.cpu.rob.rob_writes 1655077473 # The number of ROB writes 928system.cpu.timesIdled 1260592 # Number of times that the entire CPU went into an idle state and unscheduled itself 929system.cpu.idleCycles 190901851 # Total number of cycles that the CPU has spent unscheduled due to idling 930system.cpu.quiesceCycles 9814061063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 931system.cpu.committedInsts 407751929 # Number of Instructions Simulated 932system.cpu.committedOps 806002693 # Number of Ops (including micro ops) Simulated 933system.cpu.committedInsts_total 407751929 # Number of Instructions Simulated 934system.cpu.cpi 1.112958 # CPI: Cycles Per Instruction 935system.cpu.cpi_total 1.112958 # CPI: Total CPI of All Threads 936system.cpu.ipc 0.898507 # IPC: Instructions Per Cycle 937system.cpu.ipc_total 0.898507 # IPC: Total IPC of All Threads 938system.cpu.int_regfile_reads 1088763208 # number of integer regfile reads 939system.cpu.int_regfile_writes 653821136 # number of integer regfile writes 940system.cpu.fp_regfile_reads 54 # number of floating regfile reads 941system.cpu.cc_regfile_reads 415622850 # number of cc regfile reads 942system.cpu.cc_regfile_writes 321492626 # number of cc regfile writes 943system.cpu.misc_regfile_reads 264082516 # number of misc regfile reads 944system.cpu.misc_regfile_writes 402300 # number of misc regfile writes 945system.cpu.toL2Bus.throughput 53661983 # Throughput (bytes/s) 946system.cpu.toL2Bus.trans_dist::ReadReq 3016761 # Transaction distribution 947system.cpu.toL2Bus.trans_dist::ReadResp 3016231 # Transaction distribution 948system.cpu.toL2Bus.trans_dist::WriteReq 13762 # Transaction distribution 949system.cpu.toL2Bus.trans_dist::WriteResp 13762 # Transaction distribution 950system.cpu.toL2Bus.trans_dist::Writeback 1581663 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::UpgradeReq 2241 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::UpgradeResp 2241 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::ReadExReq 334732 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::ReadExResp 288041 # Transaction distribution 955system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution 956system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916491 # Packet count per connected master and slave (bytes) 957system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123200 # Packet count per connected master and slave (bytes) 958system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19443 # Packet count per connected master and slave (bytes) 959system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154439 # Packet count per connected master and slave (bytes) 960system.cpu.toL2Bus.pkt_count::total 8213573 # Packet count per connected master and slave (bytes) 961system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61324288 # Cumulative packet size per connected master and slave (bytes) 962system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207594695 # Cumulative packet size per connected master and slave (bytes) 963system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 616960 # Cumulative packet size per connected master and slave (bytes) 964system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5463872 # Cumulative packet size per connected master and slave (bytes) 965system.cpu.toL2Bus.tot_pkt_size::total 274999815 # Cumulative packet size per connected master and slave (bytes) 966system.cpu.toL2Bus.data_through_bus 274973191 # Total data (bytes) 967system.cpu.toL2Bus.snoop_data_through_bus 523840 # Total snoop data (bytes) 968system.cpu.toL2Bus.reqLayer0.occupancy 4039348922 # Layer occupancy (ticks) |
| 971system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 969system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 972system.cpu.toL2Bus.snoopLayer0.occupancy 603000 # Layer occupancy (ticks) | 970system.cpu.toL2Bus.snoopLayer0.occupancy 624000 # Layer occupancy (ticks) |
| 973system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 971system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 974system.cpu.toL2Bus.respLayer0.occupancy 1442983054 # Layer occupancy (ticks) | 972system.cpu.toL2Bus.respLayer0.occupancy 1440815600 # Layer occupancy (ticks) |
| 975system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 973system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 976system.cpu.toL2Bus.respLayer1.occupancy 3140518579 # Layer occupancy (ticks) | 974system.cpu.toL2Bus.respLayer1.occupancy 3139539816 # Layer occupancy (ticks) |
| 977system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 975system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 978system.cpu.toL2Bus.respLayer2.occupancy 13344744 # Layer occupancy (ticks) | 976system.cpu.toL2Bus.respLayer2.occupancy 14707994 # Layer occupancy (ticks) |
| 979system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 977system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 980system.cpu.toL2Bus.respLayer3.occupancy 105297384 # Layer occupancy (ticks) | 978system.cpu.toL2Bus.respLayer3.occupancy 103656142 # Layer occupancy (ticks) |
| 981system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 979system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 982system.cpu.icache.tags.replacements 959142 # number of replacements 983system.cpu.icache.tags.tagsinuse 509.299647 # Cycle average of tags in use 984system.cpu.icache.tags.total_refs 7468451 # Total number of references to valid blocks. 985system.cpu.icache.tags.sampled_refs 959654 # Sample count of references to valid blocks. 986system.cpu.icache.tags.avg_refs 7.782441 # Average number of references to valid blocks. | 980system.cpu.icache.tags.replacements 957724 # number of replacements 981system.cpu.icache.tags.tagsinuse 509.254964 # Cycle average of tags in use 982system.cpu.icache.tags.total_refs 7477774 # Total number of references to valid blocks. 983system.cpu.icache.tags.sampled_refs 958236 # Sample count of references to valid blocks. 984system.cpu.icache.tags.avg_refs 7.803687 # Average number of references to valid blocks. |
| 987system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit. | 985system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit. |
| 988system.cpu.icache.tags.occ_blocks::cpu.inst 509.299647 # Average occupied blocks per requestor 989system.cpu.icache.tags.occ_percent::cpu.inst 0.994726 # Average percentage of cache occupancy 990system.cpu.icache.tags.occ_percent::total 0.994726 # Average percentage of cache occupancy 991system.cpu.icache.ReadReq_hits::cpu.inst 7468451 # number of ReadReq hits 992system.cpu.icache.ReadReq_hits::total 7468451 # number of ReadReq hits 993system.cpu.icache.demand_hits::cpu.inst 7468451 # number of demand (read+write) hits 994system.cpu.icache.demand_hits::total 7468451 # number of demand (read+write) hits 995system.cpu.icache.overall_hits::cpu.inst 7468451 # number of overall hits 996system.cpu.icache.overall_hits::total 7468451 # number of overall hits 997system.cpu.icache.ReadReq_misses::cpu.inst 1013022 # number of ReadReq misses 998system.cpu.icache.ReadReq_misses::total 1013022 # number of ReadReq misses 999system.cpu.icache.demand_misses::cpu.inst 1013022 # number of demand (read+write) misses 1000system.cpu.icache.demand_misses::total 1013022 # number of demand (read+write) misses 1001system.cpu.icache.overall_misses::cpu.inst 1013022 # number of overall misses 1002system.cpu.icache.overall_misses::total 1013022 # number of overall misses 1003system.cpu.icache.ReadReq_miss_latency::cpu.inst 14172498740 # number of ReadReq miss cycles 1004system.cpu.icache.ReadReq_miss_latency::total 14172498740 # number of ReadReq miss cycles 1005system.cpu.icache.demand_miss_latency::cpu.inst 14172498740 # number of demand (read+write) miss cycles 1006system.cpu.icache.demand_miss_latency::total 14172498740 # number of demand (read+write) miss cycles 1007system.cpu.icache.overall_miss_latency::cpu.inst 14172498740 # number of overall miss cycles 1008system.cpu.icache.overall_miss_latency::total 14172498740 # number of overall miss cycles 1009system.cpu.icache.ReadReq_accesses::cpu.inst 8481473 # number of ReadReq accesses(hits+misses) 1010system.cpu.icache.ReadReq_accesses::total 8481473 # number of ReadReq accesses(hits+misses) 1011system.cpu.icache.demand_accesses::cpu.inst 8481473 # number of demand (read+write) accesses 1012system.cpu.icache.demand_accesses::total 8481473 # number of demand (read+write) accesses 1013system.cpu.icache.overall_accesses::cpu.inst 8481473 # number of overall (read+write) accesses 1014system.cpu.icache.overall_accesses::total 8481473 # number of overall (read+write) accesses 1015system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119439 # miss rate for ReadReq accesses 1016system.cpu.icache.ReadReq_miss_rate::total 0.119439 # miss rate for ReadReq accesses 1017system.cpu.icache.demand_miss_rate::cpu.inst 0.119439 # miss rate for demand accesses 1018system.cpu.icache.demand_miss_rate::total 0.119439 # miss rate for demand accesses 1019system.cpu.icache.overall_miss_rate::cpu.inst 0.119439 # miss rate for overall accesses 1020system.cpu.icache.overall_miss_rate::total 0.119439 # miss rate for overall accesses 1021system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13990.316834 # average ReadReq miss latency 1022system.cpu.icache.ReadReq_avg_miss_latency::total 13990.316834 # average ReadReq miss latency 1023system.cpu.icache.demand_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency 1024system.cpu.icache.demand_avg_miss_latency::total 13990.316834 # average overall miss latency 1025system.cpu.icache.overall_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency 1026system.cpu.icache.overall_avg_miss_latency::total 13990.316834 # average overall miss latency 1027system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked | 986system.cpu.icache.tags.occ_blocks::cpu.inst 509.254964 # Average occupied blocks per requestor 987system.cpu.icache.tags.occ_percent::cpu.inst 0.994639 # Average percentage of cache occupancy 988system.cpu.icache.tags.occ_percent::total 0.994639 # Average percentage of cache occupancy 989system.cpu.icache.ReadReq_hits::cpu.inst 7477774 # number of ReadReq hits 990system.cpu.icache.ReadReq_hits::total 7477774 # number of ReadReq hits 991system.cpu.icache.demand_hits::cpu.inst 7477774 # number of demand (read+write) hits 992system.cpu.icache.demand_hits::total 7477774 # number of demand (read+write) hits 993system.cpu.icache.overall_hits::cpu.inst 7477774 # number of overall hits 994system.cpu.icache.overall_hits::total 7477774 # number of overall hits 995system.cpu.icache.ReadReq_misses::cpu.inst 1011731 # number of ReadReq misses 996system.cpu.icache.ReadReq_misses::total 1011731 # number of ReadReq misses 997system.cpu.icache.demand_misses::cpu.inst 1011731 # number of demand (read+write) misses 998system.cpu.icache.demand_misses::total 1011731 # number of demand (read+write) misses 999system.cpu.icache.overall_misses::cpu.inst 1011731 # number of overall misses 1000system.cpu.icache.overall_misses::total 1011731 # number of overall misses 1001system.cpu.icache.ReadReq_miss_latency::cpu.inst 14180716030 # number of ReadReq miss cycles 1002system.cpu.icache.ReadReq_miss_latency::total 14180716030 # number of ReadReq miss cycles 1003system.cpu.icache.demand_miss_latency::cpu.inst 14180716030 # number of demand (read+write) miss cycles 1004system.cpu.icache.demand_miss_latency::total 14180716030 # number of demand (read+write) miss cycles 1005system.cpu.icache.overall_miss_latency::cpu.inst 14180716030 # number of overall miss cycles 1006system.cpu.icache.overall_miss_latency::total 14180716030 # number of overall miss cycles 1007system.cpu.icache.ReadReq_accesses::cpu.inst 8489505 # number of ReadReq accesses(hits+misses) 1008system.cpu.icache.ReadReq_accesses::total 8489505 # number of ReadReq accesses(hits+misses) 1009system.cpu.icache.demand_accesses::cpu.inst 8489505 # number of demand (read+write) accesses 1010system.cpu.icache.demand_accesses::total 8489505 # number of demand (read+write) accesses 1011system.cpu.icache.overall_accesses::cpu.inst 8489505 # number of overall (read+write) accesses 1012system.cpu.icache.overall_accesses::total 8489505 # number of overall (read+write) accesses 1013system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119174 # miss rate for ReadReq accesses 1014system.cpu.icache.ReadReq_miss_rate::total 0.119174 # miss rate for ReadReq accesses 1015system.cpu.icache.demand_miss_rate::cpu.inst 0.119174 # miss rate for demand accesses 1016system.cpu.icache.demand_miss_rate::total 0.119174 # miss rate for demand accesses 1017system.cpu.icache.overall_miss_rate::cpu.inst 0.119174 # miss rate for overall accesses 1018system.cpu.icache.overall_miss_rate::total 0.119174 # miss rate for overall accesses 1019system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.290921 # average ReadReq miss latency 1020system.cpu.icache.ReadReq_avg_miss_latency::total 14016.290921 # average ReadReq miss latency 1021system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency 1022system.cpu.icache.demand_avg_miss_latency::total 14016.290921 # average overall miss latency 1023system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency 1024system.cpu.icache.overall_avg_miss_latency::total 14016.290921 # average overall miss latency 1025system.cpu.icache.blocked_cycles::no_mshrs 5333 # number of cycles access was blocked |
| 1028system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1026system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1029system.cpu.icache.blocked::no_mshrs 172 # number of cycles access was blocked | 1027system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked |
| 1030system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 1028system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1031system.cpu.icache.avg_blocked_cycles::no_mshrs 26.023256 # average number of cycles each access was blocked | 1029system.cpu.icache.avg_blocked_cycles::no_mshrs 28.827027 # average number of cycles each access was blocked |
| 1032system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1033system.cpu.icache.fast_writes 0 # number of fast writes performed 1034system.cpu.icache.cache_copies 0 # number of cache copies performed | 1030system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1031system.cpu.icache.fast_writes 0 # number of fast writes performed 1032system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 1035system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53298 # number of ReadReq MSHR hits 1036system.cpu.icache.ReadReq_mshr_hits::total 53298 # number of ReadReq MSHR hits 1037system.cpu.icache.demand_mshr_hits::cpu.inst 53298 # number of demand (read+write) MSHR hits 1038system.cpu.icache.demand_mshr_hits::total 53298 # number of demand (read+write) MSHR hits 1039system.cpu.icache.overall_mshr_hits::cpu.inst 53298 # number of overall MSHR hits 1040system.cpu.icache.overall_mshr_hits::total 53298 # number of overall MSHR hits 1041system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959724 # number of ReadReq MSHR misses 1042system.cpu.icache.ReadReq_mshr_misses::total 959724 # number of ReadReq MSHR misses 1043system.cpu.icache.demand_mshr_misses::cpu.inst 959724 # number of demand (read+write) MSHR misses 1044system.cpu.icache.demand_mshr_misses::total 959724 # number of demand (read+write) MSHR misses 1045system.cpu.icache.overall_mshr_misses::cpu.inst 959724 # number of overall MSHR misses 1046system.cpu.icache.overall_mshr_misses::total 959724 # number of overall MSHR misses 1047system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11694537694 # number of ReadReq MSHR miss cycles 1048system.cpu.icache.ReadReq_mshr_miss_latency::total 11694537694 # number of ReadReq MSHR miss cycles 1049system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11694537694 # number of demand (read+write) MSHR miss cycles 1050system.cpu.icache.demand_mshr_miss_latency::total 11694537694 # number of demand (read+write) MSHR miss cycles 1051system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11694537694 # number of overall MSHR miss cycles 1052system.cpu.icache.overall_mshr_miss_latency::total 11694537694 # number of overall MSHR miss cycles 1053system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for ReadReq accesses 1054system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113155 # mshr miss rate for ReadReq accesses 1055system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for demand accesses 1056system.cpu.icache.demand_mshr_miss_rate::total 0.113155 # mshr miss rate for demand accesses 1057system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for overall accesses 1058system.cpu.icache.overall_mshr_miss_rate::total 0.113155 # mshr miss rate for overall accesses 1059system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12185.313376 # average ReadReq mshr miss latency 1060system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12185.313376 # average ReadReq mshr miss latency 1061system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency 1062system.cpu.icache.demand_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency 1063system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency 1064system.cpu.icache.overall_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency | 1033system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53432 # number of ReadReq MSHR hits 1034system.cpu.icache.ReadReq_mshr_hits::total 53432 # number of ReadReq MSHR hits 1035system.cpu.icache.demand_mshr_hits::cpu.inst 53432 # number of demand (read+write) MSHR hits 1036system.cpu.icache.demand_mshr_hits::total 53432 # number of demand (read+write) MSHR hits 1037system.cpu.icache.overall_mshr_hits::cpu.inst 53432 # number of overall MSHR hits 1038system.cpu.icache.overall_mshr_hits::total 53432 # number of overall MSHR hits 1039system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958299 # number of ReadReq MSHR misses 1040system.cpu.icache.ReadReq_mshr_misses::total 958299 # number of ReadReq MSHR misses 1041system.cpu.icache.demand_mshr_misses::cpu.inst 958299 # number of demand (read+write) MSHR misses 1042system.cpu.icache.demand_mshr_misses::total 958299 # number of demand (read+write) MSHR misses 1043system.cpu.icache.overall_mshr_misses::cpu.inst 958299 # number of overall MSHR misses 1044system.cpu.icache.overall_mshr_misses::total 958299 # number of overall MSHR misses 1045system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11693776143 # number of ReadReq MSHR miss cycles 1046system.cpu.icache.ReadReq_mshr_miss_latency::total 11693776143 # number of ReadReq MSHR miss cycles 1047system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11693776143 # number of demand (read+write) MSHR miss cycles 1048system.cpu.icache.demand_mshr_miss_latency::total 11693776143 # number of demand (read+write) MSHR miss cycles 1049system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11693776143 # number of overall MSHR miss cycles 1050system.cpu.icache.overall_mshr_miss_latency::total 11693776143 # number of overall MSHR miss cycles 1051system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for ReadReq accesses 1052system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112880 # mshr miss rate for ReadReq accesses 1053system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for demand accesses 1054system.cpu.icache.demand_mshr_miss_rate::total 0.112880 # mshr miss rate for demand accesses 1055system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for overall accesses 1056system.cpu.icache.overall_mshr_miss_rate::total 0.112880 # mshr miss rate for overall accesses 1057system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12202.638365 # average ReadReq mshr miss latency 1058system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12202.638365 # average ReadReq mshr miss latency 1059system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency 1060system.cpu.icache.demand_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency 1061system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency 1062system.cpu.icache.overall_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency |
| 1065system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1063system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1066system.cpu.itb_walker_cache.tags.replacements 8004 # number of replacements 1067system.cpu.itb_walker_cache.tags.tagsinuse 6.959011 # Cycle average of tags in use 1068system.cpu.itb_walker_cache.tags.total_refs 21893 # Total number of references to valid blocks. 1069system.cpu.itb_walker_cache.tags.sampled_refs 8020 # Sample count of references to valid blocks. 1070system.cpu.itb_walker_cache.tags.avg_refs 2.729800 # Average number of references to valid blocks. 1071system.cpu.itb_walker_cache.tags.warmup_cycle 5103903665500 # Cycle when the warmup percentage was hit. 1072system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.959011 # Average occupied blocks per requestor 1073system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.434938 # Average percentage of cache occupancy 1074system.cpu.itb_walker_cache.tags.occ_percent::total 0.434938 # Average percentage of cache occupancy 1075system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21891 # number of ReadReq hits 1076system.cpu.itb_walker_cache.ReadReq_hits::total 21891 # number of ReadReq hits | 1064system.cpu.itb_walker_cache.tags.replacements 8926 # number of replacements 1065system.cpu.itb_walker_cache.tags.tagsinuse 6.004704 # Cycle average of tags in use 1066system.cpu.itb_walker_cache.tags.total_refs 20407 # Total number of references to valid blocks. 1067system.cpu.itb_walker_cache.tags.sampled_refs 8940 # Sample count of references to valid blocks. 1068system.cpu.itb_walker_cache.tags.avg_refs 2.282662 # Average number of references to valid blocks. 1069system.cpu.itb_walker_cache.tags.warmup_cycle 5105549292500 # Cycle when the warmup percentage was hit. 1070system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.004704 # Average occupied blocks per requestor 1071system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375294 # Average percentage of cache occupancy 1072system.cpu.itb_walker_cache.tags.occ_percent::total 0.375294 # Average percentage of cache occupancy 1073system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20415 # number of ReadReq hits 1074system.cpu.itb_walker_cache.ReadReq_hits::total 20415 # number of ReadReq hits |
| 1077system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 1078system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 1075system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 1076system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 1079system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21893 # number of demand (read+write) hits 1080system.cpu.itb_walker_cache.demand_hits::total 21893 # number of demand (read+write) hits 1081system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21893 # number of overall hits 1082system.cpu.itb_walker_cache.overall_hits::total 21893 # number of overall hits 1083system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8894 # number of ReadReq misses 1084system.cpu.itb_walker_cache.ReadReq_misses::total 8894 # number of ReadReq misses 1085system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8894 # number of demand (read+write) misses 1086system.cpu.itb_walker_cache.demand_misses::total 8894 # number of demand (read+write) misses 1087system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8894 # number of overall misses 1088system.cpu.itb_walker_cache.overall_misses::total 8894 # number of overall misses 1089system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 101842497 # number of ReadReq miss cycles 1090system.cpu.itb_walker_cache.ReadReq_miss_latency::total 101842497 # number of ReadReq miss cycles 1091system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 101842497 # number of demand (read+write) miss cycles 1092system.cpu.itb_walker_cache.demand_miss_latency::total 101842497 # number of demand (read+write) miss cycles 1093system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 101842497 # number of overall miss cycles 1094system.cpu.itb_walker_cache.overall_miss_latency::total 101842497 # number of overall miss cycles 1095system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30785 # number of ReadReq accesses(hits+misses) 1096system.cpu.itb_walker_cache.ReadReq_accesses::total 30785 # number of ReadReq accesses(hits+misses) | 1077system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20417 # number of demand (read+write) hits 1078system.cpu.itb_walker_cache.demand_hits::total 20417 # number of demand (read+write) hits 1079system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20417 # number of overall hits 1080system.cpu.itb_walker_cache.overall_hits::total 20417 # number of overall hits 1081system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9803 # number of ReadReq misses 1082system.cpu.itb_walker_cache.ReadReq_misses::total 9803 # number of ReadReq misses 1083system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9803 # number of demand (read+write) misses 1084system.cpu.itb_walker_cache.demand_misses::total 9803 # number of demand (read+write) misses 1085system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9803 # number of overall misses 1086system.cpu.itb_walker_cache.overall_misses::total 9803 # number of overall misses 1087system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 109186247 # number of ReadReq miss cycles 1088system.cpu.itb_walker_cache.ReadReq_miss_latency::total 109186247 # number of ReadReq miss cycles 1089system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 109186247 # number of demand (read+write) miss cycles 1090system.cpu.itb_walker_cache.demand_miss_latency::total 109186247 # number of demand (read+write) miss cycles 1091system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 109186247 # number of overall miss cycles 1092system.cpu.itb_walker_cache.overall_miss_latency::total 109186247 # number of overall miss cycles 1093system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30218 # number of ReadReq accesses(hits+misses) 1094system.cpu.itb_walker_cache.ReadReq_accesses::total 30218 # number of ReadReq accesses(hits+misses) |
| 1097system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1098system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 1095system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 1096system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 1099system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30787 # number of demand (read+write) accesses 1100system.cpu.itb_walker_cache.demand_accesses::total 30787 # number of demand (read+write) accesses 1101system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30787 # number of overall (read+write) accesses 1102system.cpu.itb_walker_cache.overall_accesses::total 30787 # number of overall (read+write) accesses 1103system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.288907 # miss rate for ReadReq accesses 1104system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.288907 # miss rate for ReadReq accesses 1105system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.288888 # miss rate for demand accesses 1106system.cpu.itb_walker_cache.demand_miss_rate::total 0.288888 # miss rate for demand accesses 1107system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.288888 # miss rate for overall accesses 1108system.cpu.itb_walker_cache.overall_miss_rate::total 0.288888 # miss rate for overall accesses 1109system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11450.696762 # average ReadReq miss latency 1110system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11450.696762 # average ReadReq miss latency 1111system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency 1112system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11450.696762 # average overall miss latency 1113system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency 1114system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11450.696762 # average overall miss latency | 1097system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30220 # number of demand (read+write) accesses 1098system.cpu.itb_walker_cache.demand_accesses::total 30220 # number of demand (read+write) accesses 1099system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30220 # number of overall (read+write) accesses 1100system.cpu.itb_walker_cache.overall_accesses::total 30220 # number of overall (read+write) accesses 1101system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.324409 # miss rate for ReadReq accesses 1102system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.324409 # miss rate for ReadReq accesses 1103system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.324388 # miss rate for demand accesses 1104system.cpu.itb_walker_cache.demand_miss_rate::total 0.324388 # miss rate for demand accesses 1105system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.324388 # miss rate for overall accesses 1106system.cpu.itb_walker_cache.overall_miss_rate::total 0.324388 # miss rate for overall accesses 1107system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11138.044170 # average ReadReq miss latency 1108system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11138.044170 # average ReadReq miss latency 1109system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency 1110system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11138.044170 # average overall miss latency 1111system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency 1112system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11138.044170 # average overall miss latency |
| 1115system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1116system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1117system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1118system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1119system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1120system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1121system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1122system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 1113system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1114system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1115system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1116system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1117system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1118system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1119system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1120system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 1123system.cpu.itb_walker_cache.writebacks::writebacks 2197 # number of writebacks 1124system.cpu.itb_walker_cache.writebacks::total 2197 # number of writebacks 1125system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8894 # number of ReadReq MSHR misses 1126system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses 1127system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8894 # number of demand (read+write) MSHR misses 1128system.cpu.itb_walker_cache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses 1129system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8894 # number of overall MSHR misses 1130system.cpu.itb_walker_cache.overall_mshr_misses::total 8894 # number of overall MSHR misses 1131system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 84047009 # number of ReadReq MSHR miss cycles 1132system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 84047009 # number of ReadReq MSHR miss cycles 1133system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 84047009 # number of demand (read+write) MSHR miss cycles 1134system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 84047009 # number of demand (read+write) MSHR miss cycles 1135system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 84047009 # number of overall MSHR miss cycles 1136system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 84047009 # number of overall MSHR miss cycles 1137system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.288907 # mshr miss rate for ReadReq accesses 1138system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.288907 # mshr miss rate for ReadReq accesses 1139system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for demand accesses 1140system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.288888 # mshr miss rate for demand accesses 1141system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for overall accesses 1142system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.288888 # mshr miss rate for overall accesses 1143system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average ReadReq mshr miss latency 1144system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9449.854846 # average ReadReq mshr miss latency 1145system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency 1146system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency 1147system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency 1148system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency | 1121system.cpu.itb_walker_cache.writebacks::writebacks 1993 # number of writebacks 1122system.cpu.itb_walker_cache.writebacks::total 1993 # number of writebacks 1123system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9803 # number of ReadReq MSHR misses 1124system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9803 # number of ReadReq MSHR misses 1125system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9803 # number of demand (read+write) MSHR misses 1126system.cpu.itb_walker_cache.demand_mshr_misses::total 9803 # number of demand (read+write) MSHR misses 1127system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9803 # number of overall MSHR misses 1128system.cpu.itb_walker_cache.overall_mshr_misses::total 9803 # number of overall MSHR misses 1129system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 89573259 # number of ReadReq MSHR miss cycles 1130system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 89573259 # number of ReadReq MSHR miss cycles 1131system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 89573259 # number of demand (read+write) MSHR miss cycles 1132system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 89573259 # number of demand (read+write) MSHR miss cycles 1133system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 89573259 # number of overall MSHR miss cycles 1134system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 89573259 # number of overall MSHR miss cycles 1135system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.324409 # mshr miss rate for ReadReq accesses 1136system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.324409 # mshr miss rate for ReadReq accesses 1137system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for demand accesses 1138system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.324388 # mshr miss rate for demand accesses 1139system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for overall accesses 1140system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.324388 # mshr miss rate for overall accesses 1141system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average ReadReq mshr miss latency 1142system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9137.331327 # average ReadReq mshr miss latency 1143system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency 1144system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency 1145system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency 1146system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency |
| 1149system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1147system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1150system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements 1151system.cpu.dtb_walker_cache.tags.tagsinuse 14.134079 # Cycle average of tags in use 1152system.cpu.dtb_walker_cache.tags.total_refs 90874 # Total number of references to valid blocks. 1153system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks. 1154system.cpu.dtb_walker_cache.tags.avg_refs 1.315737 # Average number of references to valid blocks. 1155system.cpu.dtb_walker_cache.tags.warmup_cycle 4994243678000 # Cycle when the warmup percentage was hit. 1156system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.134079 # Average occupied blocks per requestor 1157system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.883380 # Average percentage of cache occupancy 1158system.cpu.dtb_walker_cache.tags.occ_percent::total 0.883380 # Average percentage of cache occupancy 1159system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90874 # number of ReadReq hits 1160system.cpu.dtb_walker_cache.ReadReq_hits::total 90874 # number of ReadReq hits 1161system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90874 # number of demand (read+write) hits 1162system.cpu.dtb_walker_cache.demand_hits::total 90874 # number of demand (read+write) hits 1163system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90874 # number of overall hits 1164system.cpu.dtb_walker_cache.overall_hits::total 90874 # number of overall hits 1165system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70157 # number of ReadReq misses 1166system.cpu.dtb_walker_cache.ReadReq_misses::total 70157 # number of ReadReq misses 1167system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70157 # number of demand (read+write) misses 1168system.cpu.dtb_walker_cache.demand_misses::total 70157 # number of demand (read+write) misses 1169system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70157 # number of overall misses 1170system.cpu.dtb_walker_cache.overall_misses::total 70157 # number of overall misses 1171system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 871654701 # number of ReadReq miss cycles 1172system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 871654701 # number of ReadReq miss cycles 1173system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 871654701 # number of demand (read+write) miss cycles 1174system.cpu.dtb_walker_cache.demand_miss_latency::total 871654701 # number of demand (read+write) miss cycles 1175system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 871654701 # number of overall miss cycles 1176system.cpu.dtb_walker_cache.overall_miss_latency::total 871654701 # number of overall miss cycles 1177system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161031 # number of ReadReq accesses(hits+misses) 1178system.cpu.dtb_walker_cache.ReadReq_accesses::total 161031 # number of ReadReq accesses(hits+misses) 1179system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161031 # number of demand (read+write) accesses 1180system.cpu.dtb_walker_cache.demand_accesses::total 161031 # number of demand (read+write) accesses 1181system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161031 # number of overall (read+write) accesses 1182system.cpu.dtb_walker_cache.overall_accesses::total 161031 # number of overall (read+write) accesses 1183system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435674 # miss rate for ReadReq accesses 1184system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435674 # miss rate for ReadReq accesses 1185system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435674 # miss rate for demand accesses 1186system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435674 # miss rate for demand accesses 1187system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435674 # miss rate for overall accesses 1188system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435674 # miss rate for overall accesses 1189system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.343986 # average ReadReq miss latency 1190system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.343986 # average ReadReq miss latency 1191system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency 1192system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.343986 # average overall miss latency 1193system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency 1194system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.343986 # average overall miss latency | 1148system.cpu.dtb_walker_cache.tags.replacements 68011 # number of replacements 1149system.cpu.dtb_walker_cache.tags.tagsinuse 14.842846 # Cycle average of tags in use 1150system.cpu.dtb_walker_cache.tags.total_refs 91726 # Total number of references to valid blocks. 1151system.cpu.dtb_walker_cache.tags.sampled_refs 68027 # Sample count of references to valid blocks. 1152system.cpu.dtb_walker_cache.tags.avg_refs 1.348376 # Average number of references to valid blocks. 1153system.cpu.dtb_walker_cache.tags.warmup_cycle 4994240386000 # Cycle when the warmup percentage was hit. 1154system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.842846 # Average occupied blocks per requestor 1155system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.927678 # Average percentage of cache occupancy 1156system.cpu.dtb_walker_cache.tags.occ_percent::total 0.927678 # Average percentage of cache occupancy 1157system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91726 # number of ReadReq hits 1158system.cpu.dtb_walker_cache.ReadReq_hits::total 91726 # number of ReadReq hits 1159system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91726 # number of demand (read+write) hits 1160system.cpu.dtb_walker_cache.demand_hits::total 91726 # number of demand (read+write) hits 1161system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 91726 # number of overall hits 1162system.cpu.dtb_walker_cache.overall_hits::total 91726 # number of overall hits 1163system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 69066 # number of ReadReq misses 1164system.cpu.dtb_walker_cache.ReadReq_misses::total 69066 # number of ReadReq misses 1165system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 69066 # number of demand (read+write) misses 1166system.cpu.dtb_walker_cache.demand_misses::total 69066 # number of demand (read+write) misses 1167system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 69066 # number of overall misses 1168system.cpu.dtb_walker_cache.overall_misses::total 69066 # number of overall misses 1169system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 860977213 # number of ReadReq miss cycles 1170system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 860977213 # number of ReadReq miss cycles 1171system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 860977213 # number of demand (read+write) miss cycles 1172system.cpu.dtb_walker_cache.demand_miss_latency::total 860977213 # number of demand (read+write) miss cycles 1173system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 860977213 # number of overall miss cycles 1174system.cpu.dtb_walker_cache.overall_miss_latency::total 860977213 # number of overall miss cycles 1175system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160792 # number of ReadReq accesses(hits+misses) 1176system.cpu.dtb_walker_cache.ReadReq_accesses::total 160792 # number of ReadReq accesses(hits+misses) 1177system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160792 # number of demand (read+write) accesses 1178system.cpu.dtb_walker_cache.demand_accesses::total 160792 # number of demand (read+write) accesses 1179system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160792 # number of overall (read+write) accesses 1180system.cpu.dtb_walker_cache.overall_accesses::total 160792 # number of overall (read+write) accesses 1181system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429536 # miss rate for ReadReq accesses 1182system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429536 # miss rate for ReadReq accesses 1183system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429536 # miss rate for demand accesses 1184system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429536 # miss rate for demand accesses 1185system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429536 # miss rate for overall accesses 1186system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429536 # miss rate for overall accesses 1187system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12466.006617 # average ReadReq miss latency 1188system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12466.006617 # average ReadReq miss latency 1189system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency 1190system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12466.006617 # average overall miss latency 1191system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency 1192system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12466.006617 # average overall miss latency |
| 1195system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1196system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1197system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1198system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1199system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1200system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1201system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1202system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 1193system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1194system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1195system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1196system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1197system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1198system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1199system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 1200system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 1203system.cpu.dtb_walker_cache.writebacks::writebacks 24645 # number of writebacks 1204system.cpu.dtb_walker_cache.writebacks::total 24645 # number of writebacks 1205system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70157 # number of ReadReq MSHR misses 1206system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70157 # number of ReadReq MSHR misses 1207system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70157 # number of demand (read+write) MSHR misses 1208system.cpu.dtb_walker_cache.demand_mshr_misses::total 70157 # number of demand (read+write) MSHR misses 1209system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70157 # number of overall MSHR misses 1210system.cpu.dtb_walker_cache.overall_mshr_misses::total 70157 # number of overall MSHR misses 1211system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 731216933 # number of ReadReq MSHR miss cycles 1212system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 731216933 # number of ReadReq MSHR miss cycles 1213system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 731216933 # number of demand (read+write) MSHR miss cycles 1214system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 731216933 # number of demand (read+write) MSHR miss cycles 1215system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 731216933 # number of overall MSHR miss cycles 1216system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 731216933 # number of overall MSHR miss cycles 1217system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for ReadReq accesses 1218system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435674 # mshr miss rate for ReadReq accesses 1219system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for demand accesses 1220system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435674 # mshr miss rate for demand accesses 1221system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for overall accesses 1222system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435674 # mshr miss rate for overall accesses 1223system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average ReadReq mshr miss latency 1224system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10422.579828 # average ReadReq mshr miss latency 1225system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency 1226system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency 1227system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency 1228system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency | 1201system.cpu.dtb_walker_cache.writebacks::writebacks 21216 # number of writebacks 1202system.cpu.dtb_walker_cache.writebacks::total 21216 # number of writebacks 1203system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 69066 # number of ReadReq MSHR misses 1204system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 69066 # number of ReadReq MSHR misses 1205system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 69066 # number of demand (read+write) MSHR misses 1206system.cpu.dtb_walker_cache.demand_mshr_misses::total 69066 # number of demand (read+write) MSHR misses 1207system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 69066 # number of overall MSHR misses 1208system.cpu.dtb_walker_cache.overall_mshr_misses::total 69066 # number of overall MSHR misses 1209system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 722730929 # number of ReadReq MSHR miss cycles 1210system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 722730929 # number of ReadReq MSHR miss cycles 1211system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 722730929 # number of demand (read+write) MSHR miss cycles 1212system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 722730929 # number of demand (read+write) MSHR miss cycles 1213system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 722730929 # number of overall MSHR miss cycles 1214system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 722730929 # number of overall MSHR miss cycles 1215system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for ReadReq accesses 1216system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429536 # mshr miss rate for ReadReq accesses 1217system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for demand accesses 1218system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429536 # mshr miss rate for demand accesses 1219system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for overall accesses 1220system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429536 # mshr miss rate for overall accesses 1221system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average ReadReq mshr miss latency 1222system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10464.351910 # average ReadReq mshr miss latency 1223system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency 1224system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency 1225system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency 1226system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency |
| 1229system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1227system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1230system.cpu.dcache.tags.replacements 1657437 # number of replacements 1231system.cpu.dcache.tags.tagsinuse 511.988912 # Cycle average of tags in use 1232system.cpu.dcache.tags.total_refs 18989388 # Total number of references to valid blocks. 1233system.cpu.dcache.tags.sampled_refs 1657949 # Sample count of references to valid blocks. 1234system.cpu.dcache.tags.avg_refs 11.453542 # Average number of references to valid blocks. | 1228system.cpu.dcache.tags.replacements 1656829 # number of replacements 1229system.cpu.dcache.tags.tagsinuse 511.997280 # Cycle average of tags in use 1230system.cpu.dcache.tags.total_refs 18997986 # Total number of references to valid blocks. 1231system.cpu.dcache.tags.sampled_refs 1657341 # Sample count of references to valid blocks. 1232system.cpu.dcache.tags.avg_refs 11.462931 # Average number of references to valid blocks. |
| 1235system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit. | 1233system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit. |
| 1236system.cpu.dcache.tags.occ_blocks::cpu.data 511.988912 # Average occupied blocks per requestor 1237system.cpu.dcache.tags.occ_percent::cpu.data 0.999978 # Average percentage of cache occupancy 1238system.cpu.dcache.tags.occ_percent::total 0.999978 # Average percentage of cache occupancy 1239system.cpu.dcache.ReadReq_hits::cpu.data 10890920 # number of ReadReq hits 1240system.cpu.dcache.ReadReq_hits::total 10890920 # number of ReadReq hits 1241system.cpu.dcache.WriteReq_hits::cpu.data 8095777 # number of WriteReq hits 1242system.cpu.dcache.WriteReq_hits::total 8095777 # number of WriteReq hits 1243system.cpu.dcache.demand_hits::cpu.data 18986697 # number of demand (read+write) hits 1244system.cpu.dcache.demand_hits::total 18986697 # number of demand (read+write) hits 1245system.cpu.dcache.overall_hits::cpu.data 18986697 # number of overall hits 1246system.cpu.dcache.overall_hits::total 18986697 # number of overall hits 1247system.cpu.dcache.ReadReq_misses::cpu.data 2234479 # number of ReadReq misses 1248system.cpu.dcache.ReadReq_misses::total 2234479 # number of ReadReq misses 1249system.cpu.dcache.WriteReq_misses::cpu.data 316198 # number of WriteReq misses 1250system.cpu.dcache.WriteReq_misses::total 316198 # number of WriteReq misses 1251system.cpu.dcache.demand_misses::cpu.data 2550677 # number of demand (read+write) misses 1252system.cpu.dcache.demand_misses::total 2550677 # number of demand (read+write) misses 1253system.cpu.dcache.overall_misses::cpu.data 2550677 # number of overall misses 1254system.cpu.dcache.overall_misses::total 2550677 # number of overall misses 1255system.cpu.dcache.ReadReq_miss_latency::cpu.data 33004921637 # number of ReadReq miss cycles 1256system.cpu.dcache.ReadReq_miss_latency::total 33004921637 # number of ReadReq miss cycles 1257system.cpu.dcache.WriteReq_miss_latency::cpu.data 12257889032 # number of WriteReq miss cycles 1258system.cpu.dcache.WriteReq_miss_latency::total 12257889032 # number of WriteReq miss cycles 1259system.cpu.dcache.demand_miss_latency::cpu.data 45262810669 # number of demand (read+write) miss cycles 1260system.cpu.dcache.demand_miss_latency::total 45262810669 # number of demand (read+write) miss cycles 1261system.cpu.dcache.overall_miss_latency::cpu.data 45262810669 # number of overall miss cycles 1262system.cpu.dcache.overall_miss_latency::total 45262810669 # number of overall miss cycles 1263system.cpu.dcache.ReadReq_accesses::cpu.data 13125399 # number of ReadReq accesses(hits+misses) 1264system.cpu.dcache.ReadReq_accesses::total 13125399 # number of ReadReq accesses(hits+misses) 1265system.cpu.dcache.WriteReq_accesses::cpu.data 8411975 # number of WriteReq accesses(hits+misses) 1266system.cpu.dcache.WriteReq_accesses::total 8411975 # number of WriteReq accesses(hits+misses) 1267system.cpu.dcache.demand_accesses::cpu.data 21537374 # number of demand (read+write) accesses 1268system.cpu.dcache.demand_accesses::total 21537374 # number of demand (read+write) accesses 1269system.cpu.dcache.overall_accesses::cpu.data 21537374 # number of overall (read+write) accesses 1270system.cpu.dcache.overall_accesses::total 21537374 # number of overall (read+write) accesses 1271system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170241 # miss rate for ReadReq accesses 1272system.cpu.dcache.ReadReq_miss_rate::total 0.170241 # miss rate for ReadReq accesses 1273system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037589 # miss rate for WriteReq accesses 1274system.cpu.dcache.WriteReq_miss_rate::total 0.037589 # miss rate for WriteReq accesses 1275system.cpu.dcache.demand_miss_rate::cpu.data 0.118430 # miss rate for demand accesses 1276system.cpu.dcache.demand_miss_rate::total 0.118430 # miss rate for demand accesses 1277system.cpu.dcache.overall_miss_rate::cpu.data 0.118430 # miss rate for overall accesses 1278system.cpu.dcache.overall_miss_rate::total 0.118430 # miss rate for overall accesses 1279system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14770.745949 # average ReadReq miss latency 1280system.cpu.dcache.ReadReq_avg_miss_latency::total 14770.745949 # average ReadReq miss latency 1281system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38766.497676 # average WriteReq miss latency 1282system.cpu.dcache.WriteReq_avg_miss_latency::total 38766.497676 # average WriteReq miss latency 1283system.cpu.dcache.demand_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency 1284system.cpu.dcache.demand_avg_miss_latency::total 17745.410598 # average overall miss latency 1285system.cpu.dcache.overall_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency 1286system.cpu.dcache.overall_avg_miss_latency::total 17745.410598 # average overall miss latency 1287system.cpu.dcache.blocked_cycles::no_mshrs 397669 # number of cycles access was blocked | 1234system.cpu.dcache.tags.occ_blocks::cpu.data 511.997280 # Average occupied blocks per requestor 1235system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy 1236system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy 1237system.cpu.dcache.ReadReq_hits::cpu.data 10898836 # number of ReadReq hits 1238system.cpu.dcache.ReadReq_hits::total 10898836 # number of ReadReq hits 1239system.cpu.dcache.WriteReq_hits::cpu.data 8096443 # number of WriteReq hits 1240system.cpu.dcache.WriteReq_hits::total 8096443 # number of WriteReq hits 1241system.cpu.dcache.demand_hits::cpu.data 18995279 # number of demand (read+write) hits 1242system.cpu.dcache.demand_hits::total 18995279 # number of demand (read+write) hits 1243system.cpu.dcache.overall_hits::cpu.data 18995279 # number of overall hits 1244system.cpu.dcache.overall_hits::total 18995279 # number of overall hits 1245system.cpu.dcache.ReadReq_misses::cpu.data 2236048 # number of ReadReq misses 1246system.cpu.dcache.ReadReq_misses::total 2236048 # number of ReadReq misses 1247system.cpu.dcache.WriteReq_misses::cpu.data 316058 # number of WriteReq misses 1248system.cpu.dcache.WriteReq_misses::total 316058 # number of WriteReq misses 1249system.cpu.dcache.demand_misses::cpu.data 2552106 # number of demand (read+write) misses 1250system.cpu.dcache.demand_misses::total 2552106 # number of demand (read+write) misses 1251system.cpu.dcache.overall_misses::cpu.data 2552106 # number of overall misses 1252system.cpu.dcache.overall_misses::total 2552106 # number of overall misses 1253system.cpu.dcache.ReadReq_miss_latency::cpu.data 33041447208 # number of ReadReq miss cycles 1254system.cpu.dcache.ReadReq_miss_latency::total 33041447208 # number of ReadReq miss cycles 1255system.cpu.dcache.WriteReq_miss_latency::cpu.data 12234670517 # number of WriteReq miss cycles 1256system.cpu.dcache.WriteReq_miss_latency::total 12234670517 # number of WriteReq miss cycles 1257system.cpu.dcache.demand_miss_latency::cpu.data 45276117725 # number of demand (read+write) miss cycles 1258system.cpu.dcache.demand_miss_latency::total 45276117725 # number of demand (read+write) miss cycles 1259system.cpu.dcache.overall_miss_latency::cpu.data 45276117725 # number of overall miss cycles 1260system.cpu.dcache.overall_miss_latency::total 45276117725 # number of overall miss cycles 1261system.cpu.dcache.ReadReq_accesses::cpu.data 13134884 # number of ReadReq accesses(hits+misses) 1262system.cpu.dcache.ReadReq_accesses::total 13134884 # number of ReadReq accesses(hits+misses) 1263system.cpu.dcache.WriteReq_accesses::cpu.data 8412501 # number of WriteReq accesses(hits+misses) 1264system.cpu.dcache.WriteReq_accesses::total 8412501 # number of WriteReq accesses(hits+misses) 1265system.cpu.dcache.demand_accesses::cpu.data 21547385 # number of demand (read+write) accesses 1266system.cpu.dcache.demand_accesses::total 21547385 # number of demand (read+write) accesses 1267system.cpu.dcache.overall_accesses::cpu.data 21547385 # number of overall (read+write) accesses 1268system.cpu.dcache.overall_accesses::total 21547385 # number of overall (read+write) accesses 1269system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170237 # miss rate for ReadReq accesses 1270system.cpu.dcache.ReadReq_miss_rate::total 0.170237 # miss rate for ReadReq accesses 1271system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037570 # miss rate for WriteReq accesses 1272system.cpu.dcache.WriteReq_miss_rate::total 0.037570 # miss rate for WriteReq accesses 1273system.cpu.dcache.demand_miss_rate::cpu.data 0.118442 # miss rate for demand accesses 1274system.cpu.dcache.demand_miss_rate::total 0.118442 # miss rate for demand accesses 1275system.cpu.dcache.overall_miss_rate::cpu.data 0.118442 # miss rate for overall accesses 1276system.cpu.dcache.overall_miss_rate::total 0.118442 # miss rate for overall accesses 1277system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14776.716425 # average ReadReq miss latency 1278system.cpu.dcache.ReadReq_avg_miss_latency::total 14776.716425 # average ReadReq miss latency 1279system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38710.206725 # average WriteReq miss latency 1280system.cpu.dcache.WriteReq_avg_miss_latency::total 38710.206725 # average WriteReq miss latency 1281system.cpu.dcache.demand_avg_miss_latency::cpu.data 17740.688563 # average overall miss latency 1282system.cpu.dcache.demand_avg_miss_latency::total 17740.688563 # average overall miss latency 1283system.cpu.dcache.overall_avg_miss_latency::cpu.data 17740.688563 # average overall miss latency 1284system.cpu.dcache.overall_avg_miss_latency::total 17740.688563 # average overall miss latency 1285system.cpu.dcache.blocked_cycles::no_mshrs 395761 # number of cycles access was blocked |
| 1288system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1286system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1289system.cpu.dcache.blocked::no_mshrs 42042 # number of cycles access was blocked | 1287system.cpu.dcache.blocked::no_mshrs 42262 # number of cycles access was blocked |
| 1290system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1288system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1291system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.458851 # average number of cycles each access was blocked | 1289system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.364465 # average number of cycles each access was blocked |
| 1292system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1293system.cpu.dcache.fast_writes 0 # number of fast writes performed 1294system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1290system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1291system.cpu.dcache.fast_writes 0 # number of fast writes performed 1292system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1295system.cpu.dcache.writebacks::writebacks 1558744 # number of writebacks 1296system.cpu.dcache.writebacks::total 1558744 # number of writebacks 1297system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864490 # number of ReadReq MSHR hits 1298system.cpu.dcache.ReadReq_mshr_hits::total 864490 # number of ReadReq MSHR hits 1299system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25919 # number of WriteReq MSHR hits 1300system.cpu.dcache.WriteReq_mshr_hits::total 25919 # number of WriteReq MSHR hits 1301system.cpu.dcache.demand_mshr_hits::cpu.data 890409 # number of demand (read+write) MSHR hits 1302system.cpu.dcache.demand_mshr_hits::total 890409 # number of demand (read+write) MSHR hits 1303system.cpu.dcache.overall_mshr_hits::cpu.data 890409 # number of overall MSHR hits 1304system.cpu.dcache.overall_mshr_hits::total 890409 # number of overall MSHR hits 1305system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369989 # number of ReadReq MSHR misses 1306system.cpu.dcache.ReadReq_mshr_misses::total 1369989 # number of ReadReq MSHR misses 1307system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290279 # number of WriteReq MSHR misses 1308system.cpu.dcache.WriteReq_mshr_misses::total 290279 # number of WriteReq MSHR misses 1309system.cpu.dcache.demand_mshr_misses::cpu.data 1660268 # number of demand (read+write) MSHR misses 1310system.cpu.dcache.demand_mshr_misses::total 1660268 # number of demand (read+write) MSHR misses 1311system.cpu.dcache.overall_mshr_misses::cpu.data 1660268 # number of overall MSHR misses 1312system.cpu.dcache.overall_mshr_misses::total 1660268 # number of overall MSHR misses 1313system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17836083706 # number of ReadReq MSHR miss cycles 1314system.cpu.dcache.ReadReq_mshr_miss_latency::total 17836083706 # number of ReadReq MSHR miss cycles 1315system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11362753211 # number of WriteReq MSHR miss cycles 1316system.cpu.dcache.WriteReq_mshr_miss_latency::total 11362753211 # number of WriteReq MSHR miss cycles 1317system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29198836917 # number of demand (read+write) MSHR miss cycles 1318system.cpu.dcache.demand_mshr_miss_latency::total 29198836917 # number of demand (read+write) MSHR miss cycles 1319system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29198836917 # number of overall MSHR miss cycles 1320system.cpu.dcache.overall_mshr_miss_latency::total 29198836917 # number of overall MSHR miss cycles 1321system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364613500 # number of ReadReq MSHR uncacheable cycles 1322system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364613500 # number of ReadReq MSHR uncacheable cycles 1323system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538583500 # number of WriteReq MSHR uncacheable cycles 1324system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538583500 # number of WriteReq MSHR uncacheable cycles 1325system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903197000 # number of overall MSHR uncacheable cycles 1326system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903197000 # number of overall MSHR uncacheable cycles 1327system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses 1328system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses 1329system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034508 # mshr miss rate for WriteReq accesses 1330system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034508 # mshr miss rate for WriteReq accesses 1331system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses 1332system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses 1333system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses 1334system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses 1335system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13019.143735 # average ReadReq mshr miss latency 1336system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13019.143735 # average ReadReq mshr miss latency 1337system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39144.248158 # average WriteReq mshr miss latency 1338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39144.248158 # average WriteReq mshr miss latency 1339system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency 1340system.cpu.dcache.demand_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency 1341system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency 1342system.cpu.dcache.overall_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency | 1293system.cpu.dcache.writebacks::writebacks 1558454 # number of writebacks 1294system.cpu.dcache.writebacks::total 1558454 # number of writebacks 1295system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866560 # number of ReadReq MSHR hits 1296system.cpu.dcache.ReadReq_mshr_hits::total 866560 # number of ReadReq MSHR hits 1297system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25905 # number of WriteReq MSHR hits 1298system.cpu.dcache.WriteReq_mshr_hits::total 25905 # number of WriteReq MSHR hits 1299system.cpu.dcache.demand_mshr_hits::cpu.data 892465 # number of demand (read+write) MSHR hits 1300system.cpu.dcache.demand_mshr_hits::total 892465 # number of demand (read+write) MSHR hits 1301system.cpu.dcache.overall_mshr_hits::cpu.data 892465 # number of overall MSHR hits 1302system.cpu.dcache.overall_mshr_hits::total 892465 # number of overall MSHR hits 1303system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369488 # number of ReadReq MSHR misses 1304system.cpu.dcache.ReadReq_mshr_misses::total 1369488 # number of ReadReq MSHR misses 1305system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290153 # number of WriteReq MSHR misses 1306system.cpu.dcache.WriteReq_mshr_misses::total 290153 # number of WriteReq MSHR misses 1307system.cpu.dcache.demand_mshr_misses::cpu.data 1659641 # number of demand (read+write) MSHR misses 1308system.cpu.dcache.demand_mshr_misses::total 1659641 # number of demand (read+write) MSHR misses 1309system.cpu.dcache.overall_mshr_misses::cpu.data 1659641 # number of overall MSHR misses 1310system.cpu.dcache.overall_mshr_misses::total 1659641 # number of overall MSHR misses 1311system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17811534705 # number of ReadReq MSHR miss cycles 1312system.cpu.dcache.ReadReq_mshr_miss_latency::total 17811534705 # number of ReadReq MSHR miss cycles 1313system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11340798474 # number of WriteReq MSHR miss cycles 1314system.cpu.dcache.WriteReq_mshr_miss_latency::total 11340798474 # number of WriteReq MSHR miss cycles 1315system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29152333179 # number of demand (read+write) MSHR miss cycles 1316system.cpu.dcache.demand_mshr_miss_latency::total 29152333179 # number of demand (read+write) MSHR miss cycles 1317system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29152333179 # number of overall MSHR miss cycles 1318system.cpu.dcache.overall_mshr_miss_latency::total 29152333179 # number of overall MSHR miss cycles 1319system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363398000 # number of ReadReq MSHR uncacheable cycles 1320system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363398000 # number of ReadReq MSHR uncacheable cycles 1321system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536146500 # number of WriteReq MSHR uncacheable cycles 1322system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536146500 # number of WriteReq MSHR uncacheable cycles 1323system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99899544500 # number of overall MSHR uncacheable cycles 1324system.cpu.dcache.overall_mshr_uncacheable_latency::total 99899544500 # number of overall MSHR uncacheable cycles 1325system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104263 # mshr miss rate for ReadReq accesses 1326system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104263 # mshr miss rate for ReadReq accesses 1327system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034491 # mshr miss rate for WriteReq accesses 1328system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034491 # mshr miss rate for WriteReq accesses 1329system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077023 # mshr miss rate for demand accesses 1330system.cpu.dcache.demand_mshr_miss_rate::total 0.077023 # mshr miss rate for demand accesses 1331system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077023 # mshr miss rate for overall accesses 1332system.cpu.dcache.overall_mshr_miss_rate::total 0.077023 # mshr miss rate for overall accesses 1333system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.980852 # average ReadReq mshr miss latency 1334system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.980852 # average ReadReq mshr miss latency 1335system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39085.580621 # average WriteReq mshr miss latency 1336system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39085.580621 # average WriteReq mshr miss latency 1337system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17565.445285 # average overall mshr miss latency 1338system.cpu.dcache.demand_avg_mshr_miss_latency::total 17565.445285 # average overall mshr miss latency 1339system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17565.445285 # average overall mshr miss latency 1340system.cpu.dcache.overall_avg_mshr_miss_latency::total 17565.445285 # average overall mshr miss latency |
| 1343system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1344system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1345system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1346system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1347system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1348system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1349system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1341system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1342system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1343system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1344system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1345system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1346system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1347system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1350system.cpu.l2cache.tags.replacements 111632 # number of replacements 1351system.cpu.l2cache.tags.tagsinuse 64821.705622 # Cycle average of tags in use 1352system.cpu.l2cache.tags.total_refs 3786761 # Total number of references to valid blocks. 1353system.cpu.l2cache.tags.sampled_refs 175570 # Sample count of references to valid blocks. 1354system.cpu.l2cache.tags.avg_refs 21.568383 # Average number of references to valid blocks. | 1348system.cpu.l2cache.tags.replacements 111322 # number of replacements 1349system.cpu.l2cache.tags.tagsinuse 64824.350244 # Cycle average of tags in use 1350system.cpu.l2cache.tags.total_refs 3788284 # Total number of references to valid blocks. 1351system.cpu.l2cache.tags.sampled_refs 175285 # Sample count of references to valid blocks. 1352system.cpu.l2cache.tags.avg_refs 21.612140 # Average number of references to valid blocks. |
| 1355system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1353system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1356system.cpu.l2cache.tags.occ_blocks::writebacks 50709.515998 # Average occupied blocks per requestor 1357system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.756367 # Average occupied blocks per requestor 1358system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126012 # Average occupied blocks per requestor 1359system.cpu.l2cache.tags.occ_blocks::cpu.inst 3028.517183 # Average occupied blocks per requestor 1360system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.790063 # Average occupied blocks per requestor 1361system.cpu.l2cache.tags.occ_percent::writebacks 0.773766 # Average percentage of cache occupancy 1362system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000118 # Average percentage of cache occupancy | 1354system.cpu.l2cache.tags.occ_blocks::writebacks 50850.934653 # Average occupied blocks per requestor 1355system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.783858 # Average occupied blocks per requestor 1356system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126014 # Average occupied blocks per requestor 1357system.cpu.l2cache.tags.occ_blocks::cpu.inst 3002.561725 # Average occupied blocks per requestor 1358system.cpu.l2cache.tags.occ_blocks::cpu.data 10960.943994 # Average occupied blocks per requestor 1359system.cpu.l2cache.tags.occ_percent::writebacks 0.775924 # Average percentage of cache occupancy 1360system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000149 # Average percentage of cache occupancy |
| 1363system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 1361system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 1364system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046212 # Average percentage of cache occupancy 1365system.cpu.l2cache.tags.occ_percent::cpu.data 0.169003 # Average percentage of cache occupancy 1366system.cpu.l2cache.tags.occ_percent::total 0.989101 # Average percentage of cache occupancy 1367system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64846 # number of ReadReq hits 1368system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7222 # number of ReadReq hits 1369system.cpu.l2cache.ReadReq_hits::cpu.inst 943511 # number of ReadReq hits 1370system.cpu.l2cache.ReadReq_hits::cpu.data 1333169 # number of ReadReq hits 1371system.cpu.l2cache.ReadReq_hits::total 2348748 # number of ReadReq hits 1372system.cpu.l2cache.Writeback_hits::writebacks 1585586 # number of Writeback hits 1373system.cpu.l2cache.Writeback_hits::total 1585586 # number of Writeback hits 1374system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits 1375system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits 1376system.cpu.l2cache.ReadExReq_hits::cpu.data 155047 # number of ReadExReq hits 1377system.cpu.l2cache.ReadExReq_hits::total 155047 # number of ReadExReq hits 1378system.cpu.l2cache.demand_hits::cpu.dtb.walker 64846 # number of demand (read+write) hits 1379system.cpu.l2cache.demand_hits::cpu.itb.walker 7222 # number of demand (read+write) hits 1380system.cpu.l2cache.demand_hits::cpu.inst 943511 # number of demand (read+write) hits 1381system.cpu.l2cache.demand_hits::cpu.data 1488216 # number of demand (read+write) hits 1382system.cpu.l2cache.demand_hits::total 2503795 # number of demand (read+write) hits 1383system.cpu.l2cache.overall_hits::cpu.dtb.walker 64846 # number of overall hits 1384system.cpu.l2cache.overall_hits::cpu.itb.walker 7222 # number of overall hits 1385system.cpu.l2cache.overall_hits::cpu.inst 943511 # number of overall hits 1386system.cpu.l2cache.overall_hits::cpu.data 1488216 # number of overall hits 1387system.cpu.l2cache.overall_hits::total 2503795 # number of overall hits | 1362system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045815 # Average percentage of cache occupancy 1363system.cpu.l2cache.tags.occ_percent::cpu.data 0.167251 # Average percentage of cache occupancy 1364system.cpu.l2cache.tags.occ_percent::total 0.989141 # Average percentage of cache occupancy 1365system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64096 # number of ReadReq hits 1366system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7642 # number of ReadReq hits 1367system.cpu.l2cache.ReadReq_hits::cpu.inst 942107 # number of ReadReq hits 1368system.cpu.l2cache.ReadReq_hits::cpu.data 1332840 # number of ReadReq hits 1369system.cpu.l2cache.ReadReq_hits::total 2346685 # number of ReadReq hits 1370system.cpu.l2cache.Writeback_hits::writebacks 1581663 # number of Writeback hits 1371system.cpu.l2cache.Writeback_hits::total 1581663 # number of Writeback hits 1372system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits 1373system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits 1374system.cpu.l2cache.ReadExReq_hits::cpu.data 155094 # number of ReadExReq hits 1375system.cpu.l2cache.ReadExReq_hits::total 155094 # number of ReadExReq hits 1376system.cpu.l2cache.demand_hits::cpu.dtb.walker 64096 # number of demand (read+write) hits 1377system.cpu.l2cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits 1378system.cpu.l2cache.demand_hits::cpu.inst 942107 # number of demand (read+write) hits 1379system.cpu.l2cache.demand_hits::cpu.data 1487934 # number of demand (read+write) hits 1380system.cpu.l2cache.demand_hits::total 2501779 # number of demand (read+write) hits 1381system.cpu.l2cache.overall_hits::cpu.dtb.walker 64096 # number of overall hits 1382system.cpu.l2cache.overall_hits::cpu.itb.walker 7642 # number of overall hits 1383system.cpu.l2cache.overall_hits::cpu.inst 942107 # number of overall hits 1384system.cpu.l2cache.overall_hits::cpu.data 1487934 # number of overall hits 1385system.cpu.l2cache.overall_hits::total 2501779 # number of overall hits |
| 1388system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses 1389system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses | 1386system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses 1387system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses |
| 1390system.cpu.l2cache.ReadReq_misses::cpu.inst 16089 # number of ReadReq misses 1391system.cpu.l2cache.ReadReq_misses::cpu.data 36006 # number of ReadReq misses 1392system.cpu.l2cache.ReadReq_misses::total 52161 # number of ReadReq misses 1393system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses 1394system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses 1395system.cpu.l2cache.ReadExReq_misses::cpu.data 133062 # number of ReadExReq misses 1396system.cpu.l2cache.ReadExReq_misses::total 133062 # number of ReadExReq misses | 1388system.cpu.l2cache.ReadReq_misses::cpu.inst 16085 # number of ReadReq misses 1389system.cpu.l2cache.ReadReq_misses::cpu.data 35964 # number of ReadReq misses 1390system.cpu.l2cache.ReadReq_misses::total 52115 # number of ReadReq misses 1391system.cpu.l2cache.UpgradeReq_misses::cpu.data 1454 # number of UpgradeReq misses 1392system.cpu.l2cache.UpgradeReq_misses::total 1454 # number of UpgradeReq misses 1393system.cpu.l2cache.ReadExReq_misses::cpu.data 132906 # number of ReadExReq misses 1394system.cpu.l2cache.ReadExReq_misses::total 132906 # number of ReadExReq misses |
| 1397system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses 1398system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses | 1395system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses 1396system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses |
| 1399system.cpu.l2cache.demand_misses::cpu.inst 16089 # number of demand (read+write) misses 1400system.cpu.l2cache.demand_misses::cpu.data 169068 # number of demand (read+write) misses 1401system.cpu.l2cache.demand_misses::total 185223 # number of demand (read+write) misses | 1397system.cpu.l2cache.demand_misses::cpu.inst 16085 # number of demand (read+write) misses 1398system.cpu.l2cache.demand_misses::cpu.data 168870 # number of demand (read+write) misses 1399system.cpu.l2cache.demand_misses::total 185021 # number of demand (read+write) misses |
| 1402system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses 1403system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses | 1400system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses 1401system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses |
| 1404system.cpu.l2cache.overall_misses::cpu.inst 16089 # number of overall misses 1405system.cpu.l2cache.overall_misses::cpu.data 169068 # number of overall misses 1406system.cpu.l2cache.overall_misses::total 185223 # number of overall misses 1407system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5260500 # number of ReadReq miss cycles 1408system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389750 # number of ReadReq miss cycles 1409system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1277797734 # number of ReadReq miss cycles 1410system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940044940 # number of ReadReq miss cycles 1411system.cpu.l2cache.ReadReq_miss_latency::total 4223492924 # number of ReadReq miss cycles 1412system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17900790 # number of UpgradeReq miss cycles 1413system.cpu.l2cache.UpgradeReq_miss_latency::total 17900790 # number of UpgradeReq miss cycles 1414system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9477459899 # number of ReadExReq miss cycles 1415system.cpu.l2cache.ReadExReq_miss_latency::total 9477459899 # number of ReadExReq miss cycles 1416system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5260500 # number of demand (read+write) miss cycles 1417system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389750 # number of demand (read+write) miss cycles 1418system.cpu.l2cache.demand_miss_latency::cpu.inst 1277797734 # number of demand (read+write) miss cycles 1419system.cpu.l2cache.demand_miss_latency::cpu.data 12417504839 # number of demand (read+write) miss cycles 1420system.cpu.l2cache.demand_miss_latency::total 13700952823 # number of demand (read+write) miss cycles 1421system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5260500 # number of overall miss cycles 1422system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389750 # number of overall miss cycles 1423system.cpu.l2cache.overall_miss_latency::cpu.inst 1277797734 # number of overall miss cycles 1424system.cpu.l2cache.overall_miss_latency::cpu.data 12417504839 # number of overall miss cycles 1425system.cpu.l2cache.overall_miss_latency::total 13700952823 # number of overall miss cycles 1426system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64907 # number of ReadReq accesses(hits+misses) 1427system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7227 # number of ReadReq accesses(hits+misses) 1428system.cpu.l2cache.ReadReq_accesses::cpu.inst 959600 # number of ReadReq accesses(hits+misses) 1429system.cpu.l2cache.ReadReq_accesses::cpu.data 1369175 # number of ReadReq accesses(hits+misses) 1430system.cpu.l2cache.ReadReq_accesses::total 2400909 # number of ReadReq accesses(hits+misses) 1431system.cpu.l2cache.Writeback_accesses::writebacks 1585586 # number of Writeback accesses(hits+misses) 1432system.cpu.l2cache.Writeback_accesses::total 1585586 # number of Writeback accesses(hits+misses) 1433system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1776 # number of UpgradeReq accesses(hits+misses) 1434system.cpu.l2cache.UpgradeReq_accesses::total 1776 # number of UpgradeReq accesses(hits+misses) 1435system.cpu.l2cache.ReadExReq_accesses::cpu.data 288109 # number of ReadExReq accesses(hits+misses) 1436system.cpu.l2cache.ReadExReq_accesses::total 288109 # number of ReadExReq accesses(hits+misses) 1437system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64907 # number of demand (read+write) accesses 1438system.cpu.l2cache.demand_accesses::cpu.itb.walker 7227 # number of demand (read+write) accesses 1439system.cpu.l2cache.demand_accesses::cpu.inst 959600 # number of demand (read+write) accesses 1440system.cpu.l2cache.demand_accesses::cpu.data 1657284 # number of demand (read+write) accesses 1441system.cpu.l2cache.demand_accesses::total 2689018 # number of demand (read+write) accesses 1442system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64907 # number of overall (read+write) accesses 1443system.cpu.l2cache.overall_accesses::cpu.itb.walker 7227 # number of overall (read+write) accesses 1444system.cpu.l2cache.overall_accesses::cpu.inst 959600 # number of overall (read+write) accesses 1445system.cpu.l2cache.overall_accesses::cpu.data 1657284 # number of overall (read+write) accesses 1446system.cpu.l2cache.overall_accesses::total 2689018 # number of overall (read+write) accesses 1447system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000940 # miss rate for ReadReq accesses 1448system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000692 # miss rate for ReadReq accesses 1449system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016766 # miss rate for ReadReq accesses 1450system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026298 # miss rate for ReadReq accesses 1451system.cpu.l2cache.ReadReq_miss_rate::total 0.021726 # miss rate for ReadReq accesses 1452system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823198 # miss rate for UpgradeReq accesses 1453system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823198 # miss rate for UpgradeReq accesses 1454system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461846 # miss rate for ReadExReq accesses 1455system.cpu.l2cache.ReadExReq_miss_rate::total 0.461846 # miss rate for ReadExReq accesses 1456system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000940 # miss rate for demand accesses 1457system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000692 # miss rate for demand accesses 1458system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016766 # miss rate for demand accesses 1459system.cpu.l2cache.demand_miss_rate::cpu.data 0.102015 # miss rate for demand accesses 1460system.cpu.l2cache.demand_miss_rate::total 0.068881 # miss rate for demand accesses 1461system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000940 # miss rate for overall accesses 1462system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000692 # miss rate for overall accesses 1463system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016766 # miss rate for overall accesses 1464system.cpu.l2cache.overall_miss_rate::cpu.data 0.102015 # miss rate for overall accesses 1465system.cpu.l2cache.overall_miss_rate::total 0.068881 # miss rate for overall accesses 1466system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86237.704918 # average ReadReq miss latency 1467system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77950 # average ReadReq miss latency 1468system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79420.581391 # average ReadReq miss latency 1469system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81654.305949 # average ReadReq miss latency 1470system.cpu.l2cache.ReadReq_avg_miss_latency::total 80970.321198 # average ReadReq miss latency 1471system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12244.042408 # average UpgradeReq miss latency 1472system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12244.042408 # average UpgradeReq miss latency 1473system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71225.893937 # average ReadExReq miss latency 1474system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71225.893937 # average ReadExReq miss latency 1475system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency 1476system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency 1477system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency 1478system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency 1479system.cpu.l2cache.demand_avg_miss_latency::total 73970.040562 # average overall miss latency 1480system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency 1481system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency 1482system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency 1483system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency 1484system.cpu.l2cache.overall_avg_miss_latency::total 73970.040562 # average overall miss latency | 1402system.cpu.l2cache.overall_misses::cpu.inst 16085 # number of overall misses 1403system.cpu.l2cache.overall_misses::cpu.data 168870 # number of overall misses 1404system.cpu.l2cache.overall_misses::total 185021 # number of overall misses 1405system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5922249 # number of ReadReq miss cycles 1406system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 375500 # number of ReadReq miss cycles 1407system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1293203490 # number of ReadReq miss cycles 1408system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2919351194 # number of ReadReq miss cycles 1409system.cpu.l2cache.ReadReq_miss_latency::total 4218852433 # number of ReadReq miss cycles 1410system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17719300 # number of UpgradeReq miss cycles 1411system.cpu.l2cache.UpgradeReq_miss_latency::total 17719300 # number of UpgradeReq miss cycles 1412system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9455061655 # number of ReadExReq miss cycles 1413system.cpu.l2cache.ReadExReq_miss_latency::total 9455061655 # number of ReadExReq miss cycles 1414system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5922249 # number of demand (read+write) miss cycles 1415system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 375500 # number of demand (read+write) miss cycles 1416system.cpu.l2cache.demand_miss_latency::cpu.inst 1293203490 # number of demand (read+write) miss cycles 1417system.cpu.l2cache.demand_miss_latency::cpu.data 12374412849 # number of demand (read+write) miss cycles 1418system.cpu.l2cache.demand_miss_latency::total 13673914088 # number of demand (read+write) miss cycles 1419system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5922249 # number of overall miss cycles 1420system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 375500 # number of overall miss cycles 1421system.cpu.l2cache.overall_miss_latency::cpu.inst 1293203490 # number of overall miss cycles 1422system.cpu.l2cache.overall_miss_latency::cpu.data 12374412849 # number of overall miss cycles 1423system.cpu.l2cache.overall_miss_latency::total 13673914088 # number of overall miss cycles 1424system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64157 # number of ReadReq accesses(hits+misses) 1425system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7647 # number of ReadReq accesses(hits+misses) 1426system.cpu.l2cache.ReadReq_accesses::cpu.inst 958192 # number of ReadReq accesses(hits+misses) 1427system.cpu.l2cache.ReadReq_accesses::cpu.data 1368804 # number of ReadReq accesses(hits+misses) 1428system.cpu.l2cache.ReadReq_accesses::total 2398800 # number of ReadReq accesses(hits+misses) 1429system.cpu.l2cache.Writeback_accesses::writebacks 1581663 # number of Writeback accesses(hits+misses) 1430system.cpu.l2cache.Writeback_accesses::total 1581663 # number of Writeback accesses(hits+misses) 1431system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1774 # number of UpgradeReq accesses(hits+misses) 1432system.cpu.l2cache.UpgradeReq_accesses::total 1774 # number of UpgradeReq accesses(hits+misses) 1433system.cpu.l2cache.ReadExReq_accesses::cpu.data 288000 # number of ReadExReq accesses(hits+misses) 1434system.cpu.l2cache.ReadExReq_accesses::total 288000 # number of ReadExReq accesses(hits+misses) 1435system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64157 # number of demand (read+write) accesses 1436system.cpu.l2cache.demand_accesses::cpu.itb.walker 7647 # number of demand (read+write) accesses 1437system.cpu.l2cache.demand_accesses::cpu.inst 958192 # number of demand (read+write) accesses 1438system.cpu.l2cache.demand_accesses::cpu.data 1656804 # number of demand (read+write) accesses 1439system.cpu.l2cache.demand_accesses::total 2686800 # number of demand (read+write) accesses 1440system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64157 # number of overall (read+write) accesses 1441system.cpu.l2cache.overall_accesses::cpu.itb.walker 7647 # number of overall (read+write) accesses 1442system.cpu.l2cache.overall_accesses::cpu.inst 958192 # number of overall (read+write) accesses 1443system.cpu.l2cache.overall_accesses::cpu.data 1656804 # number of overall (read+write) accesses 1444system.cpu.l2cache.overall_accesses::total 2686800 # number of overall (read+write) accesses 1445system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000951 # miss rate for ReadReq accesses 1446system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000654 # miss rate for ReadReq accesses 1447system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016787 # miss rate for ReadReq accesses 1448system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026274 # miss rate for ReadReq accesses 1449system.cpu.l2cache.ReadReq_miss_rate::total 0.021725 # miss rate for ReadReq accesses 1450system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.819617 # miss rate for UpgradeReq accesses 1451system.cpu.l2cache.UpgradeReq_miss_rate::total 0.819617 # miss rate for UpgradeReq accesses 1452system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461479 # miss rate for ReadExReq accesses 1453system.cpu.l2cache.ReadExReq_miss_rate::total 0.461479 # miss rate for ReadExReq accesses 1454system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000951 # miss rate for demand accesses 1455system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000654 # miss rate for demand accesses 1456system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016787 # miss rate for demand accesses 1457system.cpu.l2cache.demand_miss_rate::cpu.data 0.101925 # miss rate for demand accesses 1458system.cpu.l2cache.demand_miss_rate::total 0.068863 # miss rate for demand accesses 1459system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000951 # miss rate for overall accesses 1460system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000654 # miss rate for overall accesses 1461system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016787 # miss rate for overall accesses 1462system.cpu.l2cache.overall_miss_rate::cpu.data 0.101925 # miss rate for overall accesses 1463system.cpu.l2cache.overall_miss_rate::total 0.068863 # miss rate for overall accesses 1464system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 97086.049180 # average ReadReq miss latency 1465system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75100 # average ReadReq miss latency 1466system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80398.103202 # average ReadReq miss latency 1467system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81174.262985 # average ReadReq miss latency 1468system.cpu.l2cache.ReadReq_avg_miss_latency::total 80952.747443 # average ReadReq miss latency 1469system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12186.588721 # average UpgradeReq miss latency 1470system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12186.588721 # average UpgradeReq miss latency 1471system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71140.969219 # average ReadExReq miss latency 1472system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71140.969219 # average ReadExReq miss latency 1473system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 97086.049180 # average overall miss latency 1474system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75100 # average overall miss latency 1475system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80398.103202 # average overall miss latency 1476system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73277.745301 # average overall miss latency 1477system.cpu.l2cache.demand_avg_miss_latency::total 73904.659947 # average overall miss latency 1478system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 97086.049180 # average overall miss latency 1479system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75100 # average overall miss latency 1480system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80398.103202 # average overall miss latency 1481system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73277.745301 # average overall miss latency 1482system.cpu.l2cache.overall_avg_miss_latency::total 73904.659947 # average overall miss latency |
| 1485system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1486system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1487system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1488system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1489system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1490system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1491system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1492system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1483system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1484system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1485system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1486system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1487system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1488system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1489system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1490system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1493system.cpu.l2cache.writebacks::writebacks 101920 # number of writebacks 1494system.cpu.l2cache.writebacks::total 101920 # number of writebacks 1495system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits | 1491system.cpu.l2cache.writebacks::writebacks 101656 # number of writebacks 1492system.cpu.l2cache.writebacks::total 101656 # number of writebacks 1493system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits |
| 1496system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits | 1494system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits |
| 1497system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1498system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits | 1495system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 1496system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits |
| 1499system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits | 1497system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits |
| 1500system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 1501system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits | 1498system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 1499system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits |
| 1502system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits | 1500system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits |
| 1503system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits | 1501system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits |
| 1504system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses 1505system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses | 1502system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses 1503system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses |
| 1506system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16087 # number of ReadReq MSHR misses 1507system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36005 # number of ReadReq MSHR misses 1508system.cpu.l2cache.ReadReq_mshr_misses::total 52158 # number of ReadReq MSHR misses 1509system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1462 # number of UpgradeReq MSHR misses 1510system.cpu.l2cache.UpgradeReq_mshr_misses::total 1462 # number of UpgradeReq MSHR misses 1511system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133062 # number of ReadExReq MSHR misses 1512system.cpu.l2cache.ReadExReq_mshr_misses::total 133062 # number of ReadExReq MSHR misses | 1504system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16084 # number of ReadReq MSHR misses 1505system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35963 # number of ReadReq MSHR misses 1506system.cpu.l2cache.ReadReq_mshr_misses::total 52113 # number of ReadReq MSHR misses 1507system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1454 # number of UpgradeReq MSHR misses 1508system.cpu.l2cache.UpgradeReq_mshr_misses::total 1454 # number of UpgradeReq MSHR misses 1509system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132906 # number of ReadExReq MSHR misses 1510system.cpu.l2cache.ReadExReq_mshr_misses::total 132906 # number of ReadExReq MSHR misses |
| 1513system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses 1514system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses | 1511system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses 1512system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses |
| 1515system.cpu.l2cache.demand_mshr_misses::cpu.inst 16087 # number of demand (read+write) MSHR misses 1516system.cpu.l2cache.demand_mshr_misses::cpu.data 169067 # number of demand (read+write) MSHR misses 1517system.cpu.l2cache.demand_mshr_misses::total 185220 # number of demand (read+write) MSHR misses | 1513system.cpu.l2cache.demand_mshr_misses::cpu.inst 16084 # number of demand (read+write) MSHR misses 1514system.cpu.l2cache.demand_mshr_misses::cpu.data 168869 # number of demand (read+write) MSHR misses 1515system.cpu.l2cache.demand_mshr_misses::total 185019 # number of demand (read+write) MSHR misses |
| 1518system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses 1519system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses | 1516system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses 1517system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses |
| 1520system.cpu.l2cache.overall_mshr_misses::cpu.inst 16087 # number of overall MSHR misses 1521system.cpu.l2cache.overall_mshr_misses::cpu.data 169067 # number of overall MSHR misses 1522system.cpu.l2cache.overall_mshr_misses::total 185220 # number of overall MSHR misses 1523system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4502000 # number of ReadReq MSHR miss cycles 1524system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles 1525system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075523016 # number of ReadReq MSHR miss cycles 1526system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2491735810 # number of ReadReq MSHR miss cycles 1527system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3572087076 # number of ReadReq MSHR miss cycles 1528system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15586943 # number of UpgradeReq MSHR miss cycles 1529system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15586943 # number of UpgradeReq MSHR miss cycles 1530system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7807116101 # number of ReadExReq MSHR miss cycles 1531system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7807116101 # number of ReadExReq MSHR miss cycles 1532system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4502000 # number of demand (read+write) MSHR miss cycles 1533system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles 1534system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075523016 # number of demand (read+write) MSHR miss cycles 1535system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10298851911 # number of demand (read+write) MSHR miss cycles 1536system.cpu.l2cache.demand_mshr_miss_latency::total 11379203177 # number of demand (read+write) MSHR miss cycles 1537system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4502000 # number of overall MSHR miss cycles 1538system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles 1539system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075523016 # number of overall MSHR miss cycles 1540system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10298851911 # number of overall MSHR miss cycles 1541system.cpu.l2cache.overall_mshr_miss_latency::total 11379203177 # number of overall MSHR miss cycles 1542system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251387000 # number of ReadReq MSHR uncacheable cycles 1543system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251387000 # number of ReadReq MSHR uncacheable cycles 1544system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372677500 # number of WriteReq MSHR uncacheable cycles 1545system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372677500 # number of WriteReq MSHR uncacheable cycles 1546system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624064500 # number of overall MSHR uncacheable cycles 1547system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624064500 # number of overall MSHR uncacheable cycles 1548system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for ReadReq accesses 1549system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for ReadReq accesses 1550system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for ReadReq accesses 1551system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026297 # mshr miss rate for ReadReq accesses 1552system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses 1553system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823198 # mshr miss rate for UpgradeReq accesses 1554system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823198 # mshr miss rate for UpgradeReq accesses 1555system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461846 # mshr miss rate for ReadExReq accesses 1556system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461846 # mshr miss rate for ReadExReq accesses 1557system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for demand accesses 1558system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for demand accesses 1559system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for demand accesses 1560system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for demand accesses 1561system.cpu.l2cache.demand_mshr_miss_rate::total 0.068880 # mshr miss rate for demand accesses 1562system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for overall accesses 1563system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for overall accesses 1564system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for overall accesses 1565system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for overall accesses 1566system.cpu.l2cache.overall_mshr_miss_rate::total 0.068880 # mshr miss rate for overall accesses 1567system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average ReadReq mshr miss latency 1568system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency 1569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66856.655436 # average ReadReq mshr miss latency 1570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69205.271768 # average ReadReq mshr miss latency 1571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68485.890487 # average ReadReq mshr miss latency 1572system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.383721 # average UpgradeReq mshr miss latency 1573system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.383721 # average UpgradeReq mshr miss latency 1574system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.769844 # average ReadExReq mshr miss latency 1575system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.769844 # average ReadExReq mshr miss latency 1576system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency 1577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency 1578system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency 1579system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency 1580system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency 1581system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency 1582system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency 1583system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency 1584system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency 1585system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency | 1518system.cpu.l2cache.overall_mshr_misses::cpu.inst 16084 # number of overall MSHR misses 1519system.cpu.l2cache.overall_mshr_misses::cpu.data 168869 # number of overall MSHR misses 1520system.cpu.l2cache.overall_mshr_misses::total 185019 # number of overall MSHR misses 1521system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5166251 # number of ReadReq MSHR miss cycles 1522system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 312500 # number of ReadReq MSHR miss cycles 1523system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1091253760 # number of ReadReq MSHR miss cycles 1524system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2471371556 # number of ReadReq MSHR miss cycles 1525system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3568104067 # number of ReadReq MSHR miss cycles 1526system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15558435 # number of UpgradeReq MSHR miss cycles 1527system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15558435 # number of UpgradeReq MSHR miss cycles 1528system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7786682845 # number of ReadExReq MSHR miss cycles 1529system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7786682845 # number of ReadExReq MSHR miss cycles 1530system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5166251 # number of demand (read+write) MSHR miss cycles 1531system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) MSHR miss cycles 1532system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1091253760 # number of demand (read+write) MSHR miss cycles 1533system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10258054401 # number of demand (read+write) MSHR miss cycles 1534system.cpu.l2cache.demand_mshr_miss_latency::total 11354786912 # number of demand (read+write) MSHR miss cycles 1535system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5166251 # number of overall MSHR miss cycles 1536system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 312500 # number of overall MSHR miss cycles 1537system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1091253760 # number of overall MSHR miss cycles 1538system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10258054401 # number of overall MSHR miss cycles 1539system.cpu.l2cache.overall_mshr_miss_latency::total 11354786912 # number of overall MSHR miss cycles 1540system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250274500 # number of ReadReq MSHR uncacheable cycles 1541system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250274500 # number of ReadReq MSHR uncacheable cycles 1542system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370476500 # number of WriteReq MSHR uncacheable cycles 1543system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370476500 # number of WriteReq MSHR uncacheable cycles 1544system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91620751000 # number of overall MSHR uncacheable cycles 1545system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91620751000 # number of overall MSHR uncacheable cycles 1546system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for ReadReq accesses 1547system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for ReadReq accesses 1548system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for ReadReq accesses 1549system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026273 # mshr miss rate for ReadReq accesses 1550system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021725 # mshr miss rate for ReadReq accesses 1551system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.819617 # mshr miss rate for UpgradeReq accesses 1552system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.819617 # mshr miss rate for UpgradeReq accesses 1553system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461479 # mshr miss rate for ReadExReq accesses 1554system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461479 # mshr miss rate for ReadExReq accesses 1555system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for demand accesses 1556system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for demand accesses 1557system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for demand accesses 1558system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for demand accesses 1559system.cpu.l2cache.demand_mshr_miss_rate::total 0.068862 # mshr miss rate for demand accesses 1560system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for overall accesses 1561system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for overall accesses 1562system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for overall accesses 1563system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for overall accesses 1564system.cpu.l2cache.overall_mshr_miss_rate::total 0.068862 # mshr miss rate for overall accesses 1565system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average ReadReq mshr miss latency 1566system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 1567system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67847.162397 # average ReadReq mshr miss latency 1568system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68719.838612 # average ReadReq mshr miss latency 1569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68468.598373 # average ReadReq mshr miss latency 1570system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10700.436726 # average UpgradeReq mshr miss latency 1571system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10700.436726 # average UpgradeReq mshr miss latency 1572system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58587.895543 # average ReadExReq mshr miss latency 1573system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58587.895543 # average ReadExReq mshr miss latency 1574system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency 1575system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1576system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency 1577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency 1578system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency 1579system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency 1580system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1581system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency 1582system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency 1583system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency |
| 1586system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1587system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1588system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1589system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1590system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1591system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1592system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1593system.cpu.kern.inst.arm 0 # number of arm instructions executed 1594system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1595 1596---------- End Simulation Statistics ---------- | 1584system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1585system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1586system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1587system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1588system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1589system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1590system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1591system.cpu.kern.inst.arm 0 # number of arm instructions executed 1592system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1593 1594---------- End Simulation Statistics ---------- |